Ethernet data transmission interface design method based on optical computing chip

Abstract

The invention discloses an Ethernet data transmission interface design method based on an optical computing chip, which comprises the following steps: S1, a W5500 receives an Ethernet data packet, analyzes and optimizes a path and a rate; s2, ESP32-S3, de-encapsulating the data, and analyzing control data, real-time data and common data; s3, analyzing an error rate and a packet loss rate, and dynamically adjusting correction parameters; s4, adapting the signal into an optical computing chip input format; s5, the optical calculation chip calculates and outputs an optical signal; and S6, converting the optical signal into an electric signal, optimizing and outputting. By optimizing the integrated design of the optical computing chip and the Ethernet interface, full-link optimization from optical signal receiving, data analysis to dynamic path selection and rate adjustment is realized, and the efficiency, the stability and the real-time performance of data transmission are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a design method for an Ethernet data transmission interface based on an optical computing chip. Background Art

[0002] With the rapid development of information technology, the speed and efficiency of data transmission have become important research directions in the field of communications. Although traditional copper cable communication technology has certain advantages in terms of low cost and easy deployment, with the continuous increase in data transmission needs, its bottlenecks in bandwidth, anti-interference ability and transmission distance are becoming more and more obvious. Optical communication technology has gradually become an important part of modern communication systems due to its advantages of high bandwidth, low loss and long-distance transmission. In particular, in scenarios such as data center interconnection, ultra-high-speed networks and high-performance computing, optical computing chips have played a key role as core devices.

[0003] The data transmission of optical computing chips needs to be seamlessly integrated with the Ethernet system in order to access the existing network infrastructure. However, the existing technology still has many problems in the design and optimization of the interface between optical computing chips and Ethernet. Traditional methods usually require additional protocol converters or adapters, which not only increases the design complexity of the system, but also puts higher requirements on the performance of the hardware. In addition, there are differences in the interface standards and communication protocols between optical computing chips and Ethernet devices produced by different manufacturers, resulting in poor compatibility of system integration. In the actual deployment process, this compatibility problem will lead to reduced stability and reliability of data transmission, which in turn affects the overall performance of the system.

[0004] In the existing optical computing chip data transmission solutions, although some technologies have achieved the conversion of optical signals and electrical signals by using dedicated control chips and customized interface designs, these solutions usually only focus on the optimization of a single link, such as signal conversion or data transmission protocol, and lack the full-link optimization design from signal reception, analysis, encapsulation to data packet transmission. For example, during the signal reception and analysis process, noise interference and signal attenuation may cause the accuracy of data transmission to decrease, and the methods used for filtering and noise suppression in the existing technology are mostly based on fixed parameters, which cannot be dynamically adjusted according to the real-time communication environment, and it is difficult to maintain efficient and stable signal quality in complex environments.

[0005] In addition, in terms of data encapsulation and transmission path selection, existing technologies often use static parameter configuration and cannot be dynamically optimized according to changes in network load. Although the Ethernet protocol provides a certain degree of transmission efficiency, the existing encapsulation and transmission mechanism lacks sufficient flexibility for high-priority data or real-time data, which can easily lead to delays or data loss. In terms of path selection, traditional solutions usually rely on fixed routing tables or simple delay measurements, while ignoring key performance indicators such as bandwidth utilization and bit error rate, thereby limiting the overall optimization effect of data transmission.

[0006] As a highly integrated communication device, the W5500 Ethernet module has significant advantages in data transmission performance. However, the use of the W5500 module in the prior art is mostly focused on basic data transmission functions, and its dynamic optimization capabilities have not been fully explored. For example, in the generation and transmission of Ethernet data packets, the existing solutions lack fine control over transmission rate, path selection, and priority sorting. This deficiency is particularly prominent in application scenarios with large data volumes and high real-time requirements.

[0007] Therefore, how to provide a design method for an Ethernet data transmission interface based on an optical computing chip is an urgent problem that those skilled in the art need to solve. Summary of the invention

[0008] One purpose of the present invention is to propose a design method for an Ethernet data transmission interface based on an optical computing chip. The present invention describes in detail the full-link implementation process of optical computing chip data transmission by optimizing key technical links such as optical signal reception and analysis, dynamic noise suppression, hierarchical packaging algorithm, path selection and transmission rate adjustment, and utilizes the highly integrated capabilities of the W5500 Ethernet module and the ESP32-S3 microcontroller to significantly improve the efficiency and reliability of data transmission. The present invention has the advantages of strong compatibility, high real-time performance, fast transmission rate and low cost, and is suitable for application scenarios such as modern data centers, network equipment interconnection and high-performance computing.

[0009] A method for designing an Ethernet data transmission interface based on an optical computing chip according to an embodiment of the present invention comprises the following steps:

[0010] S1. Receive Ethernet data packets through the W5500 Ethernet module, parse the destination address, source address, protocol type and data field of the data packets, and optimize the path selection and adjust the transmission rate;

[0011] S2, input the optimized Ethernet data packet into the ESP32-S3 microcontroller, and use the hierarchical encapsulation algorithm to decapsulate the data in layers to parse control data, real-time data and ordinary data;

[0012] S3, using the ESP32-S3 microcontroller combined with an improved adaptive error correction algorithm, real-time analysis of the error rate and packet loss rate in the decapsulated data, and dynamic adjustment of error correction parameters;

[0013] S4, adjusting the decapsulated and corrected data to a signal format adapted to the input of the optical computing chip through a dynamic signal adaptation module, thereby completing data preprocessing;

[0014] S5, transmitting the adjusted data to the optical computing chip, which performs calculations and outputs optical signals, which are converted into electrical signals through photoelectric conversion;

[0015] S6. The electrical signal enters the high-precision filtering module for interference suppression and signal cleaning, and then enters the signal amplification module to enhance the signal amplitude. Finally, the optimized electrical signal is output to the target device.

[0016] Optionally, the S2 specifically includes:

[0017] S21, inputting the optimized Ethernet data packet into the ESP32-S3 microcontroller, extracting the header information of the data packet, including a data type field, a priority field, and a timestamp field;

[0018] S22. According to the identifier of the data type field in the header information, the data is divided into control data, real-time data and ordinary data:

[0019]

[0020] Among them, D type Represents the classification result of the data, T d Indicates the data type field, D control represents the control data set, D real-time Indicates real-time data, D bulk Indicates D bulk , Control represents control data;

[0021] S23, preferentially decapsulating the control data and extracting key parameters for device configuration or system management;

[0022] S24, decapsulating the real-time data one by one in the order of the timestamp fields;

[0023] S25, decapsulating the common data in batch processing mode, and recording the parsing status of each data block;

[0024] S26. Reclassify and store the hierarchical data according to the decapsulation result.

[0025] Optionally, the S3 specifically includes:

[0026] S31, real-time monitoring of the error rate and packet loss rate in the decapsulated data, and obtaining the fluctuation range thereof through statistical analysis;

[0027] S32, dynamically adjusting the number of retransmissions of the data packet according to the change of the error rate;

[0028] S33. Combine the real-time data of packet loss rate to optimize the packet verification density:

[0029]

[0030] Among them, D c Indicates the check density of the data packet. is the basic calibration density, k1 is the adjustment factor, ΔP l is the variation of packet loss rate;

[0031] S34. Adjust the redundant coding ratio through comprehensive analysis of error rate and packet loss rate:

[0032]

[0033] Among them, R e represents the redundant coding ratio, represents the basic redundant coding ratio, k2 is the adjustment factor, ΔE r is the variation of error rate;

[0034] S35, recording the data integrity after each error correction adjustment and generating feedback information;

[0035] S36. When the error rate and packet loss rate return to below the set threshold, reduce the redundant coding ratio and the check density.

[0036] Optionally, the S4 specifically includes:

[0037] S41, receiving the decapsulated and corrected data, and analyzing the amplitude, frequency range and encoding format of the data;

[0038] S42. According to the analysis result, the amplitude of the data is adjusted by the dynamic signal adaptation module, and the adjustment amplitude meets the input requirements of the optical computing chip:

[0039]

[0040] Among them, A represents the adjusted signal amplitude, A raw is the original signal amplitude, k is the dynamic adjustment factor, ΔA is the amplitude adjustment difference, A max The maximum amplitude supported by the optical computing chip;

[0041] S43, performing frequency range adaptation on the data after the amplitude adjustment, filtering out unnecessary frequency bands, and retaining the effective frequency range supported by the optical computing chip;

[0042] S44, converting the frequency-adapted data into a target coding format according to a coding specification of the optical computing chip, and reorganizing the signal structure;

[0043] S45, performing integrity check on the data after adjusting the amplitude, frequency and encoding format to complete data preprocessing.

[0044] Optionally, the S5 specifically includes:

[0045] S51, transmitting the data adjusted by the dynamic signal adaptation module to the input interface of the optical computing chip;

[0046] S52, the optical computing chip processes the input data, including data analysis, calculation and optimization operations:

[0047]

[0048] Among them, S optical represents the intensity of the optical signal output by the optical computing chip, G is the global gain coefficient of the optical signal, and F(D input (t)) represents the input data D input The result of the operation at time t, e -α·t is the attenuation factor, t0 and t1 represent the time range of data input;

[0049] S53, the optical computing chip outputs an optical signal according to the processing result, and transmits the optical signal to the photoelectric conversion module through its output interface;

[0050] S54, the photoelectric conversion module receives the optical signal and converts it into a corresponding electrical signal;

[0051] S55. Perform integrity check on the converted electrical signal, and output the electrical signal that passes the integrity check.

[0052] The beneficial effects of the present invention are:

[0053] The present invention solves the problems of poor compatibility, insufficient signal processing capability, and lack of flexibility in transmission mechanism in optical computing chip data transmission in the prior art by proposing a full-link optimized data transmission method based on the integration of optical computing chip and Ethernet interface. In the signal reception and analysis stage, the present invention introduces high-precision filtering and dynamic noise suppression modules to achieve real-time optimization in the process of converting optical signals to electrical signals. It can dynamically adjust filtering parameters and noise suppression strategies according to changes in the communication environment, thereby improving the quality and stability of the signal. In terms of data encapsulation, the present invention adopts a hierarchical encapsulation algorithm to classify and hierarchically process data, and encapsulates it in combination with priority and real-time requirements, which greatly improves the efficiency and reliability of data transmission.

[0054] In the path selection and rate adjustment link, the present invention combines the dynamic capabilities of the W5500 Ethernet module, selects the optimal path and dynamically adjusts the transmission rate according to real-time network performance indicators (such as delay, bandwidth, bit error rate, etc.), so that the data packet can reach the target device in the most efficient way. In addition, by sorting the priority of data packets and monitoring the path performance, the present invention realizes the priority protection of key data and adapts to complex communication scenarios with high real-time requirements.

[0055] In general, the present invention effectively solves the complexity problem of integrating optical computing chips with Ethernet interfaces, and achieves a significant improvement in data transmission performance through full-link optimization design. It has the beneficial effects of strong compatibility, stable transmission, high real-time performance and low cost, and provides reliable technical support for the realization of modern data center interconnection, high-performance computing and intelligent communication systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0057] Figure 1 This is a flow chart of a method for designing an Ethernet data transmission interface based on an optical computing chip proposed by the present invention;

[0058] Figure 2 This is a structural schematic diagram of optical signal reception and analysis of an Ethernet data transmission interface design method based on an optical computing chip proposed by the present invention. DETAILED DESCRIPTION

[0059] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0060] refer to Figure 1-2, a method for designing an Ethernet data transmission interface based on an optical computing chip, comprising the following steps:

[0061] S1. Receive Ethernet data packets through the W5500 Ethernet module, parse the destination address, source address, protocol type and data field of the data packets, and optimize the path selection and adjust the transmission rate;

[0062] S2, input the optimized Ethernet data packet into the ESP32-S3 microcontroller, and use the hierarchical encapsulation algorithm to decapsulate the data in layers to parse control data, real-time data and ordinary data;

[0063] S3, using the ESP32-S3 microcontroller combined with an improved adaptive error correction algorithm, real-time analysis of the error rate and packet loss rate in the decapsulated data, and dynamic adjustment of error correction parameters;

[0064] S4, adjusting the decapsulated and corrected data to a signal format adapted to the input of the optical computing chip through a dynamic signal adaptation module, thereby completing data preprocessing;

[0065] S5, transmitting the adjusted data to the optical computing chip, which performs calculations and outputs optical signals, which are converted into electrical signals through photoelectric conversion;

[0066] S6. The electrical signal enters the high-precision filtering module for interference suppression and signal cleaning, and then enters the signal amplification module to enhance the signal amplitude. Finally, the optimized electrical signal is output to the target device.

[0067] In this implementation, S2 specifically includes:

[0068] S21, inputting the optimized Ethernet data packet into the ESP32-S3 microcontroller, extracting the header information of the data packet, including a data type field, a priority field, and a timestamp field;

[0069] S22. According to the identifier of the data type field in the header information, the data is divided into control data, real-time data and ordinary data:

[0070]

[0071] Among them, D type Represents the classification result of the data, T d Indicates the data type field, D control represents the control data set, D real-time Indicates real-time data, D bulk Indicates D bulk , Control represents control data;

[0072] S23, preferentially decapsulating the control data and extracting key parameters for device configuration or system management;

[0073] S24, decapsulating the real-time data one by one in the order of the timestamp fields;

[0074] S25, decapsulating the common data in batch processing mode, and recording the parsing status of each data block;

[0075] S26. Reclassify and store the hierarchical data according to the decapsulation result.

[0076] In this implementation, S3 specifically includes:

[0077] S31, real-time monitoring of the error rate and packet loss rate in the decapsulated data, and obtaining the fluctuation range thereof through statistical analysis;

[0078] S32, dynamically adjusting the number of retransmissions of the data packet according to the change of the error rate;

[0079] S33. Combine the real-time data of packet loss rate to optimize the packet verification density:

[0080]

[0081] Among them, D c Indicates the check density of the data packet. is the basic calibration density, k1 is the adjustment factor, ΔP l is the variation of packet loss rate;

[0082] S34. Adjust the redundant coding ratio through comprehensive analysis of error rate and packet loss rate:

[0083]

[0084] Among them, R e represents the redundant coding ratio, represents the basic redundant coding ratio, k2 is the adjustment factor, ΔE r is the variation of error rate;

[0085] S35, recording the data integrity after each error correction adjustment and generating feedback information;

[0086] S36. When the error rate and packet loss rate return to below the set threshold, reduce the redundant coding ratio and the check density.

[0087] In this implementation, S4 specifically includes:

[0088] S41, receiving the decapsulated and corrected data, and analyzing the amplitude, frequency range and encoding format of the data;

[0089] S42. According to the analysis result, the amplitude of the data is adjusted by the dynamic signal adaptation module, and the adjustment amplitude meets the input requirements of the optical computing chip:

[0090]

[0091] Among them, A represents the adjusted signal amplitude, A raw is the original signal amplitude, k is the dynamic adjustment factor, ΔA is the amplitude adjustment difference, A max The maximum amplitude supported by the optical computing chip;

[0092] S43, performing frequency range adaptation on the data after the amplitude adjustment, filtering out unnecessary frequency bands, and retaining the effective frequency range supported by the optical computing chip;

[0093] S44, converting the frequency-adapted data into a target coding format according to a coding specification of the optical computing chip, and reorganizing the signal structure;

[0094] S45, performing integrity check on the data after adjusting the amplitude, frequency and encoding format to complete data preprocessing.

[0095] In this implementation manner, S5 specifically includes:

[0096] S51, transmitting the data adjusted by the dynamic signal adaptation module to the input interface of the optical computing chip;

[0097] S52, the optical computing chip processes the input data, including data analysis, calculation and optimization operations:

[0098]

[0099] Among them, S optical represents the intensity of the optical signal output by the optical computing chip, G is the global gain coefficient of the optical signal, and F(D input (t)) represents the input data D input The result of the operation at time t, e -α·t is the attenuation factor, t0 and t1 represent the time range of data input;

[0100] S53, the optical computing chip outputs an optical signal according to the processing result, and transmits the optical signal to the photoelectric conversion module through its output interface;

[0101] S54, the photoelectric conversion module receives the optical signal and converts it into a corresponding electrical signal;

[0102] S55. Perform integrity check on the converted electrical signal, and output the electrical signal that passes the integrity check.

[0103] Embodiment 1:

[0104] In order to verify the feasibility of the present invention in implementation, the present invention is applied to a data center. In the high-speed data transmission scenario of the data center, optical computing chips are widely used due to their high bandwidth and low latency characteristics. However, the data transmission interface of the traditional optical computing chip faces problems such as poor compatibility, unstable transmission rate and inflexible path selection when integrated with Ethernet, which limits the further promotion and optimization of optical communication technology.

[0105] In the data center scenario, high-speed data interconnection is required between server A and server B to meet the needs of real-time task scheduling and big data analysis. The experiment uses ESP32-S3 microcontroller and W5500 Ethernet module as core components to transmit data through optical computing chips. The traditional method uses fixed parameter settings and simple path selection, resulting in insufficient transmission efficiency and large delay fluctuations. The present invention significantly improves transmission performance through signal reception optimization, hierarchical encapsulation algorithm, path selection and dynamic adjustment of transmission rate.

[0106] First, in the signal receiving stage, the optical computing chip converts the high-speed data of server A into optical signals and generates preliminary electrical signals through the optoelectronic conversion module. In the experiment, high-precision filtering and dynamic noise suppression modules were used to increase the signal-to-noise ratio of the electrical signal from 28.4dB of the traditional method to 36.7dB, and the noise suppression efficiency was improved by 29%. These optimization measures keep the signal quality stable under different network loads and reduce the data bit error rate during transmission.

[0107] Subsequently, in the data encapsulation stage, the ESP32-S3 microcontroller divides the data into three categories according to priority: control data, real-time data, and ordinary data, according to the hierarchical encapsulation algorithm proposed by the present invention. Experimental data shows that after adopting hierarchical encapsulation, the average delay of control data is 1.2ms, which is 55.6% less than the 2.7ms of the traditional method; the packet loss rate of real-time data is reduced from 1.5% to 0.4%; and the bandwidth utilization of ordinary data is increased from 67% to 85%. These improvements ensure that critical data can be transmitted first, while improving the overall data transmission efficiency.

[0108] In terms of path selection and transmission rate adjustment, the present invention uses the dynamic optimization capability of the W5500 Ethernet module to select the optimal path according to the real-time network status. Experimental results show that among the three candidate paths, the path selected by the present invention has the lowest delay, which is only 4.2ms, which is 38.2% less than the 6.8ms of the traditional static path selection. In addition, the dynamic transmission rate adjustment function of the W5500 module increases the average bandwidth utilization by 18% and significantly enhances the transmission stability.

[0109] To verify the overall performance of the present invention, the experiment conducted multi-scenario and multi-load tests within one day, including file transfer tasks with data volumes of 100MB, 500MB and 1GB.

[0110] Table 1 Comparison of data transmission signal quality of optical computing chips

[0111]

[0112] Table 2 Comparison of transmission performance of hierarchical encapsulation algorithms

[0113]

[0114] Table 3 Path selection and transmission rate optimization effect table

[0115]

[0116] The data in Table 1 show that the present invention significantly improves the signal-to-noise ratio. Under low, medium and high load conditions, the signal-to-noise ratio is improved by 19.9%, 29.2% and 30.2% respectively compared with the traditional method. This shows that the high-precision filtering and dynamic noise suppression module of the present invention can effectively improve the signal quality, especially under high load conditions, and still maintain the stability of transmission.

[0117] Table 2 reflects the advantages of the hierarchical encapsulation algorithm. For control data and real-time data, the delay is reduced by 55.6% and 44.7% respectively, the packet loss rate is reduced by 85.7% and 73.3% respectively, and the bandwidth utilization of ordinary data is increased by 18%. These data show that the present invention not only gives priority to the transmission of key data, but also improves the overall transmission efficiency.

[0118] The path selection optimization and rate adjustment in Table 3 further verify the effectiveness of the present invention. The delay is reduced by 32% on average under various load conditions, and the bandwidth utilization rate is increased by nearly 23%. This shows that the present invention fully utilizes the potential of network resources through dynamic path selection and rate optimization, and significantly improves transmission efficiency and stability.

[0119] In summary, the present invention shows significant improvements in signal quality, data transmission performance and path optimization. It is particularly suitable for high-load and high-real-time scenarios, and provides a reliable and efficient solution for data transmission in optical computing chips.

[0120] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for designing an Ethernet data transmission interface based on an optical computing chip, characterized in that: The steps include: S1. Receive Ethernet data packets through the W5500 Ethernet module, parse the destination address, source address, protocol type and data field of the data packets, and optimize the path selection and adjust the transmission rate; S2, input the optimized Ethernet data packet into the ESP32-S3 microcontroller, and use the hierarchical encapsulation algorithm to decapsulate the data in layers to parse control data, real-time data and ordinary data; S3, using the ESP32-S3 microcontroller combined with an improved adaptive error correction algorithm, real-time analysis of the error rate and packet loss rate in the decapsulated data, and dynamic adjustment of error correction parameters; S4, adjusting the decapsulated and corrected data to a signal format adapted to the input of the optical computing chip through a dynamic signal adaptation module, thereby completing data preprocessing; S5, transmitting the adjusted data to the optical computing chip, which performs calculations and outputs optical signals, which are converted into electrical signals through photoelectric conversion; S6. The electrical signal enters the high-precision filtering module for interference suppression and signal cleaning, and then enters the signal amplification module to enhance the signal amplitude. Finally, the optimized electrical signal is output to the target device.

2. The method for designing an Ethernet data transmission interface based on an optical computing chip according to claim 1, characterized in that: The S2 specifically includes: S21, inputting the optimized Ethernet data packet into the ESP32-S3 microcontroller, extracting the header information of the data packet, including a data type field, a priority field, and a timestamp field; S22. According to the identifier of the data type field in the header information, the data is divided into control data, real-time data and ordinary data: Among them, D type Represents the classification result of the data, T d Indicates the data type field, D control represents the control data set, D real-time Indicates real-time data, D bulk Indicates D bulk , Control represents control data; S23, preferentially decapsulating the control data and extracting key parameters for device configuration or system management; S24, decapsulating the real-time data one by one in the order of the timestamp fields; S25, decapsulating the common data in batch processing mode, and recording the parsing status of each data block; S26. Reclassify and store the hierarchical data according to the decapsulation result.

3. The method for designing an Ethernet data transmission interface based on an optical computing chip according to claim 1, characterized in that: The S3 specifically includes: S31, real-time monitoring of the error rate and packet loss rate in the decapsulated data, and obtaining the fluctuation range thereof through statistical analysis; S32, dynamically adjusting the number of retransmissions of the data packet according to the change of the error rate; S33. Combine the real-time data of packet loss rate to optimize the packet verification density: Among them, D c Indicates the check density of the data packet. is the basic calibration density, k1 is the adjustment factor, ΔP l is the variation of packet loss rate; S34. Adjust the redundant coding ratio through comprehensive analysis of error rate and packet loss rate: Among them, R e represents the redundant coding ratio, represents the basic redundant coding ratio, k2 is the adjustment factor, ΔE r is the variation of error rate; S35, recording the data integrity after each error correction adjustment and generating feedback information; S36. When the error rate and packet loss rate return to below the set threshold, reduce the redundant coding ratio and the check density.

4. The method for designing an Ethernet data transmission interface based on an optical computing chip according to claim 1, characterized in that: The S4 specifically includes: S41, receiving the decapsulated and corrected data, and analyzing the amplitude, frequency range and encoding format of the data; S42. According to the analysis result, the amplitude of the data is adjusted by the dynamic signal adaptation module, and the adjustment amplitude meets the input requirements of the optical computing chip: Among them, A represents the adjusted signal amplitude, A raw is the original signal amplitude, k is the dynamic adjustment factor, ΔA is the amplitude adjustment difference, A max The maximum amplitude supported by the optical computing chip; S43, performing frequency range adaptation on the data after the amplitude adjustment, filtering out unnecessary frequency bands, and retaining the effective frequency range supported by the optical computing chip; S44, converting the frequency-adapted data into a target coding format according to the coding specification of the optical computing chip, and reorganizing the signal structure; S45, performing integrity check on the data after adjusting the amplitude, frequency and encoding format to complete data preprocessing.

5. The method for designing an Ethernet data transmission interface based on an optical computing chip according to claim 1, characterized in that: The S5 specifically includes: S51, transmitting the data adjusted by the dynamic signal adaptation module to the input interface of the optical computing chip; S52, the optical computing chip processes the input data, including data analysis, calculation and optimization operations: Among them, S optical represents the intensity of the optical signal output by the optical computing chip, G is the global gain coefficient of the optical signal, and F(D input (t)) represents the input data D input The result of the operation at time t, e -α·t is the attenuation factor, t0 and t1 represent the time range of data input; S53, the optical computing chip outputs an optical signal according to the processing result, and transmits the optical signal to the photoelectric conversion module through its output interface; S54, the photoelectric conversion module receives the optical signal and converts it into a corresponding electrical signal; S55. Perform integrity check on the converted electrical signal, and output the electrical signal that passes the integrity check.

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