Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: providing a substrate; forming a laminated structure on the substrate, wherein the laminated structure comprises first dielectric layers and conductive layers which are sequentially stacked from bottom to top; forming insulating layers corresponding to the side surfaces of the first dielectric layers; sequentially depositing channel material layers, isolation layers and gate conductive layers on the side surfaces of the conductive layers and the surfaces of the insulating layers; removing the insulating layers to expose the channel material layers corresponding to the first dielectric layers; and removing the exposed channel material layers to obtain channel layers located on the side surfaces of the conductive layers. The semiconductor structure preparation method can improve the device performance, ensure normal operation of the device and reduce the leakage current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of semiconductor structure and semiconductor structure. BACKGROUND

[0002] With the development of semiconductor technology, the 3D memory currently proposed is a memory with a new type of channel material. It selects metal oxide as the channel material, stacks multiple transistor devices, which can improve the integration density while ensuring the performance of the memory. In the related art, the surface of each layer of dielectric layer serving as insulation isolation in the memory with multiple layers stacked will also deposit channel material, which will cause the upper and lower two devices to be connected through the channel material in the dielectric layer, thereby generating a parasitic transistor. Therefore, the related art has the problem of parasitic transistor affecting the normal work of the device and increasing the leakage current. SUMMARY

[0003] Therefore, it is necessary to provide a preparation method of semiconductor structure and semiconductor structure for the problem of parasitic transistor in the related art.

[0004] In a first aspect, the present application provides a preparation method of semiconductor structure, comprising:

[0005] providing a substrate;

[0006] forming a stack structure on the substrate, the stack structure comprising a first dielectric layer and a conductive layer stacked in turn from bottom to top;

[0007] forming an insulating layer corresponding to the side surface of each layer of the first dielectric layer;

[0008] depositing a channel material layer, an isolation layer and a gate conductive layer in turn on the side surface of each layer of the conductive layer and the surface of the insulating layer;

[0009] removing each layer of the insulating layer to expose each layer of the channel material layer corresponding to each layer of the first dielectric layer;

[0010] removing the exposed each layer of the channel material layer to obtain a channel layer located on the side surface of each layer of the conductive layer.

[0011] The method for manufacturing the semiconductor structure includes the following steps: forming a stack structure on the substrate, the stack structure including first dielectric layers and conductive layers stacked in sequence from bottom to top; forming insulating layers corresponding to the side surfaces of the first dielectric layers; sequentially depositing channel material layers, isolation layers and gate conductive layers on the side surfaces of the conductive layers and the surfaces of the insulating layers; removing the insulating layers to expose the channel material layers corresponding to the first dielectric layers; and removing the exposed channel material layers to obtain channel layers on the side surfaces of the conductive layers. Since the channel material layers corresponding to the conductive layers are not exposed, the channel material layers covering the side surfaces of the first dielectric layers are completely exposed. Then, the channel material layers are removed by etching, which can increase the etching contact area of the channel material layers, so that the channel material layers corresponding to the first dielectric layers can be quickly removed to quickly remove the parasitic transistors, and the channel layers on the side surfaces of the conductive layers can be reserved without being damaged, thereby improving the device performance, ensuring the normal operation of the device and reducing the leakage current.

[0012] In one embodiment, the conductive layers include main body portions extending along a first direction and a plurality of extension portions arranged at intervals along the first direction, each of the extension portions being located on opposite sides of the main body portion, the main body portion being integrally connected with each of the extension portions, and an end portion of each of the extension portions connected with the main body portion serving as a channel region.

[0013] A first groove penetrating the channel regions is formed by etching, and the side walls of the first groove expose the side surfaces of the first dielectric layers and the side surfaces of the conductive layers alternately stacked in sequence.

[0014] Based on the first groove, the first dielectric layers are laterally etched to form second grooves between the conductive layers, the bottom size of the second grooves being smaller than the opening size of the second grooves.

[0015] Insulating layers are formed on the bottoms of the second grooves, so that the insulating layers cover the side surfaces of the first dielectric layers.

[0016] In one embodiment, the insulating layers are formed on the bottoms of the second grooves to cover the side surfaces of the first dielectric layers, including the following steps:

[0017] A continuously distributed insulating material layer is formed on the inner walls of the first grooves and the inner walls of the second grooves, and the thickness of the insulating material layer at the bottoms of the second grooves is greater than the thickness of the insulating material layer at the side walls of the second grooves.

[0018] removing the insulating material layer on the inner wall of the first trench and part of the insulating material layer on the sidewall of the second trench to obtain an insulating layer reserved on the bottom of the second trench.

[0019] In one of the embodiments, the removing the insulating material layer on the inner wall of the first trench and part of the insulating material layer on the sidewall of the second trench comprises:

[0020] The removing the insulating material layer on the inner wall of the first trench and part of the insulating material layer on the sidewall of the second trench is performed by a wet etching process.

[0021] In one of the embodiments, after the forming the stack structure on the substrate, before the forming the insulating layer corresponding to the side of each layer of the first dielectric layer, the method further comprises:

[0022] depositing a third dielectric layer, which fills the gap of the stack structure.

[0023] In one of the embodiments, the part of the extension away from the main body part serves as a first electrode, after the depositing the third dielectric layer, the method further comprises:

[0024] removing the sacrificial layer on the surface of the first electrode to expose the surface of the first electrode;

[0025] forming a capacitor dielectric layer and a second electrode on the exposed surface of the first electrode in sequence.

[0026] In one of the embodiments, the removing each layer of the insulating layer to expose each layer of the channel material layer corresponding to each layer of the first dielectric layer comprises:

[0027] forming a third trench penetrating the third dielectric layer between adjacent channel regions, so that the sidewall of the third trench exposes the surface of each layer of the insulating layer;

[0028] removing each layer of the insulating layer based on the third trench to expose each layer of the channel material layer corresponding to each layer of the first dielectric layer.

[0029] In one of the embodiments, the insulating layer is an aluminum oxide layer.

[0030] In one of the embodiments, the forming a third trench penetrating the third dielectric layer between adjacent channel regions, so that the sidewall of the third trench exposes the surface of each layer of the insulating layer comprises:

[0031] forming a third trench penetrating the third dielectric layer between adjacent channel regions by a dry etching process.

[0032] A portion of the third dielectric layer on the inner wall of the third trench is removed by etching with an acidic solution to expose the surface of each layer of the aluminum oxide layer.

[0033] In one embodiment, the removing each layer of the insulating layer based on the third trench comprises:

[0034] Each layer of the aluminum oxide layer is removed based on the third trench by etching with an alkaline solution.

[0035] In one embodiment, after the removing each layer of the channel material layer to obtain a channel layer located on the side of each layer of the conductive layer, the method further comprises:

[0036] The third trench is filled with a fourth filling layer.

[0037] In a second aspect, the present application provides a semiconductor structure, comprising:

[0038] a substrate;

[0039] a stack structure located on the substrate, the stack structure comprising a first dielectric layer and a conductive layer stacked in order from bottom to top, each layer of the conductive layer comprising a main body portion extending along a first direction and a plurality of extension portions arranged at intervals along the first direction, each of the extension portions being located on the opposite sides of the main body portion, the main body portion being integrally connected with each of the extension portions, and the end portion of the extension portion connected with the main body portion serving as a channel region;

[0040] a gate conductive layer extending along a direction perpendicular to the substrate and penetrating each layer of the channel region;

[0041] an isolation layer surrounding the sidewall of the gate conductive layer;

[0042] a plurality of channel layers surrounding the sidewall of the isolation layer and arranged at intervals along a direction perpendicular to the substrate, each layer of the channel layer being in one-to-one contact with each layer of the conductive layer.

[0043] The semiconductor structure comprises a substrate, a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive layers stacked in sequence from bottom to top, each of the conductive layers comprising a main body part extending in a first direction and a plurality of extension parts arranged at intervals in the first direction, each of the extension parts being located on opposite sides of the main body part, the main body part being integrally connected with each of the extension parts, and an end of the extension part connected with the main body part serving as a channel region; a gate conductive layer extending through each of the channel regions in a direction perpendicular to the substrate; an isolation layer surrounding a sidewall of the gate conductive layer; and a plurality of channel layers surrounding a sidewall of the isolation layer and arranged at intervals in a direction perpendicular to the substrate, each of the channel layers being in one-to-one correspondence with each of the conductive layers. Since each of the first dielectric layers corresponding to the channel material layer can be quickly removed to quickly remove a parasitic transistor, and the channel layer on the side of each of the conductive layers can be preserved without being damaged, the normal read-write work of the device can be ensured, and the leakage current can be reduced.

[0044] In one of the embodiments, the semiconductor structure further comprises a capacitor, the capacitor comprising a first electrode, a capacitor dielectric layer covering a surface of the first electrode, and a second electrode, and a part of the extension part away from the main body part serving as the first electrode of the capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0046] Figure 1 A flow chart of a preparation method of the semiconductor structure provided in an embodiment;

[0047] Figure 2 A step flow chart of step S20 in the preparation method of the semiconductor structure provided in an embodiment;

[0048] Figure 3 A 3D structure schematic diagram of a structure obtained in step S201 in the preparation method of the semiconductor structure provided in an embodiment;

[0049] Figure 4 A 3D structure schematic diagram of a structure obtained in step S202 in the preparation method of the semiconductor structure provided in an embodiment;

[0050] Figure 5 A 3D structure schematic diagram of a structure obtained in step S203 in the preparation method of the semiconductor structure provided in an embodiment; Figure 4The diagram shows a 3D structural diagram of the structure obtained after the first filling layer is used to fill the structure and form a frame structure.

[0051] Figure 6 This is a schematic diagram of the 3D structure of the semiconductor structure obtained in step S203 of the semiconductor structure fabrication method provided in one embodiment.

[0052] Figure 7 In one embodiment, the method for fabricating a semiconductor structure provides the following: Figure 6 A 3D structural diagram of the structure obtained after removing the first filling layer from the structure in the image;

[0053] Figure 8 This is a schematic diagram of the 3D structure of the semiconductor structure obtained in step S204 of the semiconductor structure fabrication method provided in one embodiment.

[0054] Figure 9 This is a schematic diagram of the 3D structure of the semiconductor structure obtained in step S205 of the semiconductor structure fabrication method provided in one embodiment.

[0055] Figure 10 In one embodiment, the method for fabricating a semiconductor structure provides the following: Figure 9 A 3D structural diagram of the structure obtained after filling the third filling layer in the structure;

[0056] Figure 11 This is a schematic diagram of the 3D structure of the semiconductor structure obtained in step S2052 of the semiconductor structure fabrication method provided in one embodiment;

[0057] Figure 12 This is a flowchart of step S30 in the method for fabricating a semiconductor structure provided in one embodiment;

[0058] Figure 13 This is a schematic diagram of the 3D structure of the semiconductor structure obtained in step S301 of the semiconductor structure fabrication method provided in one embodiment.

[0059] Figure 14 for Figure 13 A schematic diagram of the cross-sectional structure along the AA' direction;

[0060] Figure 15 This is a schematic cross-sectional view of the structure obtained in step S302 of the semiconductor structure fabrication method provided in one embodiment;

[0061] Figure 16 This is a flowchart of step S303 in the method for preparing a semiconductor structure provided in one embodiment;

[0062] Figure 17 This is a schematic diagram of the 3D structure of the semiconductor structure obtained in step S3031 of the semiconductor structure fabrication method provided in one embodiment.

[0063] Figure 18 A 3D structure schematic diagram of the structure obtained in step S3032 in the preparation method of the semiconductor structure provided in an embodiment;

[0064] Figure 19 A 3D structure schematic diagram of the structure obtained in step S40 in the preparation method of the semiconductor structure provided in an embodiment;

[0065] Figure 20 A cross-sectional structure schematic diagram of the structure in the AA' direction in Figure 19

[0066] Figure 21 A step flowchart of step S50 in the preparation method of the semiconductor structure provided in an embodiment;

[0067] Figure 22 A 3D structure schematic diagram of the structure obtained in step S501 in the preparation method of the semiconductor structure provided in an embodiment;

[0068] Figure 23 A step flowchart of step S501 in the preparation method of the semiconductor structure provided in an embodiment;

[0069] Figure 24 A cross-sectional structure schematic diagram of the structure obtained in step S502 in the preparation method of the semiconductor structure provided in an embodiment;

[0070] Figure 25 A cross-sectional structure schematic diagram of the structure obtained in step S60 in the preparation method of the semiconductor structure provided in an embodiment.

[0071] BRIEF DESCRIPTION OF THE DRAWINGS 1 - substrate, 20 - initial stack structure, 21 - stack structure, 201 - first dielectric layer, 2011 - initial main part, 2012 - initial extension part, 202 - second dielectric layer, 203 - conductive layer, 2031 - main part, 2032 - extension part, 31 - first filling layer, 41 - frame structure, 42 - second filling layer, 43 - insulating layer, 431 - insulating material layer, 32 - third filling layer, 501 - capacitor dielectric layer, 502 - second electrode, 601 - first trench, 602 - second trench, 603 - third trench, 701 - channel layer, 7011 - channel material layer, 702 - isolation layer, 703 - gate conductive layer. DETAILED DESCRIPTION

[0072] ​For the purposes of the present invention, a more complete description of the application will be presented in the following detailed description of the application. The description of the application is presented with reference to the accompanying drawings. The description of the application is presented for purposes of illustration and description, and is not intended to limit the application as defined by the appended claims.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0074] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. For example, a first doped type could be a P-type and a second doped type could be an N-type, or a first doped type could be an N-type and a second doped type could be a P-type.

[0075] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional orientations. It is to be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional orientations.

[0076] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0077] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0078] Please see Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0079] S10: Provides a substrate;

[0080] S20: A stacked structure is formed on a substrate, the stacked structure including a first dielectric layer and a conductive layer stacked sequentially from bottom to top;

[0081] S30: An insulating layer is formed on the side surface of each first dielectric layer;

[0082] S40: A channel material layer, an isolation layer, and a gate conductive layer are sequentially deposited on the side surfaces of each conductive layer and the surface of the insulating layer.

[0083] S50: Remove each insulating layer to expose the channel material layers corresponding to each first dielectric layer;

[0084] S60: Remove the exposed channel material layers to obtain the channel layers located on the sides of the conductive layers.

[0085] The method for manufacturing the semiconductor structure includes the following steps: forming a stack structure on a substrate, the stack structure comprising first dielectric layers and conductive layers stacked in sequence from bottom to top; forming insulating layers corresponding to the side surfaces of the first dielectric layers; sequentially depositing channel material layers, isolation layers and gate conductive layers on the side surfaces of the conductive layers and the surfaces of the insulating layers; removing the insulating layers to expose the channel material layers corresponding to the first dielectric layers; and removing the exposed channel material layers to obtain channel layers on the side surfaces of the conductive layers. Since the channel material layers corresponding to the conductive layers are not exposed, the channel material layers covering the side surfaces of the first dielectric layers are completely exposed. Then, the channel material layers are removed by etching, which can increase the etching contact area of the channel material layers, so that the channel material layers corresponding to the first dielectric layers can be quickly removed to quickly remove the parasitic transistors, and the channel layers on the side surfaces of the conductive layers can be reserved without being damaged, thereby improving the device performance, ensuring the normal operation of the device and reducing the leakage current. Moreover, the manufacturing method can reduce the process difficulty, improve the process precision and simplify the process flow.

[0086] In step S20, referring to steps S10 and S20 in Figure 1 and Figure 9 , a stack structure 21 is formed on a substrate 1, the stack structure 21 comprising first dielectric layers 201 and conductive layers 203 stacked in sequence from bottom to top.

[0087] The material of the substrate 1 can be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including a multilayer structure formed by these semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-silicon-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI), or double-side polished wafers (DSP), ceramic substrates such as aluminum oxide, quartz or glass substrates, etc. The present embodiment is not limited in this regard.

[0088] The first dielectric layers 201 can comprise oxide materials or nitride materials, for example, silicon oxide or silicon nitride. The material of the conductive layers 203 can comprise metal materials, for example, tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta) or other suitable metals.

[0089] In some embodiments, as shown in Figure 2 S20 comprises:

[0090] S201: forming an initial stack structure 20 on the substrate 1, the initial stack structure 20 comprising a first dielectric layer 201 and a second dielectric layer 202 stacked in sequence from bottom to top, as shown in Figure 3 .

[0091] Wherein, the first dielectric layer 201 and the second dielectric layer 202 can be deposited in sequence on the substrate 1 by using a deposition process to obtain the initial stack structure 20. The material of the second dielectric layer 202 can comprise a nitride material, and the material of the second dielectric layer 202 is different from the material of the first dielectric layer 201. For example, the material of the second dielectric layer 202 can be silicon nitride (Si3N4), and the material of the first dielectric layer 201 can be silicon oxide (SiO2), or the first dielectric layer 201 and the second dielectric layer 202 can also be other suitable material combinations, which are not limited in the present embodiment.

[0092] S202: patterning the initial stack structure 20, so that each layer of the first dielectric layer 201 comprises an initial main body part 2011 extending along a first direction and a plurality of initial extension parts 2012 arranged at intervals along the first direction, each initial extension part 2012 is located on the opposite side of the initial main body part 2011, the initial main body part 2011 and each initial extension part 2012 are integrally connected, and the end of the initial extension part 2012 connected with the initial main body part 2011 serves as a preset channel region, as shown in Figure 4 .

[0093] Wherein, the first direction can be a column extension direction parallel to the substrate 1, as shown in Figure 4 , and the second direction can be a row extension direction parallel to the substrate 1, as shown in Figure 4 . The first direction can be perpendicular to the second direction. Of course, the first direction, the second direction and the direction perpendicular to the substrate 1 are only for the convenience of explaining the structure of the present scheme, and do not constitute any limitation on the present scheme. Moreover, in other suitable application scenarios, the first direction, the second direction and the direction perpendicular to the substrate 1 can also be other suitable directions, as long as the scheme of the present application is reasonable, which is not limited in the present embodiment.

[0094] Wherein, the initial stack structure 20 can be patterned by using a process combining lithography and etching.

[0095] Optionally, as shown in Figure 5As shown, after patterning the initial stacked structure 20, a first filling layer 31 can be used to fill the gap regions of the patterned initial stacked structure 20. Subsequently, an etching process can be used to remove portions located on both sides of the initial stacked structure 20, and then a deposition process can be used to form a frame structure 41 on both sides of the initial stacked structure 20. The material of the frame structure 41 may include a nitride material.

[0096] S203: Etching forms a first filling trench that penetrates the pre-defined channel area of ​​each layer, and a second filling layer 42 is formed within the first filling trench, such as... Figure 6 As shown.

[0097] The material of the second filler layer 42 may include polysilicon. The second filler layer 42 extends along a direction perpendicular to the substrate 1 and is used to connect each first dielectric layer 201 and define the positions of subsequent channel regions.

[0098] Optionally, after forming the second filler layer 42, a step of removing the first filler layer 31 can be performed to form as shown in the figure. Figure 7 The structure shown.

[0099] S204: Remove the second dielectric layer 202 from each layer of the initial stacked structure 20, such as Figure 8 As shown.

[0100] Etching can be used to selectively remove each second dielectric layer 202 while retaining each first dielectric layer 201. During selective etching, due to the supporting effect of the second filler layer 42, each first dielectric layer 201 can maintain its original morphology.

[0101] S205: Conductive layers 203 are formed between each first dielectric layer 201 to obtain a stacked structure 21. The stacked structure 21 includes first dielectric layers 201 and conductive layers 203 stacked sequentially from bottom to top. Figure 9 As shown.

[0102] In some embodiments, such as Figure 9 As shown, each conductive layer 203 includes: a main body portion 2031 extending along a first direction and a plurality of extension portions 2032 spaced apart along the first direction. Each extension portion 2032 is located on opposite sides of the main body portion 2031. The main body portion 2031 and each extension portion 2032 are integrally connected. The end of the extension portion 2032 connected to the main body portion 2031 serves as a channel region.

[0103] In some embodiments, after step S20 and before step S30, the method for fabricating the semiconductor structure further includes: depositing a third dielectric layer 32, wherein the third dielectric layer 32 fills the gaps in the stacked structure 21. Figure 10In some embodiments, the material of the third dielectric layer 32 can be the same as the first dielectric layer 201, thus in some embodiments, the structure as shown in Figure 11 may be obtained.

[0104] Based on the above embodiments, in some embodiments, the part of the extension 2032 away from the main body 2031 as the first electrode, after the deposition of the third dielectric layer 32, the method for preparing the semiconductor structure further comprises:

[0105] S2051: removing the sacrificial layer on the surface of the first electrode to expose the surface of the first electrode. In the removal process, the second dielectric layer 202 can be removed together.

[0106] S2052: sequentially forming a capacitor dielectric layer 501 and a second electrode 502 on the exposed surface of the first electrode, as shown in Figure 11 .

[0107] Among them, the deposition process can be used to sequentially deposit the capacitor dielectric layer 501 and the second electrode 502 on the exposed surface of the first electrode, and then the mechanical grinding process is used to polish the surface of the obtained structure to obtain the structure as shown in Figure 11 .

[0108] Among them, the material of the first electrode can include metal materials, such as copper, gold, titanium, silver, aluminum, tungsten, etc. The material of the capacitor dielectric layer 501 can include HK dielectric material. The material of the second electrode 502 can include conductive material, and the second electrode 502 can be further composed of a conductive barrier layer and an electrode conductive layer 203, wherein the conductive barrier layer can include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN) or a combination thereof; the material of the electrode conductive layer 203 can include polysilicon.

[0109] In step S30, please refer to Figure 1 step S30 and Figure 18 , the insulating layer 43 is formed corresponding to the side surface of each layer of the first dielectric layer 201.

[0110] In some embodiments, as shown in Figure 12 , the above step S30 comprises:

[0111] S301: etching to form a first groove 601 penetrating the channel region of each layer, the side wall of the first groove 601 exposing the side surface of the dielectric layer and the side surface of the conductive layer 203 alternately stacked in sequence, as shown in Figure 13-14 .

[0112] The second filling layer 42 can be removed directly by etching process, and the trench obtained after the removal is the first trench 601.

[0113] S302: Perform lateral etching on the first dielectric layer 201 based on the first trench 601 to form a second trench 602 between the conductive layers 203, and the bottom size of the second trench 602 is smaller than the opening size of the second trench 602, as shown in FIG. 3B. Figure 15

[0114] The lateral etching on the first dielectric layer 201 based on the first trench 601 can be performed by wet etching process. By controlling the etching parameters of the wet etching process and utilizing the isotropy of the wet etching, the second trench 602 formed after the etching of the first dielectric layer 201 will not have a regular morphology, but will have a bowl-like morphology similar to that of a horizontally placed bowl, as shown in FIG. 3B. Figure 15

[0115] S303: Form an insulating layer 43 at the bottom of the second trench 602 to cover the side surface of the first dielectric layer 201, as shown in FIG. 3C. Figure 18

[0116] In an embodiment, as shown in FIG. 3C, the step S303 includes: Figure 16

[0117] S3031: Form a continuously distributed insulating material layer 431 on the inner wall of the first trench 601 and the inner wall of the second trench 602, and the thickness of the insulating material layer 431 at the bottom of the second trench 602 is greater than the thickness of the insulating material layer 431 at the sidewall of the second trench 602, as shown in FIG. 3C. Figure 17

[0118] The material of the insulating material layer 431 can include aluminum oxide. The insulating material layer 431 can be formed by deposition process. Since the space at the bottom of the second trench 602 is narrow and the sidewall of the second trench 602 is relatively flat, the insulating material layer 431 will first close at the bottom of the second trench 602, so that the thickness of the insulating material layer 431 at the bottom of the second trench 602 is greater than the thickness of the insulating material layer 431 at the sidewall of the second trench 602. In addition, the aluminum oxide in the second trench 602 can have certain gaps during the deposition process.

[0119] S3032: Remove the insulating material layer 431 on the inner wall of the first trench 601 and the partial insulating material layer 431 on the sidewall of the second trench 602 to obtain the insulating layer 43 reserved at the bottom of the second trench 602, as shown in FIG. 3C. Figure 18

[0120] ​​​​​​In one embodiment, the step S3032 includes removing the insulating material layer 431 on the inner wall of the first groove 601 and the partial insulating material layer 431 on the sidewall of the second groove 602 by using a wet etching process.

[0121] During the removing process, since the insulating material layer 431 on the bottom of the second groove 602 is thicker, by controlling the etching time and other etching parameters, the insulating material layer 431 on the bottom of the second groove 602 can be ensured to have a certain residual, and the insulating layer 43 as shown in Figure 18 is formed. The insulating layer 43 is the insulating material layer 431 remaining on the bottom of the second groove 602. Figure 18 It can be seen that after the step S3032, the side surface of each layer of the first dielectric layer 201 will be covered by the insulating layer 43 (here, the insulating layer 43 is the insulating material layer 431 remaining on the bottom of the second groove 602), and the side surface of each layer of the conductive layer 203 will be exposed again.

[0122] In the step S40, please refer to the step S40 in Figure 1 and Figure 19-20 , the channel material layer 7011, the isolation layer 702 and the gate conductive layer 703 are sequentially deposited on the side surface of each layer of the conductive layer 203 and the surface of the insulating layer 43.

[0123] The channel material layer 7011, the isolation layer 702 and the gate conductive layer 703 can be sequentially deposited in the first groove 601 by using a deposition process, so as to form a structure as shown in Figure 19-20 .

[0124] The material of the channel material layer 7011 can include a metal oxide semiconductor, for example, Indium Gallium Zinc Oxide (IGZO). When the metal oxide semiconductor is IGZO, the leakage current of the transistor is small (less than or equal to 10-15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation. The material of the isolation layer 702 can include an HK dielectric material. The material of the gate conductive layer 703 can include Indium tin oxide (ITO) or indium oxide-zinc oxide-based oxide (IZO).

[0125] In step S50, please refer to Figure 1 and Figure 24 , remove each layer of the insulating layer 43 to expose each layer of the channel material layer 7011 corresponding to each layer of the first dielectric layer 201.

[0126] In one embodiment, as shown in Figure 21 , the above step S50 includes:

[0127] S501: Form a third trench 603 penetrating the third dielectric layer between adjacent channel regions, so that the sidewall of the third trench 603 exposes the surface of each layer of the insulating layer 43, as shown in Figure 22 .

[0128] In one embodiment, the insulating layer 43 includes an aluminum oxide layer, and the above step S501 includes: Figure 23

[0129] S5011: Form a third trench 603 penetrating the third dielectric layer between adjacent channel regions by using a dry etching process. At this time, the inner sidewall of the third trench 603 can be a continuous distribution of the third dielectric layer, and the aluminum oxide layer has not been exposed.

[0130] ​S5012: etching and removing part of the third dielectric layer on the inner wall of the third trench 603 by using an acid solution to expose the surface of each layer of aluminum oxide.

[0131] A small amount of acid solution is used to remove part of the third dielectric layer to ensure that the surface of each layer of aluminum oxide is exposed. At this time, the position of the exposed each layer of aluminum oxide in the third trench 603 corresponds to the position of each layer of the first dielectric layer 201.

[0132] S502: removing each layer of insulating layer 43 based on the third trench 603 to expose each layer of channel material layer 7011 corresponding to each layer of the first dielectric layer 201, as shown in Figure 24 .

[0133] In one embodiment, the channel material layer 7011 includes an aluminum oxide layer, and the step S502 includes: etching and removing each layer of aluminum oxide based on the third trench 603 by using an alkaline solution.

[0134] In step S60, please refer to step S60 in Figure 1 and Figure 25 , removing the exposed each layer of channel material layer 7011 to obtain the channel layer 701 on the side of each layer of conductive layer 203.

[0135] After removing each layer of insulating layer 43, the corresponding each layer of channel material layer 7011 of each layer of conductive layer 203 will not be exposed, and each layer of channel material layer 7011 covering the side of each layer of the first dielectric layer 201 will be completely exposed. At this time, using etching process to remove the channel material layer 7011 can increase the etching contact area of the channel material layer 7011, so as to quickly remove the channel material layer 7011 corresponding to each layer of the first dielectric layer 201 to quickly remove the parasitic transistor. The channel layer 701 on the side of each layer of conductive layer 203 can be preserved without being damaged, as shown in Figure 25 .

[0136] In some embodiments, after the above step S502, the method further comprises: filling the third trench 603 with a fourth filling layer.

[0137] The application also provides a semiconductor structure, as shown in Figure 25As shown, the semiconductor structure comprises: a substrate 1; a stack structure 21 located above the substrate 1, the stack structure 21 comprising first dielectric layers 201 and conductive layers 203 stacked in sequence from bottom to top, each conductive layer 203 comprising: a main body portion 2031 extending along a first direction, and a plurality of extension portions 2032 arranged at intervals along the first direction, each extension portion 2032 being located on opposite sides of the main body portion 2031, the main body portion 2031 being integrally connected with each extension portion 2032, and an end portion of the extension portion 2032 connected with the main body portion 2031 serving as a channel region; a gate conductive layer 703 extending along a direction perpendicular to the substrate 1 and penetrating each channel region; an isolation layer 702 surrounding a sidewall of the gate conductive layer 703; and a plurality of channel layers 701 surrounding sidewalls of the isolation layer 702 and arranged at intervals along a direction perpendicular to the substrate 1, each channel layer 701 being in one-to-one correspondence with each conductive layer 203.

[0138] The material of the substrate 1 can be any suitable substrate material known in the art, for example, can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, also including a multilayer structure composed of these semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-silicon-insulator (SSOI), silicon-germanium-on-silicon-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or can also be double-side polished wafers (DSP), can also be a ceramic substrate such as aluminum oxide, a quartz or glass substrate, etc., and the present embodiment is not limited thereto.

[0139] The first dielectric layer 201 can include an oxide material or a nitride material, for example, silicon oxide or silicon nitride. The material of the conductive layer 203 can include a metal material, for example, tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other suitable metals. The material of the channel material layer 7011 can include a metal oxide semiconductor, for example, indium gallium zinc oxide (IGZO). When the metal oxide semiconductor is IGZO, the leakage current of the transistor is small (less than or equal to 10-15 A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, and other materials, as long as the leakage current of the transistor meets the requirements, which can be adjusted according to actual conditions. The material of the isolation layer 702 can include an HK dielectric material. The material of the gate conductive layer 703 can include ITO or IZO.

[0140] Since each layer of the conductive layer 203 in the semiconductor structure does not expose the corresponding channel material layer 7011, and each layer of the channel material layer 7011 covering the side surface of the first dielectric layer 201 will be completely exposed, the etching process is used to remove the channel material layer 7011, which can increase the etching contact area of the channel material layer 7011, thereby quickly removing the channel material layer 7011 corresponding to each layer of the first dielectric layer 201 to quickly remove the parasitic transistor. The channel layer 701 on the side surface of each layer of the conductive layer 203 can be not damaged and retained, thereby ensuring the normal read and write work of the device and reducing the leakage current.

[0141] The semiconductor structure comprises: a substrate 1; a stack structure 21 located above the substrate 1, the stack structure 21 comprising first dielectric layers 201 and conductive layers 203 stacked in sequence from bottom to top, each conductive layer 203 comprising: a main body part 2031 extending in a first direction, and a plurality of extension parts 2032 arranged at intervals in the first direction, each extension part 2032 being located on opposite sides of the main body part 2031, the main body part 2031 being integrally connected with each extension part 2032, and an end part of the extension part 2032 connected with the main body part 2031 serving as a channel region; a gate conductive layer 703 penetrating each channel region and extending in a direction perpendicular to the substrate 1; an isolation layer 702 surrounding a side wall of the gate conductive layer 703; and a plurality of channel layers 701 surrounding side walls of the isolation layer 702 and arranged at intervals in a direction perpendicular to the substrate 1, each channel layer 701 being in one-to-one correspondence with each conductive layer 203. Since the corresponding channel material layer 7011 of each first dielectric layer 201 can be quickly removed to quickly remove a parasitic transistor, and the channel layer 701 on the side of each conductive layer 203 can be preserved without being damaged, the normal read and write work of the device can be ensured, and the leakage current can be reduced.

[0142] In one embodiment, as shown in Figure 25 the semiconductor structure further comprises a capacitor, the capacitor comprising a first electrode, and a capacitor dielectric layer 501 and a second electrode 502 covering a surface of the first electrode in sequence, and a part of the extension part 2032 away from the main body part 2031 serving as the first electrode of the capacitor.

[0143] The material of the first electrode can comprise a metal material, such as copper, gold, titanium, silver, aluminum, tungsten, etc. The material of the capacitor dielectric layer 501 can comprise an HK dielectric material. The material of the second electrode 502 can comprise a conductive material, and the second electrode 502 can further comprise a conductive barrier layer and an electrode conductive layer 203, wherein the conductive barrier layer can comprise titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof; and the material of the electrode conductive layer 203 can comprise polysilicon.

[0144] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above embodiments are described, but as long as the combinations of the technical features do not contradict, they should be considered as within the scope of the present disclosure.

[0145] The above embodiments only express several implementation manners of the present application, the description is more specific and detailed, but cannot be understood as the limitation of the patent application scope. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application patent should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate; forming a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive layers stacked in turn from bottom to top; forming insulating layers corresponding to the side surfaces of each of the first dielectric layers; depositing channel material layers, isolation layers and gate conductive layers in turn on the side surfaces of each of the conductive layers and the surfaces of the insulating layers; removing each of the insulating layers to expose each of the channel material layers corresponding to each of the first dielectric layers; removing the exposed channel material layers to obtain channel layers located on the side surfaces of each of the conductive layers.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Each of the conductive layers comprises a main body portion extending along a first direction and a plurality of extension portions arranged at intervals along the first direction, each of the extension portions being located on the opposite sides of the main body portion, the main body portion being integrally connected with each of the extension portions, the end portion of the extension portion connected with the main body portion serving as a channel region, and the forming of the insulating layers corresponding to the side surfaces of each of the dielectric layers comprises the following steps: etching to form first grooves penetrating through each of the channel regions, the side walls of the first grooves exposing the side surfaces of the first dielectric layers and the side surfaces of the conductive layers stacked in turn and alternately; based on the first grooves, performing lateral etching on each of the first dielectric layers to form second grooves between each of the conductive layers, the bottom size of the second grooves being smaller than the opening size of the second grooves; forming insulating layers on the bottoms of each of the second grooves so that each of the insulating layers covers the side surfaces of each of the first dielectric layers.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The forming of the insulating layers on the bottoms of each of the second grooves so that each of the insulating layers covers the side surfaces of each of the first dielectric layers comprises the following steps: forming a continuously distributed insulating material layer on the inner walls of the first grooves and the inner walls of the second grooves, wherein the thickness of the insulating material layer located at the bottom of the second groove is greater than the thickness of the insulating material layer located at the side wall of the second groove; removing the insulating material layer located on the inner walls of the first grooves and part of the insulating material layer located on the side walls of the second grooves to obtain the insulating layer reserved at the bottom of the second groove.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The removing of the insulating material layer located on the inner walls of the first grooves and part of the insulating material layer located on the side walls of the second grooves comprises the following steps: adopting a wet etching process to remove the insulating material layer located on the inner walls of the first grooves and part of the insulating material layer located on the side walls of the second grooves.

5. The method of producing a semiconductor structure according to any one of claims 2 to 4, wherein After forming the stack structure on the substrate and before forming the insulating layers corresponding to the side surfaces of each of the first dielectric layers, the method further comprises the following steps: depositing a third dielectric layer, the third dielectric layer filling the gaps of the stack structure.

6. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: The part of the extension portion away from the main body portion serves as a first electrode, and after depositing the third dielectric layer, the method further comprises the following steps: removing a sacrificial layer located on the surface of the first electrode to expose the surface of the first electrode; forming a capacitor dielectric layer and a second electrode in turn on the exposed surface of the first electrode.

7. The method of claim 5, wherein the step of forming the semiconductor structure is performed by a method comprising: The removing of each of the insulating layers to expose each of the channel material layers corresponding to each of the first dielectric layers comprises the following steps: forming a third trench through the third dielectric layer between adjacent channel regions, so that sidewalls of the third trench expose surfaces of the insulating layers; removing the insulating layers based on the third trench to expose the channel material layers corresponding to the first dielectric layers.

8. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: The insulating layers are aluminum oxide layers.

9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The forming a third trench through the third dielectric layer between adjacent channel regions, so that sidewalls of the third trench expose surfaces of the insulating layers, comprises: forming a third trench through the third dielectric layer between adjacent channel regions by using a dry etching process; removing part of the third dielectric layer on the inner wall of the third trench by using an acid solution etching to expose surfaces of the aluminum oxide layers.

10. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The removing the insulating layers based on the third trench comprises: removing the aluminum oxide layers based on the third trench by using an alkaline solution etching.

11. The method of claim 7, wherein the semiconductor structure is prepared by a method comprising: After the removing the exposed channel material layers to obtain channel layers located on the sides of the conductive layers, the method further comprises: filling the third trench by using a fourth filling layer.

12. A semiconductor structure, characterized by Comprises: a substrate; a stack structure located on the substrate, the stack structure comprising first dielectric layers and conductive layers stacked in order from bottom to top, each of the conductive layers comprising a main body part extending along a first direction and a plurality of extension parts arranged at intervals along the first direction, each of the extension parts being located on opposite sides of the main body part, the main body part and each of the extension parts being integrally connected, and the end part of the extension part connected to the main body part serving as a channel region; a gate conductive layer extending through each of the channel regions in a direction perpendicular to the substrate; an isolation layer surrounding the sidewalls of the gate conductive layer; a plurality of channel layers surrounding the sidewalls of the isolation layer and arranged at intervals along a direction perpendicular to the substrate, each of the channel layers being in one-to-one contact with each of the conductive layers.

13. The semiconductor structure of claim 12, wherein, The semiconductor structure further comprises a capacitor, the capacitor comprising a first electrode and a second electrode covering the surface of the first electrode in order, and the part of the extension part away from the main body part serving as the first electrode of the capacitor.

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