Magnetoresistive random access memory structure and manufacturing method thereof

Abstract

The invention discloses a magnetoresistive random access memory structure and a manufacturing method thereof, the magnetoresistive random access memory structure comprises a first memory unit and a second memory unit, a conductive line is arranged between the first memory unit and the second memory unit, and the conductive line is arranged between the first memory unit and the second memory unit. An SOT metal conductive line contacts and electrically connects an end of the first memory cell, an end of the conductive line, and an end of the second memory cell, a first switching element electrically connected to an end of the SOT metal conductive line, a second switching element electrically connected to another end of the SOT metal conductive line, and a third switching element electrically connected to another end of the second memory cell. A third switching element is electrically connected to the other end of the first memory cell, a fourth switching element is electrically connected to the other end of the conductive line, and a fifth switching element is electrically connected to the other end of the second memory cell.

Description

Technical Field

[0001] The present invention relates to a magnetoresistive random access memory structure, and in particular to a memory structure that utilizes a spin-orbit torque (SOT) conductive line to electrically connect a plurality of magnetoresistive random access memory units at the same time. Background Art

[0002] Magnetic random access memory provides performance comparable to volatile static random access memory, and density comparable to volatile dynamic random access memory and has low power consumption. Compared with flash memory, magnetic random access memory provides faster access time and minimal degradation over time. There are two types of magnetic random access memory. One type is spin transfer torque (STT) magnetic random access memory. STT magnetic random access memory operates by passing current vertically through a magnetic tunneling junction (MTJ). The other type of magnetic random access memory is spin orbit torque (SOT) magnetic random access memory, which changes the direction of the magnetic moment by changing the spin direction of the electrons in the free layer with current, thereby achieving the purpose of writing or erasing. Summary of the invention

[0003] According to a preferred embodiment of the present invention, a magnetoresistive random access memory structure includes a first memory cell, wherein the first memory cell includes a first magnetic tunnel junction, a second memory cell, wherein the second memory cell includes a second magnetic tunnel junction, a conductive wire is arranged between the first memory cell and the second memory cell, a spin-orbit torque (SOT) metal conductive wire is arranged above the first memory cell, the conductive wire and the second memory cell, wherein the SOT metal conductive wire contacts and electrically connects one end of the first memory cell, one end of the conductive wire and one end of the second memory cell, a first switching element electrically connected to one end of the SOT metal conductive wire, a second switching element electrically connected to another end of the SOT metal conductive wire, a third switching element electrically connected to another end of the first memory cell, a fourth switching element electrically connected to another end of the conductive wire and a fifth switching element electrically connected to another end of the second memory cell.

[0004] According to another preferred embodiment of the present invention, a method for manufacturing a magnetoresistive random access memory structure includes providing a lower electrode material layer, a reference material layer, a barrier material layer, a free material layer and a SOT metal layer stacked from bottom to top, etching the SOT metal layer, the free material layer, the barrier material layer, the reference material layer and the lower electrode material layer to form a first memory cell and a second memory cell, then forming a conductive line arranged between the first memory cell and the second memory cell, successively forming a spin-orbit moment SOT metal conductive line contacting and electrically connecting one end of the first memory cell, one end of the conductive line and one end of the second memory cell, then forming a first switching element electrically connecting one end of the SOT metal conductive line, and finally forming a second switching element electrically connecting another end of the SOT metal conductive line.

[0005] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 5 A schematic diagram of a magnetoresistive random access memory structure depicted in a preferred embodiment of the present invention;

[0007] Figures 6 to 8 is a schematic diagram of the operation mode of writing the magnetoresistive random access memory structure of the present invention;

[0008] Figures 9 and 10 It is a schematic diagram of the read / write operation mode of the magnetoresistive random access memory structure of the present invention.

[0009] Main component symbols

[0010] 10: Material layer

[0011] 12a: Metal interconnects

[0012] 12b: Metal interconnect

[0013] 12c: Metal interconnects

[0014] 12d: Metal interconnect

[0015] 12e: Metal interconnects

[0016] 12f: Metal interconnect

[0017] 12g: Metal inner connection

[0018] 14: Lower electrode material layer

[0019] 14a: first lower electrode

[0020] 14b: Second lower electrode

[0021] 14c: third lower electrode

[0022] 16: Reference material layer

[0023] 16a: First reference layer

[0024] 16b: Second reference layer

[0025] 16c: Third reference layer

[0026] 18: Barrier material layer

[0027] 18a: First barrier layer

[0028] 18b: Second barrier layer

[0029] 18c: Third barrier layer

[0030] 20: Free material layer

[0031] 20a: First free layer

[0032] 20b: Second free layer

[0033] 20c: The third free layer

[0034] 22: SOT metal layer

[0035] 22a: First SOT metal layer

[0036] 22b: Second SOT metal layer

[0037] 22c: Third SOT metal layer

[0038] 24: Etch stop layer

[0039] 26: Dielectric layer

[0040] 28a: Conductive thread

[0041] 28b: Conductive thread

[0042] 28c: Conductive thread

[0043] 28d: Conductive thread

[0044] 28e: Conductive thread

[0045] 28f: Conductive thread

[0046] 28g: Conductive thread

[0047] 28h: Conductive thread

[0048] 30: SOT metal conductive wire

[0049] 32: Stop layer

[0050] 34: Dielectric layer

[0051] 100: Magnetoresistive random access memory structure

[0052] C1: copper conductor

[0053] C2: Copper conductor

[0054] C3: Copper conductor

[0055] C4: Copper conductor

[0056] C5: Copper conductor

[0057] C6: Copper conductor

[0058] C7: Copper conductor

[0059] I1: Current

[0060] I2: Current

[0061] I3: Current

[0062] I4: Current

[0063] I5: Current

[0064] L: Logic circuit area

[0065] M: Memory area

[0066] MTJ1: First Magnetic Tunnel Junction

[0067] MTJ2: Second Magnetic Tunnel Junction

[0068] MTJ3: Third Magnetic Tunnel Junction

[0069] T1: First switch element

[0070] T2: Second switch element

[0071] T3: The third switching element

[0072] T4: the fourth switching element

[0073] T5: The fifth switching element

[0074] T6: Sixth switch element

[0075] T7: Seventh switching element

[0076] U1: First memory unit

[0077] U2: Second memory unit

[0078] U3: The third memory unit

[0079] W1: Tungsten plug

[0080] W2: Tungsten plug

[0081] W3: Tungsten plug DETAILED DESCRIPTION

[0082] Figures 1 to 5 A magnetoresistive random access memory structure is shown according to a preferred embodiment of the present invention.

[0083] like Figure 1As shown, a material layer 10 is provided, and the material layer is divided into a memory area M and a logic circuit area L. The material layer 10 is formed by stacking a semiconductor substrate and a dielectric layer. The semiconductor substrate includes a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate or a silicon-covered insulating substrate, and the dielectric layer includes insulating materials such as silicon oxide, silicon nitride or silicon oxynitride. A third switch element T3, a fourth switch element T4, a fifth switch element T5, a sixth switch element T6 and a seventh switch element T7 are arranged in the memory area M of the material layer 10. One terminal of each of the third switch element T3, the fifth switch element T5 and the seventh switch element T7 is respectively in contact with and electrically connected to the metal inner connection 12a / 12b / 12c, and one terminal of each of the fourth switch element T4 and the sixth switch element T6 is respectively in contact with and electrically connected to the metal inner connection 12d / 12e. The metal interconnects 12a / 12b / 12c include copper conductors C1 / C2 / C3 and tungsten plugs W1 / W2 / W3 on the copper conductors C1 / C2 / C3. The metal interconnects 12d / 12e only include copper conductors C4 / C5. The metal interconnects 12f / 12g are in the logic circuit area L. The metal interconnects 12f / 12g only include copper conductors C6 / C7. The metal interconnects 12a / 12b / 12c12d / 12e are in the memory area M. The above-mentioned copper conductors C1 / C2 / C3 C4 / C5 C6 / C7 all belong to the same metal layer and are located below the tungsten plugs W1 / W2 / W3. The upper surface of the tungsten plug W1 / W2 / W3 is exposed by the material layer 10, and then a lower electrode material layer 14, a reference material layer 16, a barrier material layer 18, a free material layer 20 and a spin-orbit torque (SOT) metal layer 22 are stacked from bottom to top on the material layer 10, and the lower electrode material layer 14 directly contacts the tungsten plug W1 / W2 / W3. The SOT metal layer 20 includes ruthenium, tungsten, tantalum, iridium, platinum, hafnium, beryllium copper alloy, iridium copper alloy or gold tungsten alloy, and the material of the SOT metal layer 22 has high spin-orbit coupling strength and high resistivity, for example, a resistivity of about 150μΩ-cm to about 250μΩ-cm.

[0084] Please also see Figure 1 and Figure 2, the SOT metal layer 22, the free material layer 20, the barrier material layer 18, the reference material layer 16 and the lower electrode material layer 14 are etched to form a plurality of memory cells, such as a first memory cell U1, a second memory cell U2 and a third memory cell U3, on the material layer 10 of the memory area M, and the SOT metal layer 22, the free material layer 20, the barrier material layer 18, the reference material layer 16 and the lower electrode material layer 14 in the logic circuit area L are completely removed. Since the SOT metal layer 22 is above the free material layer 20, the free material layer 20 will not be damaged by etching during etching. The first memory unit U1 includes a first lower electrode 14a, a first magnetic tunnel junction MTJ1 and a first SOT metal layer 22a stacked from bottom to top, the second memory unit U2 includes a second lower electrode 14b, a second magnetic tunnel junction MTJ2 and a second SOT metal layer 22b stacked from bottom to top, and the third memory unit U3 includes a third lower electrode 14c, a third magnetic tunnel junction MTJ3 and a third SOT metal layer 22c stacked from bottom to top. Then, an etching stop layer 24 is formed to conformably cover the first memory unit U1, a second memory unit U2 and a third memory unit U3 and the material layer 10.

[0085] like Figure 3 As shown, a dielectric layer 26 is formed to cover the first memory unit U1 , a second memory unit U2 , a third memory unit U3 and the logic circuit region L, and the dielectric layer 26 is planarized using the etching stop layer 24 as a stop layer.

[0086] like Figure 4 As shown, four conductive wires 28a / 28b / 28c / 28d are formed by the same manufacturing process. The conductive wires 28a / 28b are respectively arranged between the first memory unit U1 and the second memory unit U2 and between the second memory unit U2 and the third memory unit U3, and contact the metal interconnects 12d / 12e. The conductive wires 28c / 28d are located in the logic circuit area L and contact the metal interconnects 12f / 12g. The conductive wires 28a / 28b / 28c / 28d are preferably a copper dual damascene structure. After the manufacturing process of the conductive wires 28a / 28b / 28c / 28d is completed, the upper surface of the conductive wires 28a / 28b / 28c / 28d, one end of the first memory unit U1, one end of the second memory unit U2 and one end of the third memory unit U3 are all exposed from the dielectric layer 26.

[0087] Please continue to refer to Figure 4, forming a spin-orbit torque (SOT) metal conductive line 30 in the memory area M and the logic circuit area L, the SOT metal conductive line 30 contacts and electrically connects one end of the first memory unit U1, one end of the second memory unit U2, one end of the third memory unit U3 and one end of each of the conductive lines 28a / 28b / 28c / 28d. The SOT metal conductive line 30 includes ruthenium, tungsten, tantalum, iridium, platinum, hafnium, beryllium copper alloy, iridium copper alloy or gold tungsten alloy.

[0088] like Figure 5 As shown, the SOT metal conductive line 30 located in the logic circuit area L is removed, and then a stop layer 32 is formed to conformably cover the SOT metal conductive line 30 and the dielectric layer 26, and then a dielectric layer 34 is formed to cover the stop layer 32, and then the same step is used to form conductive lines 28e / 28f / 28g / 28h to penetrate the dielectric layer 34 and the stop layer 32, and the conductive lines 28e / 28f are directly in contact with the two ends of the SOT metal conductive line 30, and the conductive lines 28g / 28h are directly in contact with the conductive lines 28c / 28d. A first switch element T1 and a second switch element T2 are subsequently formed, and one end of the first switch element T1 contacts the conductive line 28e, and one end of the second switch element T2 contacts the conductive line 28f. At this point, the magnetoresistive random access memory structure 100 of the present invention has been completed.

[0089] The total number of switch elements mentioned above will vary with the number of memory cells, and the number of memory cells can be adjusted according to demand. For example, if the number of memory cells is M, the total number of switch elements is 2×M+1, where M is a positive integer and is not less than 1. The conductive lines 28a / 28b / 28c / 28d / 28e / 28f / 28g / 28h are preferably made of copper, aluminum or tungsten, and the first switch element T1, the second switch element T2, the third switch element T3, the fourth switch element T4, the fifth switch element T5, the sixth switch element T6 and the seventh switch element T7 are preferably metal oxide semiconductor transistors.

[0090] like Figure 5As shown, a magnetoresistive random access memory structure 100 of the present invention includes a first memory unit U1, a second memory unit U2 and a third memory unit U3, wherein the first memory unit U1 includes a first lower electrode 14a, a first magnetic tunnel junction MTJ1 and a first SOT metal layer 22a stacked from bottom to top, the second memory unit U2 includes a second lower electrode 14b, a second magnetic tunnel junction MTJ2 and a second SOT metal layer 22b stacked from bottom to top, and the third memory unit U3 It includes a third lower electrode 14c, a third magnetic tunnel junction MTJ3 and a third SOT metal layer 22c stacked from bottom to top, the width of the first lower electrode 14a, the width of the first magnetic tunnel junction MTJ1 and the width of the first SOT metal layer 22a are the same, the width of the second lower electrode 14b, the width of the second magnetic tunnel junction MTJ2 and the width of the second SOT metal layer 22b are the same, and the width of the third lower electrode 14c, the width of the third magnetic tunnel junction MTJ3 and the width of the third SOT metal layer 22c are the same.

[0091] Conductive wire 28a is arranged between first memory cell U1 and second memory cell U2, conductive wire 28b is arranged between second memory cell U2 and third memory cell U3, and a spin-orbit torque (SOT) metal conductive wire 30 is arranged above first memory cell U1, second memory cell U2, third memory cell U3 and conductive wire 28a / 28b, wherein SOT metal conductive wire 30 contacts and electrically connects one end of first memory cell U1, one end of second memory cell U2, one end of third memory cell U3 and one end of conductive wire 28a and one end of conductive wire 28b. It is worth noting that the SOT metal in the present invention is arranged in two positions respectively, one is in first memory cell U1, second memory cell U2 and third memory cell U3, namely, first SOT metal layer 22a, second SOT metal layer 22b and third SOT metal layer 22c, and the other is SOT metal conductive wire 30. The reason for such design is as mentioned above. Figure 2 As described in the manufacturing process, when etching the free material layer 20, the barrier material layer 18, the reference material layer 16 and the lower electrode material layer 14, in order to prevent the etchant from damaging the surface of the free material layer 20, a SOT material layer 22 is formed on the free material layer 20 as protection.

[0092] Please continue to read Figure 5A first switch element T1 is electrically connected to one end of the SOT metal conductive line 30 through a conductive line 28e, a second switch element T2 is electrically connected to another end of the SOT metal conductive line 30 through a conductive line 28f, a third switch element T3 is electrically connected to one end of the first memory unit U1, a fourth switch element T4 is electrically connected to one end of the conductive line 28a, a fifth switch element T5 is electrically connected to one end of the second memory unit U2, a sixth switch element T6 is electrically connected to one end of the conductive line 28b, and a seventh switch element T7 is electrically connected to one end of the third memory unit U3.

[0093] The first magnetic tunnel junction MTJ1 includes a first reference layer 16a, a first barrier layer 18a and a first free layer 20a stacked from bottom to top, the second magnetic tunnel junction MTJ2 includes a second reference layer 16b, a second barrier layer 18b and a second free layer 20b stacked from bottom to top, and the third magnetic tunnel junction MTJ3 includes a third reference layer 16c, a third barrier layer 18c and a third free layer 20c stacked from bottom to top. The first SOT metal layer 22a directly contacts the first free layer 20a, the second SOT metal layer 22b directly contacts the second free layer 20b, and the third SOT metal layer 22c directly contacts the third free layer 20c.

[0094] The first SOT metal layer 22a, the second SOT metal layer 22b, and the third SOT metal layer 22b each contain ruthenium, tungsten, tantalum, iridium, platinum, hafnium, beryllium copper alloy, iridium copper alloy, or gold tungsten alloy. The SOT metal conductive line 30 contains ruthenium, tungsten, tantalum, iridium, platinum, hafnium, beryllium copper alloy, iridium copper alloy, or gold tungsten alloy. The material of the SOT metal layer 22a / 22b / 22b and the SOT metal conductive line 30 has a high spin-orbit coupling strength and a high resistivity, for example, a resistivity of about 150 μΩ-cm to about 250 μΩ-cm.

[0095] The first lower electrode 14a, the second lower electrode 14b and the third lower electrode 14c each include a conductive material such as ruthenium, tantalum, nickel-chromium alloy, etc., the first reference layer 16a, the second reference layer 16c and the third reference layer 16c each include nickel, iron, cobalt, germanium, boron or manganese and alloys thereof, the first barrier layer 18a, the second barrier layer 18b and the third barrier layer 18c each include magnesium oxide or hafnium oxide, the first free layer 20a, the second free layer 20b and the third free layer 20c each include nickel, iron, cobalt, germanium, boron or manganese and alloys thereof,

[0096] Figures 6 to 8 The illustrated example is a write operation method of the magnetoresistive random access memory structure of the present invention. Each memory cell in the magnetoresistive random access memory structure of the present invention can be written separately or simultaneously.

[0097] like Figure 6As shown, this embodiment demonstrates the single writing of the first memory cell U1, and the writing method includes turning on the first switch element T1 and the fourth switch element T4 at the same time to write the first memory cell U1, and turning off the second switch element T2, the third switch element T3, the fifth switch element T5, the sixth switch element T6 and the seventh switch element T7. At this time, the current I1 will flow between the first switch element T1, the conductive line 28e, the SOT metal conductive line 30, the conductive line 28a, the metal inner connection 12d and the fourth switch element T4. Since the current I1 passes through the first SOT metal layer 22a above the first free layer 20a, the magnetic moment direction of the first free layer 20a will change, so that the operation of writing the first memory cell U1 can be completed. Since the current I passes through the magnetic moment direction of the first free layer 20a in parallel, it is called SOT writing.

[0098] like Figure 7 As shown, this embodiment demonstrates that the first memory cell U1 and the second memory cell U2 are written at the same time, but the third memory cell U3 is not written. The writing method includes turning on the first switch element T and the sixth switch element T6 at the same time to write the first memory cell U1 and the second memory cell U2, and turning off the second switch element T2, the third switch element T3, the fourth switch element T4, the fifth switch element T5 and the seventh switch element T7. At this time, the current I2 will flow between the first switch element T1, the conductive line 28e, the SOT metal conductive line 30, the conductive line 28b, the metal inner connection 12e and the sixth switch element T6. In this operation, the magnetic moment directions of the first free layer 20a and the second free layer 20b will change, so that the operation of writing the first memory cell U1 and the second memory cell U2 can be completed. and Figure 6 Similarly, the current I2 of this embodiment also passes through the first free layer 20 a and the second free layer 20 b in parallel, and thus is also SOT writing.

[0099] like Figure 8 As shown, this embodiment demonstrates writing into the first memory cell U1, the second memory cell U2 and the third memory cell U3 at the same time. The writing method includes turning on the first switch element T1 and the second switch element T2 at the same time, and turning off the third switch element T3, the fourth switch element T4, the fifth switch element T5, the sixth switch element T6 and the seventh switch element T7. At this time, the current I3 will flow between the first switch element T1, the conductive wire 28e, the SOT metal conductive wire 30, the conductive wire 28f and the second switch element T2. In this operation, the magnetic moment directions of the first free layer 20a, the second free layer 20b and the third free layer 20c will change, so that the operation of writing into the first memory cell U1, the second memory cell U2 and the third memory cell U3 can be completed. and Figure 7Similarly, the current I3 of this embodiment also passes through the first free layer 20a, the second free layer 20b and the third free layer 20c in parallel, and thus is also SOT writing.

[0100] like Fig. 9 As shown, this embodiment demonstrates the single reading or single writing of the first memory cell U1. The reading or writing method includes simultaneously turning on the first switch element T1 and the third switch element T3 to read or write the first memory cell U1, and turning off the second switch element T2, the fourth switch element T4, the fifth switch element T5, the sixth switch element T6 and the seventh switch element T7. At this time, the current I4 will flow between the first switch element T1, the conductive line 28e, the SOT metal conductive line 30, the first memory cell U1, the metal inner connection 12a and the third switch element T3. Since the current I4 passes perpendicularly through the magnetic moment direction of the first free layer 20a, it is called STT (Spin-Torque Transfer) reading or STT writing.

[0101] like Fig.10 As shown, this embodiment demonstrates the single reading or single writing of the second memory cell U2. The reading or writing method includes simultaneously turning on the first switch element T1 and the fifth switch element T5 to read or write the second memory cell U2, and turning off the second switch element T2, the third switch element T3, the fourth switch element T4, the sixth switch element T6 and the seventh switch element T7. At this time, the current I5 flows between the first switch element T1, the conductive line 28e, the SOT metal conductive line 30, the second memory cell U2, the metal inner connection 12b and the fifth switch element T5, and Fig. 9 Similarly, the current in this embodiment passes through the magnetic moment direction of the second free layer 20 b perpendicularly, so it is called STT (Spin-Torque Transfer) reading or STT writing.

[0102] The present invention additionally sets conductive lines 28a / 28b between memory cells, so that a single memory cell can be written using SOT writing, or several memory cells can be written using SOT writing at the same time, thereby increasing the variability of the memory cell in the way of storing bits.

[0103] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A magnetoresistive random access memory structure, comprising: a first memory cell, wherein the first memory cell comprises a first magnetic tunneling junction; a second memory cell, wherein the second memory cell comprises a second magnetic tunneling junction; A conductive line disposed between the first memory cell and the second memory cell; A spin-orbit moment metal conductive line is disposed above the first memory cell, the conductive line and the second memory cell, wherein the spin-orbit moment metal conductive line contacts and electrically connects an end of the first memory cell, an end of the conductive line and an end of the second memory cell; A first switch element electrically connected to an end of the spin-orbit moment metal conductive line; A second switch element electrically connected to the other end of the spin-orbit moment metal conductive line; a third switch element, electrically connected to the other end of the first memory cell; a fourth switch element, electrically connected to the other end of the conductive line; and The fifth switch element is electrically connected to the other end of the second memory unit.

2. The magnetoresistive random access memory structure as claimed in claim 1, wherein the first magnetic tunnel junction comprises a first reference layer, a first barrier layer and a first free layer stacked from bottom to top, and the second magnetic tunnel junction comprises a second reference layer, a second barrier layer and a second free layer stacked from bottom to top.

3. The magnetoresistive random access memory structure as claimed in claim 2, wherein the first memory unit further comprises: The first spin-orbit moment metal layer is disposed on the first magnetic tunnel junction, wherein the first spin-orbit moment metal layer contacts the first magnetic tunnel junction, and the width of the first spin-orbit moment metal layer is the same as the width of the first magnetic tunnel junction. 4 . The magnetoresistive random access memory structure as claimed in claim 3 , wherein the first free layer contacts the first spin-track moment metal layer.

5. The magnetoresistive random access memory structure of claim 3, wherein the first spin-orbit moment metal layer comprises ruthenium (Ru), tungsten (W), tantalum (Ta), iridium (Ir), platinum (Pt), hafnium (Hf), beryllium copper alloy (CuBe), iridium copper alloy (CuIr) or gold tungsten alloy (AuW).

6. The magnetoresistive random access memory structure as claimed in claim 2, wherein the second memory unit further comprises: The second spin-orbit moment metal layer is disposed on the second magnetic tunnel junction, wherein the second spin-orbit moment metal layer contacts the second magnetic tunnel junction, and the width of the second spin-orbit moment metal layer is the same as the width of the second magnetic tunnel junction. 7 . The magnetoresistive random access memory structure as claimed in claim 6 , wherein the second free layer contacts the second spin-orbit moment metal layer.

8. The magnetoresistive random access memory structure of claim 6, wherein the second spin-orbit moment metal layer comprises ruthenium (Ru), tungsten (W), tantalum (Ta), iridium (Ir), platinum (Pt), hafnium (Hf), beryllium copper alloy (CuBe), iridium copper alloy (CuIr) or gold tungsten alloy (AuW).

9. The magnetoresistive random access memory structure of claim 1, wherein the spin-orbit moment metal conductive line comprises ruthenium (Ru), tungsten (W), tantalum (Ta), iridium (Ir), platinum (Pt), hafnium (Hf), beryllium copper alloy (CuBe), iridium copper alloy (CuIr) or gold tungsten alloy (AuW).

10. The magnetoresistive random access memory structure of claim 1, comprising a writing method using one of the following: Turning on the first switch element and the fourth switch element simultaneously to write into the first memory cell; Turning on the first switch element and the second switch element simultaneously to write into the first memory cell and the second memory cell simultaneously; Turning on the first switch element and the third switch element simultaneously to write into the first memory cell; as well as The first switch element and the fifth switch element are turned on simultaneously to write into the second memory cell.

11. The magnetoresistive random access memory structure of claim 1, comprising a reading method using one of the following: Turning on the first switch element and the third switch element simultaneously to read the first memory cell; and The first switch element and the fifth switch element are turned on simultaneously to read the second memory cell.

12. The magnetoresistive random access memory structure as claimed in claim 1, wherein an upper surface of the first memory cell is aligned with an upper surface of the spin-orbit moment metal conductive line, and an upper surface of the second memory cell is aligned with an upper surface of the spin-orbit moment metal conductive line.

13. A method for manufacturing a magnetoresistive random access memory structure, comprising: Providing a lower electrode material layer, a reference material layer, a barrier material layer, a free material layer and a spin-orbit moment metal layer stacked from bottom to top; Etching the spin-orbit moment metal layer, the free material layer, the barrier material layer, the reference material layer and the lower electrode material layer to form a first memory cell and a second memory cell; forming a conductive line disposed between the first memory cell and the second memory cell; forming a spin-orbit moment metal conductive line contact and electrically connecting an end of the first memory cell, an end of the conductive line, and an end of the second memory cell; Form a first switch element electrically connected to an end of the spin-orbit moment metal conductive line; as well as A second switch element is formed to electrically connect the other end of the spin-orbit torque metal conductive line.

14. The method for manufacturing a magnetoresistive random access memory structure as claimed in claim 13, wherein when forming the conductive line, a dual damascene copper conductive line is simultaneously formed in the logic element region.

15. The method for manufacturing a magnetoresistive random access memory structure according to claim 13, further comprising: Before forming the first memory cell and the second memory cell, a third switching element, a fourth switching element and a fifth switching element are formed, wherein the third switching element is electrically connected to the other end of the first memory cell, the fourth switching element is electrically connected to the other end of the conductive line, and the fifth switching element is electrically connected to the other end of the second memory cell.

16. The method for manufacturing a magnetoresistive random access memory structure as claimed in claim 13, wherein the spin-orbit moment metal layer comprises ruthenium (Ru), tungsten (W), tantalum (Ta), iridium (Ir), platinum (Pt), hafnium (Hf), beryllium copper alloy (CuBe), iridium copper alloy (CuIr) or gold tungsten alloy (AuW).

17. The method for manufacturing a magnetoresistive random access memory structure as claimed in claim 13, wherein the spin-orbit moment metal conductive line comprises ruthenium (Ru), tungsten (W), tantalum (Ta), iridium (Ir), platinum (Pt), hafnium (Hf), beryllium copper alloy (CuBe), iridium copper alloy (CuIr) or gold tungsten alloy (AuW).

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