Power semiconductor device structure and manufacturing method thereof

Abstract

The present invention provides a power semiconductor device structure and a manufacturing method thereof. By forming a sidewall structure on the top sidewall of a polysilicon layer, a self-aligned window is defined by the sidewall structure. For small-cell power semiconductor devices, the lateral spacing between a source contact hole and a trench is limited by controlling the lateral width of the sidewall structure. In particular, for an IGBT in which the distance between the source contact hole and the trench gate polysilicon is less than 0.2 microns, the accuracy of the distance between the source contact hole and the polysilicon layer can be greatly improved, and the subsequent alignment accuracy requirements for the source contact hole mask and the trench gate mask can be reduced, thereby greatly improving the consistency of the saturation voltage drop within and between IGBT wafers.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a power semiconductor device structure and a manufacturing method thereof. Background Art

[0002] As a hybrid power device, the insulated-gate bipolar transistor (IGBT) features a MOS input structure and a bipolar output structure. This allows it to combine the advantages of a MOSFET (high input impedance, low drive circuit power, simple drive, fast switching speed, and low switching losses) with the high current density, strong current handling capability, and low on-state saturation voltage of a bipolar power transistor. Since the early 1980s, IGBTs have been extensively researched both domestically and internationally. Currently, IGBTs have broad application prospects, with widespread use in a variety of fields, including new energy vehicles, industrial frequency conversion, photovoltaics, smart grids, and locomotives. Furthermore, the Chinese IGBT market accounts for approximately one-third of the global IGBT market.

[0003] After nearly four decades of development, IGBTs have evolved from planar to trench-type, with the pitch (minimum repeating unit) of the cell becoming increasingly smaller. The distance between the active area contact hole and the trench gate is also shrinking, leading to increasingly stringent requirements for the alignment accuracy of the contact hole mask and the trench gate mask. If the alignment accuracy of the contact hole mask and the trench gate mask is poor, resulting in an insufficient distance from the contact hole to the trench gate, the saturation voltage drop (Vcesat) within the IGBT wafer will become discrete and increase. The consistency of the contact hole to trench gate distance depends entirely on the alignment consistency of the mask and the trench gate mask. The strict alignment of the mask and the trench gate mask places high demands on the process and equipment, which increases production costs and makes it difficult to guarantee product yield.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a power semiconductor device structure and a manufacturing method thereof, so as to solve the problem of poor consistency in the distance from the source contact hole to the trench gate in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for manufacturing a power semiconductor device structure, the manufacturing method comprising: providing a semiconductor substrate, forming a hard mask layer on the front surface of the semiconductor substrate, the hard mask layer having an etching window, forming a plurality of spaced-apart gate trenches in the semiconductor substrate based on the etching window, with a source region between adjacent gate trenches; forming a gate oxide layer at the bottom and sidewalls of each gate trench, forming a polysilicon layer in the gate trench and in the etching window; removing the hard mask layer to expose the top sidewall of the polysilicon layer; forming a sidewall structure on the top sidewall of the polysilicon layer, the sidewall structure shielding a portion of the source region, and defining a self-aligned window between the sidewall structures to expose the surface of the source region; forming a first etching resist in the self-aligned window. The invention relates to a method for etch-blocking a gate electrode and a semiconductor substrate, wherein the first etch barrier layer is deposited on the source region, wherein the second etch barrier layer is deposited on the source region, wherein the second etch barrier layer fills at least the first groove and the second groove, and the second etch barrier layer is removed from the source region until the surface of the source region is exposed; the source region is etched using the remaining second etch barrier layer as a self-aligned mask to form a source contact hole in the source region; a contact metal layer is formed in the source contact hole and a metal layer is formed on the front side of the semiconductor substrate.

[0007] Optionally, the lateral distance between the source contact hole and the gate trench is limited by controlling the lateral width of the spacer structure.

[0008] Optionally, a lateral distance between the source contact hole and the gate trench is less than 0.2 microns.

[0009] Optionally, the material of the sidewall structure includes one or a composite layer composed of two or more of nitride, oxide and oxynitride.

[0010] Optionally, a portion of the source region is removed by a wet etching process or a dry etching process to form a second groove, the top size of the second groove is larger than its bottom size, and the top size of the second etch stop layer subsequently filled into the second groove is larger than its bottom size.

[0011] Optionally, a top dimension of the source contact hole is larger than a bottom dimension thereof, and an inclination angle of a sidewall of the source contact hole is 80° to 85°.

[0012] Optionally, forming the first etch stop layer in the self-aligned window includes: etching the source region to form a receiving groove on a surface of the source region, and forming the first etch stop layer in the receiving groove.

[0013] Optionally, the first etch stop layer has a thickness of 0.2 micrometers to 0.5 micrometers; and / or the first etch stop layer includes organic matter.

[0014] Optionally, the preparation method further comprises the step of: performing ion implantation on the semiconductor substrate in sequence to form a carrier storage region, a body region and a source region in the semiconductor substrate.

[0015] Optionally, the depth of the first groove and the second groove is less than the depth of the source region, and the depth of the first groove and the second groove is 0.5 micrometer to 1 micrometer.

[0016] Optionally, after forming the front metal, the method further includes the following steps: performing ion implantation on the back side of the semiconductor substrate to form a collector region; performing ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is arranged adjacent to the collector region; and forming a back metal layer on the back side of the semiconductor substrate.

[0017] The present invention further provides a power semiconductor device structure, which is manufactured using the method for manufacturing a power semiconductor device structure according to any one of claims 1 to 11.

[0018] The present invention further provides a power semiconductor device structure, which is manufactured using the method for manufacturing a power semiconductor device structure according to any one of the above solutions.

[0019] As described above, the power semiconductor device structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0020] The present invention forms a sidewall structure on the top sidewall of the polysilicon layer, and defines a self-aligned window through the sidewall structure. For small-cell power semiconductor devices, the lateral spacing between the source contact hole and the polysilicon layer in the trench is limited by controlling the lateral width of the sidewall structure. In particular, for IGBTs with a distance between the source contact hole and the trench gate polysilicon less than 0.2 microns, the accuracy of the distance between the source contact hole and the polysilicon can be greatly improved, and the subsequent alignment accuracy requirements for the source contact hole mask and the trench gate mask can be reduced, thereby greatly improving the consistency of the saturation voltage drop (Vcesat) within and between IGBT wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to illustrate the implementation of the present application and, together with the text description, to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0022] Figures 1 to 14 It is a structural schematic diagram showing the steps of the method for manufacturing a power semiconductor device structure according to an embodiment of the present invention, wherein: Figure 14 Shown is a schematic structural diagram of a power semiconductor device structure according to an embodiment of the present invention.

[0023] Component number description

[0024] 1. Semiconductor substrate

[0025] 2 Carrier storage area

[0026] 3 body regions

[0027] 4 Source area

[0028] 5 Hard mask layer

[0029] 6 Gate trench

[0030] 7 Gate oxide

[0031] 8 Polysilicon layer

[0032] 9 Side wall structure

[0033] 9a Self-aligning window

[0034] 10 First etch stop layer

[0035] 11 First groove

[0036] 12 Second groove

[0037] 111 blank area

[0038] 13. Second etch stop layer

[0039] 14 Source contact hole

[0040] 15 Contact metal layer

[0041] 16 front metal layer

[0042] 17 Hydrogen ion doped region

[0043] 18 Collector region

[0044] 19 Back metal layer DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0047] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0048] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0049] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0050] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0051] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0052] like Figures 1 to 14 As shown, this embodiment provides a method for manufacturing a power semiconductor device structure. The power semiconductor device may be, for example, an IGBT device. The manufacturing method includes the following steps:

[0053] like Figure 1 As shown, step 1 is first performed to provide a semiconductor substrate 1, and a hard mask layer 5 is formed on the semiconductor substrate. The hard mask layer 5 has an etching window. Based on the etching window, a plurality of spaced-apart gate trenches 6 are formed in the semiconductor substrate 1, and source regions 4 are located between adjacent gate trenches 6.

[0054] In one embodiment, semiconductor substrate 1 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or the like. Semiconductor substrate 1 may be doped, and its doping concentration and thickness may be set based on the withstand voltage requirements of the IGBT device. In this embodiment, semiconductor substrate 1 is a silicon substrate, and its doping type is N-type doping.

[0055] In one embodiment, the method further includes sequentially performing ion implantation on the semiconductor substrate 1 to form a carrier storage region 2 , a body region 3 and a source region 4 in the semiconductor substrate 1 .

[0056] Specifically, the carrier storage area 2 is injected through a mask or the carrier storage area 2 is generally injected without a mask. The injected ions may be phosphorus and the injection dose may be 1e12 cm -2 ~5e13cm -2 The implantation energy can be 80KeV~2MeV, the push temperature can be 1050℃~1250℃, the time can be 30min~300min, and then the body region 3 general implantation can be performed. The implanted ions can be boron, and the implantation dose is 4e13cm -2 ~1e14cm -2 The injection energy is 60keV~200keV, the push temperature can be 1050℃~1250℃, the time is 10min~120min, and then the source region is injected through the mask. The injected ion can be arsenic and the injection dose can be 5e15cm -2 ~2e16cm -2 The injection energy can be 60keV to 600keV, the advancement temperature can be 900℃ to 1000℃, and the time can be 30min to 120min.

[0057] Next, a hard mask layer 5 is deposited, preferably with a thickness of 3000 to 8000 angstroms. Etching windows are formed in the hard mask layer 5 through a photolithography and etching process. Multiple, spaced-apart gate trenches 6 are then etched through the etched windows into the semiconductor substrate 1. The depth of the gate trenches 6 may be 2 to 6 microns. The hard mask layer 5 may be, for example, silicon dioxide, silicon nitride, silicon oxynitride, a carbon-containing dielectric material, or a stack of these materials.

[0058] like Figure 2 As shown, step 2) is then performed to form a gate oxide layer 7 at the bottom and sidewall of each gate trench 6, and a polysilicon layer 8 is formed in the gate trench 6 and the etching window.

[0059] like Figure 2 As shown, first, a gate oxide layer 7 can be formed at the bottom and sidewalls of the gate trench 6 by thermal growth. The thickness of the gate oxide layer 7 can be 1000 angstroms to 1500 angstroms. Then, a polysilicon layer 8 is deposited, and the polysilicon layer 8 above the surface of the hard mask layer 5 is etched back to remove.

[0060] like Figure 3 As shown, step 3) is then performed to remove the hard mask layer 5 to expose the top sidewall of the polysilicon layer 8.

[0061] In one embodiment, the hard mask layer 5 may be removed by a wet etching process.

[0062] It should be noted that the carrier storage region 2 , the body region 3 and the source region 4 are prepared after the hard mask layer 5 is removed, and are not limited to the examples listed above.

[0063] like Figure 4 As shown, step 4 is then performed to form a sidewall structure 9 on the top sidewall of the polysilicon layer 8. The sidewall structure 9 blocks part of the source region 4. The sidewall structures 9 define a self-aligned window 9a that exposes the surface of the source region 4.

[0064] In one embodiment, the sidewall spacer 9 is preferably made of a material having a high etch selectivity with the source region 4. The material may include a composite layer of one or more of nitride, oxide, and oxynitride. The nitride may be, for example, silicon nitride, the oxide may be, for example, silicon oxide, and the oxynitride may be, for example, silicon oxynitride. In this embodiment, the sidewall spacer 9 is made of silicon nitride with a thickness of 3,000 to 10,000 angstroms. The silicon nitride is then etched through a sidewall spacer manufacturing process, ultimately leaving the silicon nitride on the top sidewalls of the polysilicon layer 8, forming the silicon nitride sidewall spacer 9.

[0065] In one embodiment, the lateral spacing between the source contact hole 14 and the gate trench 6 is limited by controlling the lateral width of the sidewall structure 9. For example, based on the requirement of the lateral spacing between the source contact hole 14 and the gate trench 6, the lateral width of the sidewall structure 9 can be set to vary between 0.05 microns and 5 microns, thereby ultimately limiting the lateral spacing between the source contact hole 14 and the gate trench 6.

[0066] In a preferred example, the lateral distance between the source contact hole 14 and the gate trench 6 can be controlled to be less than 0.2 microns by adjusting the lateral width of the spacer structure 9 to meet the requirements of small cell power devices.

[0067] like Figure 5 As shown, step 5) is then performed to form a first etch stop layer 10 in the self-aligned window 9a.

[0068] In one embodiment, forming the first etch stop layer 10 in the self-aligned window 9 a includes etching the source region 4 to form a receiving groove on a surface of the source region 4 , and forming the first etch stop layer 10 in the receiving groove.

[0069] In one embodiment, the thickness of the first etch stop layer 10 is 0.2 microns to 0.5 microns. The first etch stop layer 10 is formed in the receiving groove by a spin coating process. The first etch stop layer 10 includes an organic material, such as photoresist, epoxy resin, etc.

[0070] By first forming a receiving groove on the surface of the source region 4 and then spin-coating the first etch stop layer 10 in the receiving groove, the stability of the first etch stop layer 10 can be greatly improved. For example, the damage to the first etch stop layer 10 caused by the subsequent removal of the polysilicon layer 8 and the sidewall structure 9 can be greatly reduced, thereby improving its accuracy as a mask.

[0071] like Figure 6 As shown, step 6 is then performed to remove the sidewall structure 9 and the polysilicon layer 8 located on the surface of the first etch stop layer 10 to expose the source region 4 between the first etch stop layer 10 and the polysilicon layer 8 .

[0072] In one embodiment, the spacer structure 9 may be removed by a wet process first, and then the polysilicon layer 8 on the first etch stop layer 10 may be removed by a chemical mechanical polishing (CMP) process.

[0073] In another embodiment, the polysilicon layer 8 may be first etched by an etching process so that the height of the polysilicon layer 8 is flush with the surface of the first etch stop layer 10 or slightly higher than the surface of the first etch stop layer 10 or slightly lower than the surface of the first etch stop layer 10, and then the sidewall structure 9 is removed by a wet etching process.

[0074] like Figure 7 As shown, step 7 is then performed to remove a portion of the polysilicon in the gate trench 6 by etching the barrier layer to form a first groove 11 , and to remove a portion of the exposed source region 4 to form a second groove 12 .

[0075] In one embodiment, Figure 7 As shown, a portion of the source region 4 is removed by a dry etching process to form a second groove 12. The top size of the second groove 12 is larger than its bottom size. The top size of the second etch stop layer 13 subsequently filled into the second groove 12 is larger than its bottom size. For example, the second groove 12 can be an inverted triangle formed by the area sandwiched by the gate oxide layer 7 and the source region 4.

[0076] In one embodiment, the depth of the first groove 11 and the second groove 12 is less than the depth of the source region 4 , and the depth of the first groove 11 and the second groove 12 is 0.5 micrometers to 1 micrometer.

[0077] In another embodiment, Figure 8As shown, the first groove 11 and the second groove 12 are formed simultaneously by a wet etching process. At the same time, the gate oxide layer 7 between the first groove 11 and the second groove 12 is also removed, so that the first groove 11 and the second groove 12 are connected to form a blank area 111.

[0078] like Figure 9 As shown, step 8 is then performed to remove the first etching stop layer 10 to expose the surface of the source region 4.

[0079] In one embodiment, the first etch stop layer 10 may be removed by a dry process or a wet process.

[0080] like Figures 10 and 11 As shown, step 9 is then performed to deposit a second etch stop layer 13 on the source region 4, the second etch stop layer 13 at least filling the first groove 11 and the second groove 12, and remove the second etch stop layer 13 on the surface of the source region 4 until the surface of the source region 4 is exposed.

[0081] In one embodiment, Figure 10 As shown, a BPSG layer (boron phosphosilicate glass) is deposited on the source region 4 through a deposition process as the second etch stop layer 13. The thickness of the BPSG layer can be 0.8 microns to 1.5 microns.

[0082] In one embodiment, Figure 10 As shown, the top size of the second etch stopper layer 13 filled into the second groove 12 is larger than the bottom size thereof. For example, the second etch stopper layer 13 in the second groove 12 may be in an inverted triangle shape.

[0083] In one embodiment, Figure 11 As shown, the BPSG layer and the gate oxide layer 7 are dry-etched until the surface of the source region 4 is exposed.

[0084] like Figure 12 As shown, step 10 is then performed to etch the source region 4 using the remaining second etch stop layer 13 as a self-aligned mask to form a source contact hole 14 in the source region 4 . The source contact hole 14 extends into the body region 3 .

[0085] In one embodiment, the top dimension of the source contact hole 14 is larger than its bottom dimension, and the sidewall of the source contact hole 14 has an inclination angle of 80° to 85°. Preferably, the source contact hole 14 may be in the shape of an inverted trapezoid. The inverted triangular self-aligned mask and the inverted trapezoidal source contact hole 14 can allow the sidewalls of the source contact hole 14 to retain a certain lateral width of the source region 4. The source contact hole 14 can simultaneously contact the four sides of the source region 4, thereby effectively improving the contact between the source contact hole 14 and the source region 4 and reducing the contact resistance. Figure 12 shown.

[0086] like Figure 13 As shown, step 11 is then performed to form a contact metal layer 15 in the source contact hole 14 and a front metal layer 16 on the semiconductor substrate.

[0087] In one embodiment, Ti / TiN / W is formed in the source contact hole 14 as the contact metal layer 15 , and then an AlCu alloy layer is formed on the semiconductor substrate as the front metal layer 16 .

[0088] like Figure 14 As shown, step 12) is finally performed, including: ion implantation on the back side of the semiconductor substrate to form a collector region 18; ion implantation on the back side of the semiconductor substrate to form a hydrogen ion doped region 17, wherein the hydrogen ion doped region 17 is arranged adjacent to the collector region 18; and forming a back metal layer 19 on the back side of the semiconductor substrate.

[0089] In one embodiment, the semiconductor substrate is first turned over and thinned to a certain thickness, which depends on the withstand voltage requirement of the power device. Then, boron ion implantation is performed once, with an implantation energy of 60KeV to 20KeV and an implantation dose of 3e12cm -2 ~1e14cm -2 , forming a P-type collector region 18, and then using laser annealing equipment to activate the injected boron ions; then secondary hydrogen injection and annealing are performed from the back side of the semiconductor substrate to form a hydrogen ion doped region 17, and finally a back metal layer 19 is formed on the back side of the semiconductor substrate. The back metal layer 19 can be Al / Ti / Ni / Ag.

[0090] like Figure 14 As shown, this embodiment further provides a power semiconductor device structure, which is manufactured using the manufacturing method of the power semiconductor device structure of the above embodiment.

[0091] It should be noted that, in some embodiments, there are multiple gate trenches 6 and source contact holes 14. Through the manufacturing method of the above embodiment, it can be ensured that the multiple source contact holes 14 and the polysilicon layer 8 in the corresponding gate trenches 6 have basically the same spacing, thereby greatly improving the consistency of the saturation voltage drop (Vcesat) within and between IGBT wafers.

[0092] As described above, the power semiconductor device structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0093] The present invention forms a sidewall structure 9 on the top sidewall of the polysilicon layer 8, and defines a self-aligned window 9a through the sidewall structure 9. For small-cell power semiconductor devices, the lateral spacing between the source contact hole 14 and the polysilicon layer 8 in the gate trench 6 is limited by controlling the lateral width of the sidewall structure 9. In particular, for IGBTs in which the distance between the source contact hole 14 and the gate polysilicon of the trench 6 is less than 0.2 microns, the accuracy of the distance between the source contact hole 14 and the polysilicon layer can be greatly improved, and the alignment accuracy requirement for the subsequent contact hole mask and the gate mask of the trench 6 can be reduced, thereby greatly improving the consistency of the saturation voltage drop (Vcesat) within and between IGBT wafers.

[0094] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a power semiconductor device structure, characterized in that: The manufacturing method comprises: Providing a semiconductor substrate, forming a hard mask layer on the front surface of the semiconductor substrate, the hard mask layer having an etching window, forming a plurality of spaced-apart gate trenches in the semiconductor substrate based on the etching window, with source regions between adjacent gate trenches; forming a gate oxide layer at the bottom and sidewall of each gate trench, and forming a polysilicon layer in the gate trench and in the etching window; removing the hard mask layer to expose the top sidewall of the polysilicon layer; forming a sidewall structure on the top sidewall of the polysilicon layer, wherein the sidewall structure shields a portion of the source region, and a self-aligned window is defined between the sidewall structures to expose the surface of the source region; forming a first etch stop layer in the self-aligned window; removing the sidewall structure and the polysilicon layer located on the surface of the first etch stop layer to expose the source region between the first etch stop layer and the polysilicon layer; Etching the barrier layer to remove a portion of the polysilicon in the gate trench to form a first groove, and removing a portion of the exposed source region to form a second groove; removing the first etch stop layer to expose the surface of the source region; Depositing a second etch stop layer on the source region, wherein the second etch stop layer at least fills the first groove and the second groove, and removing the second etch stop layer above the surface of the source region until the surface of the source region is exposed; Using the remaining second etch stop layer as a self-aligned mask, etching the source region to form a source contact hole in the source region; A contact metal layer is formed in the source contact hole and a metal layer is formed on the front surface of the semiconductor substrate.

2. The method for manufacturing a power semiconductor device structure according to claim 1, wherein: The lateral distance between the source contact hole and the gate trench is limited by controlling the lateral width of the spacer structure.

3. The method for manufacturing a power semiconductor device structure according to claim 2, wherein: The lateral distance between the source contact hole and the gate trench is less than 0.2 microns.

4. The method for manufacturing a power semiconductor device structure according to claim 1, wherein: The material of the sidewall structure includes one or a composite layer composed of two or more of nitride, oxide and oxynitride.

5. The method for manufacturing a power semiconductor device structure according to claim 1, wherein: A second groove is formed by removing part of the source region through a wet etching process or a dry etching process, wherein the top size of the second groove is larger than the bottom size thereof, and the top size of the second etch stop layer subsequently filled into the second groove is larger than the bottom size thereof.

6. The method for manufacturing a power semiconductor device structure according to claim 1, wherein: The top size of the source contact hole is larger than the bottom size thereof, and the sidewall inclination angle of the source contact hole is 80° to 85°.

7. The method for manufacturing a power semiconductor device structure according to claim 1, wherein: Forming the first etch stop layer in the self-aligned window includes: etching the source region to form a receiving groove on the surface of the source region, and forming the first etch stop layer in the receiving groove.

8. The method for manufacturing a power semiconductor device structure according to claim 7, wherein: The thickness of the first etch stop layer is 0.2 micrometer to 0.5 micrometer; and / or The first etch stop layer includes organic matter.

9. The method for manufacturing a power semiconductor device structure according to claim 1, wherein: The preparation method further comprises the steps of: performing ion implantation on the semiconductor substrate in sequence to form a carrier storage region, a body region and a source region in the semiconductor substrate.

10. The method for manufacturing a power semiconductor device structure according to claim 9, wherein: The depths of the first groove and the second groove are smaller than the depth of the source region, and the depths of the first groove and the second groove are 0.5 micrometers to 1 micrometer.

11. The method for manufacturing a power semiconductor device structure according to claim 1, wherein: After forming the front metal, the following steps are also included: Performing ion implantation on the back side of the semiconductor substrate to form a collector region; Performing ion implantation on the back surface of the semiconductor substrate to form a hydrogen ion doped region, wherein the hydrogen ion doped region is disposed adjacent to the collector region; A back metal layer is formed on the back side of the semiconductor substrate.

12. A power semiconductor device structure, characterized in that: The power semiconductor device structure is manufactured by using the method for manufacturing a power semiconductor device structure according to any one of claims 1 to 11.

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