A ferroelectric transistor capable of generating thousands of polarization states and its fabrication and application method

Abstract

This invention discloses a ferroelectric transistor capable of generating thousands of polarization states and its fabrication and application method. The ferroelectric transistor is fabricated based on a Gr / hBN heterojunction, with a Gr sheet as the top layer and an hBN sheet as the bottom layer. The rotation angle between Gr and hBN is controlled within 1° using a dry transfer method. The Gr / hBN heterojunction is fixed on a silicon substrate (SiO2 / Si). Source and drain electrodes are further deposited using electron beam lithography and electron beam evaporation processes to construct the Gr / hBN ferroelectric transistor. A single device can generate dozens of discrete polarization states through source-drain pulse modulation. Simultaneously, by superimposing a gate voltage while applying source-drain pulses, the Fermi level of graphene can be reversibly tuned between dozens of non-volatile doping levels, and the polarization state can be modulated by source-drain pulses at each doping level. The number of stable polarization states reaches thousands at room temperature; different polarization states can be retained for more than 10^6 times. 5 Seconds, and based on linear extrapolation, it could last for more than 10 years.

Description

Technical Field

[0001] This invention relates to the field of ferroelectric functional devices, and more particularly to a ferroelectric transistor capable of generating thousands of polarization states and its preparation and use method. Background Technology

[0002] Large-scale neural networks require the measurement of billions of parameters, and the enormous data throughput poses a significant challenge to existing hardware architectures. Emerging neuromorphic computing offers an effective way to overcome this challenge, requiring the realization of multiple stable states within a single unit to improve computational accuracy and storage density, thereby efficiently handling complex, data-intensive tasks. In this context, ferroelectric materials capable of generating multiple electrically addressable polarization states have emerged as strong candidates for neuromorphic hardware. Despite significant efforts in traditional three-dimensional ferroelectrics and the recently emerging two-dimensional ferroelectrics, the number of stable polarization states created at room temperature does not exceed 32, severely limiting the applicability of existing ferroelectrics in future neuromorphic hardware. To address the shortcomings of existing technologies, this invention discloses a ferroelectric transistor capable of generating thousands of polarization states, two orders of magnitude higher than the optimal value of existing ferroelectric systems. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to address the deficiencies mentioned in the background art by providing a ferroelectric transistor capable of generating thousands of polarization states and a method for its fabrication and use.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] A ferroelectric transistor capable of generating thousands of polarization states has a vertically stacked structure, consisting of a Gr thin film, an hBN thin film, and a silicon substrate from top to bottom.

[0006] The Gr and hBN sheets are bonded together by van der Waals forces to form a Gr / hBN heterojunction.

[0007] The hBN sheet is fixed to the upper surface of the silicon substrate;

[0008] The upper surface of the silicon substrate is provided with metal electrodes, namely the source and the drain, which are respectively connected to both ends of the Gr thin film;

[0009] A gate is provided on the lower surface of the silicon wafer substrate.

[0010] As a further optimization of the present invention, which can generate thousands of room-temperature non-volatile polarization states of ferroelectric transistors, the thickness of the Gr sheet is 0.3~2 nm, and the thickness of the hBN sheet is 20 nm.

[0011] This invention also discloses a method for fabricating a ferroelectric transistor capable of generating thousands of polarization states, comprising the following steps:

[0012] Step 1), strips of Gr and hBN are peeled off and placed on different silicon substrates;

[0013] Step 2), prepare the PPC / PDMS transfer vector;

[0014] Step 2.1): Cut the PDMS and place it on a clean glass slide, then use oxygen plasma to treat the surface of the PDMS.

[0015] Step 2.2): Spin-coat the PPC reagent onto the PDMS surface, then heat it on a hot stage until a PPC film is formed;

[0016] Step 2.3) Surface treatment of PPC film is performed using oxygen plasma to obtain PPC / PDMS transfer carrier;

[0017] Step 3), prepare a PC film and cover the PC film onto the PPC / PDMS transfer carrier to obtain a PC / PPC / PDMS dry transfer carrier;

[0018] Step 4): At a preset threshold temperature, the PC film of the PC / PPC / PDMS dry transfer carrier is covered onto the Gr sheet. The PC / PPC / PDMS dry transfer carrier is slowly lifted to detach the target Gr sheet from the silicon substrate. Then, the Gr sheet is attached to the hBN sheet on the silicon substrate. Heating is then applied to release the heat of melting of the PPC / PC film onto the silicon substrate. Next, the PDMS carrier is slowly removed to form a Gr / hBN heterojunction on the silicon substrate. Finally, the Gr / hBN heterojunction and the PPC and PC on the surface of the silicon substrate are cleaned.

[0019] Step 5), place the Gr / hBN heterojunction on the silicon substrate horizontally so that the Gr sheet is on top;

[0020] Step 6) Spin-coating PMMA onto the surface of a silicon substrate at a speed higher than a preset speed threshold, and then heating until the solvent in the PMMA evaporates to form a PMMA layer;

[0021] Step 7), repeat step 6) until the PMMA layer on the upper surface of the silicon substrate covers the Gr film;

[0022] Step 8) The source and drain electrodes are exposed on the PMMA layer using a field emission electron microscope and an electron beam exposure system. Then, development is performed to expose the source and drain areas. Finally, Ti / Au is deposited on the source and drain areas using an electron beam deposition device.

[0023] Step 9) Perform post-processing to remove the metal thin layer carried by PMMA in the unexposed area; then clean and dry to obtain a quasi-ferroelectric transistor with source and drain electrodes;

[0024] Step 10): Lead a wire from the lower surface of the silicon substrate as the gate to obtain a Gr / hBN ferroelectric transistor.

[0025] As a further optimization of the fabrication method of the ferroelectric transistor capable of generating thousands of polarization states according to the present invention, the detailed steps for peeling off the Gr and hBN thin films in step 1) are as follows:

[0026] Step 1.1) Clean the silicon wafer using an oxygen plasma system to increase the adhesion between the silicon wafer and the Gr and hBN wafers;

[0027] Step 1.2): Use blue tape to stick a small amount of Gr crystal and hBN crystal to the silicon wafer, and then cover the silicon wafer with the tape.

[0028] Step 1.3), the silicon wafer covered with blue tape is placed on a hot table to heat it to enhance the adhesion between the tape and the silicon wafer;

[0029] Step 1.4): Remove the silicon wafer covered with blue tape from the hot stage. After cooling, slowly peel off the blue tape and mechanically peel it off to obtain Gr wafers and hBN wafers.

[0030] As a further optimization of the method for fabricating ferroelectric transistors capable of generating thousands of polarization states according to the present invention, the detailed steps for preparing the PC thin film in step 3) are as follows:

[0031] PC reagent is dropped onto the upper surface of slide 1. Then, the lower surface of slide 2 is placed over the upper surface of slide 1. Finally, slides 1 and 2 are horizontally dragged to separate them, thereby forming a PC film on the upper surface of slide 1 and the lower surface of slide 2 respectively.

[0032] As a further optimization of the preparation method of the ferroelectric transistor capable of generating thousands of polarization states according to the present invention, the mass fraction of the PPC reagent is 15%, and the solvent is anisole.

[0033] As a further optimization of the preparation method of the ferroelectric transistor capable of generating thousands of polarization states according to the present invention, the mass fraction of the PC reagent is 5%, and the solvent is dichloromethane.

[0034] As a further optimization of the method for preparing a ferroelectric transistor capable of generating thousands of polarization states according to the present invention, in step 4), when cleaning the PPC and PC on the surface of the Gr / hBN heterojunction and the silicon substrate, they are sequentially placed in dichloromethane for 20 min, acetone for 15 min, and isopropanol for 5 min for cleaning.

[0035] The present invention also discloses a method for using the ferroelectric transistor capable of generating thousands of polarization states, wherein the polarization states of the ferroelectric transistor are tuned by applying a DC pulse to the Gr channel at the source and drain; at the same time, the gate voltage is preset to control the injection and discharge of charge carriers into and out of the Gr channel, thereby achieving non-volatile doping of the Gr channel.

[0036] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0037] This invention provides a ferroelectric transistor capable of generating thousands of polarization states and its fabrication method. At room temperature, by applying a DC pulse (Vpulse) between the source and drain electrodes, the ferroelectric transistor can generate 56 stable and discrete polarization states. By simultaneously applying the source-drain pulse stack and setting the gate voltage (VG_Pre), the Dirac peak of graphene can be reversibly locked at at least 84 doping levels. At each doping level, at least 36 polarization states can be precisely modulated by the source-drain pulse, thus significantly increasing the number of tunable polarization states to 3024. Different polarization states can be retained for more than 10... 5 It can last for seconds, and according to linear extrapolation, it may last for more than 10 years, thus enabling non-volatile polymorphic operations. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the Gr / hBN ferroelectric transistor structure and its working principle in an embodiment of the present invention;

[0039] Figure 2 (a) is a schematic diagram of the modulation of multi-state polarization in a Gr / hBN ferroelectric transistor by a source-drain pulse in an embodiment of the present invention. Figure 2 (b) A schematic diagram showing the channel current as a function of time for the 56 discrete polarization states;

[0040] Figure 3 This is a schematic diagram illustrating the stability of the channel current corresponding to different polarization states of the Gr / hBN ferroelectric transistor in an embodiment of the present invention.

[0041] Figure 4 This is a schematic diagram of the transfer curves of Gr / hBN ferroelectric transistors at different doping levels at 1.5 K in an embodiment of the present invention.

[0042] Figure 5 This is a schematic diagram of the transport curves of the Gr / hBN ferroelectric transistor under different doping levels at 300 K in an embodiment of the present invention.

[0043] Figure 6 (a) The Gr / hBN ferroelectric transistors in the embodiments of the present invention are respectively in V G_PreA schematic diagram showing the change of channel current over time under positive source-drain pulse modulation at V values ​​of 0, 1, 2, 3, 4, and 5. Figure 6 (b) is Figure 6 (a) Corresponding device weights ( W d A diagram illustrating the changes over time;

[0044] Figure 7 (a) The Gr / hBN ferroelectric transistors in the embodiments of the present invention are respectively in V G_Pre A schematic diagram showing the change of channel current over time under the conditions of 5, 4, 3, 2, 1, 0 V through negative source-drain pulse modulation. Figure 7 (b) is Figure 7 (a) Schematic diagram of the change of corresponding device weights over time;

[0045] Figure 8 To adjust dynamically V pulse and V G_Pre A schematic diagram illustrating the changes of 3024 polarization states over time in a Gr / hBN ferroelectric transistor as demonstrated in this embodiment of the invention. Detailed Implementation

[0046] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:

[0047] This invention can be implemented in many different forms and should not be considered limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully express the scope of the invention to those skilled in the art. In the drawings, components are enlarged for clarity.

[0048] like Figure 1 As shown, the present invention discloses a ferroelectric transistor capable of generating thousands of polarization states, which is a vertically stacked structure, comprising, from top to bottom, a Gr thin film, an hBN thin film, and a silicon substrate;

[0049] The Gr and hBN sheets are bonded together by van der Waals forces to form a Gr / hBN heterojunction.

[0050] The hBN sheet is fixed to the upper surface of the silicon substrate;

[0051] The upper surface of the silicon substrate is provided with metal electrodes, namely the source and the drain, which are respectively connected to both ends of the Gr thin film;

[0052] A gate is provided on the lower surface of the silicon wafer substrate.

[0053] The thickness of the Gr sheet is preferably 0.3~2 nm, and the thickness of the hBN sheet is preferably 20 nm.

[0054] like Figure 1 As shown, when using this invention, the polarization state of the ferroelectric electrode is tuned by applying a DC pulse to the Gr channel of the source and drain. At the same time, the gate voltage is preset to control the injection and discharge of charge carriers into and out of the Gr channel, thereby achieving non-volatile doping of the Gr channel.

[0055] The reagents and instruments required for preparation in the embodiments of the present invention are as follows:

[0056] Graphite crystal (HQ graphene); hBN crystal (HQ graphene);

[0057] Silicon wafer (University, 300 nm SiO2 / Si); blue adhesive tape for mechanical peeling (ultronsystems); white adhesive tape (3M).

[0058] PDMS (DOW CORNING 184); PC (Sigma-Aldrich); PPC (Sigma-Aldrich); PMMA (MicroChem 495 A4);

[0059] Dichloromethane (Bailingwei, pesticide residue grade 99.9%); anisole (alladin, chromatographic grade 99.9%); acetone (Wokai, chromatographic grade 99.9%); isopropanol (Tedia, chromatographic grade 99.9%).

[0060] Two-dimensional material transfer stage (Meta Photonics), electron beam deposition equipment (Syskey E-Beam Evaporation system), oxygen plasma system (Femto Science Convance), spin coater (Spin Processor POLOS), optical microscope (Nikon LV100ND), field emission electron microscope (Zeiss Sigma 300), electron beam exposure system (Raith Quantum), atomic force microscope (SmartSPM-1000), Raman spectrometer (Horiba JY Labram EVO, 532nm), cryogenic transport equipment (OXFORD TeslatronPT), source table (Keithley 2400 / Keithley 6430).

[0061] The specific preparation method includes the following steps:

[0062] Step 1), strips of Gr and hBN are peeled off and placed on different silicon substrates;

[0063] Step 1.1) Clean the silicon wafer using an oxygen plasma system at 50W / 50sccm / 2min to increase the adhesion between the silicon wafer and the Gr and hBN wafers;

[0064] Step 1.2): Use blue tape to stick a small amount of Gr crystal and hBN crystal to the silicon wafer, and then cover the silicon wafer with the tape.

[0065] Step 1.3), the silicon wafer covered with blue tape is placed on a hot table and heated at 100°C for 1 minute to enhance the adhesion between the tape and the silicon wafer;

[0066] Step 1.4): Remove the silicon wafer covered with blue tape from the hot stage. After cooling, slowly peel off the blue tape and mechanically peel it off to obtain Gr wafers and hBN wafers.

[0067] After obtaining Gr and hBN wafers through peeling, the positions of the Gr and hBN wafers on the silicon wafers were confirmed by optical microscopy based on the difference in optical contrast; and the thickness and surface cleanliness of the two-dimensional materials at the corresponding positions were confirmed by atomic force microscopy.

[0068] Step 2), prepare the PPC / PDMS transfer vector;

[0069] Step 2.1) Cut a piece of PDMS and place it on a clean glass slide. Treat its surface with oxygen plasma at 30W / 20sccm / 30s. Turn the PDMS over and treat its surface again with oxygen plasma at 50W / 50sccm / 2min.

[0070] Step 2.2) Using a spin coater, PPC reagent (15% by mass, anisole solvent) is spin-coated onto the PDMS surface at a speed of 4000 rpm / s for 1 min, and then heated on a hot table at 105℃ for 3 min to form a PPC film;

[0071] Step 2.3) The PPC-coated PDMS was treated with oxygen plasma at 20W / 10sccm / 3s to obtain the PPC / PDMS transfer carrier;

[0072] Step 3): Take two clean glass slides, add 3 ml of PC reagent (5% by mass, dichloromethane solvent) to one of them, and immediately cover it with the other glass slide. Then slowly slide the two glass slides apart to form a PC film on the glass slide. After standing for 5 minutes, use a scalpel to cut the PC film into small pieces. Cut a square hole in the middle of a 3M white tape. The area of ​​the square hole should be slightly larger than the small piece of PDMS. Then use it to stick the PC film together and cover the PPC / PDMS transfer carrier to obtain the PC / PPC / PDMS dry transfer carrier.

[0073] Step 4): At a preset threshold temperature, the PC film of the PC / PPC / PDMS dry transfer carrier is covered on the Gr sheet. The PC / PPC / PDMS dry transfer carrier is slowly lifted to pick up the target Gr sheet from the silicon substrate. Then, the Gr sheet is attached to the hBN sheet on the silicon substrate. The temperature is then heated to 180°C and held for 2 minutes to release the heat of melting of the PPC / PC film onto the silicon substrate. Next, the PDMS carrier is slowly removed to form a Gr / hBN heterojunction on the silicon substrate. Finally, the Gr / hBN heterojunction and the PPC and PC on the surface of the silicon substrate are cleaned sequentially with dichloromethane for 20 minutes, acetone for 15 minutes, and isopropanol for 5 minutes to remove them.

[0074] Step 5), place the Gr / hBN heterojunction on the silicon substrate horizontally so that the Gr sheet is on top;

[0075] Step 6) Spin-coat PMMA onto the upper surface of the silicon substrate at a speed of 4000 rpm, and heat until the solvent in the PMMA evaporates to form a PMMA layer;

[0076] Step 7), repeat step 6) until the PMMA layer on the upper surface of the silicon substrate covers the Gr film;

[0077] Step 8) The source and drain electrodes are exposed on the PMMA layer using a field emission electron microscope and an electron beam exposure system. Then, the layer is placed in a developer (isopropanol:water = 3:1) for 30 seconds to expose the source and drain areas. Next, Ti / Au is deposited on the source and drain areas using an electron beam deposition device.

[0078] Step 9) Post-processing: Immerse the vapor-deposited device in acetone and heat it on a hot stage at 65°C to remove the metal thin layer carried by PMMA in the unexposed area; then immerse the device in isopropanol for 5 minutes and dry it with nitrogen to obtain a quasi-ferroelectric transistor with source and drain electrodes.

[0079] Step 10): Lead a wire from the lower surface of the silicon substrate as the gate to obtain a Gr / hBN ferroelectric transistor.

[0080] Source-drain pulse modulation and electrical transport testing of Gr / hBN ferroelectric transistors: Based on a sample holder using a cryogenic transport device, the device leads were completed, such as... Figure 2 As shown in (a); place the sample into the chamber and evacuate to 1×10⁻⁶. -6 torr, and reduce the chamber temperature to 1.5 K. To achieve multi-state polarization control, we designed a source-drain bias pulse with monotonically varying amplitude ( V pulse ) at gate voltage ( V G The polarization tendency and intensity are applied to the Gr channel under zero conditions. Changes in polarization tendency and intensity create carrier concentration differences within the Gr channel, allowing the change in system polarization state to be detected by the channel current. The polarization is controlled within the range of +6.5 V to +12 V. V pulse The amplitude, and after each pulse action, the source-drain voltage is 1 mV ( V DS The channel current was recorded over time; it was found that 56 discrete polarization states could be generated in a single device, and the retention performance of each state was at least over 1000 seconds. Figure 2 As shown in (b). +13 V and -13 V are applied respectively. V pulse This causes the system to be net polarized downwards and upwards; the corresponding two channel current levels are above 10. 5 It remains clearly discernible even after seconds, and based on linear extrapolation, the retention time may exceed 10 years. Figure 3 As shown.

[0081] Non-volatile doping control of Gr / hBN ferroelectric transistors: Besides the source-drain pulse, another degree of freedom in Gr / hBN devices is the bottom gate voltage. We found that by pre-setting a gate voltage while applying the source-drain pulse (…),… V G_Pre The Dirac peak of graphene can be locked at a position similar to... V G_Pre At the relevant doping levels. At 1.5 K, V G_Pre Under the conditions of +60 V ~ -60 V and -60 V ~ +60 V, such as Figure 4 As shown, source-drain pulses with an amplitude of -12 V and a width of 1 second are applied sequentially, and in each... V pulse The transmission curves are scanned after the action; the upper inset illustrates the method for controlling the non-volatile doping level, and the other inset describes the carrier density and... V G_PreThe linear relationship between the two was observed; a significant linear shift in the position of the Dirac peak of graphene was found, indicating effective modulation of the doping level of the system.

[0082] Demonstrates the manipulation of thousands of polarization states in a Gr / hBN ferroelectric transistor at room temperature: the control of non-volatile doping levels can be extended up to 300 K at room temperature. V G_Pre Under conditions of +40 V to -40 V, the transport curves of graphene exhibit dozens of different Dirac peak positions, each corresponding to a different Fermi level in graphene, such as... Figure 5 As shown. V G_Pre Taking 0, 1, 2, 3, 4, 5 V as an example, a series of positive... V pulse The application of this causes the channel current to gradually increase, such as... Figure 6 As shown in (a), different current levels correspond to the evolution of polarization states; to intuitively distinguish all polarization states, we define the device weight as 𝑊 d =𝑉 𝐺_𝑃𝑟𝑒 + 𝛼𝐼 𝐷𝑆 (where 𝛼 is the scaling factor, 𝛼 = 1 / (𝐼)) 𝐷𝑆 (𝑚𝑎𝑥)−𝐼 𝐷𝑆 (𝑚in)), 𝐼 𝐷𝑆 The unit is nanoampere (NVA); based on this, all measured channel current levels are converted into device weights, and the modulation process is represented as 𝑊 d The monotonically increasing, such as Figure 6 As shown in (b). Conversely, a series of negative pressures are applied to the device. V pulse Suppressing channel current, such as Figure 7 As shown in (a), modulate 𝑊 d Monotonically decreasing, thus making the modulation process of the polarization state reversible, such as... Figure 7 As shown in (b), we selectively demonstrate the modulation of 36 distinguishable channel current levels at 84 specific doping levels; by converting all states to the corresponding 𝑊 d We demonstrated 3024 discrete and uniformly distributed polarization states in a single Gr / hBN device, such as Figure 8 As shown.

[0083] This invention further demonstrates the realization of more than 3,000 non-volatile polarization states at room temperature within a ferroelectric transistor, and the improved test resolution has the potential to further exponentially increase the number of states, laying a solid foundation for efficient memory computing and edge hardware implementation at the atomic scale.

[0084] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless defined as herein.

[0085] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A ferroelectric transistor capable of generating thousands of polarization states, characterized in that, The ferroelectric transistor has a vertically stacked structure, which consists of graphene sheets, hBN sheets and silicon substrates from top to bottom. The graphene sheets and hBN sheets are bonded together by van der Waals forces to form a graphene / hBN heterojunction. The hBN sheet is fixed to the upper surface of the silicon substrate; The upper surface of the silicon substrate is provided with metal electrodes, namely the source and the drain, which are respectively connected to both ends of the graphene sheet. A gate is provided on the lower surface of the silicon wafer substrate; The ferroelectric transistor, capable of generating thousands of polarization states, applies a sequence of DC pulses to the drain to excite the graphene channel, enabling the tuning of at least 36 non-volatile ferroelectric polarization states, reflected as different, time-stable resistance levels in the graphene channel. By simultaneously applying DC pulses to the drain and presetting different gate voltages, carrier injection and discharge into the graphene channel can be controlled, thereby reversibly adjusting the Fermi level of graphene between at least 84 doping levels, reflected as different, time-stable Dirac point positions in the graphene transport curve. Under each graphene Fermi level condition, reversible control of at least 36 ferroelectric polarization states can be achieved by applying a sequence of electrical pulses to the drain, thus increasing the number of ferroelectric polarization states that can be generated within a single device to several thousand.

2. The ferroelectric transistor capable of generating thousands of polarization states according to claim 1, characterized in that, The thickness of the graphene sheet is 0.3~2 nm, and the thickness of the hBN sheet is 20 nm.

3. The fabrication method for ferroelectric transistors capable of generating thousands of polarization states as described in claim 1, characterized in that, Includes the following steps: Step 1), strips of graphene and hBN are peeled off and placed on different silicon substrates. Step 2), prepare the PPC / PDMS transfer vector; Step 2.1): Cut the PDMS and place it on a clean glass slide, then use oxygen plasma to treat the surface of the PDMS. Step 2.2): Spin-coat the PPC reagent onto the PDMS surface, then heat it on a hot stage until a PPC film is formed; Step 2.3) Surface treatment of PPC film is performed using oxygen plasma to obtain PPC / PDMS transfer carrier; Step 3), prepare a PC film and cover the PC film onto the PPC / PDMS transfer carrier to obtain a PC / PPC / PDMS dry transfer carrier; Step 4): At a preset threshold temperature, the PC film of the PC / PPC / PDMS dry transfer carrier is covered onto the graphene sheet. The PC / PPC / PDMS dry transfer carrier is slowly lifted to detach the target graphene sheet from the silicon substrate. Then, the graphene sheet is attached to the hBN sheet on the silicon substrate. The heat is then released to allow the heat of melting of the PPC / PC film to dissipate onto the silicon substrate. Next, the PDMS carrier is slowly removed to form a graphene / hBN heterojunction on the silicon substrate. Finally, the PPC and PC on the surface of the graphene / hBN heterojunction and the silicon substrate are cleaned. Step 5), place the graphene / hBN heterojunction on the silicon substrate horizontally so that the graphene sheet is on top; Step 6) Spin-coating PMMA onto the surface of a silicon substrate at a speed higher than a preset speed threshold, and then heating until the solvent in the PMMA evaporates to form a PMMA layer; Step 7), repeat step 6) until the PMMA layer on the upper surface of the silicon substrate covers the graphene sheet; Step 8) The source and drain electrodes are exposed on the PMMA layer using a field emission electron microscope and an electron beam exposure system. Then, development is performed to expose the source and drain areas. Finally, Ti / Au is deposited on the source and drain areas using an electron beam deposition device. Step 9) Perform post-processing to remove the metal thin layer carried by PMMA in the unexposed area; then clean and dry to obtain a quasi-ferroelectric transistor with source and drain electrodes; Step 10): Lead wires from the lower surface of the silicon substrate as gates to obtain a graphene / hBN ferroelectric transistor.

4. The method for fabricating ferroelectric transistors capable of generating thousands of polarization states according to claim 3, characterized in that, The detailed steps for peeling off the graphene and hBN sheets in step 1) are as follows: Step 1.1) Clean the silicon wafer using an oxygen plasma system to increase the adhesion between the silicon wafer and the graphene and hBN wafers; Step 1.2), use blue tape to stick a small amount of graphene crystals and hBN crystals respectively, and then cover the silicon wafer with the tape; Step 1.3), the silicon wafer covered with blue tape is placed on a hot table to heat it to enhance the adhesion between the tape and the silicon wafer; Step 1.4): Remove the silicon wafer covered with blue tape from the hot stage. After cooling, slowly peel off the blue tape and mechanically peel it off to obtain graphene sheets and hBN sheets.

5. The method for fabricating ferroelectric transistors capable of generating thousands of polarization states according to claim 3, characterized in that, The detailed steps for preparing the PC film in step 3) are as follows: PC reagent is dropped onto the upper surface of slide 1. Then, the lower surface of slide 2 is placed over the upper surface of slide 1. Finally, slides 1 and 2 are horizontally dragged to separate them, thereby forming a PC film on the upper surface of slide 1 and the lower surface of slide 2 respectively.

6. The method for fabricating ferroelectric transistors capable of generating thousands of polarization states according to claim 3, characterized in that, The PPC reagent has a mass fraction of 15% and the solvent is anisole.

7. The method for fabricating ferroelectric transistors capable of generating thousands of polarization states according to claim 5, characterized in that, The PC reagent has a mass fraction of 5% and the solvent is dichloromethane.

8. The method for fabricating a ferroelectric transistor capable of generating thousands of polarization states according to claim 3, characterized in that, In step 4), when cleaning the PPC and PC on the surface of the graphene / hBN heterojunction and silicon substrate, they are placed in dichloromethane for 20 min, acetone for 15 min, and isopropanol for 5 min in sequence for cleaning.

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