Radiation-proof VDMOS device integrated with interval doping structure and preparation method of radiation-proof VDMOS device

Abstract

The invention discloses an anti-radiation VDMOS device integrated with an interval doping structure and a preparation method of the anti-radiation VDMOS device. The anti-radiation VDMOS device comprises body regions which are located in an epitaxial layer and located on the two sides of the epitaxial layer in the first direction, and the first direction is perpendicular to the stacking direction of a substrate layer, a buffer layer and the epitaxial layer; the hole doping region and the source doping region are located in the body region; the interval doping injection region is located in the epitaxial layer and located between the body regions in the first direction, the doping type of the source doping region is different from the doping type of the interval doping injection region, and the doping type of the body regions, the doping type of the hole doping region and the doping type of the interval doping injection region are the same; the gate oxide layer is located on the upper surface of the epitaxial layer, the lower surface of the gate oxide layer is in contact with part of the upper surfaces of the body region, the epitaxial layer and the source doping region, and the interval doping injection regions are distributed in the region where the gate oxide layer is located at intervals and are not in contact with the gate oxide layer; and the polycrystalline silicon layer covers the upper surface of the gate oxide layer. The anti-radiation capability of the device can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor radiation resistance, and in particular relates to a radiation-resistant VDMOS device with an integrated interval doping structure and a preparation method thereof. Background Art

[0002] There are a large number of X-rays, gamma rays, neutrons, heavy particles, etc. in outer space. Spacecraft will be irradiated by such rays and particles when operating in space, causing disturbances in the spacecraft's electronic systems, and even causing the electronic systems to fail, seriously affecting the safe operation of the spacecraft in orbit. As one of the core components of the secondary DC / DC (Direct Current-Direct Current) power supply for satellites, the vertical double-diffused power MOSFET (full name in English: Vertical Double-Diffused-Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as VDMOS) device plays the role of power conversion or power transformation in the power supply system, providing the necessary energy for the normal operation of the satellite electronic system. X-ray and gamma-ray radiation power VDMOS devices mainly experience total ionizing radiation dose effects, causing device parameter drifts; neutron radiation power VDMOS devices mainly cause an increase in the device's own power consumption, which can be solved through redundant design; and heavy particle radiation power VDMOS devices will experience single event gate rupture (SEGR) and single event burnout (SEB) effects, causing device failure and making the electronic system lose its function, especially for power VDMOS devices based on micron / submicron manufacturing processes and planar structures. Single particle radiation hardening of power VDMOS devices has become one of the bottlenecks and shortcomings restricting the development of satellite power technology, information security control, and independent assurance of core components.

[0003] At present, the measures for VDMOS single particle effect reinforcement are mainly to reasonably set the buffer doping concentration, p-body doping concentration, N-source doping concentration, narrow neck area, etc. Although the use of existing technologies can improve the radiation resistance of VDMOS to a certain extent, for high-voltage and ultra-high-voltage power VDMOS devices, such as 600V VDMOS, the existing reinforcement measures cannot meet the device's single particle gate penetration requirements due to the limit capacity of the gate oxide layer; and the existing reinforcement measures will affect the performance indicators of the power VDMOS device itself to a certain extent, such as on-resistance, conduction loss, etc. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a radiation-resistant VDMOS device with an integrated spaced-doping structure and a preparation method thereof.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a radiation-resistant VDMOS device with an integrated spaced-doping structure, comprising:

[0007] A substrate layer, a buffer layer and an epitaxial layer are stacked in sequence;

[0008] A body region located in the epitaxial layer and on both sides of the epitaxial layer along a first direction, wherein the first direction is perpendicular to a stacking direction of the substrate layer, the buffer layer and the epitaxial layer;

[0009] a hole doping region and a source doping region located in the body region;

[0010] an interval doping implantation region located in the epitaxial layer, wherein along the first direction, the interval doping implantation region is located between the body regions, and the source doping region and the interval doping implantation region have different doping types, and the body region, the hole doping region and the interval doping implantation region have the same doping type;

[0011] A gate oxide layer located on the upper surface of the epitaxial layer, and having a lower surface in contact with the body region, the epitaxial layer and a portion of the upper surface of the source doping region, and the spacer doping implantation regions are spaced apart in the region where the gate oxide layer is located and do not contact the gate oxide layer;

[0012] A polysilicon layer covers the upper surface of the gate oxide layer.

[0013] The present invention also provides a method for preparing a radiation-resistant VDMOS device with an integrated spaced-doping structure, comprising:

[0014] S1, select the substrate layer;

[0015] S2, growing a buffer layer on the upper surface of the substrate layer, and growing an epitaxial layer on the upper surface of the buffer layer;

[0016] S3, forming body regions on both sides of the epitaxial layer along a first direction, wherein the first direction is perpendicular to a stacking direction of the substrate layer, the buffer layer, and the epitaxial layer;

[0017] S4, forming a hole doping region in each body region, and forming an interval doping implantation region in the epitaxial layer, wherein along the first direction, the interval doping implantation region is located between the body regions;

[0018] S5, growing a gate oxide layer on the epitaxial layer, wherein the body region and a portion of the upper surface of the epitaxial layer are in contact with the lower surface of the gate oxide layer, and the spaced doping implantation regions are spaced apart in the region where the gate oxide layer is located and are not in contact with the gate oxide layer;

[0019] S6, depositing a polysilicon layer on the gate oxide layer;

[0020] S7. Form a source doping region in each body region, wherein a portion of the upper surface of the source doping region contacts the lower surface of the gate oxide layer, the source doping region and the interval doping injection region have different doping types, and the body region, the hole doping region and the interval doping injection region have the same doping type.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The present invention enables the gate oxide layer to be separated by making the interval doping injection regions be distributed at intervals in the region where the gate oxide layer is located and not contacting the gate oxide layer, and forms the interval doping injection regions arranged at intervals in the region where the gate oxide layer is separated, while there is no interval doping injection region in the region where the gate oxide layer is not separated. Compared with the traditional VDMOS device, on the one hand, when the VDMOS device encounters heavy ion radiation, under the same bias condition, the accumulation amount of carriers under the gate oxide layer region after particle incidence is reduced, thereby reducing the electric field strength of the gate oxide layer during the particle incidence process, and improving the SEGR resistance capability of the VDMOS device; on the other hand, the interval doping injection regions of the VDMOS device are preferentially broken down under a larger electric field, forming a current shunt, thereby reducing the current passing through the base resistance of the parasitic transistor, and reducing the probability of SEB. In addition, the present invention makes the spaced doping injection regions spaced and distributed in the region where the gate oxide layer is located, and does not contact the gate oxide layer, so as not to significantly reduce the flow path area of ​​the current during forward conduction, thereby further improving the device's single particle radiation resistance capability without changing the performance indicators of the VDMOS device itself; and this design reduces the area of ​​the gate of the VDMOS device, reduces the gate-drain capacitance Cgd, further improves the switching speed and switching loss of the VDMOS device, and improves the power conversion efficiency of the entire power supply system where the VDMOS device is located.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of a three-dimensional cross-sectional structure of a radiation-resistant VDMOS device with an integrated spaced doping structure provided by an embodiment of the present invention;

[0025] Figure 2 It is a vertical projection diagram of the gate oxide layer and the spacer doping implantation region when the gate oxide layer includes two connecting parts provided by an embodiment of the present invention;

[0026] Figure 3 It is a flow chart of a method for preparing a radiation-resistant VDMOS device with an integrated spaced-doping structure provided by an embodiment of the present invention;

[0027] Figure 4a to Figure 4g is a schematic diagram of the cross-sectional structure of a device prepared in each step of the preparation method provided in an embodiment of the present invention;

[0028] Figure 5 It is a schematic diagram comparing the gate oxide electric field of the radiation-resistant VDMOS device provided by an embodiment of the present invention and the conventional radiation-resistant VDMOS device at the same time after incident light at 1.5 μm under the same bias condition;

[0029] Figure 6 It is a comparison diagram of the secondary breakdown voltage of the radiation-resistant VDMOS device provided by the embodiment of the present invention and the traditional radiation-resistant VDMOS device. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0031] The present invention provides a radiation-resistant VDMOS device with an integrated spaced-doping structure, comprising:

[0032] A substrate layer 1, a buffer layer 2 and an epitaxial layer 3 are stacked in sequence;

[0033] A body region 4 located in the epitaxial layer 3 and on both sides of the epitaxial layer 3 along a first direction, wherein the first direction is perpendicular to a stacking direction of the substrate layer 1, the buffer layer 2 and the epitaxial layer 3;

[0034] a hole doping region 5 and a source doping region 6 located in the body region 4;

[0035] An interval doping implantation region 10 is located in the epitaxial layer 3, wherein the interval doping implantation region 10 is located between the body regions 4 along the first direction, and the source doping region 6 and the interval doping implantation region 10 have different doping types, and the body region 4 and the hole doping region 5 have the same doping type as the interval doping implantation region 10;

[0036] A gate oxide layer 8 is located on the upper surface of the epitaxial layer 3, and the lower surface of which is in contact with the body region 4, the epitaxial layer 3 and a portion of the upper surface of the source doping region 6, and the interval doping implantation regions 10 are spaced apart and distributed in the region where the gate oxide layer 8 is located, and do not contact the gate oxide layer 8;

[0037] A polysilicon layer 9 covers the upper surface of the gate oxide layer 8 .

[0038] The radiation-resistant VDMOS device with an integrated interval doping structure provided by the present invention can be an N-channel radiation-resistant VDMOS device or a P-channel radiation-resistant VDMOS device. When the radiation-resistant VDMOS device with an integrated interval doping structure provided by the present invention is an N-channel radiation-resistant VDMOS device, the substrate layer 1 is an N-type substrate, the doping types of the body region 4, the hole doping region 5 and the interval doping injection region 10 are all P, and the doping type of the source doping region 6 is N, that is, the N-channel radiation-resistant VDMOS device provided by the present invention includes: an N-type substrate 1, a P-body region 4, a hole P+ region 5, a spacer P+ region 10 and a source N+ region 6. When the radiation-resistant VDMOS device with an integrated interval doping structure provided by the present invention is a P-channel radiation-resistant VDMOS device, the substrate layer 1 is a P-type substrate, the doping types of the body region 4, the hole doping region 5 and the interval doping injection region 10 are all N, and the doping type of the source doping region 6 is P, that is, the P-channel radiation-resistant VDMOS device provided by the present invention includes: a P-type substrate 1, an N-body region 4, a hole N+ region 5, a interval N+ region 10 and a source P+ region 6.

[0039] The radiation-resistant VDMOS device with integrated spaced doping structure provided by the present invention further comprises:

[0040] An interlayer dielectric layer 7 covering the polysilicon layer 9, a portion of the source doping region 6 and a portion of the spacer doping implantation region 10, wherein the interlayer dielectric layer 7 has a contact hole extending downward from the upper surface of the interlayer dielectric layer 7 to the upper surface of the spacer doping implantation region 10;

[0041] A source metal layer 11 covering the interlayer dielectric layer 7, the hole doping region 5 and the contact hole, and the source metal layer 11 is in contact with the upper surface of the spacer doping implantation region 10, and the source metal layer 11 is also in contact with the upper surface of the portion of the source doping region 6 not covered by the interlayer dielectric layer 7;

[0042] The drain metal layer 12 is located on the lower surface of the substrate layer 1 .

[0043] In the present invention, the gate oxide layer 8 includes: a first part, a second part and at least one connecting part, each connecting part is used to connect the first part and the second part, wherein the interval doping injection region 10 is arranged between at least one connecting part, and does not contact the lower surface of each connecting part. Specifically, when the gate oxide layer 8 includes a plurality of connecting parts, different connecting parts are used to connect different regions of the first part and the second part. At this time, the interval doping injection region 10 is arranged between two adjacent connecting parts, and does not contact the lower surface of each connecting part; for example, it can be arranged between two adjacent connecting parts, or between every two adjacent connecting parts, and does not contact the lower surface of each connecting part. When the gate oxide layer 8 includes one connecting part, the interval doping injection region 10 is arranged on both sides of the connecting part that do not connect the first part and the second part. Exemplarily, Figure 1 A three-dimensional cross-sectional structure schematic diagram of the radiation-resistant VDMOS device with integrated spaced doping structure provided by the present invention, and Figure 1 FIG. 1 shows a partial structure of the VDMOS device. To clearly show the structure of the VDMOS device, Figure 1 The dotted area in the figure represents the interlayer dielectric layer 7, and the source metal layer 11, the drain metal layer 12 and the conventional passivation layer are not shown. Figure 1 As shown, when the gate oxide layer 8 includes a first portion 81, a second portion 82 and a connecting portion 83, the vertical projection of the region where the gate oxide layer 8 is located is in an "H" shape, and the spaced doping implantation region 10 is located in the region where the gate oxide layer 8 is not distributed in the "H"-shaped region. Exemplarily, Figure 2 When the gate oxide layer 8 includes two connecting parts 83a and 83b, the vertical projection diagram of the gate oxide layer 8 and the spacer doping implantation region 10 is shown. Figure 2 As shown, three spaced doping implant regions 10a, 10b and 10c are spaced apart and distributed between the connecting portions 83a and 83b.

[0044] In the present invention, the hole doping region 5 and the source doping region 6 in each body region 4 are cross-distributed, and one side is in contact with each other. In the present invention, the hole doping region 5 and the source doping region 6 in each body region 4 are cross-distributed, which can reduce the area of ​​the source doping region 6, reduce the injection efficiency of the emitter of the parasitic transistor, and thus reduce the probability of the parasitic transistor being turned on. Combined with the above-mentioned design of the interval doping injection region, the probability of SEB occurring in the VDMOS device after single particle incidence is finally further reduced.

[0045] For example, along the first direction, the hole-doped region 5 has a plurality of protruding portions, and correspondingly, the source-doped region 6 also has a plurality of protruding portions, and a protruding portion of the source-doped region 6 is embedded between two adjacent protruding portions of the hole-doped region 5, or a protruding portion of the source-doped region 6 is embedded between every two adjacent protruding portions of the hole-doped region 5; accordingly, the portion of the source-doped region 6 not covered by the interlayer dielectric layer 7 is each protruding portion in the source-doped region 6, or a portion of each protruding portion in the source-doped region 6. Exemplarily, the above Figure 1 A distribution mode between the hole doping region 5 and the source doping region 6 in each body region 4, and between the source doping region 6 and the interlayer dielectric layer 7 is shown, such as Figure 1 As shown, a protrusion of the source doping region 6 is embedded between every two adjacent protrusions of the hole doping region 5, and the portion of the source doping region 6 not covered by the interlayer dielectric layer 7 is a part of each protrusion of the source doping region 6. In some embodiments, the vertical projection of the source doping region 6 in each body region 4 may be in a "bow" shape.

[0046] The present invention allows the interval doping injection regions to be distributed at intervals in the region where the gate oxide layer is located and not to contact the gate oxide layer, so that the gate oxide layer can be separated, and interval doping injection regions arranged at intervals are formed in the region where the gate oxide layer is separated, while there is no interval doping injection region in the region where the gate oxide layer is not separated. Compared with the traditional VDMOS device, on the one hand, when the VDMOS device encounters heavy ion radiation, under the same bias condition, the accumulation of carriers below the gate oxide layer region after particle incidence is reduced, thereby reducing the electric field strength of the gate oxide layer during particle incidence and improving the SEGR resistance of the VDMOS device; on the other hand, the interval doping injection regions of the VDMOS device are preferentially broken down under a larger electric field to form a current shunt, thereby reducing the current passing through the base resistance of the parasitic transistor and reducing the probability of SEB; at the same time, the hole doping region 5 in each body region 4 is cross-distributed with the source doping region 6, so that the area of ​​the source doping region 6 can be reduced, the injection efficiency of the emitter of the parasitic transistor is reduced, thereby reducing the probability of the parasitic transistor being turned on, and finally further reducing the probability of SEB occurring in the VDMOS device after single particle incidence. In addition, the present invention makes the spaced doping injection regions spaced and distributed in the region where the gate oxide layer is located, and does not contact the gate oxide layer, so as not to significantly reduce the flow path area of ​​the current during forward conduction, thereby further improving the single particle radiation resistance of the device without changing the performance indicators of the VDMOS device itself; and this design reduces the area of ​​the gate of the VDMOS device, reduces the gate-drain capacitance Cgd, further improves the switching speed and switching loss of the VDMOS device, and improves the power conversion efficiency of the entire power supply system where the VDMOS device is located.

[0047] The present invention also provides a method for preparing a radiation-resistant VDMOS device with an integrated spaced doping structure, and the method is used to prepare the above-mentioned radiation-resistant VDMOS device with an integrated spaced doping structure. Figure 3 As shown, the method includes:

[0048] Step S1, selecting substrate layer 1.

[0049] Exemplarily, the substrate layer 1 is a Si substrate, and has a thickness of 715 μm to 735 μm and a resistivity of 0.002 Ω.cm to 0.006 Ω.cm.

[0050] Specifically, when preparing an N-channel radiation-resistant VDMOS device, an N-type Si substrate is selected, and when preparing a P-channel radiation-resistant VDMOS device, a P-type Si substrate is selected.

[0051] Step S2 , growing a buffer layer 2 on the upper surface of the substrate layer 1 , and growing an epitaxial layer 3 on the upper surface of the buffer layer 2 .

[0052] Specifically, several buffer layers with different doping concentrations and thicknesses can be grown on the upper surface of the substrate layer 1. For example, the resistivity of the buffer layer 2 is 0.01Ω.cm to 0.5Ω.cm, the thickness of the buffer layer 2 is 20μm to 50μm, and the number of buffer layers is 2 to 5. For example, the resistivity of the epitaxial layer 3 is 2Ω.cm to 10Ω.cm, and the thickness is 5μm to 20μm.

[0053] Specifically, when preparing an N-channel radiation-resistant VDMOS device, an N-type buffer layer is grown on the upper surface of the substrate layer, and when preparing a P-channel radiation-resistant VDMOS device, a P-type buffer layer is grown on the upper surface of the substrate layer.

[0054] For example, Figure 4a It is a schematic diagram of the cross-sectional structure of the device prepared in step S2.

[0055] Step S3 , forming body regions 4 on both sides of the epitaxial layer 3 along a first direction, wherein the first direction is perpendicular to the stacking direction of the substrate layer 1 , the buffer layer 2 and the epitaxial layer 3 .

[0056] Specifically, when preparing an N-channel radiation-resistant VDMOS device, photoresist may be spin-coated on the surface of the wafer obtained in step S2, and then, a mask is used for exposure and development to obtain a body pattern window, and boron ions are implanted into the body pattern window.

[0057] Specifically, when preparing a P-channel radiation-resistant VDMOS device, photoresist may be spin-coated on the surface of the wafer obtained in step S2, and then, a mask is used for exposure and development to obtain a body pattern window, and phosphorus ions are implanted into the body pattern window.

[0058] For example, the energy is 100KeV to 300KeV, and the implantation dose is 1×10 13 ~4×10 13 .

[0059] For example, Figure 4b It is a schematic diagram of the cross-sectional structure of the device prepared in step S3.

[0060] Step S4 , forming a hole doping region 5 in each body region 4 , and forming an interval doping implantation region 10 in the epitaxial layer 3 , wherein the interval doping implantation region 10 is located between the body regions 4 along the first direction.

[0061] In some embodiments, step S4 may be implemented by step S41:

[0062] Step S41, through photolithography and implantation processes, a hole doping region 5 is formed in each body region 4 at one time, and an interval doping implantation region 10 is formed in the epitaxial layer 3 between the body regions 4, wherein the hole doping region 5 and the interval doping implantation region 10 have the same doping concentration.

[0063] Specifically, photoresist may be spin-coated on the surface of the wafer obtained in step S3, and then, a mask plate may be used for exposure and development to obtain a hole doping pattern window in each body region 4 and an interval doping injection window on the upper surface of the epitaxial layer 3 between the body regions 4, and then, boron ions may be injected into the hole doping pattern window and the interval doping injection window at the same time. Exemplarily, the injection energy is 100KeV to 300KeV, and the injection dose is 1×10 14 ~5×10 15 .

[0064] In some embodiments, step S4 may be implemented by steps S42 to S43:

[0065] Step S42 : forming a hole-doped region 5 in each body region 4 by photolithography and implantation processes.

[0066] Specifically, photoresist may be spin-coated on the surface of the wafer obtained in step S42, and then, a mask plate may be used for exposure and development to obtain a hole doping pattern window in each body region 4, and then, boron ions may be implanted in the hole doping pattern window. For example, the implantation energy is 100 KeV to 300 KeV, and the implantation dose is 1×10 14 ~5×1015 .

[0067] For example, Figure 4c It is a schematic diagram of the cross-sectional structure of the device prepared in step S42.

[0068] Step S43 , forming an interval doping implantation region 10 in the epitaxial layer 3 between the body regions 4 by photolithography and implantation processes, wherein the hole doping region 5 and the interval doping implantation region 10 have different or same doping concentrations.

[0069] Specifically, photoresist may be spin-coated on the surface of the wafer obtained in step S43, and then, a mask plate may be used for exposure and development, and an interval doping injection window may be obtained on the upper surface of the epitaxial layer 3 between the body regions 4, and boron ions may be injected into the interval doping injection window. For example, the injection energy is 100 KeV to 300 KeV, and the injection dose is 1×10 14 ~5×10 15 .

[0070] For example, Figure 4d It is a schematic diagram of the cross-sectional structure of the device prepared in step S43.

[0071] In some embodiments, after step S2 and before step S3, step S21 may be further included:

[0072] Step S21 : forming a JFET region in the central area of ​​the epitaxial layer 3 .

[0073] Specifically, when preparing an N-channel radiation-resistant VDMOS device, photoresist is spin-coated on the surface of the wafer obtained in step S2, and then, a mask is used for exposure and development to obtain a JFET injection pattern window, and then, phosphorus ions are injected into the JFET injection pattern window.

[0074] Specifically, when preparing a P-channel radiation-resistant VDMOS device, photoresist is spin-coated on the surface of the wafer obtained in step S2, and then exposed and developed using a mask to obtain a JFET injection pattern window, and then boron ions are injected into the JFET injection pattern window.

[0075] For example, the implantation energy is 200KeV to 400KeV, and the implantation dose is 2×10 12 ~2×10 13 .

[0076] Step S5, growing a gate oxide layer 8 on the epitaxial layer 3, wherein the body region 4 and a portion of the upper surface of the epitaxial layer 3 are in contact with the lower surface of the gate oxide layer 8, and the spaced doping implantation regions 10 are spaced apart and distributed in the region where the gate oxide layer 8 is located, and are not in contact with the gate oxide layer 8.

[0077] Step S6 , depositing a polysilicon layer 9 on the gate oxide layer 8 .

[0078] Specifically, the surface of the wafer obtained in step S4 is thermally oxidized to grow a gate oxide layer 8, and then a polysilicon layer 9 is deposited on the gate oxide layer 8. Then, a photoresist is spin-coated on the surface of the obtained wafer, and then, a mask is used for exposure and development to obtain a pattern window, and etching is performed according to the pattern window. Exemplarily, the position and shape of the gate oxide layer 8 and the polysilicon layer 9 after etching are as described above. Figure 1 shown.

[0079] Exemplarily, the thickness of the gate oxide layer 8 is 50 nm to 120 nm, and the thickness of the polysilicon layer 9 is 500 nm to 1000 nm.

[0080] Step S7, forming a source doping region 6 in each body region 4, wherein a portion of the upper surface of the source doping region 6 contacts the lower surface of the gate oxide layer 8, the source doping region 6 and the interval doping injection region 10 have a different doping type, and the body region 4, the hole doping region 5 and the interval doping injection region 10 have the same doping type.

[0081] Specifically, the wafer surface obtained in step S4 is spin-coated with photoresist, and then, a mask is used for exposure and development to obtain a source doping region pattern window on each body region 4, and then, arsenic ions are implanted into each source doping region pattern window. Exemplarily, the implantation energy is 100KeV to 200KeV, and the implantation dose is 9×10 14 ~5×10 15 .

[0082] For example, Figure 4e It is a schematic diagram of the cross-sectional structure of the device prepared in step S7.

[0083] The method for preparing the radiation-resistant VDMOS device with integrated spaced doping structure provided by the present invention further comprises:

[0084] Step S8, depositing an interlayer dielectric on the upper surface of the wafer obtained in step S7, and etching the deposited interlayer dielectric to expose the hole doping region 5, part of the source doping region 6 and part of the spacing doping injection region 10 and obtain contact holes to form an interlayer dielectric layer 7.

[0085] Specifically, a layer of silicon dioxide is deposited on the upper surface of the wafer obtained in step S7, and the thickness can be 600nm to 1000nm, and then a photoresist is spin-coated on the surface of the obtained wafer, and then a mask is used for exposure and development to obtain a contact hole pattern window, and etching is performed according to the contact hole pattern window to obtain a contact hole, and expose the hole doping region 5, part of the source doping region 6 and part of the spacer doping injection region 10. For example, the position and shape of the interlayer dielectric layer 7 are as described above. Figure 1 shown.

[0086] Step S9 , forming a source metal layer 11 on the upper surface of the wafer obtained in step S8 .

[0087] Specifically, a source metal is deposited on the upper surface of the wafer obtained in step S8. Exemplarily, the metal is Al with a thickness of 4μm to 6μm. After the source metal deposition is completed, photoresist is spin-coated on the obtained wafer surface, and then exposed and developed using a mask to obtain a metal interconnection line pattern window, and the source and gate are separated according to the metal interconnection line pattern window.

[0088] For example, Figure 4f It is a schematic diagram of the cross-sectional structure of the device prepared in step S9.

[0089] Step S10 , forming a drain metal layer 12 on the lower surface of the substrate layer 1 .

[0090] Specifically, a drain metal is deposited on the lower surface of the substrate layer 1 . Exemplarily, the deposited metals are Ti / Ni / Ag in sequence, with a thickness of 5 μm to 10 μm.

[0091] For example, Figure 4g It is a schematic diagram of the cross-sectional structure of the device prepared in step S10.

[0092] The following Figure 5 and Figure 6 The performance of the radiation-resistant VDMOS device with integrated spaced doping structure provided by the present invention is further described. Specifically, Figure 5 A schematic diagram comparing the gate oxide electric field (lateral direction) of the radiation-resistant VDMOS device provided by the present invention and the traditional radiation-resistant VDMOS device at the same moment after incident light at 1.5 μm under the same bias condition. Figure 6 The second breakdown voltage comparison diagram of the radiation-resistant VDMOS device provided by the present invention and the traditional radiation-resistant VDMOS device is shown in FIG. 1 , wherein the second breakdown voltage capability can characterize the SEB resistance capability of the device. Figure 5 and Figure 6As shown, the radiation-resistant VDMOS device provided by the present invention can reduce the accumulation of carriers under the gate oxide when the device encounters heavy ion radiation, and reduce the electric field strength of the gate oxide layer during particle incidence under the same bias conditions, thereby improving the device's SEGR resistance; and, after breakdown under a larger electric field, a portion of the current can be extracted to reduce the current passing through the base region of the parasitic transistor, thereby reducing the probability of SEB. Combined with the design of the source doping region, the emitter injection efficiency of the parasitic transistor is reduced, thereby reducing the probability of the parasitic transistor being turned on, further improving the device's SEB resistance, such as Figure 6 As shown, compared with the traditional VDMOS device, the secondary breakdown voltage capability of the radiation-resistant VDMOS device provided by the present invention is improved by 25V.

[0093] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0094] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0095] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0096] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A radiation-resistant VDMOS device with an integrated spacer doping structure, characterized in that: include: A substrate layer (1), a buffer layer (2) and an epitaxial layer (3) stacked in sequence; A body region (4) located in the epitaxial layer (3) and on both sides of the epitaxial layer (3) along a first direction, wherein the first direction is perpendicular to a stacking direction of the substrate layer (1), the buffer layer (2) and the epitaxial layer (3); a hole doping region (5) and a source doping region (6) located in the body region (4); an interval doping injection region (10) located in the epitaxial layer (3), wherein, along the first direction, the interval doping injection region (10) is located between the body regions (4), and the source doping region (6) and the interval doping injection region (10) have different doping types, and the body region (4), the hole doping region (5) and the interval doping injection region (10) have the same doping type; A gate oxide layer (8) located on the upper surface of the epitaxial layer (3), and having a lower surface in contact with the body region (4), the epitaxial layer (3) and a portion of the upper surface of the source doping region (6), and the spaced doping implantation regions (10) are spaced apart and distributed in the region where the gate oxide layer (8) is located, and are not in contact with the gate oxide layer (8); A polysilicon layer (9) covering the upper surface of the gate oxide layer (8).

2. The radiation-resistant VDMOS device with integrated spaced-doping structure according to claim 1, characterized in that: The gate oxide layer (8) comprises: a first portion, a second portion and at least one connecting portion, each connecting portion being used to connect the first portion and the second portion; Wherein, when the gate oxide layer (8) includes a plurality of connection parts, the plurality of connection parts are arranged at intervals between the first part and the second part, and the interval doping injection region (10) is arranged between two adjacent connection parts and does not contact the lower surface of each connection part; when the gate oxide layer (8) includes one connection part, the interval doping injection region (10) is arranged on both sides of the connection part that are not connected to the first part and the second part.

3. The radiation-resistant VDMOS device with integrated spaced-doping structure according to claim 2, characterized in that: When the gate oxide layer (8) comprises: the first part, the second part and a connecting part, a vertical projection of the region where the gate oxide layer (8) is located is in an "H" shape, and the interval doping implantation region (10) is located in a region of the "H"-shaped region where the gate oxide layer (8) is not distributed.

4. The radiation-resistant VDMOS device with integrated spaced-doping structure according to claim 1, characterized in that: The hole doping region (5) and the source doping region (6) in each body region (4) are cross-distributed and contact each other on one side.

5. The radiation-resistant VDMOS device with integrated spaced-doping structure according to claim 1, characterized in that: The radiation-resistant VDMOS device further comprises: an interlayer dielectric layer (7) covering the polysilicon layer (9), part of the source doping region (6) and part of the interval doping injection region (10), wherein the interlayer dielectric layer (7) has a contact hole, and the contact hole extends downward from the upper surface of the interlayer dielectric layer (7) to the upper surface of the interval doping injection region (10); a source metal layer (11) covering the interlayer dielectric layer (7), the hole doping region (5) and the contact hole, wherein the source metal layer (11) is in contact with an upper surface of the spacer doping injection region (10), and the source metal layer (11) is in contact with an upper surface of a portion of the source doping region (6) not covered by the interlayer dielectric layer (7); A drain metal layer (12) is located on the lower surface of the substrate layer (1).

6. The radiation-resistant VDMOS device with integrated spaced-doping structure according to claim 1, characterized in that: When the radiation-resistant VDMOS device is an N-channel radiation-resistant VDMOS device, the substrate layer (1) is an N-type substrate, the doping types of the body region (4), the hole doping region (5) and the interval doping injection region (10) are all P, and the doping type of the source doping region (6) is N; When the radiation-resistant VDMOS device is a P-channel radiation-resistant VDMOS device, the substrate layer (1) is a P-type substrate, the doping types of the body region (4), the hole doping region (5) and the interval doping injection region (10) are all N, and the doping type of the source doping region (6) is P.

7. A method for preparing a radiation-resistant VDMOS device with an integrated spacer doping structure, characterized in that: include: S1, selecting a substrate layer (1); S2, growing a buffer layer (2) on the upper surface of the substrate layer (1), and growing an epitaxial layer (3) on the upper surface of the buffer layer (2); S3, forming body regions (4) on both sides of the epitaxial layer (3) along a first direction, wherein the first direction is perpendicular to a stacking direction of the substrate layer (1), the buffer layer (2) and the epitaxial layer (3); S4, forming a hole doping region (5) in each body region (4), and forming an interval doping implantation region (10) in the epitaxial layer (3), wherein along the first direction, the interval doping implantation region (10) is located between the body regions (4); S5, growing a gate oxide layer (8) on the epitaxial layer (3), wherein the body region (4) and a portion of the upper surface of the epitaxial layer (3) are in contact with the lower surface of the gate oxide layer (8), and the spaced doping implantation regions (10) are spaced apart and distributed in the region where the gate oxide layer (8) is located, and are not in contact with the gate oxide layer (8); S6, depositing a polysilicon layer (9) on the gate oxide layer (8); S7. Forming a source doping region (6) in each body region (4), wherein a portion of the upper surface of the source doping region (6) is in contact with the lower surface of the gate oxide layer (8), the source doping region (6) and the interval doping injection region (10) have different doping types, and the body region (4), the hole doping region (5) and the interval doping injection region (10) have the same doping type.

8. The method for preparing the radiation-resistant VDMOS device with integrated spaced doping structure according to claim 7, characterized in that: The method further comprises: S8, depositing an interlayer dielectric on the upper surface of the wafer obtained in S7, and etching the deposited interlayer dielectric to expose the hole doping region (5), part of the source doping region (6) and part of the spacer doping injection region (10) and obtain contact holes, thereby forming an interlayer dielectric layer (7); S9, forming a source metal layer (11) on the upper surface of the wafer obtained in S8; S10, forming a drain metal layer (12) on the lower surface of the substrate layer (1).

9. The method for preparing the radiation-resistant VDMOS device with integrated spaced doping structure according to claim 7, characterized in that: The gate oxide layer (8) comprises: a first portion, a second portion and at least one connecting portion, each connecting portion being used to connect the first portion and the second portion; Wherein, when the gate oxide layer (8) includes a plurality of connection parts, the plurality of connection parts are arranged at intervals between the first part and the second part, and the interval doping injection region (10) is arranged between two adjacent connection parts and does not contact the lower surface of each connection part; when the gate oxide layer (8) includes one connection part, the interval doping injection region (10) is arranged on both sides of the connection part that are not connected to the first part and the second part.

10. The method for preparing the radiation-resistant VDMOS device with integrated spaced doping structure according to claim 7, characterized in that: The hole doping region (5) and the source doping region (6) in each body region (4) are cross-distributed and contact each other on one side.

Images