SiC MOS with better grid protection structure
By forming ohmic contact between the P-shield region and the N+ region in the SiC MOSFET device, the problem of easy breakdown of the gate oxide layer is solved, and good protection of the gate oxide layer of the SiC MOSFET device is achieved, and its reliability is improved.
Patent Information
- Application Number
- CN202422072689.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-08-26
AI Technical Summary
Due to the large interface state density and many defects in the SiC MOSFET device, the gate oxide layer is prone to early breakdown failure, which affects the long-term use reliability of the device.
When the device gate pressurization, the P-shield region and the N+ region are formed on the SiC Epi layer and the ohmic contact is formed on the top surface thereof to relieve the electrical stress pressure on the gate oxide layer and to shield the increase in leakage current.
It effectively protects the gate oxide layer of SiC MOSFET device, reduces the impact of electrical stress on it, and improves the reliability of the gate oxide layer of the device.
Smart Images
Figure CN222967305U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a SiC MOS with a better gate protection structure. Background Art
[0002] In voltage-controlled power switch devices, SiC MOSFET devices are considered to be the main products in the future in the high-voltage and high-power fields because they have a series of advantages such as high breakdown voltage, low on-state loss, high switching frequency, and low switching loss. At present, they have begun to gradually replace Si IGBT devices in many fields.
[0003] Although the performance advantages of SiC MOSFET devices are very significant, since the gate oxide layer inside the structure is directly grown by thermal oxidation, and compared with Si, the SiC material is rich in C element, the grown gate oxide layer has a large interface state density and many interface defects. The disadvantage is that the gate oxide layer is extremely prone to premature breakdown failure during the long-term use of the device. Therefore, SiC is used to protect the gate oxide layer in SiC MOSFET devices, and the quality of the gate oxide layer has always been the most difficult problem for SiC MOSFET devices. It can be seen that how to better protect the gate oxide layer in SiC MOSFET devices and avoid premature breakdown failure during use is crucial for the long-term stable use of the device. Summary of the Utility Model
[0004] In view of the above problems, the utility model provides a SiC MOS with a better gate protection structure, which can reduce the electrical stress on the gate oxide layer when a voltage is applied to the gate of the device, avoid the increase of Igss leakage current, and achieve a good protection effect on the gate oxide layer of the SiC MOSFET device.
[0005] The technical solution of the utility model is as follows:
[0006] A SiC MOS with a better gate protection structure includes a SiC Sub layer and a SiC Epi layer arranged from bottom to top;
[0007] On the SiC Epi layer are provided:
[0008] A P-body region extending downward from the top surface of the SiC Epi layer;
[0009] An NP region extending downward from the top surface of the P-body region;
[0010] A PP region extending downward from the top surface of the P-body region and connected to the NP region;
[0011] The P-shield region extends downward from the top surface of the P-body region and is spaced apart from the P-body region.
[0012] The N+ region extends downward from the top surface of the P-shield region.
[0013] The gate ohmic contact alloy layer is formed on the top surface of the P-shield region, and its bottom surface is connected to the P-shield region and the N+ region respectively.
[0014] The gate oxide layer is connected to the gate ohmic contact alloy layer, and its bottom surface is connected to the NP region, the P-body region and the SiC Epi layer respectively; the top surface of the gate oxide layer is lower than the bottom surface of the gate ohmic contact alloy layer.
[0015] The Poly layer is formed on the top surfaces of the gate oxide layer and the gate ohmic contact alloy layer.
[0016] The isolation dielectric layer wraps around the gate oxide layer and the Poly layer, and its side extends downward to be connected to the NP region.
[0017] The source ohmic contact alloy layer is formed on the side of the isolation dielectric layer, and its bottom surface is connected to the PP region and the NP region respectively.
[0018] The source metal layer is formed on the top surfaces of the source ohmic contact alloy layer and the isolation dielectric layer.
[0019] Specifically, the thickness of the gate oxide layer is 40nm - 60nm.
[0020] Specifically, the thickness of the Poly layer is 0.5um - 1.2um.
[0021] Specifically, the depth of the bottom surface of the P-shield region is 0.3um - 0.8um.
[0022] Specifically, the depth of the bottom surface of the N+ region is 0.5um - 1.2um.
[0023] Specifically, the P-shield region extends downward from the middle of the top surface of the P-body region.
[0024] Specifically, the N+ region extends downward from the middle of the top surface of the P-shield region.
[0025] Specifically, the bottom surface of the N+ region is lower than the bottom surface of the P-shield region.
[0026] Advantages of the present utility model - improving the reliability of the gate oxide layer of the device:
[0027] Due to the large interface state density and many defects at the interface between the gate oxide layer and SiC, the gate oxide layer of SiC MOSFET is extremely prone to premature breakdown failure, which affects the long-term reliability of the device. In the planar gate SiC MOSFET device of the present utility model, a P-shield region and an N+ region are formed by implantation at the bottom of the device gate, and ohmic contacts are formed on the top surfaces of the P-shield region and the N+ region to protect the device gate oxide layer. Due to the formation of ohmic contacts, when the device gate is pressurized, the gate voltage can achieve a certain degree of electrical stress discharge through the N+ region, thereby reducing the electrical stress on the gate oxide layer. The P-shield region can shield the current discharged from the N+ region, thus avoiding the increase of Igss leakage current. During the device blocking process, the P-shield region can also better shield the electric field concentration of the drain voltage on the gate oxide layer, thereby achieving a good protection effect on the gate oxide layer of the SiC MOSFET device and improving the reliability of the device gate oxide layer. Brief Description of the Drawings
[0028] Figure 1 is a schematic structural diagram of the SiC MOSFET of the present utility model;
[0029] Figure 2 is a schematic structural diagram of step S100 of the present utility model;
[0030] Figure 3 is a schematic structural diagram of step S200 of the present utility model;
[0031] Figure 4 is a schematic structural diagram of step S300 of the present utility model;
[0032] Figure 5 is a schematic structural diagram of step S400 of the present utility model;
[0033] Figure 6 is a schematic structural diagram of step S500 of the present utility model;
[0034] Figure 7 is a schematic structural diagram of step S600 of the present utility model;
[0035] Figure 8 is a schematic structural diagram of step S800 of the present utility model;
[0036] Figure 9 is a schematic structural diagram of step S900 of the present utility model;
[0037] Figure 10 is a schematic structural diagram of step S1000 of the present utility model;
[0038] Figure 11 is a schematic structural diagram of step S1100 of the present utility model;
[0039] Figure 12 It is a schematic structural diagram of step S1200 of the present utility model;
[0040] Figure 13 It is a schematic structural diagram of step S1300 of the present utility model;
[0041] Figure 14 It is a schematic structural diagram of step S1400 of the present utility model;
[0042] In the figure, 1 is the SiC Sub layer, 2 is the SiC Epi layer, 3 is the P-body region, 4 is the NP region, 5 is the PP region, 6 is the P-shield region, 7 is the N+ region, 8 is the gate ohmic contact alloy layer, 9 is the gate oxide layer, 10 is the Poly layer, 11 is the isolation dielectric layer, 12 is the source ohmic contact alloy layer, 13 is the source metal layer, 14 is the drain ohmic contact alloy layer, and 15 is the source metal layer. Specific embodiments
[0043] The present utility model will be described in detail below in combination with specific actual cases. The examples of the embodiments are shown in the drawings, and the schematic embodiments of the present utility model and their descriptions are only used to explain the present utility model and do not constitute a limitation to the present utility model.
[0044] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality of" is two or more.
[0045] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.
[0046] A method for preparing a SiC MOS with a better gate protection structure includes the following steps:
[0047] S100, epitaxially grow a SiC Epi layer 2 on the SiC Sub layer 1; Refer toFigure 2 as shown;
[0048] In step S100, the thickness of the SiC Sub layer 1 is 150um - 400um, and the doping concentration is 1E19 cm -2 , the thickness of the SiC Epi layer 2 is 5um - 18um, and the doping concentration is 5E16 - 1.2E16 cm -2 .
[0049] S200, initially form the P-body region 3 on the top surface of the SiC Epi layer 2 by oblique ion implantation; refer to Figure 3 as shown;
[0050] In step S200, the implanted ions for the P-body region 3 are Al ions, the bottom depth is 1um - 1.2um, and the doping concentration is 1E17 - 3E18 cm -2 .
[0051] S300, initially form the NP region 4 on the top surface of the P-body region 3 by oblique ion implantation; refer to Figure 4 as shown;
[0052] In step S300, the implanted ions for the NP region 4 are N ions, the bottom depth is 0.3um - 0.6um, and the doping concentration is 1E18 - 1E19 cm -2 .
[0053] S400, initially form the PP region 5 on the top surface of the P-body region 3 by oblique ion implantation; refer to Figure 5 as shown;
[0054] In step S400, the implanted ions for the PP region 5 are Al ions, the bottom depth is 0.5um - 1um, and the doping concentration is 1E18 - 1E19 cm -2 .
[0055] S500, initially form the P-shield region 6 on the top surface of the SiC Epi layer 2 by oblique ion implantation; refer to Figure 6 as shown;
[0056] In step S500, the implanted ions for the P-shield region 6 are Al ions, the bottom depth is 0.3um - 0.8um, and the doping concentration is 1E17 - 5E18 cm -2 .
[0057] S600, initially form the N+ region 7 on the top surface of the P-shield region 6 by oblique ion implantation; refer to Figure 7 as shown;
[0058] The ions implanted in the N+ region 7 in step S600 are N ions, the bottom depth is 0.5 um - 1.2 um, and the doping concentration is 1E18 - 1E19 cm -2 .
[0059] S700, through high-temperature ion activation, the implanted regions of the P-body region 3, NP region 4, PP region 5, P-shield region 6, and N+ region 7 are completely formed;
[0060] The high-temperature activation annealing temperature in step S700 is 1600 °C - 1900 °C.
[0061] S800, on the top surfaces of the P-shield region 6 and N+ region 7, a gate ohmic contact alloy layer 8 is formed through Ni metal sputtering followed by thermal annealing; refer to Figure 8 as shown;
[0062] The thickness of the Ni metal in step S800 is 0.1 um - 0.3 um.
[0063] S900, on the top surfaces of the SiC Epi layer 2, NP region 4, and P-shield region 6, a gate oxide layer 9 is grown through dry oxidation; refer to Figure 9 as shown;
[0064] The thickness of the gate oxide layer 9 in step S900 is 40 nm - 60 nm.
[0065] S1000, on the top surfaces of the gate ohmic contact alloy layer 8 and gate oxide layer 9, a Poly layer 10 is formed through polysilicon deposition and is used as the gate voltage path of the device; refer to Figure 10 as shown;
[0066] The thickness of the Poly layer 10 in step S1000 is 0.5 um - 1.2 um.
[0067] S1100, on the top surfaces of the NP region 4 and Poly layer 10, an isolation dielectric layer 11 is formed through oxide deposition and is used as the dielectric for isolating the gate electrode and source electrode of the device; refer to Figure 11 as shown;
[0068] S1200, on the top surfaces of the NP region 4 and PP region 5, a source ohmic contact alloy layer 12 is formed through Ni metal sputtering followed by thermal annealing; refer to Figure 12 as shown;
[0069] The thickness of the Ni metal in step S1200 is 0.1 um - 0.3 um.
[0070] S1300, on the topmost part of the device, a source metal layer 13 is formed through Ti and AlCu metal sputtering; refer to Figure 13 as shown;
[0071] The thickness of the Ti metal in step S1300 is 0.1 um - 0.3 um, and the thickness of the AlCu metal is 3 um - 5 um.
[0072] S1400, a drain ohmic contact alloy layer 14 is formed on the bottom surface of the SiC Sub layer 1 by Ni metal sputtering followed by laser annealing; refer to Figure 14 as shown;
[0073] The thickness of the Ni metal in step S1400 is 0.1 um - 0.3 um.
[0074] S1500, a drain metal layer 15 is formed on the bottom surface of the drain ohmic contact alloy layer 14 by Ti / Ni / Ag evaporation; refer to Figure 1 as shown.
[0075] The evaporation thickness of the Ti / Ni / Ag metal in step S1500 is 30 nm / 300 nm / 1200 nm.
[0076] A SiC MOS with a better gate protection structure includes a SiC Sub layer 1 and a SiC Epi layer 2 arranged from bottom to top;
[0077] On the SiC Epi layer 2 are provided:
[0078] A P-body region 3 extending downward from the top surface of the SiC Epi layer 2;
[0079] An NP region 4 extending downward from the top surface of the P-body region 3, with a spacing between its bottom surface and the bottom surface of the P-body region 3;
[0080] A PP region 5 extending downward from the top surface of the P-body region 3 and connected to the NP region 4; in this case, the bottom surface depth of the NP region 4 is 0.3 um - 0.6 um; the bottom surface depth of the PP region 5 is 0.5 um - 1 um;
[0081] A P-shield region 6 extending downward from the middle of the top surface of the P-body region 3, with a spacing from the P-body region 3;
[0082] An N+ region 7 extending downward from the middle of the top surface of the P-shield region 6, with its bottom surface lower than the bottom surface of the P-shield region 6;
[0083] A gate ohmic contact alloy layer 8 is formed on the top surface of the P-shield region 6, with its bottom surface connected to the P-shield region 6 and the N+ region 7 respectively;
[0084] The gate oxide layer 9 is connected to the gate ohmic contact alloy layer 8, and its bottom is respectively connected to the NP region 4, the P-body region 3, and the SiC Epi layer 2; the top surface of the gate oxide layer 9 is lower than the bottom surface of the gate ohmic contact alloy layer 8;
[0085] The Poly layer 10 is formed on the top surfaces of the gate oxide layer 9 and the gate ohmic contact alloy layer 8; the middle part of the Poly layer 10 bulges upward;
[0086] The isolation dielectric layer 11 wraps the gate oxide layer 9 and the Poly layer 10, and its side extends downward to be connected to the NP region 4;
[0087] The source ohmic contact alloy layer 12 is formed on the side of the isolation dielectric layer 11, and its bottom is respectively connected to the PP region 5 and the NP region 4;
[0088] The source metal layer 13 is formed on the top surfaces of the source ohmic contact alloy layer 12 and the isolation dielectric layer 11.
[0089] In the planar-gate SiC MOSFET device of the present invention, a P-shield region 6 and an N+ region 7 are formed by implantation at the bottom of the device gate, and ohmic contacts are formed on the top surfaces of the P-shield region 6 and the N+ region 7 to protect the device gate oxide layer. Due to the formation of the ohmic contacts, when the device gate is pressurized, the gate voltage can achieve a certain degree of electrical stress release through the N+ region 7, thereby reducing the electrical stress on the gate oxide layer 9. The P-shield region 6 can shield the current released from the N+ region 7, thereby avoiding the increase of Igss leakage current. Moreover, during the device blocking process, the P-shield region 6 can also better shield the electric field concentration of the drain voltage on the gate oxide layer, thus achieving a good protection effect on the gate oxide layer of the SiC MOSFET device.
Claims
1. A SiC MOS with a better gate protection structure, characterized in that: The invention comprises a SiC Sub layer (1) and a SiC Epi layer (2) arranged from bottom to top; the SiC Epi layer (2) is provided with: A P-body region (3) extending downward from the top surface of the SiC Epi layer (2); the top surface of the P-body region (3) is provided with an NP region (4) and a PP region (5) extending downward and connected to each other; A P-shield region (6) extending downward from the top surface of the P-body region (3) and having a spacing therebetween; An N+ region (7) extending downward from the top surface of the P-shield region (6); A gate ohmic contact alloy layer (8), formed on the top surface of the P-shield region (6), and having a bottom surface connected to the P-shield region (6) and the N+ region (7); A gate oxide layer (9) connected to the gate ohmic contact alloy layer (8), and having a bottom portion connected to the NP region (4), the P-body region (3) and the SiC Epi layer (2); A Poly layer (10) formed on the top surface of the gate oxide layer (9) and the gate ohmic contact alloy layer (8); An isolation dielectric layer (11), wrapped on the gate oxide layer (9) and the Poly layer (10), with a side portion extending downward to connect with the NP region (4); A source ohmic contact alloy layer (12), formed on the side of the isolation dielectric layer (11), the bottom surface of which is respectively connected to the PP region (5) and the NP region (4); A source metal layer (13) is formed on the top surfaces of the source ohmic contact alloy layer (12) and the isolation dielectric layer (11).
2. The SiC MOS with a better gate protection structure according to claim 1, characterized in that: The gate oxide layer (9) has a thickness of 40 nm to 60 nm.
3. The SiC MOS with a better gate protection structure according to claim 1, characterized in that: The thickness of the Poly layer (10) is between 0.5um and 1.2um.
4. The SiC MOS with a better gate protection structure according to claim 1, characterized in that: The bottom surface depth of the P-shield region (6) is 0.3um-0.8um.
5. The SiC MOS with a better gate protection structure according to claim 1, characterized in that: The bottom surface depth of the N+ region (7) is 0.5um-1.2um.
6. The SiC MOS with a better gate protection structure according to claim 1, characterized in that: The P-shield region (6) extends downward from the middle of the top surface of the P-body region (3).
7. The SiC MOS with a better gate protection structure according to claim 1, characterized in that: The N+ region (7) extends downward from the middle of the top surface of the P-shield region (6).
8. The SiC MOS with a better gate protection structure according to claim 1, characterized in that: The bottom surface of the N+ region (7) is lower than the bottom surface of the P-shield region (6).
Citation Information
Cited By
Super junction metal oxide semiconductor field effect transistor and manufacturing method thereof
CN120475745A