SiC power junction field effect transistor

Abstract

The invention relates to a SiC power junction field effect transistor, and belongs to the field of semiconductor power devices. The transistor includes: a substrate region of a first conductivity type; a first charge balance region formed over the substrate region; a gate semiconductor region of a second conductivity type formed over the substrate region; the semiconductor source region of the first conduction type is formed above the first charge balance region and the gate semiconductor region; a drain metal region formed below the substrate region; the source electrode metal region is formed above the semiconductor source region; and a gate metal region formed over the gate semiconductor region. The first charge balance region comprises charge balance regions I of a first conduction type and charge balance regions II of a second conduction type which are alternately arranged above the substrate region, a plurality of U-shaped grooves are formed in the first charge balance region along the arrangement direction, and the gate semiconductor regions are formed in the U-shaped grooves. According to the invention, the problem that the specific on-resistance is increased can be solved, and the breakdown voltage can be prevented from being obviously reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor power devices and relates to a SiC power junction field effect transistor. Background Art

[0002] Power switching transistors are essential basic electronic components in power electronic systems and are one of the most widely used power semiconductor devices. Their main function is to control the switching of high voltage and high current. Common power switching transistors include power junction field effect transistors (JFET), power metal oxide semiconductor field effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT). Among them, power JFET and MOSFET only have one type of carrier involved in conduction during normal operation, and are unipolar devices. Their advantages are fast switching speed and high operating frequency, and their disadvantages are large specific on-resistance and chip area of ​​the device. In order to reduce the specific on-resistance of unipolar devices while maintaining the advantages of high-speed switching, people have tried various new semiconductor materials while carrying out structural innovation. For example, wide bandgap semiconductors represented by silicon carbide (SiC) materials have received increasing attention in recent years and are a key development direction of national strategy. Compared with traditional silicon-based unipolar power switching transistors, silicon carbide-based unipolar power switching transistors have significant advantages in chip area, switching frequency and high-temperature characteristics, and have been widely used in new energy vehicles and photovoltaic power generation.

[0003] The JFET effect exists in conventional SiC power junction field effect transistors, which is caused by the gate injection region used to control the channel. The gate injection region occupies a part of the area, narrowing the path for the current to flow; at the same time, the space charge region of the PN junction will further compress the current path. The narrowing of the current path increases the series resistance of this part of the area, which ultimately leads to an increase in the specific on-resistance of the SiC power junction field effect transistor. Although increasing the doping concentration of this part of the area can reduce the series resistance, this will increase the electric field near the PN junction, resulting in a decrease in the breakdown voltage.

[0004] In order to reduce the specific on-resistance of SiC power junction field-effect transistors without affecting the breakdown voltage, it is necessary to improve the current path narrowing problem related to the JFET effect. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a SiC power junction field effect transistor that alleviates the JFET effect, by reducing the specific on-resistance that increases due to the narrowing of the current path, thereby reducing the specific on-voltage drop of the SiC power junction field effect transistor.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A SiC power junction field effect transistor, the transistor comprising:

[0008] a substrate region of a first conductivity type;

[0009] a first charge balance region formed above the substrate region;

[0010] a gate semiconductor region of a second conductivity type formed above the substrate region;

[0011] a semiconductor source region of the first conductivity type formed above the first charge balance region and the gate semiconductor region;

[0012] a drain metal region formed below the substrate region;

[0013] a source metal region formed above the semiconductor source region;

[0014] A gate metal region is formed above the gate semiconductor region.

[0015] Optionally, the first charge balance region includes charge balance region I and charge balance region II alternately arranged above the substrate region, the charge balance region I and charge balance region II are formed with a plurality of U-shaped grooves along the arrangement direction, and the gate semiconductor region is formed in the U-shaped grooves.

[0016] Among them, the charge balance region I is of the first conductivity type, and the charge balance region II is of the second conductivity type.

[0017] As a preferred embodiment, the transistor further includes a drift region of the first conductivity type, wherein the drift region is formed between the substrate region and the first charge balance region.

[0018] As a preferred embodiment, the transistor further includes a second charge balance region, wherein the second charge balance region is formed between the substrate region and the first charge balance region.

[0019] The second charge balance region includes charge balance regions III and charge balance regions IV alternately arranged on the surface of the substrate region, and the arrangement direction of charge balance regions III and charge balance regions IV is orthogonal to the arrangement direction of charge balance regions I and charge balance regions II.

[0020] Among them, the charge balance region III is of the first conductivity type, and the charge balance region IV is of the second conductivity type.

[0021] The beneficial effect of the present invention is that compared with the conventional SiC power junction field effect transistor structure, the surface charge balance structure introduced by the present invention can increase the surface doping concentration while maintaining the electric field near the PN junction at a reasonable level, which can effectively solve the problem of increased specific on-resistance due to the narrowing of the current path and prevent the breakdown voltage from being significantly reduced. The SiC power junction field effect transistor proposed by the present invention is suitable for high-efficiency power electronic circuits and systems.

[0022] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 A schematic diagram of the structure of a SiC power junction field effect transistor provided in Example 1 of the present invention;

[0025] Figure 2 A schematic diagram of the structure of a SiC power junction field effect transistor provided in Example 2 of the present invention;

[0026] Figure 3 A schematic diagram of the structure of a SiC power junction field effect transistor provided in Example 3 of the present invention;

[0027] Figure 4 This is a schematic diagram of the structure of a SiC power junction field effect transistor provided in Example 4 of the present invention.

[0028] Figure markings: 1-drain metal region; 2-source metal region; 3-gate metal region; 4-substrate region; 5-drift region; 6-charge balance region I; 7-charge balance region II; 8-charge balance region III; 9-charge balance region IV; 10-semiconductor source region; 11-gate semiconductor region. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0030] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0031] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0032] Example 1

[0033] like Figure 1 As shown, a SiC power junction field effect transistor provided in this embodiment includes:

[0034] A semiconductor heavily doped substrate region 4 of the first conductivity type;

[0035] A drain metal region 1 is formed on the lower surface of the substrate region 4, and the drain metal region 1 is in contact with the substrate region 4;

[0036] A semiconductor lightly doped drift region 5 of the first conductivity type is formed on the upper surface of the substrate region 4, and the drift region 5 is in contact with the substrate region 4;

[0037] A semiconductor charge balance region I6 of a first conductivity type and a semiconductor charge balance region II7 of a second conductivity type are formed on the upper surface of the drift region. The charge balance regions I6 and II7 are alternately arranged on the upper surface of the drift region 5. Their side surfaces are directly connected to form a charge balance structure. Their bottom surfaces are in contact with the upper surface of the drift region 6. A plurality of long straight U-shaped grooves are formed in the charge balance regions I6 and II7 along the arrangement direction. It should be noted that Figure 1 The device shown is only a portion of the device proposed by the present invention, and is not the complete structure of the device of the present invention;

[0038] A heavily doped gate semiconductor region 11 of a second conductivity type is formed in the U-shaped groove, wherein the gate semiconductor region 11 is U-shaped in the U-shaped groove;

[0039] A heavily doped semiconductor source region 10 of the first conductivity type is formed on the upper surface of the protruding portion of the charge balance region I6 and the charge balance region II7, and the semiconductor source region 10 covers a portion of the gate semiconductor region 11;

[0040] A gate metal region 3 is formed on the inner surface of the trench of the gate semiconductor region 11, and the gate metal region covers a portion of the inner surface of the trench of the gate semiconductor region 11;

[0041] A source metal region 2 is formed on the upper surface of the semiconductor source region 10 , and the source metal region 2 is in contact with the semiconductor source region 10 .

[0042] This embodiment introduces a charge balance structure on the surface of the SiC power junction field effect transistor, uses the charge balance technology to increase the surface doping concentration, and keeps the electric field near the PN junction at a low level to prevent the breakdown voltage from being significantly reduced. The increase in surface doping concentration can effectively solve the problem of increased on-resistance and on-voltage drop caused by the narrowing of the current path, thereby reducing the specific on-resistance of the SiC power junction field effect transistor.

[0043] When the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0044] The semiconductor region may be made of silicon, or may be made of germanium, gallium arsenide, gallium nitride, silicon carbide, gallium oxide, diamond, or aluminum nitride.

[0045] Example 2

[0046] like Figure 2As shown, compared with the junction field effect transistor proposed in Example 1, the gate semiconductor region 11 of this embodiment can pass through the charge balance region I6 and the charge balance region II7 to be directly formed on the upper surface of the drift region 5, and the gate semiconductor region 11 is still U-shaped; at the same time, the charge balance region I6 and the charge balance region II7 are no longer an integral structure, but are separated by the adjacent U-shaped gate semiconductor region 11, and the two sides of the U-shaped gate semiconductor region 11 are respectively in contact with the charge balance region I6 and the charge balance region II7.

[0047] Example 3

[0048] like Figure 3 As shown, compared with the junction field effect transistor proposed in Example 1, the drift region 5 is removed in this embodiment, and the charge balance region I 6 and the charge balance region II 7 are directly and alternately arranged on the upper surface of the substrate region 4 .

[0049] Example 4

[0050] like Figure 4 As shown, compared with the junction field effect transistor proposed in Example 1, the drift region 5 is removed in this embodiment, and the drift region is replaced by a charge balance region III8 of the first conductivity type and a charge balance region IV9 of the second conductivity type. Specifically, the charge balance region III8 and the charge balance region IV9 are formed on the upper surface of the substrate region 4, and the charge balance region III8 and the charge balance region IV9 are alternately arranged on the upper surface of the substrate region 4, and their sides are directly connected to form a charge balance structure. Among them, the arrangement direction of the charge balance region III8 and the charge balance region IV9 is different from the arrangement direction of the charge balance region I6 and the charge balance region II7, and the two directions can be orthogonal.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A SiC power junction field effect transistor, characterized in that: It includes: a substrate region of a first conductivity type; a first charge balance region formed above the substrate region; a gate semiconductor region of a second conductivity type formed above the substrate region; a semiconductor source region of a first conductivity type formed above the first charge balance region and the gate semiconductor region; a drain metal region formed below the substrate region; a source metal region formed above the semiconductor source region; A gate metal region is formed above the gate semiconductor region.

2. The SiC power junction field effect transistor according to claim 1, characterized in that: The first charge balance region includes a charge balance region I and a charge balance region II alternately arranged above the substrate region, the charge balance region I and the charge balance region II form a plurality of U-shaped grooves along the arrangement direction, and the gate semiconductor region is formed in the U-shaped grooves; wherein the charge balance region I is of the first conductivity type, and the charge balance region II is of the second conductivity type.

3. The SiC power junction field effect transistor according to claim 1 or 2, characterized in that: The transistor further includes a drift region of the first conductivity type formed between the substrate region and the first charge balance region.

4. The SiC power junction field effect transistor according to claim 1 or 2, characterized in that: The transistor also includes a second charge balance region formed between the substrate region and the first charge balance region.

5. The SiC power junction field effect transistor according to claim 4, characterized in that: The second charge balance region includes charge balance region III and charge balance region IV alternately arranged on the surface of the substrate region, and the arrangement direction of charge balance region III and charge balance region IV is orthogonal to the arrangement direction of charge balance region I and charge balance region II; wherein, the charge balance region III is of the first conductivity type, and the charge balance region IV is of the second conductivity type.

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