Schottky barrier integrated field effect transistor and manufacturing method therefor

Abstract

A Schottky barrier integrated field effect transistor and a manufacturing method therefor. The field effect transistor comprises: a first conductive type substrate (1); a first conductive type epitaxial layer (2), wherein the first conductive type epitaxial layer (2) comprises second conductive type doped regions (21), and a JFET region (23) is formed between adjacent second conductive type doped regions (21); gate-source isolation structures (3), wherein an accommodating region (4) is formed between adjacent gate-source isolation structures (3); a Schottky barrier layer (5), wherein the Schottky barrier layer (5) is located in the accommodating region (4) and in contact with the JFET region (23); and gates (6), separated from the Schottky barrier layer (5) by means of at least the gate-source isolation structures (3), wherein the thickness of the sides of the gate-source isolation structures (3) close to the Schottky barrier layer (5) is greater than the thickness of the sides of the gate-source isolation structures (3) distant from the Schottky barrier layer (5).

Description

Field effect transistor with integrated Schottky barrier and method for preparing the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 28, 2024, with application number 202410220368.2, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor manufacturing technology, for example, to a field effect transistor with an integrated Schottky barrier and a method for preparing the same. Background Art

[0003] The development of the power electronics industry has made it increasingly difficult for silicon devices to meet the increasingly stringent application requirements. Silicon carbide (SiC), due to its excellent physical and chemical properties, has become one of the most important semiconductor materials for manufacturing high-power devices with high withstand voltage, low on-resistance, and adaptability to extreme environments. Among SiC power devices, the metal oxide semiconductor field-effect transistor (MOSFET) is widely used due to its advantages such as simple gate drive and fast switching speed. Typically, SiC power MOSFETs adopt a vertical structure with the source and drain located on the upper and lower sides of the chip, respectively. This type of vertical power MOSFET structure often incorporates a freewheeling diode. However, due to the large bandgap of SiC, the turn-on voltage of the freewheeling diode is typically greater than 3V, which cannot effectively meet the freewheeling requirements of SiC MOSFET devices. Therefore, in practical applications, a SiC Schottky barrier diode (SBD) with a turn-on voltage below 1.5V is often connected in parallel to ensure good freewheeling characteristics.

[0004] In response to the freewheeling requirements of SiC power MOSFETs, in addition to additional parallel SBDs as freewheeling diodes, directly integrating SBDs into the power MOSFET structure has also become a feasible solution. One technical route is to form a Schottky barrier between the source ohmic contacts, and the other is to use a split-gate structure to integrate the Schottky barrier above the junction field-effect transistor (JFET) region (neck region) of the device. Both solutions achieve the integration of SBDs through additional process steps, but the integration of the Schottky barrier will cause the unit cell size to be significantly larger than the conventional structure, which will increase the device resistance.

[0005] Summary of the Invention

[0006] The present application provides a field-effect transistor with an integrated Schottky barrier and a method for preparing the same, so as to reduce the device cell size and the on-resistance of the device and improve the device performance.

[0007] An embodiment of the present application provides a field-effect transistor with an integrated Schottky barrier, comprising: a first conductive type substrate; a first conductive type epitaxial layer located on one side of the first conductive type substrate, the first conductive type epitaxial layer including a second conductive type doped region, the second conductive type doped region including a first conductive type doped region, and a JFET region formed between adjacent second conductive type doped regions; a gate-source isolation structure located on a surface of the first conductive type epitaxial layer facing away from the first conductive type substrate, an accommodating region formed between adjacent gate-source isolation structures, and the accommodating region overlapping with the JFET region in a direction perpendicular to the first conductive type epitaxial layer; a Schottky barrier layer located in the accommodating region and in contact with the JFET region; a gate located on a side of the first conductive type epitaxial layer facing away from the first conductive type substrate, the gate overlapping with at least the second conductive type doped region in a direction perpendicular to the first conductive type epitaxial layer, and the gate and the Schottky barrier layer being separated by at least the gate-source isolation structure; wherein the thickness of the gate-source isolation structure on the side close to the Schottky barrier layer is greater than its thickness on the side away from the Schottky barrier layer.

[0008] An embodiment of the present application also provides a method for preparing a field-effect transistor with an integrated Schottky barrier, which is used to prepare the field-effect transistor with an integrated Schottky barrier provided in the first aspect of the present application, the preparation method comprising: providing a first conductive type substrate; forming a first conductive type epitaxial layer on one side of the first conductive type substrate, and forming a second conductive type doped region and a first conductive type doped region in the first conductive type epitaxial layer through a selective doping process; forming a JFET region between adjacent second conductive type doped regions; preparing a gate-source isolation structure, a gate, and a Schottky barrier layer on a surface of the first conductive type epitaxial layer facing away from the first conductive type substrate, forming an accommodating region between adjacent gate-source isolation structures, and overlapping the accommodating region with the JFET region in a direction perpendicular to the first conductive type epitaxial layer; the Schottky barrier layer is located in the accommodating region and contacts the JFET region, and overlapping the gate with at least the second conductive type doped region in a direction perpendicular to the first conductive type epitaxial layer, and the gate and the Schottky barrier layer are separated by at least the gate-source isolation structure; wherein the thickness of the gate-source isolation structure on the side close to the Schottky barrier layer is greater than its thickness on the side away from the Schottky barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG1 is a schematic structural diagram of a field-effect transistor with an integrated Schottky barrier provided in an embodiment of the present application;

[0010] FIG2 is a schematic structural diagram of another field-effect transistor with integrated Schottky barrier provided in an embodiment of the present application;

[0011] FIG3 is a schematic structural diagram of another field-effect transistor with integrated Schottky barrier provided in an embodiment of the present application;

[0012] FIG4 is a schematic structural diagram of another field-effect transistor with integrated Schottky barrier provided in an embodiment of the present application;

[0013] FIG5 is a schematic structural diagram of another field-effect transistor with integrated Schottky barrier provided in an embodiment of the present application;

[0014] FIG6 is a schematic structural diagram of another field-effect transistor with integrated Schottky barrier provided in an embodiment of the present application;

[0015] FIG7 is a schematic structural diagram of another field-effect transistor with integrated Schottky barrier provided in an embodiment of the present application;

[0016] FIG8 is a schematic structural diagram of another field-effect transistor with integrated Schottky barrier provided in an embodiment of the present application;

[0017] FIG9 is a flow chart of a method for preparing a field-effect transistor with an integrated Schottky barrier according to an embodiment of the present application;

[0018] FIG10 is a schematic diagram of a method for preparing a field-effect transistor with an integrated Schottky barrier according to an embodiment of the present application;

[0019] FIG11 is a schematic diagram of another method for preparing a field-effect transistor with an integrated Schottky barrier according to an embodiment of the present application;

[0020] FIG12 is a schematic diagram of another method for preparing a field effect transistor with an integrated Schottky barrier provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The present application is described below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments described herein are intended only to explain the present application and are not intended to limit the present application. It should also be noted that, for ease of description, only the structures relevant to the present application are shown in the accompanying drawings.

[0022] In addition, in the description of this application, the terms "central", "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description. They do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0023] In addition, the "first conductivity type" and "second conductivity type" described in the embodiments of the present application are two different carrier doping types in the semiconductor device. For example, the first conductivity type may be N-type doping, and the second conductivity type may be P-type doping, or the first conductivity type may be P-type doping, and the second conductivity type may be N-type doping. This application does not limit this.

[0024] In related technologies, a split-gate structure is used to integrate a Schottky barrier layer above the JFET region of the device to form a field-effect transistor with an integrated Schottky barrier. Due to the gate-source isolation spacing requirements of the device itself, a certain distance must be left between the gate and the Schottky barrier layer to ensure process reliability and product yield. In addition, the Schottky barrier layer annealing process may cause deformation of the gate-source isolation dielectric, which requires the device to have a longer gate-source isolation spacing. However, the applicant's research found that the increase in the gate-source isolation spacing leads to a decrease in the Schottky barrier layer area between the split gates and a significant increase in the width of the device cell. The former is not conducive to the full realization of the body diode performance, and the latter will lead to a decrease in the overall current flow capacity of the device and an increase in the on-resistance.

[0025] In view of this, the present application proposes a field-effect transistor with an integrated Schottky barrier, comprising: a first conductive type substrate; a first conductive type epitaxial layer located on one side of the first conductive type substrate, the first conductive type epitaxial layer including a second conductive type doped region, the second conductive type doped region including a first conductive type doped region, and a JFET region formed between adjacent second conductive type doped regions; a gate-source isolation structure located on a surface of the first conductive type epitaxial layer facing away from the first conductive type substrate, an accommodating region formed between adjacent gate-source isolation structures, and the accommodating region overlapping with the JFET region in a direction perpendicular to the first conductive type epitaxial layer; a Schottky barrier layer located in the accommodating region and in contact with the JFET region; a gate located on a side of the first conductive type epitaxial layer facing away from the first conductive type substrate, the gate overlapping with the second conductive type doped region in a direction perpendicular to the first conductive type epitaxial layer, and the gate and the Schottky barrier layer being separated by at least the gate-source isolation structure; wherein the thickness of the gate-source isolation structure on the side close to the Schottky barrier layer is greater than its thickness on the side away from the Schottky barrier layer.

[0026] The above technical solution, while ensuring sufficient spacing between the gate and the Schottky barrier layer, can further reduce the lateral distance between the Schottky barrier layer and the gate. This not only ensures a large Schottky barrier layer area, but also reduces the device cell size, lowers the device on-resistance, improves the device's body diode freewheeling capability, reduces Miller capacitance, and enhances the device's dynamic performance. Furthermore, the presence of the Schottky barrier layer enhances the ability to extract excess carriers during single-particle irradiation, achieving single-particle reinforcement of the device, strengthening gate protection, and effectively suppressing gate dielectric damage caused by single-particle irradiation, resulting in overall improved device performance.

[0027] The above is the core concept of this application. The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0028] FIG1 is a schematic structural diagram of a field effect transistor with an integrated Schottky barrier provided in an embodiment of the present application. Referring to FIG1 , the field effect transistor with an integrated Schottky barrier includes: a first conductive type substrate 1; a first conductive type epitaxial layer 2 located on one side of the first conductive type substrate 1, the first conductive type epitaxial layer 2 including a second conductive type doped region 21, the second conductive type doped region 21 including a first conductive type doped region 22, and a JFET region 23 formed between adjacent second conductive type doped regions 21; a gate-source isolation structure 3 located on a surface of the first conductive type epitaxial layer 2 facing away from the first conductive type substrate 1, and a gate-source isolation structure 3 between adjacent gate-source isolation structures 3. An accommodating region 4 is formed therebetween, and the accommodating region 4 overlaps with the JFET region 23 along a direction perpendicular to the first conductive type epitaxial layer 2; a Schottky barrier layer 5, the Schottky barrier layer 5 is located in the accommodating region 4 and in contact with the JFET region 23; a gate 6, located on a side of the first conductive type epitaxial layer 2 away from the first conductive type substrate 1, and along a direction perpendicular to the first conductive type epitaxial layer 2, the gate 6 at least overlaps with the second conductive type doped region 21, and the gate 6 and the Schottky barrier layer 5 are separated by at least a gate-source isolation structure 3; wherein the thickness of the gate-source isolation structure 3 on the side close to the Schottky barrier layer 5 is greater than its thickness on the side away from the Schottky barrier layer 5.

[0029] As shown in FIG1 , a field-effect transistor with an integrated Schottky barrier (hereinafter referred to as a “field-effect transistor”) includes a first-conductivity-type substrate 1, a first-conductivity-type epitaxial layer 2, a gate-source isolation structure 3, a Schottky barrier layer 5, and a gate 6. The first-conductivity-type substrate 1 may be a first-conductivity-type SiC substrate, and the first-conductivity-type epitaxial layer 2 may be a first-conductivity-type SiC epitaxial layer.

[0030] Continuing with reference to FIG1 , in this embodiment, two symmetrical second conductivity type doped regions 21, two symmetrical first conductivity type doped regions 22, and a JFET region 23 can be formed in the first conductivity type epitaxial layer 2. The JFET region 23 is also referred to as a neck region. The JFET region 23 is located between the two symmetrical second conductivity type doped regions 21. The first conductivity type doped region 22 is located within the second conductivity type doped region 21. The embodiments of this application do not limit the doping concentrations of the multiple doped regions, and those skilled in the art can set them according to actual needs.

[0031] In the present application, two opposing gate-source isolation structures 3 may be provided on the side of the first conductive type epitaxial layer 2 facing away from the first conductive type substrate 1. The two gate-source isolation structures 3 are respectively located on either side of the JFET region 23. In a direction perpendicular to the first conductive type epitaxial layer 2, the gate-source isolation structure 3 may overlap with a portion of the first conductive type epitaxial layer 2. The gate-source isolation structure 3 has a certain thickness, and an accommodation region 4 is formed between two adjacent gate-source isolation structures 3. The accommodation region 4 is located above the JFET region 23. A Schottky barrier layer 5 is provided within the accommodation region 4 and in contact with the JFET region 23.

[0032] The gate-source isolation structure 3 is made of a dielectric material, such as SiO2 or a composite layer of SiO2 and Si3N4, which is not limited in this embodiment of the present application. The Schottky metal material used to make the Schottky barrier layer 5 can be Ti, Ni, or W. The Schottky barrier layer 5 can be an alloy layer formed by high-temperature annealing of a Schottky metal material and a semiconductor material. Generally, the thickness of the Schottky barrier layer 5 does not exceed half the maximum thickness of the gate-source isolation structure 3.

[0033] Continuing with reference to FIG. 1 , the field-effect transistor in the embodiment of the present application can be fabricated based on a split-gate structure. That is, two gates 6 are provided on the side of the first conductivity-type epitaxial layer 2 facing away from the first conductivity-type substrate 1. The two gates 6 are located on either side of the JFET region 23. In a direction perpendicular to the first conductivity-type epitaxial layer 2, the gate 6, the gate-source isolation structure 3, and the second conductivity-type doped region 21 overlap. Furthermore, the gate 6 and the Schottky barrier layer 5 are separated by at least the gate-source isolation structure 3 to achieve electrical insulation between the gate 6 and the Schottky barrier layer 5.

[0034] In the present application, the gate-source isolation structure 3 can be configured to have different thicknesses in different regions. As shown in FIG1 , the thickness of the gate-source isolation structure 3 on the side close to the Schottky barrier layer 5 can be greater than the thickness on the side away from the Schottky barrier layer 5. Since the gate-source isolation structure 3 is on both sides of the Schottky barrier layer 5, the thickness of the gate-source isolation structure 3 decreases along the Schottky barrier layer 5 toward the gate-source isolation structure 3 on either side.

[0035] This configuration transforms the purely lateral gate-source isolation spacing between gate 6 and Schottky barrier layer 5 into a longitudinal and lateral separation. While ensuring sufficient spacing between gate 6 and Schottky barrier layer 5, the lateral distance between Schottky barrier layer 5 and gate 6 can be further reduced. This not only ensures a larger area for Schottky barrier layer 5, but also reduces the device cell size, lowers device on-resistance, improves the device's body diode freewheeling capability, reduces Miller capacitance, and enhances device dynamic performance. Furthermore, the presence of Schottky barrier layer 5 enhances the ability to extract excess carriers during single-particle irradiation, achieving single-particle reinforcement for the device, strengthening the protection of gate 6, and effectively suppressing gate dielectric damage caused by single-particle irradiation, resulting in overall device performance improvements.

[0036] The embodiment of the present application does not limit the shape of the gate-source isolation structure 3. Those skilled in the art can set it according to actual needs. Any gate-source isolation structure 3 that meets the above-mentioned thickness characteristics is within the scope of the technical solution protected by the embodiment of the present application. For example, in an optional embodiment, the thickness of the gate-source isolation structure 3 on the side close to the Schottky barrier layer 5 can be 80 to 600 nm, optionally 120 to 400 nm, and the thickness on the side away from the Schottky barrier layer 5 can be 0 nm, that is, the thickness of the gate-source isolation structure 3 is reduced from 120 to 400 nm to 0 nm, but is not limited to this. The thickness of the Schottky barrier layer 5 can be 10 to 300 nm, and the optional thickness can be 50 nm to 150 nm, but is not limited to this. In actual application, those skilled in the art can set it according to actual needs. In addition, the cross-sectional shape of the gate-source isolation structure 3 shown in Figure 1 is a triangle, but is not limited to this.

[0037] The direction parallel to the first conductive type epitaxial layer 2 can be considered as the horizontal direction X (i.e., horizontal). In some embodiments, the ratio of the maximum thickness of the gate-source isolation structure 3 to its width in the horizontal direction X can be set in the range of 1:5 to 3:1, and can be optionally 1:3 to 3:2. Designing the gate-source isolation structure 3 according to the above parameters can make the overall performance of the device better.

[0038] In an embodiment of the present application, a field-effect transistor with an integrated Schottky barrier includes: a first conductive type substrate; a first conductive type epitaxial layer located on one side of the first conductive type substrate, the first conductive type epitaxial layer including a second conductive type doped region, the second conductive type doped region including a first conductive type doped region, and a JFET region formed between adjacent second conductive type doped regions; a gate-source isolation structure located on a surface of the first conductive type epitaxial layer facing away from the first conductive type substrate, an accommodating region formed between adjacent gate-source isolation structures, and the accommodating region overlapping with the JFET region in a direction perpendicular to the first conductive type epitaxial layer; a Schottky barrier layer located in the accommodating region and in contact with the JFET region; a gate located on a side of the first conductive type epitaxial layer facing away from the first conductive type substrate, the gate overlapping with the second conductive type doped region in a direction perpendicular to the first conductive type epitaxial layer, and the gate and the Schottky barrier layer being separated by at least the gate-source isolation structure; wherein the thickness of the gate-source isolation structure on the side close to the Schottky barrier layer is greater than its thickness on the side away from the Schottky barrier layer. Through the above solution, while ensuring sufficient spacing between the gate and the Schottky barrier layer, the lateral distance between the Schottky barrier layer and the gate can be further reduced. This not only ensures a large contact area between the Schottky barrier layer and the JFET region, but also reduces the device cell size, reduces the device on-resistance, improves the device's body diode freewheeling capability, reduces Miller capacitance, and enhances the device's dynamic performance. Furthermore, the presence of the Schottky barrier layer can enhance the ability to extract excess carriers during single-particle irradiation, achieving single-particle reinforcement of the device, enhancing gate protection, and effectively suppressing gate dielectric damage caused by single-particle irradiation, resulting in an overall improvement in device performance.

[0039] Optionally, referring to Figure 1, in some possible embodiments, the second conductive type doping region 21 may also include a high-doping region 21-1 and a low-doping region 21-2, and the high-doping region 21-1, the low-doping region 21-2 and the first conductive type doping region 22 all extend downward from the first conductive type epitaxial layer 2 toward one side surface of the gate-source isolation structure 3; the high-doping region 21-1 is located between the first conductive type doping region 22 and the low-doping region 21-2; the gate-source isolation structure 3 covers at least part of the low-doping region 21-2, and along the direction perpendicular to the first conductive type epitaxial layer 2, the gate-source isolation structure 3 does not overlap with the high-doping region 21-1.

[0040] As shown in FIG1 , in this embodiment, the second conductivity type doped region 21 can also be divided into a high-doped region 21-1 and a low-doped region 21-2. As the name implies, the doping concentration of the high-doped region 21-1 is greater than the doping concentration of the low-doped region 21-2. The high-doped region 21-1 can surround the first conductivity type doped region 22, and the low-doped region 21-2 is located on the side of the high-doped region 21-1 facing away from the first conductivity type doped region 22. It can also be understood that, along a direction parallel to the first conductivity type epitaxial layer 2, the low-doped region 21-2 is closest to the JFET region 23, the high-doped region 21-1 is second, and the first conductivity type doped region 22 is farther away.

[0041] Those skilled in the art will understand that, generally, the multiple doping regions located in the first conductive type epitaxial layer 2 all extend downward from the surface of the first conductive type epitaxial layer 2 (i.e., extend toward the side of the first conductive type substrate 1). The second conductive type doping region 21 is located below the gate 6, where the surface of the first conductive type epitaxial layer 2 is the channel region of the field effect transistor. When the second conductive type doping region 21 includes the above-mentioned high-doping region 21-1 and the low-doping region 21-2, the surface of the first conductive type epitaxial layer 2 corresponding to the high-doping region 21-1 can be the first channel region of the field effect transistor, and the surface of the first conductive type epitaxial layer 2 corresponding to the low-doping region 21-2 can be the second channel region of the field effect transistor.

[0042] In this embodiment, as shown in Figure 1, along the direction perpendicular to the first conductive type epitaxial layer 2, the gate-source isolation structure 3 overlaps with the low-doped region 21-2 and does not overlap with the high-doped region 21-1, that is, the side of the gate-source isolation structure 3 away from the Schottky barrier layer 5 falls into the second channel region and is at a certain distance from the edge of the first channel region.

[0043] For example, in the embodiment shown in FIG1 , the depths of the high-doped region 21 - 1 and the low-doped region 21 - 2 are substantially the same, but the doping concentration of the low-doped region 21 - 2 is much lower than that of the high-doped region 21 - 1. Typically, at the upper surface of the first conductive type epitaxial layer 2 , the doping concentration of the low-doped region 21 - 2 does not exceed half of that of the high-doped region 21 - 1. The concentration range of the low-doped region 21 - 2 may be 1E15 to 5E16 cm -3 , can be selected as 1E15~1E16cm -3 The width of the second channel region along the horizontal direction X can be 100 to 600 nm, optionally 200 to 400 nm. The width of the first channel region along the horizontal direction X can be 200 to 800 nm, optionally 300 to 600 nm. The horizontal spacing between the side of the gate-source isolation structure 3 away from the Schottky barrier layer 5 and the first channel region is greater than or equal to 10 nm, optionally greater than 100 nm.

[0044] In this embodiment, the introduction of a highly doped region 21-1 and a lowly doped region 21-2, along with a corresponding dual-channel design, within the second conductivity-type doped region 21 further enhances the second conductivity-type doped region 21's ability to extract excess carriers during irradiation, reduces the series resistance of the second conductivity-type doped region 21, and suppresses parasitic effects of irradiation. Furthermore, because the doping concentration of the lowly doped region 21-2 is very low, even if the gate-source isolation structure 3 partially falls over the second channel region, the low doping concentration and high mobility of this region have minimal impact on the device's forward characteristics, thus avoiding the significant increase in on-resistance during conduction associated with conventional thick gate oxide structures.

[0045] FIG2 is a schematic diagram of the structure of another field-effect transistor with an integrated Schottky barrier according to an embodiment of the present application, and FIG3 is a schematic diagram of the structure of yet another field-effect transistor with an integrated Schottky barrier according to an embodiment of the present application. Referring to FIG2 and FIG3 , in some other embodiments, the depth of the low-doped region 21-2 in the first conductivity type epitaxial layer 2 is greater than or equal to the depth of the high-doped region 21-1 in the first conductivity type epitaxial layer 2; or, the depth of the low-doped region 21-2 in the first conductivity type epitaxial layer 2 is less than the depth of the high-doped region 21-1 in the first conductivity type epitaxial layer 2.

[0046] The main difference between the embodiment shown in FIG2 and the embodiment shown in FIG1 is that different implant energies are used for the high-doped region 21-1 and the low-doped region 21-2. The implant energy used for the low-doped region 21-2 is lower than that for the high-doped region 21-1, making the low-doped region 21-2 shallower than the high-doped region 21-1. This results in a wider horizontal dimension of the JFET region 23 of the field-effect transistor, a weaker pinch-off effect of the JFET region 23, and a lower forward on-resistance of the device, making it suitable for device structures with narrower JFET regions 23.

[0047] The main difference between the embodiment shown in Figure 3 and the embodiment shown in Figure 1 is that the injection energy used in the low-doped region 21-2 is higher than the injection energy of the high-doped region 21-1, so that the low-doped region 21-2 is deeper than the high-doped region 21-1. In this way, the horizontal size of the JFET region 23 of the field-effect transistor is narrower, the reverse bias leakage of the device is reduced, and it is suitable for the device structure design with a wider JFET region 23.

[0048] Optionally, Figure 4 is a structural schematic diagram of another field effect transistor with an integrated Schottky barrier provided in an embodiment of the present application. Referring to Figure 4, in some embodiments, the positive projection of the gate-source isolation structure 3 on the first conductive type epitaxial layer 2 is located within the JFET region 23; along the direction of the JFET region 23 pointing to the second conductive type doped region 21, the distance between the side of the gate-source isolation structure 3 away from the Schottky barrier layer 5 and the second conductive type doped region 21 is greater than or equal to 10 nm.

[0049] In this embodiment, the entire second conductivity type doped region 21 can be doped with a high concentration. It can be understood that the entire second conductivity type doped region 21 is the above-mentioned highly doped region 21-1. In this case, the gate-source isolation structure 3 can be set only above the JFET region 23, and the side of the gate-source isolation structure 3 away from the Schottky barrier layer 5 is separated from the boundary of the second conductivity type doped region 21 (i.e., the edge of the channel region) by a certain distance in the horizontal direction X. For example, the distance can be greater than or equal to 10nm, and can be greater than or equal to 100nm, but is not limited thereto. This structure is conducive to appropriately reducing the on-resistance of the device.

[0050] In addition, it should be noted that in the embodiment of the present application, the orthographic projection of the Schottky barrier layer 5 on the first conductive type epitaxial layer 2 does not overlap with the second conductive type doped region 21, that is, the Schottky barrier layer 5 is not in direct contact with the channel region, and in the horizontal direction X, there is a certain distance between the Schottky barrier layer 5 and the boundary of the second conductive type doped region 21 (that is, the edge of the channel region). For example, the distance between the two can be 10 to 800 nm, and can be optionally 20 to 300 nm, but is not limited to this.

[0051] Optionally, Figure 5 is a structural schematic diagram of another field effect transistor with integrated Schottky barrier provided in an embodiment of the present application. Please refer to Figures 1 and 5. In the embodiment of the present application, the field effect transistor with integrated Schottky barrier also includes a gate dielectric layer 7 and a first isolation dielectric layer 8. The gate dielectric layer 7 covers at least a portion of the gate-source isolation structure 3 and the second conductive type doped region 21. The gate 6 is located on the side surface of the gate dielectric layer 7 facing away from the first conductive type epitaxial layer 2; the first isolation dielectric layer 8 covers the gate 6 and a portion of the first conductive type doped region 22; the side wall of the gate 6 facing the Schottky barrier layer 5 is the first side wall 61 of the gate 6, and the side wall of the gate-source isolation structure 3 facing the Schottky barrier layer 5 is the second side wall 31 of the gate-source isolation structure 3. In the embodiment shown in Figure 1, the gate dielectric layer 7 covers the entire surface of the gate-source isolation structure 3 on the side facing away from the first conductive type epitaxial layer 2, and the field-effect transistor with integrated Schottky barrier also includes a second isolation dielectric layer 10, which covers the portion of the Schottky barrier layer 5, the first side wall 61, the second side wall 31 and the first isolation dielectric layer 8 connected to the first side wall 61; or, in the embodiment shown in Figure 5, the surface of the gate-source isolation structure 3 on the side facing away from the first conductive type epitaxial layer 2 includes a first surface 32 and a second surface 33 that are connected, the first surface 32 is used to connect the second side wall 31 and the second surface 33, the gate dielectric layer 7 covers the second surface 33, and the first isolation dielectric layer 8 also covers the first surface 32 and the first side wall 61.

[0052] As shown in Figures 1 and 5, a gate dielectric layer 7 can be disposed on a side of the first conductive type epitaxial layer 2 facing away from the first conductive type substrate 1, and can cover at least a portion of the gate-source isolation structure 3, a portion of the first channel region, and the second channel region. A gate 6 is formed on a surface of the gate dielectric layer 7 facing away from the first conductive type epitaxial layer 2. The gate 6 is separated from the Schottky barrier layer 5 by the gate-source isolation structure 3 and the gate dielectric layer 7. The gate 6 is separated from a portion of the second conductive type doped region 21 by the gate-source isolation structure 3 and the gate dielectric layer 7. The gate 6 is partially separated from another portion of the second conductive type doped region 21 by the gate dielectric layer 7. The gate dielectric layer 7 can be made of SiO2, but is not limited thereto. The gate dielectric layer 7 and the side of the gate 6 facing away from the Schottky barrier layer 5 can extend above a portion of the first conductive type doped region 22.

[0053] Continuing with reference to Figures 1 and 5 , the first isolation dielectric layer 8 is located on a side of the gate 6 facing away from the second conductivity type doped region 21. The first isolation dielectric layer 8 covers at least the gate 6 and a portion of the upper surface of the first conductivity type epitaxial layer 2 corresponding to the first conductivity type doped region 22. The first isolation dielectric layer 8 can be SiO2 or a composite material of SiO2 and Si3N4, but is not limited thereto.

[0054] In the embodiment shown in FIG1 , the gate dielectric layer 7 completely covers all surfaces of the gate-source isolation structure 3 except the second sidewall 31. At this point, the second sidewall 31 of the gate-source isolation structure 3 and the first sidewall 61 of the gate 6 are approximately flush. To ensure the insulation of the gate 6, a second isolation dielectric layer 10 may be additionally provided. The second isolation dielectric layer 10 covers the portion of the upper surface of the Schottky barrier layer 5 adjacent to the gate-source isolation structure 3, the second sidewall 31 of the gate-source isolation structure 3, the first sidewall 61 of the gate 6, and the entire first isolation dielectric layer 8. That is, in a direction perpendicular to the first conductivity type epitaxial layer 2, the second isolation dielectric layer 10 covers a portion of the Schottky barrier layer 5, the gate-source isolation structure 3, the gate dielectric layer 7, the gate 6, and the first isolation dielectric layer 8. The first isolation dielectric layer 8 and the second isolation dielectric layer 10 achieve gate-source isolation, improving the electrical insulation between the gate 6 and the Schottky barrier layer 5.

[0055] In the embodiment shown in FIG5 , the gate dielectric layer 7 may only cover a portion of the surface of the gate-source isolation structure 3 (the second surface 33 on the side away from the Schottky barrier layer 5), and the gate dielectric layer 7 and the gate 6 are not disposed above the first surface 32. The first isolation dielectric layer 8 may extend to the first surface 32, covering the first surface 32 of the gate-source isolation structure 3 and the entire upper surface of the gate 6. That is, in a direction perpendicular to the first conductivity type epitaxial layer 2, the first isolation dielectric layer 8 covers the gate-source isolation structure 3, the gate dielectric layer 7, and the gate 6. By utilizing only the first isolation dielectric layer 8 to achieve gate-source isolation, the second isolation dielectric layer 10 is not required, simplifying the fabrication process and reducing the overall thickness of the device.

[0056] In the embodiment shown in FIG1 , the width of the second isolation dielectric layer 10 in the JFET region 23 , that is, the horizontal width of the second isolation dielectric layer 10 located above the Schottky barrier layer 5 , is not less than 200 nm, and may be, for example, 200 to 800 nm, or optionally 300 to 600 nm, to ensure sufficient isolation spacing between the gate 6 and the Schottky barrier layer 5 .

[0057] The embodiments shown in FIG. 1 and FIG. 5 differ in their preparation processes. Only the structural differences between the two are described here, and the differences in preparation work are described in the following embodiments.

[0058] Optionally, the thickness of the first isolation dielectric layer 8 or the second isolation dielectric layer 10 can be set by those skilled in the art according to actual needs, for example, it can be set within 100 nm, but is not limited thereto.

[0059] Optionally, in an embodiment of the present application, it can be arranged that in the horizontal direction X, the distance between the first side wall 61 and the Schottky barrier layer 5 is greater than the distance between the second side wall 31 and the Schottky barrier layer 5, that is, the positive projection of the first side wall 61 on the first conductive type epitaxial layer 2 is located within the projection range of the gate-source isolation structure 3. Part of the gate 6 can be laterally etched away so that the first side wall 61 is recessed inward compared to the second side wall 31. This is conducive to preventing the Schottky barrier layer 5 from contacting the gate 6 during preparation, resulting in a gate-source short circuit. In addition, in the embodiment shown in Figure 5, in the horizontal direction X, the spacing between the first side wall 61 of the gate 6 and the second side wall 31 of the gate-source isolation structure 3 can be greater than or equal to 200nm, and can be optionally 300 to 500nm, but is not limited thereto.

[0060] In the embodiments shown in Figures 1 to 5, the Schottky barrier layer 5 is in direct contact with the gate-source isolation structure 3. However, the present invention is not limited thereto. Optionally, Figure 6 is a schematic structural diagram of another field-effect transistor with an integrated Schottky barrier provided in an embodiment of the present application. In the embodiment shown in Figure 6, the sidewalls of the accommodating area 4 may also be provided with a third isolation medium 11, and the gate-source isolation structure 3 and the Schottky barrier layer 5 are separated by the third isolation medium 11.

[0061] As shown in Figure 6, in this embodiment, the Schottky barrier layer 5 is not in direct contact with the gate-source isolation structure 3. The two are separated by a third isolation dielectric 11. The third isolation dielectric 11 can cover the sidewalls of the gate-source isolation structure 3 and the sidewalls of the gate 6. At this time, the presence of the third isolation dielectric 11 can ensure that the Schottky barrier layer 5 does not contact the gate 6. When preparing the Schottky barrier layer 5, the entire Schottky metal layer 19 can be directly deposited. The alloy layer formed after annealing of the portion of the Schottky metal layer 19 located in the accommodating area 4 and in contact with the JFET area 23 is the Schottky barrier layer 5. Under this setting, the Schottky barrier layer 5 does not need to be prepared using an etching process, which can reduce the difficulty of preparing the Schottky barrier layer 5. On the basis of ensuring gate-source isolation, the registration error during etching of the two-layer structure is avoided. One thing that needs to be explained is that when the third isolation dielectric 11 is prepared, a whole layer of the third isolation dielectric layer to be processed is first deposited, and then the third isolation dielectric layer to be processed except for the side wall of the accommodating area 4 is etched away to form the third isolation dielectric 11. However, due to the influence of the etching process, some step areas will still retain part of the third isolation dielectric layer to be processed.

[0062] Illustratively, the width of the third isolation medium 11 in the horizontal direction X may be less than or equal to 800 nm, and optionally less than or equal to 500 nm, but is not limited thereto.

[0063] Figure 7 is a schematic structural diagram of another field-effect transistor with an integrated Schottky barrier provided in an embodiment of the present application. Referring to Figure 7, in a possible embodiment, the first conductive type epitaxial layer 2 may also include a second conductive type electric field suppression region 24 and a first conductive type current extension region 25. The second conductive type electric field suppression region 24 is located in the middle of the JFET region 23 and contacts the Schottky barrier layer 5. The first conductive type current extension region 25 is at least located in the JFET region 23 and surrounds the second conductive type electric field suppression region 24.

[0064] As shown in Figure 7, a second-conductivity-type electric field suppression region 24 is provided at the central top of the JFET region 23. The second-conductivity-type electric field suppression region 24 contacts the middle portion of the Schottky barrier layer 5. Its width in the horizontal direction X can be greater than or equal to 200 nm, and can optionally be 500 nm to 1 μm. The JFET region 23 is also provided with a first-conductivity-type current expansion region 25, which surrounds the second-conductivity-type electric field suppression region 24. Taking a single side of the accommodation region 4 as an example, the horizontal width of the region where the Schottky barrier layer 5 does not contact the second-conductivity-type electric field suppression region 24 (i.e., the region where the Schottky barrier layer 5 contacts the first-conductivity-type current expansion region 25) is no less than 300 nm, and can optionally be no less than 500 nm. The provision of the second-conductivity-type electric field suppression region 24 can reduce Schottky barrier leakage in the device's blocking state, i.e., reverse bias leakage in the blocking state.

[0065] In addition, in this embodiment, the doping concentration of the first conductive type current extension region 25 can be set to be lower than the doping concentration of part of the second conductive type doping region 21. For example, the first conductive type current extension region 25 can be formed by selectively doping in the JFET region 23. In this case, the doping concentration of the first conductive type current extension region 25 can be higher than the doping concentration of the low-doping region 21-2 and lower than the doping concentration of the high-doping region 21-1. Alternatively, the first conductive type current extension region 25 can be formed by implanting doping in the entire unit cell. In this case, the doping concentration of the first conductive type current extension region 25 can be lower than or equal to the doping concentration of the low-doping region 21-2. By providing the first conductive type current extension region 25, the current conduction capability can be improved and the on-resistance can be reduced.

[0066] Optionally, Figure 8 is a structural schematic diagram of another field-effect transistor with an integrated Schottky barrier provided in an embodiment of the present application, which can be combined with reference to Figures 1, 5 and 8. The cross-sectional shape of the gate-source isolation structure 3 on the plane perpendicular to the first conductive type epitaxial layer 2 is triangular, quasi-triangular, trapezoidal or quasi-trapezoidal.

[0067] When preparing the gate-source isolation structure 3, the gate-source isolation structure 3 can be prepared into a triangle, a quasi-triangle, a trapezoid or a quasi-trapezoidal shape by wet etching and / or dry etching process. The etching method can be selected by a person skilled in the art according to actual needs, and this application does not limit this. As shown in Figure 1, when the cross-sectional shape of the gate-source isolation structure 3 is a triangle or a quasi-triangle, the thickness of the gate-source isolation structure 3 gradually decreases along the gate-source isolation structure 3 close to the Schottky barrier layer 5 and pointing away from the Schottky barrier layer 5; at this time, the thickest area of ​​the gate-source isolation structure 3 is shorter in the lateral direction, the device gate control capability is stronger, and the device on-resistance is lower; and under the same unit cell size, the horizontal size of the Schottky barrier layer 5 is larger, the body diode freewheeling capability and the irradiation excess carrier extraction capability are stronger. As shown in Figures 5 and 8 , when the cross-sectional shape of the gate-source isolation structure 3 is trapezoidal or quasi-trapezoidal, a constant-thickness region of a certain length exists on the side of the gate-source isolation structure 3 near the Schottky barrier layer 5. That is, the thickness of the portion of the gate-source isolation structure 3 near the Schottky barrier layer 5 remains substantially constant, and the dimension of the constant-thickness region along the horizontal direction X can be less than or equal to 500 nm, and can optionally be less than or equal to 200 nm. With this arrangement, when etching the accommodation region 4, the accommodation region 4 is formed in a flat region of the gate-source isolation structure 3, which can appropriately reduce the precision requirements of the photolithography etching process.

[0068] Optionally, referring to Figures 1 to 8 , the first conductive type epitaxial layer 2 may further include a second conductive type heavily doped region 26, and the second conductive type heavily doped region 26 is located on the side of the first conductive type doped region 22 away from the JFET region 23; the field effect transistor with integrated Schottky barrier may further include an ohmic contact layer 12, a source 9 and a drain 13, and the ohmic contact layer 12 covers part of the first conductive type doped region 22 and the second conductive type heavily doped region 26; the source 9 covers the Schottky barrier layer 5 and the ohmic contact layer 12, and the drain 13 is located on the side of the first conductive type substrate 1 away from the first conductive type epitaxial layer 2.

[0069] As shown in Figures 1 to 8 , a heavily doped second conductivity type region 26 may also be formed on the side of the second conductivity type doped region 21 away from the JFET region 23. The heavily doped second conductivity type region 26 extends downward from the upper surface of the first conductivity type epitaxial layer 2. The presence of the heavily doped second conductivity type region 26 improves the electrical contact of the second conductivity type, reduces series resistance, and further enhances the ability to extract excess carriers during irradiation. The ohmic contact layer 12 may cover a portion of the first conductivity type doped region 22 and the heavily doped second conductivity type region 26. The second isolation dielectric layer 10 may extend to and cover a portion of the ohmic contact layer 12. The source 9 of the field effect transistor may be provided as a single layer. The source 9 may be a thickened source metal that covers the ohmic contact layer 12, the second isolation dielectric layer 10 (or the first isolation dielectric layer 8), and the Schottky barrier layer 5. The source 9 and the Schottky barrier layer 5 are electrically interconnected. The drain 13 is located on a side of the first conductive type substrate 1 away from the first conductive type epitaxial layer 2 , forming a vertical structured field effect transistor with an integrated Schottky barrier.

[0070] Optionally, the source electrode 9 and the drain electrode 13 may be Ni, Al, or alloys such as Ti / Al, Al / Cu, and Ba / Au, which is not limited in the embodiment of the present application.

[0071] The field effect transistor with integrated Schottky barrier provided in the embodiments of the present application may also include any structural features known to those skilled in the art, which will not be elaborated or limited in the present application.

[0072] Based on the same concept, the embodiments of the present application also provide a method for preparing a field-effect transistor with an integrated Schottky barrier, which is used to prepare a field-effect transistor with an integrated Schottky barrier provided in any embodiment of the present application. The method for preparing a field-effect transistor with an integrated Schottky barrier provided in the embodiments of the present application includes all the technical features of the field-effect transistor with an integrated Schottky barrier provided in any embodiment of the present application. The following embodiments mainly introduce the content related to the preparation method. For content not fully described, please refer to the above embodiments.

[0073] FIG9 is a flow chart of a method for preparing a field effect transistor with an integrated Schottky barrier according to an embodiment of the present application. Referring to FIG9 , the preparation method includes the following steps.

[0074] S110 , providing a first conductive type substrate.

[0075] S120, forming a first conductive type epitaxial layer on one side of the first conductive type substrate, and forming a second conductive type doped region and a first conductive type doped region in the first conductive type epitaxial layer through a selective doping process; forming a JFET region between adjacent second conductive type doped regions.

[0076] S130. Prepare a gate-source isolation structure, a gate, and a Schottky barrier layer on the surface of the first conductive type epitaxial layer facing away from the first conductive type substrate, and form an accommodating region between adjacent gate-source isolation structures. The accommodating region overlaps with the JFET region along a direction perpendicular to the first conductive type epitaxial layer; the Schottky barrier layer is located in the accommodating region and contacts the JFET region. The gate overlaps with at least the second conductive type doped region along a direction perpendicular to the first conductive type epitaxial layer, and the gate and the Schottky barrier layer are separated by at least the gate-source isolation structure.

[0077] The thickness of the gate-source isolation structure on a side close to the Schottky barrier layer is greater than the thickness of the gate-source isolation structure on a side away from the Schottky barrier layer.

[0078] This approach not only ensures a large contact area between the Schottky barrier layer and the JFET region, but also reduces the device cell size, lowers the device on-resistance, and improves the device's body diode freewheeling capability. Furthermore, the presence of the Schottky barrier layer enhances the ability to extract excess carriers during single-particle irradiation, achieving single-particle reinforcement for the device, strengthening gate protection, and effectively suppressing gate dielectric damage caused by single-particle irradiation, ultimately improving overall device performance.

[0079] The processes of the multiple steps in the above preparation method can be set by those skilled in the art according to actual conditions, and this application does not limit this. The preparation method is introduced below with several optional embodiments.

[0080] For example, FIG10 is a schematic diagram of a method for preparing a field-effect transistor with an integrated Schottky barrier provided in an embodiment of the present application. The structure of the field-effect transistor with an integrated Schottky barrier prepared using this preparation method can be referred to FIG1 . Referring to FIG10 , a first conductive type substrate 1 (FIG. 10(a)) is first provided, for example, a SiC substrate; then, a first conductive type epitaxial layer 2 (FIG. 10(b)) is grown on one side surface of the first conductive type substrate 1, for example, a SiC epitaxial layer.

[0081] Referring to FIG. 10 (c), a second conductivity type doped region 21, a first conductivity type doped region 22, and a second conductivity type heavily doped region 26 are formed in the first conductivity type epitaxial layer 2 through a selective doping implantation process using a mask, and carriers in the doped regions are activated by high-temperature annealing; wherein, a JFET region 23 is located between the two symmetrical second conductivity type doped regions 21; the first conductivity type doped region 22 is located within the second conductivity type doped region 21, and the second conductivity type heavily doped region 26 is located on the side of the first conductivity type doped region 22 facing away from the second conductivity type doped region 21. Optionally, in this step, a highly doped region 21-1 and a low doped region 21-2 may also be prepared in the second conductivity type doped region 21, wherein the highly doped region 21-1, the low doped region 21-2, and the first conductivity type doped region 22 all extend downward from the upper surface of the first conductivity type epitaxial layer 2; the highly doped region 21-1 is located between the first conductivity type doped region 22 and the low doped region 21-2. The injection energy of the high-doped region 21-1 and the low-doped region 21-2 can be set to be the same, and the injection dose of the low-doped region 21-2 is lower than the injection energy of the high-doped region 21-1, ensuring that the doping concentration at the upper surface of the low-doped region 21-2 is lower.

[0082] Referring to FIG. 10 (d), a gate-source isolation dielectric layer 14 is grown on the upper surface of the first conductivity type epitaxial layer 2. An entire layer of the gate-source isolation dielectric layer to be processed can be grown first, and then the gate-source isolation dielectric layer 14 is formed through photolithography and etching processes. The gate-source isolation dielectric layer 14 covers the JFET region 23, and the cross-section of the gate-source isolation dielectric layer 14 is trapezoidal. The etching process in this step can be wet etching or dry etching, with wet etching being preferred. Optionally, after deposition, the gate-source isolation dielectric layer 14 can be subjected to a high-temperature annealing treatment at 850°C using an inert gas such as N2 or Ar.

[0083] Referring to FIG. 10( e ), a gate dielectric layer 15 to be processed and a gate layer 16 to be processed are sequentially grown on the side of the gate-source isolation dielectric layer 14 facing away from the first conductivity type epitaxial layer 2. The gate dielectric layer 15 to be processed covers the gate-source isolation dielectric layer 14, the JFET region 23, the second conductivity type doped region 21, and a portion of the first conductivity type doped region 22. The gate layer 16 to be processed covers the surface of the gate dielectric layer 15 to be processed facing away from the first conductivity type epitaxial layer 2. An entire layer of the gate dielectric layer to be processed and an entire layer of the gate layer to be processed can be grown first, and then the gate dielectric layer 15 to be processed and the gate layer 16 to be processed can be formed using photolithography and etching processes.

[0084] Referring to Figure 10 (f), a first isolation dielectric layer 17 to be processed is grown on the surface of the side of the gate layer 16 to be processed away from the first conductive type epitaxial layer 2, and the first isolation dielectric layer 17 to be processed covers the gate metal layer 16 and a portion of the first conductive type doped region 22; then, an ohmic contact layer 12 is deposited on the upper surface of a portion of the first conductive type doped region 22 and the second conductive type heavily doped region 26 (not covering the surface of the first isolation dielectric layer 17 to be processed) and annealed to form an ohmic contact.

[0085] Referring to Figure 10 (g), the first isolation dielectric layer 17 to be processed, the gate layer 16 to be processed, the gate dielectric layer 15 to be processed, and the gate-source isolation dielectric layer 14 above the JFET region 23 are etched to form an accommodating region 4 above the JFET region. The first isolation dielectric layer 17 to be processed that remains after etching is the first isolation dielectric layer 8 shown in Figure 1, the gate layer 16 to be processed that remains after etching is the gate 6 shown in Figure 1, the gate dielectric layer 15 to be processed that remains after etching is the gate dielectric layer 7 shown in Figure 1, and the gate-source isolation dielectric layer 14 to be processed that remains after etching is the gate-source isolation structure 3 shown in Figure 2. Subsequently, a Schottky barrier layer 5 is formed at the bottom of the accommodating region 4. In this step, a lift-off process can be used to first deposit an entire layer of Schottky metal layer, then remove the Schottky metal layer outside the accommodating region 4 and anneal it to form the Schottky barrier layer 5. Alternatively, before depositing the Schottky metal layer, an additional wet etching process may be used to laterally etch away part of the gate 6 so that the sidewalls of the gate 6 are recessed, thereby preventing the Schottky barrier layer 5 from contacting the gate 6 during preparation and causing a gate-source short circuit.

[0086] Referring to FIG. 10( h ), a second isolation dielectric layer 10 is grown on the upper surface of the first isolation dielectric layer 8. The second isolation dielectric layer 10 covers the portion of the upper surface of the Schottky barrier layer 5 near the gate-source isolation structure 3, the second sidewall of the gate-source isolation structure 3, the first sidewall of the gate, and the entire first isolation dielectric layer 7. The entire second isolation dielectric layer to be processed can be deposited first, and then the portion of the second isolation dielectric layer to be processed above the accommodating region 4 and above the ohmic contact layer 12 can be etched away to form the second isolation dielectric layer 10. Subsequently, a source electrode 9 is formed above the ohmic contact layer 12, the second isolation dielectric layer 10, and the Schottky barrier layer 5, and a drain electrode 13 is formed on the side of the first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2.

[0087] For example, Figure 11 is a schematic diagram of another method for fabricating a field-effect transistor with an integrated Schottky barrier according to an embodiment of the present application. The structure of the field-effect transistor with an integrated Schottky barrier fabricated using this method can be seen in Figure 5 . As shown in Figure 11 , in this embodiment, the steps from providing the first conductivity type substrate 1 to fabricating the gate-source isolation dielectric layer 14 are identical to the steps shown in Figures (a) to (d) of Figure 10 above and are not further described here.

[0088] The difference from the above embodiment is that, in this embodiment, referring to FIG. 11 (e), a gate dielectric layer 15 to be processed and a gate layer 16 to be processed are sequentially grown on the side of the gate-source isolation dielectric layer 14 away from the first conductive type epitaxial layer 2 using photolithography and etching processes. The gate dielectric layer 15 to be processed covers the gate-source isolation dielectric layer 14, the JFET region 23, the second conductive type doped region 21, and a portion of the first conductive type doped region 22. The gate layer 16 to be processed covers the surface of the gate dielectric layer 15 to be processed away from the first conductive type epitaxial layer 2. Subsequently, the gate dielectric layer 15 to be processed and the gate layer 16 to be processed above the JFET region 23 are etched away to form an opening above the gate-source isolation dielectric layer 14 corresponding to the JFET region 23, with a portion of the gate-source isolation dielectric layer 14 exposed from the opening. The gate layer 16 to be processed that remains after etching is the gate 6 shown in FIG. 2, and the gate dielectric layer 15 to be processed that remains after etching is the gate dielectric layer 7 shown in FIG. 2.

[0089] Referring to Figure 11 (f), the first isolation dielectric layer 17 to be processed continues to grow, and the first isolation dielectric layer 17 to be processed covers the gate 6, the exposed gate-source isolation dielectric layer 14 and a portion of the first conductive type doped region 22; then, an ohmic contact layer 11 is deposited on the upper surface of a portion of the first conductive type doped region 22 and the second conductive type heavily doped region 26 (not covering the surface of the first isolation dielectric layer 17 to be processed) and annealed to form an ohmic contact.

[0090] Referring to Figure 11 (g), the first isolation dielectric layer 17 to be processed and the gate-source isolation dielectric layer 14 above the JFET region 23 are etched to form a first isolation dielectric layer 8 and a gate-source isolation structure 3. The horizontal dimension of the etched area is smaller than the spacing between the two gates 6, that is, the boundary of the etched area can be located in the flat area on the upper surface of the gate-source isolation dielectric layer 14. At this time, along the direction perpendicular to the first conductive type epitaxial layer 2, the first isolation dielectric layer 8 covers the gate-source isolation structure 3, the gate dielectric layer 7 and the gate 6. Under this setting, there is no need to set a second isolation dielectric layer, and gate-source isolation can be achieved using only the first isolation dielectric layer 8, thereby simplifying the preparation process and reducing the overall thickness of the device. The preparation method of the source 9 and the drain 13 is the same as that of the embodiment shown in Figure 10 above, and will not be described here.

[0091] For example, Figure 12 is a schematic diagram illustrating another method for fabricating a field-effect transistor with an integrated Schottky barrier according to an embodiment of the present application. The structure of the field-effect transistor with an integrated Schottky barrier fabricated using this method can be seen in Figure 6 . As shown in Figure 12 , in this embodiment, the steps from providing a first conductive type substrate 1 to preparing a first isolation dielectric layer 17 to be processed are identical to the steps illustrated in Figures (a) through (f) of Figure 10 above and are not further described here.

[0092] The difference from the embodiment shown in FIG10 is that, referring to FIG12(g), in this embodiment, after etching the first isolation dielectric layer 17 to be processed, the gate layer 16 to be processed, the gate dielectric layer 15 to be processed, and the gate-source isolation dielectric layer 14 above the JFET region 23 to form the first isolation dielectric layer 8, the gate 6, the gate dielectric layer 7, the gate-source isolation structure 3, and the accommodating region 4, a full layer of the third isolation dielectric layer 18 to be processed can be grown on the side of the first isolation dielectric layer 8 away from the first conductivity type epitaxial layer 2. Subsequently, a portion of the third isolation dielectric layer 18 to be processed is etched away, leaving only a portion of the third isolation dielectric layer 18 to be processed on the sidewall of the accommodating region 4 to form the third isolation dielectric 11. Subsequently, a full layer of Schottky metal layer 19 is prepared, and the portion of the Schottky metal layer 19 located within the accommodating region 4 and in contact with the JFET region 23 serves as the Schottky barrier layer 5. Due to the presence of the third isolation dielectric 11, in this embodiment, there is no need to use an etching process to remove part of the Schottky metal layer 19, which can reduce the difficulty of preparing the Schottky barrier layer 5 and avoid registration errors during etching of the two-layer structure while ensuring gate-source isolation.

[0093] Referring to Figure 12 (h), the source electrode 9 can be directly prepared on the upper surface of the Schottky metal layer 19, and the drain electrode 12 can be prepared on the side of the first conductive type substrate 1 away from the first conductive type epitaxial layer 2, without growing a second isolation dielectric layer, thereby simplifying the process flow.

Claims

1. A field-effect transistor with an integrated Schottky barrier, comprising: a first conductive type substrate; an epitaxial layer of the first conductivity type located on one side of the substrate of the first conductivity type, the epitaxial layer of the first conductivity type including a doped region of the second conductivity type, the doped region of the second conductivity type including a doped region of the first conductivity type, and a junction field effect transistor (JFET) region formed between adjacent doped regions of the second conductivity type; a gate-source isolation structure, located on a surface of the first conductive type epitaxial layer facing away from the first conductive type substrate, wherein an accommodation region is formed between adjacent gate-source isolation structures, and the accommodation region overlaps the JFET region along a direction perpendicular to the first conductive type epitaxial layer; a Schottky barrier layer, the Schottky barrier layer being located in the accommodating region and contacting the JFET region; a gate located on a side of the first conductive type epitaxial layer facing away from the first conductive type substrate, wherein along a direction perpendicular to the first conductive type epitaxial layer, the gate at least overlaps with the second conductive type doped region, and the gate and the Schottky barrier layer are separated by at least the gate-source isolation structure; The thickness of the gate-source isolation structure on a side close to the Schottky barrier layer is greater than the thickness of the gate-source isolation structure on a side away from the Schottky barrier layer.

2. The field-effect transistor with integrated Schottky barrier according to claim 1, wherein: The second conductive type doping region further includes a high doping region and a low doping region, wherein the high doping region, the low doping region and the first conductive type doping region all extend downward from the first conductive type epitaxial layer toward a side surface of the gate-source isolation structure; the high doping region is located between the first conductive type doping region and the low doping region; The gate-source isolation structure covers at least a portion of the low-doping region, and along a direction perpendicular to the first conductive type epitaxial layer, the gate-source isolation structure does not overlap with the high-doping region.

3. The field effect transistor with integrated Schottky barrier according to claim 2, wherein: The depth of the low-doped region in the first conductive type epitaxial layer is greater than or equal to the depth of the high-doped region in the first conductive type epitaxial layer; or, The depth of the low-doping region in the first conductive type epitaxial layer is smaller than the depth of the high-doping region in the first conductive type epitaxial layer.

4. The field effect transistor with integrated Schottky barrier according to claim 1, wherein: The orthographic projection of the gate-source isolation structure on the first conductive type epitaxial layer is located within the JFET region; Along the direction from the JFET region to the second conductive type doping region, the distance between the side of the gate-source isolation structure away from the Schottky barrier layer and the second conductive type doping region is greater than or equal to 10nm.

5. The field-effect transistor with integrated Schottky barrier according to claim 1 , further comprising a gate dielectric layer and a first isolation dielectric layer, wherein the gate dielectric layer at least partially covers the gate-source isolation structure and the second conductivity type doped region, and the gate is located on a surface of the gate dielectric layer facing away from the first conductivity type epitaxial layer; The first isolation dielectric layer covers the gate and a portion of the first conductive type doped region; The side wall of the gate facing the Schottky barrier layer is defined as a first side wall of the gate, and the side wall of the gate-source isolation structure facing the Schottky barrier layer is defined as a second side wall of the gate-source isolation structure; The gate dielectric layer covers the entire surface of the gate-source isolation dielectric on a side facing away from the first conductive type epitaxial layer, and the field effect transistor with integrated Schottky barrier further includes a second isolation dielectric layer, which covers a portion of the Schottky barrier layer in contact with the second sidewall, the first sidewall, the second sidewall, and the first isolation dielectric layer; Alternatively, the surface of the gate-source isolation structure facing away from the first conductive type epitaxial layer includes a first surface and a second surface that are connected, the first surface is used to connect the second side wall and the second surface, the gate dielectric layer covers the second surface, and the first isolation dielectric layer also covers the first surface and the first side wall.

6. The field effect transistor with integrated Schottky barrier according to claim 1, wherein: A third isolation dielectric is provided on the sidewall of the accommodating region, and the gate-source isolation structure and the Schottky barrier layer are separated by the third isolation dielectric.

7. The field effect transistor with integrated Schottky barrier according to claim 1, wherein: The first conductive type epitaxial layer also includes a second conductive type electric field suppression region and a first conductive type current extension region. The second conductive type electric field suppression region is located in the middle of the JFET region and contacts the Schottky barrier layer. The first conductive type current extension region surrounds the second conductive type electric field suppression region.

8. The field effect transistor with integrated Schottky barrier according to claim 1, wherein: The cross-sectional shape of the gate-source isolation structure on a plane perpendicular to the first conductive type epitaxial layer is triangular, quasi-triangular, trapezoidal or quasi-trapezoidal.

9. The field effect transistor with integrated Schottky barrier according to claim 1, wherein: The first conductive type epitaxial layer further includes a second conductive type heavily doped region, and the second conductive type heavily doped region is located on a side of the first conductive type doped region away from the JFET region; The field effect transistor with integrated Schottky barrier also includes an ohmic contact layer, a source and a drain, wherein the ohmic contact layer covers a portion of the first conductive type doped region and the second conductive type heavily doped region; the source covers the Schottky barrier layer and the ohmic contact layer, and the drain is located on the side of the first conductive type substrate away from the first conductive type epitaxial layer.

10. A method for preparing a field-effect transistor with an integrated Schottky barrier, for preparing the field-effect transistor with an integrated Schottky barrier according to any one of claims 1 to 9, the method comprising: providing a first conductive type substrate; forming a first conductive type epitaxial layer on one side of the first conductive type substrate, and forming a second conductive type doped region and a first conductive type doped region in the first conductive type epitaxial layer by a selective doping process; and forming a junction field effect transistor (JFET) region between adjacent second conductive type doped regions; A gate-source isolation structure, a gate, and a Schottky barrier layer are prepared on the surface of the first conductive type epitaxial layer facing away from the first conductive type substrate, and an accommodating region is formed between adjacent gate-source isolation structures. The accommodating region overlaps with the JFET region along a direction perpendicular to the first conductive type epitaxial layer; the Schottky barrier layer is located in the accommodating region and contacts the JFET region, and the gate overlaps with at least the second conductive type doped region along a direction perpendicular to the first conductive type epitaxial layer, and the gate and the Schottky barrier layer are separated by at least the gate-source isolation structure; wherein the thickness of the gate-source isolation structure on the side close to the Schottky barrier layer is greater than its thickness on the side away from the Schottky barrier layer.

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