Novel junction field effect transistor

Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a novel junction field effect transistor, which comprises a JFET (junction field effect transistor), a parasitic PNP (plug-and-play) transistor and a parasitic high-voltage diode which are arranged on the same P-type epitaxy, the base electrode and the emitter electrode of the PNP tube are in short circuit with the source electrode of the JFET, the collector electrode of the PNP tube is connected with the bulk end of the JFET, the cathode of the high-voltage diode is connected with the drain electrode of the JFET, the anode of the high-voltage diode is connected with the bulk end of the JFET, and the grid electrode of the JFET is connected with the bulk end of the JFET.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a novel junction field effect transistor. Background Art

[0002] In the prior art, junction field effect transistors (JFETs) are usually not protected against ESD and have poor ESD pulse resistance, especially when used as BSDs in a half-bridge process, the ESD resistance of the source of the JFET will affect the overall reliability of the entire circuit.

[0003] Therefore, there is an urgent need for a junction field effect transistor that is resistant to ESD pulses. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide a novel junction field effect transistor, which can effectively improve the reliability of the junction field effect transistor.

[0005] The present invention provides a novel junction field effect transistor, comprising: a JFET, a parasitic PNP tube and a parasitic high-voltage diode arranged on the same P-type epitaxial layer;

[0006] The base and emitter of the PNP tube short-circuit the source of the JFET, the collector of the PNP tube is connected to the bulk end of the JFET, the cathode of the high-voltage diode is connected to the drain of the JFET, the anode of the high-voltage diode is connected to the bulk end of the JFET, and the gate of the JFET is connected to the bulk end of the JFET.

[0007] In a possible implementation, the breakdown voltage of the PNP tube is greater than the pinch-off voltage of the JFET.

[0008] In a possible implementation, the P-type epitaxy is placed above a P substrate, and an N-type buried layer is provided in a partial area between the P-type epitaxy and the P substrate;

[0009] A first N-well region is provided above the P-type epitaxy, a second N-well region is provided inside the first N-well region, a first P-well region is provided outside the first N-well region, and a first N-type depletion layer region is provided between the first N-well region and the first P-well region;

[0010] A first N+ doping region is provided inside the second N-well region, a second N+ doping region, a third N+ doping region and a first P+ doping region are provided inside the first N-type depletion layer region, and a second P+ doping region is provided inside the first P-well region;

[0011] The first N-type depletion layer region is used as the base of the PNP tube, and the second N+ doping region and the third N+ doping region are used as the base of the PNP tube;

[0012] The first P+ doping region is the emitter of the PNP tube; the first P well region is the collector of the PNP tube, and the second P+ doping region is the collector lead of the PNP tube.

[0013] In a possible implementation manner, the second N+ doping region and the third N+ doping region are led out as the base of the PNP transistor.

[0014] In a possible implementation manner, the second N+ doped region is led out as the base of the PNP transistor.

[0015] In a possible implementation manner, the third N+ doped region is led out as the base of the PNP transistor.

[0016] In a possible implementation manner, a first P-type buried layer region is provided below the first N-type depletion layer region.

[0017] In a possible implementation, the first N-well region includes: a high-voltage well region DNW, a low-voltage well region NW and an N-type depletion layer region Ndrft;

[0018] The high-voltage well region DNW is located at the bottom and serves as the drift region of the JFET for carrying the withstand voltage; the low-voltage well region NW serves as the drain of the JFET, and the N-type depletion layer region Ndrft serves as the source of the JFET; the structure of the second N-well region is the same as that of the first N-well region.

[0019] In a possible implementation, a portion of the N-type depletion layer region Ndrft is located below the GT end of the JFET, serving as a channel of the JFET; the second N+ doped region is located above the N-type depletion layer region Ndrft, serving as a source lead of the JFET.

[0020] In a possible implementation, the third N+ doped region is located above the N-type depletion layer region Ndrft, and is used to adjust the breakdown voltage of the parasitic PNP tube so that the breakdown voltage of the parasitic PNP tube is greater than the pinch-off voltage of the JFET.

[0021] The novel junction field effect transistor provided by the present invention adds a PNP transistor to the conventional structure in an innovative manner, which can effectively improve the reliability of the junction field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of an existing JFET;

[0023] Figure 2 It is the circuit schematic diagram of the existing JFET;

[0024] Figure 3A schematic diagram of the structure of a novel junction field effect transistor provided by an embodiment of the present invention;

[0025] Figure 4 A circuit schematic diagram of a novel junction field effect transistor provided by an embodiment of the present invention;

[0026] Figure 5 A schematic diagram of a derivative structure of a novel junction field effect transistor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following detailed description of the embodiments of the present invention is further described in detail in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention, that is, the present invention is not limited to the preferred embodiments described, and the scope of the present invention is defined by the claims.

[0028] In the description of the present invention, it should be noted that, unless otherwise specified, “plurality” means two or more than two; the terms “first”, “second”, etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; for ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0029] Figure 4 The circuit schematic diagram of the novel junction field effect transistor provided by the embodiment of the present invention is as follows: Figure 4 As shown, the present invention provides a novel junction field effect transistor, comprising: a JFET, a parasitic PNP tube Q1 and a parasitic high-voltage diode D1 arranged on the same P-type epitaxial;

[0030] The base and emitter of the PNP tube Q1 short-circuit the source of the JFET, the collector of the PNP tube Q1 is connected to the bulk end of the JFET, the cathode of the high-voltage diode D1 is connected to the drain of the JFET, the anode of the high-voltage diode D1 is connected to the bulk end of the JFET, and the gate of the JFET is connected to the bulk end of the JFET.

[0031] Figure 2 FIG. 1 is a circuit schematic diagram of an existing JFET. The PNP transistor Q1 of the present invention can effectively improve the ESD capability of the JFET by utilizing this structure without adding any additional layers.

[0032] In a possible implementation, the breakdown voltage of the PNP transistor Q1 is greater than the pinch-off voltage of the JFET, which can effectively ensure that the JFET will be pinched off without leakage under high voltage.

[0033] Figure 3 A schematic diagram of the structure of a novel junction field effect transistor provided by an embodiment of the present invention is shown in FIG. Figure 3As shown, the novel junction field effect transistor includes: substrate layer Psub, N+ buried layer Nbury, P-type epitaxial Pepi, high-voltage N well DNW, low-voltage N well region NW, low-voltage P well region PW, N-type depletion layer region Ndrft, P-type buried layer region Pdrft, field oxygen region Fox, gate polyGT, P+ active region P+, N+ active region N+. The present invention improves the ESD pulse resistance of JFET by optimizing the source of JFET to form a PNP structure with high electrostatic discharge capability.

[0034] The P-type epitaxy 300 is placed on the P substrate 100, and an N-type buried layer 200 is provided in a part of the area between the P-type epitaxy 300 and the P substrate 100;

[0035] A first N-well region 400 is disposed above the P-type epitaxy 300, a second N-well region 401 is disposed inside the first N-well region 400, a first P-well region 402 is disposed outside the first N-well region 400, and a first N-type depletion layer region 500 is disposed between the first N-well region 400 and the first P-well region 402;

[0036] A first N+ doping region 705 is provided inside the second N-well region 401, a second N+ doping region 704, a third N+ doping region 702 and a first P+ doping region 703 are provided inside the first N-type depletion layer region 500, and a second P+ doping region 701 is provided inside the first P-well region 402;

[0037] The first N-type depletion layer region 500 serves as the base of the PNP transistor Q1 , and the second N+ doping region 704 and the third N+ doping region 702 serve as the base of the PNP transistor Q1 ;

[0038] The first P+ doping region 703 is the emitter of the PNP transistor Q1 ; the first P well region 701 is the collector of the PNP transistor Q1 ; and the second P+ doping region 701 is the collector lead of the PNP transistor Q1 .

[0039] In a possible implementation, the second N+ doping region 704 and the third N+ doping region 702 are led out as the base of the PNP transistor Q1 .

[0040] In a possible implementation, the second N+ doping region 704 is led out as the base of the PNP transistor Q1 .

[0041] In a possible implementation, the third N+ doping region 702 is led out as the base of the PNP transistor Q1 .

[0042] In a possible implementation, a first P-type buried layer region 501 is provided below the first N-type depletion layer region 500. The first P-type buried layer region 501 can be removed or used as a PNP tube as an ESD discharge tube.

[0043] In a possible implementation, the first N-well region includes: a high-voltage well region DNW, a low-voltage well region NW and an N-type depletion layer region Ndrft;

[0044] The high-voltage well region DNW is located at the bottom and serves as the drift region of the JFET for carrying the withstand voltage; the low-voltage well region NW serves as the drain of the JFET, and the N-type depletion layer region Ndrft serves as the source of the JFET; the structure of the second N-well region is the same as that of the first N-well region.

[0045] In a possible implementation, a portion of the N-type depletion layer region Ndrft is located below the GT end of the JFET, serving as the channel of the JFET; the second N+ doped region 704 is located above the N-type depletion layer region Ndrft, serving as the source lead of the JFET.

[0046] In a possible implementation, the third N+ doping region 702 is located on the upper portion of the N-type depletion layer region Ndrft, and is used to adjust the breakdown voltage of the parasitic PNP tube so that the breakdown voltage of the parasitic PNP tube is greater than the pinch-off voltage of the JFET.

[0047] like Figure 5 is Figure 3 Based on this, the structure is deformed, and the P-type buried layer area Pdrft501 can be removed below the N-type depletion layer area Ndrft. Since this Pdrft is located in P-epi and connected to PW, the concentration of Pepi can be reduced and the parasitic resistance of the anode area of ​​the high-voltage diode can be increased after removal, so the ESD resistance of JFET can be enhanced.

[0048] When the ESD signal occurs at the drain of the JFET, the source voltage of the JFET is raised and the transistor is quickly cut off. The ESD discharges current through the parasitic high-voltage diode. However, since the breakdown point of the high-voltage diode is located at the junction where the first N-well region, the first P-type buried layer region and the first N-type depletion layer region intersect, the breakdown current first passes through the P-type buried layer region, then to PW, and finally flows out through the anode lead-out terminal. Since the P-type buried layer region is relatively light, a large resistance will be generated, causing the voltage of the P-type buried layer region at the junction of the high-voltage diode to be raised, generating a voltage higher than the source of the JFET, and current will flow from the source of the JFET to GND. At this time, the PNP parasitic on the source quickly starts to discharge current, avoiding damage to the source due to excessive voltage.

[0049] The novel junction field effect transistor provided by the present invention has a structural innovation of the source electrode based on the original conventional JFET, and uses the existing layers to make structural changes to parasitize a PNP tube with strong ESD discharge capability, while ensuring that the pinch-off of the JFET is not affected, effectively improving the reliability of the JFET, and improving the disadvantage of poor ESD capability when used in some special places, such as as a BSD. However, the use of the structure of the present invention is not limited to BSD, and is applicable to any place where JFET is used.

[0050] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A novel junction field effect transistor, characterized in that: include: A JFET, a parasitic PNP tube (Q1) and a parasitic high-voltage diode (D1) arranged on the same P-type epitaxial layer; The base and emitter of the PNP tube (Q1) short-circuit the source of the JFET, the collector of the PNP tube (Q1) is connected to the bulk end of the JFET, the cathode of the high-voltage diode (D1) is connected to the drain of the JFET, the anode of the high-voltage diode (D1) is connected to the bulk end of the JFET, and the gate of the JFET is connected to the bulk end of the JFET.

2. The novel junction field effect transistor according to claim 1, characterized in that: The breakdown voltage of the PNP tube (Q1) is greater than the pinch-off voltage of the JFET.

3. The novel junction field effect transistor according to claim 1, characterized in that: The P-type epitaxy (300) is placed above the P substrate (100), and an N-type buried layer (200) is provided in a partial area between the P-type epitaxy (300) and the P substrate (100); A first N-well region (400) is provided above the P-type epitaxy (300), a second N-well region (401) is provided inside the first N-well region (400), a first P-well region (402) is provided outside the first N-well region (400), and a first N-type depletion layer region (500) is provided between the first N-well region (400) and the first P-well region (402); A first N+ doping region (705) is provided inside the second N-well region (401), a second N+ doping region (704), a third N+ doping region (702) and a first P+ doping region (703) are provided inside the first N-type depletion layer region (500), and a second P+ doping region (701) is provided inside the first P-well region (402); The first N-type depletion layer region (500) serves as the base of the PNP transistor (Q1), and the second N+ doping region (704) and the third N+ doping region (702) serve as the base of the PNP transistor (Q1); The first P+ doping region (703) is the emitter of the PNP transistor (Q1); the first P well region (701) is the collector of the PNP transistor (Q1); and the second P+ doping region (701) is the collector lead of the PNP transistor (Q1).

4. The novel junction field effect transistor according to claim 3, characterized in that: The second N+ doping region (704) and the third N+ doping region (702) are used as base leads of the PNP transistor (Q1).

5. The novel junction field effect transistor according to claim 3, characterized in that: The second N+ doped region (704) is led out as the base of the PNP transistor (Q1).

6. The novel junction field effect transistor according to claim 3, characterized in that: The third N+ doping region (702) is led out as the base of the PNP transistor (Q1).

7. The novel junction field effect transistor according to claim 3, characterized in that: A first P-type buried layer region (501) is provided below the first N-type depletion layer region (500).

8. The novel junction field effect transistor according to claim 3, characterized in that: The first N-well region includes: a high-voltage well region DNW, a low-voltage well region NW and an N-type depletion layer region Ndrft; The high-voltage well region DNW is located at the bottom and serves as the drift region of the JFET for carrying the withstand voltage; the low-voltage well region NW serves as the drain of the JFET, and the N-type depletion layer region Ndrft serves as the source of the JFET; the structure of the second N-well region is the same as that of the first N-well region.

9. The novel junction field effect transistor according to claim 8, characterized in that: A portion of the N-type depletion layer region Ndrft is located below the GT end of the JFET, serving as a channel of the JFET; the second N+ doped region (704) is located above the N-type depletion layer region Ndrft, serving as a source lead of the JFET.

10. The novel junction field effect transistor according to claim 9, characterized in that: The third N+ doping region (702) is located on the upper part of the N-type depletion layer region Ndrft and is used to adjust the breakdown voltage of the parasitic PNP tube so that the breakdown voltage of the parasitic PNP tube is greater than the pinch-off voltage of the JFET.

Images