Semiconductor structure and forming method thereof
By forming a specific gate dielectric layer and work function layer structure on the substrate surface of the Schottky diode, the problem of large junction capacitance of Schottky diodes is solved, and the effect of reducing the junction capacitance and maintaining the reverse breakdown voltage is achieved.
Patent Information
- Application Number
- CN202311288472.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-07
- Publication Date
- 2025-04-11
AI Technical Summary
The Schottky diode structure in the existing complementary metal oxide semiconductor process has the problem of large junction capacitance, which limits the operating frequency of the device.
By forming a first gate dielectric layer on the second region surface of the substrate and exposing it to the first region surface, while forming a first work function layer and a first gate layer on the first region surface and the first gate dielectric layer surface, a field plate structure is formed to reduce the edge electric field and make the first work function layer come into direct contact with the silicon substrate to reduce the junction capacitance.
It effectively reduces the junction capacitance of Schottky diodes, alleviates the concentrated electric field effect, and ensures the reverse breakdown voltage of the device, providing more choices for the process.
Smart Images
Figure CN119815896A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor manufacturing process, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] Schottky diode, also known as Schottky barrier diode, is a diode based on the barrier formed by the contact between metal and semiconductor. Compared with the silicon diode formed by PN junction, Schottky diode has the advantages of extremely short reverse recovery time and lower forward conduction voltage drop. Therefore, Schottky diode is widely used in the field of semiconductor technology as a low-power, high-current, ultra-high-speed semiconductor device. At present, Schottky diodes in complementary metal oxide semiconductor (CMOS) processes mostly use metal silicide and silicon to form Schottky contacts.
[0003] However, the structure of Schottky diodes in current complementary metal oxide semiconductor processes needs to be improved. Summary of the invention
[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, propose a Schottky diode structure in which a work function layer and silicon form a Schottky contact and reduce the junction capacitance of the Schottky diode structure.
[0005] In order to solve the above technical problems, the technical solution of the present invention proposes a semiconductor structure and a method for forming the same, wherein the formation method comprises: providing a substrate, the substrate comprising a diode region, the diode region comprising a first region and a second region located around the first region; forming a first gate dielectric layer on the surface of the second region, the first gate dielectric layer exposing the surface of the first region; forming a first work function layer on the surface of the first region and the surface of the first gate dielectric layer; and forming a first gate layer on the surface of the first work function layer.
[0006] Optionally, a well region is provided in the substrate, and the first region and the second region are located in the well region.
[0007] Optionally, the method further includes: forming an interlayer dielectric layer on the surface of the substrate, wherein the interlayer dielectric layer has an opening, the opening exposes the diode region, and the first gate dielectric layer, the first work function layer and the first gate layer are located in the opening.
[0008] Optionally, the method further includes: forming a first sidewall spacer on the sidewall surface of the opening, wherein the first sidewall spacer is located on the sidewall surfaces of the first gate dielectric layer, the first work function layer and the first gate layer.
[0009] Optionally, the method for forming the first gate dielectric layer includes: forming an initial first gate dielectric layer on the surfaces of the first region and the second region of the diode region; forming a first mask layer on the top surface of the interlayer dielectric layer, the top surface of the first sidewall, the surface of the first sidewall, and a portion of the surface of the initial first gate dielectric layer, the first mask layer exposing a portion of the surface of the initial first gate dielectric layer; using the first mask layer as a mask, etching the initial first gate dielectric layer and the substrate to form a first gate dielectric layer located on the surface of the second region, the first gate dielectric layer exposing the surface of the first region.
[0010] Optionally, the method for forming the initial first gate dielectric layer includes: forming an initial first gate dielectric layer and a dummy gate located on the surface of the initial first gate dielectric layer on the surface of the diode region; forming an interlayer dielectric layer on the surface of the side walls of both sides of the dummy gate, wherein the top surface of the interlayer dielectric layer is flush with the top surface of the dummy gate; removing the dummy gate, forming an opening in the interlayer dielectric layer, wherein the opening exposes the diode region; the method for removing the dummy gate includes: dry etching.
[0011] Optionally, the method further includes: performing ion implantation on the well region; the process parameters of the ion implantation include: the implanted ions are N-type conductive ions.
[0012] Optionally, the method for forming the first work function layer and the first gate layer includes: forming an initial first work function layer and an initial first gate layer located on the surface of the initial first work function layer on the top surface of the interlayer dielectric layer, the surface of the first region, and the surface of the first gate dielectric layer; and planarizing the initial first work function layer and the initial first gate layer until the top surface of the interlayer dielectric layer is exposed to form the first work function layer and the first gate layer.
[0013] Optionally, the substrate further includes a MOS region; the MOS region includes a second gate dielectric layer, a second work function layer located on a surface of the second gate dielectric layer, and a second gate layer located on a surface of the second work function layer.
[0014] Optionally, the method further includes: forming the second gate dielectric layer when forming the first gate dielectric layer; forming the second work function layer when forming the first work function layer; and forming the second gate layer when forming the first gate layer.
[0015] Optionally, a width ratio between the first region and the second region ranges from 1:1 to 4:1.
[0016] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate, the substrate including a diode region, the diode region including a first region and a second region located around the first region; a first gate dielectric layer located on the surface of the second region, the first gate dielectric layer exposing the surface of the first region; a first work function layer located on the surface of the first region and the surface of the first gate dielectric layer; and a first gate layer located on the surface of the first work function layer.
[0017] Optionally, a well region is provided in the substrate; and the first region and the second region are located in the well region.
[0018] Optionally, it further includes: an interlayer dielectric layer located on the surface of the substrate, the interlayer dielectric layer has an opening, the opening exposes the diode region, and the first gate dielectric layer, the first work function layer and the first gate layer are located in the opening.
[0019] Optionally, the first gate dielectric layer includes an oxide layer, a high dielectric constant layer, or both of them overlap.
[0020] Optionally, it also includes: a first sidewall spacer located on the sidewall surface of the opening, wherein the first sidewall spacer is located on the sidewall surfaces of the first gate dielectric layer, the first work function layer and the first gate layer.
[0021] Optionally, the material of the first gate layer includes aluminum.
[0022] Optionally, the substrate also includes a MOS tube region; the semiconductor structure also includes: a gate structure located on the MOS tube region, the gate structure including: a second gate dielectric layer, a second work function layer located on the surface of the second gate dielectric layer, and a second gate layer located on the surface of the second work function layer.
[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0024] In the semiconductor structure provided by the technical solution of the present invention, the first gate dielectric layer is located on the surface of the second region, and the first gate dielectric layer exposes the surface of the first region, and the first work function layer and the first gate layer are located on the surface of the first region and the surface of the first gate dielectric layer. On the one hand, a field plate structure is formed between the first gate dielectric layer and the first gate layer, which reduces the edge electric field of the Schottky diode, alleviates the electric field concentration effect, and ensures the reverse breakdown voltage of the Schottky diode while reducing the junction capacitance; on the other hand, the first work function layer and the first gate layer are located on the surface of the first region and the surface of the first gate dielectric layer, so that the first work function layer is in direct contact with the silicon substrate, forming a Schottky diode structure combining the silicon substrate and the first work function layer, which reduces the junction capacitance of the semiconductor structure and provides more options for the process.
[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first gate dielectric layer is formed on the surface of the second region, the first gate dielectric layer exposes the surface of the first region, and a first work function layer and a first gate layer located on the surface of the first work function layer are formed on the surface of the first region and the surface of the first gate dielectric layer. On the one hand, a field plate structure is formed between the first gate dielectric layer and the first gate layer, which reduces the edge electric field of the Schottky diode, alleviates the electric field concentration effect, and ensures the reverse breakdown voltage of the Schottky diode while reducing the junction capacitance; on the other hand, the first work function layer and the first gate layer are formed on the surface of the first region and the surface of the first gate dielectric layer, so that the first work function layer is in direct contact with the silicon substrate, forming a Schottky diode structure combining the silicon substrate and the first work function layer, reducing the junction capacitance of the semiconductor structure while providing more options for the process. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figures 1 to 6 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0027] As described in the background art, the structure of the Schottky diode in the existing complementary metal oxide semiconductor process needs to be improved.
[0028] In a semiconductor structure of an embodiment, a gate dielectric layer and a substrate form a Schottky diode, and the material of the gate dielectric layer includes metal silicide, which makes the junction capacitance of the semiconductor structure larger and limits the operating frequency of the Schottky diode.
[0029] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein a first gate dielectric layer is formed on the surface of the second region, the first gate dielectric layer exposes the surface of the first region, and a first work function layer and a first gate layer located on the surface of the first work function layer are formed on the surface of the first region and the surface of the first gate dielectric layer. On the one hand, a field plate structure is formed between the first gate dielectric layer and the first gate layer, which reduces the edge electric field of the Schottky diode, alleviates the electric field concentration effect, and ensures the reverse breakdown voltage of the Schottky diode while reducing the junction capacitance; on the other hand, a first work function layer and a first gate layer located on the surface of the first work function layer are formed on the surface of the first region and the surface of the first gate dielectric layer, so that the first work function layer is in direct contact with the silicon substrate, forming a Schottky diode structure combining the silicon substrate and the first work function layer, which reduces the junction capacitance of the semiconductor structure and provides more options for the process.
[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0031] Figures 1 to 6 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.
[0032] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a diode region, wherein the diode region includes a first region I and a second region II located around the first region I.
[0033] The substrate 100 is made of silicon, silicon carbide, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).
[0034] The substrate 100 has a well region therein, and the first region I and the second region II are located in the well region.
[0035] The method for forming the well region includes: performing ion implantation on the substrate 100 ; the process parameters of the ion implantation include: the implanted ions are N-type conductive ions.
[0036] The diode region provides a structural basis for a subsequent Schottky diode structure in which the first work function layer 107 and the substrate 100 form a Schottky contact.
[0037] Specifically, in this embodiment, the substrate 100 further includes a MOS region. The MOS region provides a structural basis for the subsequent formation of a second gate dielectric layer (not shown), a second work function layer (not shown) located on the surface of the second gate dielectric layer (not shown), and a second gate layer (not shown) located on the surface of the second work function layer (not shown).
[0038] A first gate dielectric layer 101 is formed on the surface of the second region II, and the first gate dielectric layer 101 exposes the surface of the first region I. The specific formation process is as follows Figures 2 to 4 shown.
[0039] Please refer to Figure 2 An initial first gate dielectric layer 102 and a dummy gate 103 located on the surface of the initial first gate dielectric layer 102 are formed on the surface of the diode region; an interlayer dielectric layer 104 is formed on the sidewall surfaces of both sides of the dummy gate 103, and the top surface of the interlayer dielectric layer 104 is flush with the top surface of the dummy gate 103.
[0040] Specifically, in this embodiment, the initial first gate dielectric layer 102 includes an oxide layer, a high dielectric constant layer, or both of them overlap.
[0041] The initial first gate dielectric layer 102 serves to space the substrate 100 from the dummy gate 103 , thereby reducing leakage current of the first gate layer 108 subsequently formed in the opening 106 .
[0042] The material of the dummy gate 103 includes polysilicon; the thickness of the dummy gate 103 determines the depth of the opening 106 formed subsequently.
[0043] Specifically, in this embodiment, a first spacer 105 is further provided between the interlayer dielectric layer 104 and the dummy gate 103 . The first spacer 105 is located on the sidewall surfaces of the dummy gate 103 and the initial first gate dielectric layer 102 .
[0044] Please refer to Figure 3 , the dummy gate 103 is removed, and an opening 106 is formed in the interlayer dielectric layer 104 , wherein the opening 106 exposes the diode region.
[0045] The method for removing the dummy gate 103 includes: dry etching.
[0046] Please refer to Figure 4 A first mask layer (not shown) is formed on the top surface of the interlayer dielectric layer 104, the top surface of the first sidewall 105, the sidewall surface of the first sidewall 105, and a portion of the surface of the initial first gate dielectric layer 102, wherein the first mask layer (not shown) exposes a portion of the surface of the initial first gate dielectric layer 102; using the first mask layer (not shown) as a mask, the initial first gate dielectric layer 102 and the substrate 100 are etched to form a first gate dielectric layer 101 located on the surface of the second region II, wherein the first gate dielectric layer 101 exposes the surface of the first region I.
[0047] The etching method includes: dry etching.
[0048] The first gate dielectric layer 101 exposes the surface of the first region I, and subsequently a first work function layer 107 and a first gate layer 108 located on the surface of the first work function layer 107 are formed on the surface of the first region I. On the one hand, a field plate structure is formed between the first gate dielectric layer 101 and the subsequently formed first gate layer 108, which reduces the edge electric field of the Schottky diode, alleviates the electric field concentration effect, and ensures the reverse breakdown voltage of the Schottky diode while reducing the junction capacitance; on the other hand, the subsequently formed first work function layer 107 is in direct contact with the substrate 100, forming a Schottky diode structure combining the substrate 100 and the first work function layer 107, which reduces the junction capacitance of the semiconductor structure and provides more options for the process.
[0049] Specifically, in this embodiment, when the first gate dielectric layer 101 is formed, the second gate dielectric layer (not shown) is formed.
[0050] After forming the first gate dielectric layer 101, a first work function layer 107 is formed on the surface of the first region I and the surface of the first gate dielectric layer 101; and a first gate layer 108 is formed on the surface of the first work function layer 107. For details, please refer to Figures 5 and 6 .
[0051] Please refer to Figure 5 An initial first work function layer 109 and an initial first gate layer 110 located on the surface of the initial first work function layer 109 are formed on the top surface of the interlayer dielectric layer 104 , the surface of the first region I, and the surface of the first gate dielectric layer 101 .
[0052] The initial first work function layer 109 provides a structural basis for the subsequent formation of the first work function layer 107. The first work function layer 107 formed subsequently is in direct contact with the substrate 100, forming a Schottky diode structure combining the substrate 100 and the first work function layer 107, reducing the junction capacitance of the semiconductor structure and providing more options for the process.
[0053] The material of the initial first gate layer 110 includes aluminum.
[0054] The initial first gate layer 110 provides a structural basis for the subsequent formation of the first gate layer 108. A field plate structure is formed between the first gate dielectric layer 101 and the subsequently formed first gate layer 108, which reduces the edge electric field of the Schottky diode, alleviates the electric field concentration effect, and ensures the reverse breakdown voltage of the Schottky diode while reducing the junction capacitance.
[0055] Please refer to Figure 6 , for the initial first work function layer 109 (such as Figure 5 ) and the initial first gate layer 110 (as shown Figure 5 As shown in the figure, a planarization process is performed until the top surface of the interlayer dielectric layer 104 is exposed, thereby forming the first work function layer 107 and the first gate layer 108.
[0056] The material of the first gate layer 108 includes aluminum.
[0057] Specifically, in this embodiment, when the first work function layer 107 is formed, the second work function layer (not shown) is formed; when the first gate layer 108 is formed, the second gate layer (not shown) is formed.
[0058] The planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics.
[0059] Specifically, in this embodiment, the width ratio of the first region I to the second region II is in the range of 1:1 to 4:1.
[0060] Specifically, in this embodiment, by adjusting the depth of the first region I and the width of the first region I, the breakdown voltage of the Schottky diode can be adjusted.
[0061] In the method for forming the semiconductor structure, a first gate dielectric layer 101 is formed on the surface of the second region II, the first gate dielectric layer 101 exposes the surface of the first region I, and a first work function layer 107 and a first gate layer 108 located on the surface of the first work function layer 107 are formed on the surface of the first region I and the surface of the first gate dielectric layer 101. On the one hand, a field plate structure is formed between the first gate dielectric layer 101 and the first gate layer 108, which reduces the edge electric field of the Schottky diode, alleviates the electric field concentration effect, and ensures the reverse breakdown voltage of the Schottky diode while reducing the junction capacitance; on the other hand, the first work function layer 107 and the first gate layer 108 located on the surface of the first work function layer 107 are formed on the surface of the first region I and the surface of the first gate dielectric layer 101, so that the first work function layer 107 is in direct contact with the substrate 100, forming a Schottky diode structure combining the substrate 100 and the first work function layer 107, reducing the junction capacitance of the semiconductor structure and providing more options for the process.
[0062] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 6 , comprising: a substrate 100, the substrate 100 comprising a diode region, the diode region comprising a first region I and a second region II located around the first region I; a first gate dielectric layer located on the surface of the second region II, the first gate dielectric layer 101 exposing the surface of the first region I; a first work function layer 107 located on the surface of the first region I and the surface of the first gate dielectric layer 101; and a first gate layer 108 located on the surface of the first work function layer 107.
[0063] The semiconductor structure includes a substrate 100 . The substrate 100 includes a diode region. The diode region includes a first region I and a second region II located around the first region I.
[0064] The substrate 100 is made of silicon, silicon carbide, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).
[0065] The substrate 100 has a well region therein, and the first region I and the second region II are located in the well region.
[0066] The process parameters of the well region ion implantation include: the implanted ions are N-type conductive ions.
[0067] Specifically, in this embodiment, the substrate 100 further includes a MOS region. The MOS region includes: a second gate dielectric layer (not shown), a second work function layer (not shown) located on the surface of the second gate dielectric layer (not shown), and a second gate layer (not shown) located on the surface of the second work function layer (not shown).
[0068] The semiconductor structure includes: a first gate dielectric layer 101 located on the surface of the second region II, wherein the first gate dielectric layer 101 exposes the surface of the first region I.
[0069] The first gate dielectric layer 101 includes an oxide layer, a high dielectric constant layer, or a combination of the two.
[0070] The semiconductor structure includes an interlayer dielectric layer 104 located on the surface of the substrate 100, and the interlayer dielectric layer 104 has an opening 106 (such as Figure 3 As shown), the opening 106 (as Figure 3 The diode region is exposed, and the first gate dielectric layer 101, the first work function layer 107 and the first gate layer 108 are located in the opening 106 (as shown in FIG. Figure 3 shown).
[0071] The semiconductor structure includes: a first spacer 105 located on the sidewall surface of the opening 106 , and the first spacer 105 is located on the sidewall surfaces of the first gate dielectric layer 101 , the first work function layer 107 and the first gate layer 108 .
[0072] The semiconductor structure includes: a first work function layer 107 located on the surface of the first region I and the surface of the first gate dielectric layer 101 .
[0073] The semiconductor structure includes: a first gate layer 108 located on the surface of the first work function layer 107 .
[0074] The material of the first gate layer 108 includes aluminum.
[0075] The width ratio of the first region I to the second region II is in the range of 1:1 to 4:1.
[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a diode region, the diode region comprising a first region and a second region located around the first region; A first gate dielectric layer located on a surface of the second region, wherein the first gate dielectric layer exposes a surface of the first region; A first work function layer located on a surface of the first region and a surface of the first gate dielectric layer; A first gate layer is located on the surface of the first work function layer.
2. The semiconductor structure according to claim 1, wherein: The substrate has a well region therein; the first region and the second region are located in the well region.
3. The semiconductor structure according to claim 1, wherein: Also includes: An interlayer dielectric layer is located on the surface of the substrate, wherein the interlayer dielectric layer has an opening, wherein the opening exposes the diode region, and wherein the first gate dielectric layer, the first work function layer and the first gate layer are located in the opening.
4. The semiconductor structure according to claim 1, wherein: The first gate dielectric layer includes an oxide layer, a high dielectric constant layer, or a combination of the two.
5. The semiconductor structure according to claim 3, wherein: Also includes: A first sidewall spacer is located on the sidewall surface of the opening, wherein the first sidewall spacer is located on the sidewall surfaces of the first gate dielectric layer, the first work function layer and the first gate layer.
6. The semiconductor structure according to claim 1, wherein: The material of the first gate layer includes aluminum.
7. The semiconductor structure according to claim 1, wherein: The substrate also includes a MOS tube region; The semiconductor structure further includes: a gate structure located on the MOS tube region, the gate structure including: a second gate dielectric layer, a second work function layer located on the surface of the second gate dielectric layer, and a second gate layer located on the surface of the second work function layer.
8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a diode region, the diode region comprising a first region and a second region located around the first region; forming a first gate dielectric layer on the surface of the second region, wherein the first gate dielectric layer exposes the surface of the first region; forming a first work function layer on the surface of the first region and the surface of the first gate dielectric layer; A first gate layer is formed on the surface of the first work function layer.
9. The method for forming a semiconductor structure according to claim 8, wherein: The substrate has a well region therein, and the first region and the second region are located in the well region.
10. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: An interlayer dielectric layer is formed on the surface of the substrate. The interlayer dielectric layer has an opening therein. The opening exposes the diode region. The first gate dielectric layer, the first work function layer and the first gate layer are located in the opening.
11. The method for forming a semiconductor structure according to claim 10, wherein: Also includes: A first sidewall spacer is formed on the sidewall surface of the opening, and the first sidewall spacer is located on the sidewall surfaces of the first gate dielectric layer, the first work function layer and the first gate layer.
12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the first gate dielectric layer includes: forming an initial first gate dielectric layer on the surfaces of the first region and the second region of the diode region; forming a first mask layer on the top surface of the interlayer dielectric layer, the top surface of the first sidewall, the sidewall surface of the first sidewall, and a portion of the surface of the initial first gate dielectric layer, wherein the first mask layer exposes a portion of the surface of the initial first gate dielectric layer; using the first mask layer as a mask, etching the initial first gate dielectric layer and the substrate to form a first gate dielectric layer located on the surface of the second region, wherein the first gate dielectric layer exposes the surface of the first region.
13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the initial first gate dielectric layer comprises: forming the initial first gate dielectric layer and a dummy gate located on the surface of the initial first gate dielectric layer on the surface of the diode region; forming an interlayer dielectric layer on the sidewall surfaces of both sides of the dummy gate, wherein the top surface of the interlayer dielectric layer is flush with the top surface of the dummy gate; removing the dummy gate, and forming an opening in the interlayer dielectric layer, wherein the opening exposes the diode region; The method for removing the dummy gate includes: dry etching.
14. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: Performing ion implantation on the well region; The process parameters of the ion implantation include: the implanted ions are N-type conductive ions.
15. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the first work function layer and the first gate layer includes: forming an initial first work function layer and an initial first gate layer located on the surface of the initial first work function layer on the top surface of the interlayer dielectric layer, the surface of the first region, and the surface of the first gate dielectric layer; and planarizing the initial first work function layer and the initial first gate layer until the top surface of the interlayer dielectric layer is exposed to form the first work function layer and the first gate layer.
16. The method for forming a semiconductor structure according to claim 8, wherein: The substrate further comprises a MOS region; the MOS region comprises a second gate dielectric layer, a second work function layer located on a surface of the second gate dielectric layer, and a second gate layer located on a surface of the second work function layer.
17. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: When forming the first gate dielectric layer, the second gate dielectric layer is formed; when forming the first work function layer, the second work function layer is formed; When the first gate layer is formed, the second gate layer is formed.
18. The method for forming a semiconductor structure according to claim 8, wherein: The width ratio of the first area to the second area is in the range of 1:1 to 4:1.