Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a semiconductor structure which comprises a semiconductor layer, a first dummy gate structure and a second dummy gate structure, and the semiconductor layer comprises a first well region and a second well region which are located on the upper surface layer of the semiconductor layer, first source and drain structures located on the two opposite sides of the first dummy gate structure are formed on the upper surface layer of the first well region, second source and drain structures located on the two opposite sides of the second dummy gate structure are formed on the upper surface layer of the second well region, and the first dummy gate structure and the second dummy gate structure are located on the upper surfaces of the first well region and the second well region respectively; forming a pressure stress layer covering the upper surface of the semiconductor structure; removing the first dummy gate structure and forming a first metal gate structure, and removing the second dummy gate structure and forming a second metal gate structure; and forming each electrode of the device. The compressive stress layer is formed on the upper surface of the semiconductor structure, and the first source and drain structure parts protruding out of the upper surface of the first well region are extruded by the compressive stress layer, so that the channel stress of the device is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor device and a preparation method thereof. Background Art

[0002] With the development of integrated circuit manufacturing technology, the size of semiconductor devices is getting smaller and smaller, and the requirements for the manufacturing process of devices are getting higher and higher. In order to improve the performance of small-size devices, contact etch barrier layer strain technology is widely used. At present, in high-K metal gate (HKMG) devices with a process of 28nm and below, a tensile stress contact etch barrier layer strain (CESL) layer covering the dummy gate and the upper surface of the substrate is usually used to enhance the channel stress of the N-type metal oxide semiconductor field effect transistor (NMOS), and a SiGe process is used to enhance the channel stress of the P-type metal oxide semiconductor field effect transistor (PMOS). However, after the dummy gate is replaced by a metal gate, the tensile stress CESL layer is destroyed, resulting in the tensile stress CESL layer. The effect of the performance of the NMOS is not obvious, and the performance of the PMOS is lower than that of the normal device due to the small volume of SiGe in the PMOS and insufficient stress. At the same time, due to the high height of the SiGe protrusion, the tensile stress CESL layer has a greater effect, resulting in a further reduction in the stress generated by the SiGe, which further reduces the performance of the PMOS.

[0003] Therefore, there is an urgent need to find a method for preparing a semiconductor device that can improve the performance of metal gate devices. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem of low performance of metal gate devices with a process of 28 nm or less in the prior art.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0006] A semiconductor structure is provided, comprising a semiconductor layer and a first dummy gate structure and a second dummy gate structure arranged at intervals, wherein the semiconductor layer comprises at least one first conductive type first well region and at least one second conductive type second well region located on an upper surface layer of the semiconductor layer, a first source structure and a first drain structure located on opposite sides of the first dummy gate structure are formed on an upper surface layer of the first well region, a second source structure and a second drain structure located on opposite sides of the second dummy gate structure are formed on an upper surface layer of the second well region, and the first dummy gate structure and the second dummy gate structure are located on upper surfaces of the first well region and the second well region, respectively;

[0007] forming a compressive stress layer covering the upper surface of the semiconductor structure;

[0008] removing the first dummy gate structure and forming a first metal gate structure, and removing the second dummy gate structure and forming a second metal gate structure;

[0009] A first source electrically connected to the first source structure, a first drain electrically connected to the first drain structure, a second source electrically connected to the second source structure, a second drain electrically connected to the second drain structure, a first gate electrically connected to the first metal gate structure, and a second gate electrically connected to the second metal gate structure are formed.

[0010] Optionally, the first source structure is embedded in the upper surface layer of the semiconductor layer and the upper surface of the first source structure protrudes from the upper surface of the first well region, and the first drain structure is embedded in the upper surface layer of the first well region and the upper surface of the first drain structure protrudes from the upper surface of the first well region.

[0011] Optionally, a material of the first source structure includes SiGe; a material of the first drain structure includes SiGe.

[0012] Optionally, the thickness of the compressive stress layer is in the range of

[0013] Optionally, the material of the compressive stress layer includes silicon nitride.

[0014] Optionally, the first dummy gate structure includes at least a first dielectric layer located on the upper surface of the first well region and a first dummy gate layer located on the upper surface of the first dielectric layer; the second dummy gate structure includes at least a second dielectric layer located on the upper surface of the second well region and a second dummy gate layer located on the upper surface of the second dielectric layer; the first metal gate structure includes at least a third dielectric layer and a first metal layer, the third dielectric layer covers the upper surface of the first well region between the first source structure and the first drain structure, and the first metal layer is located on the upper surface of the third dielectric layer; the second metal gate structure includes at least a fourth dielectric layer and a second metal layer, the fourth dielectric layer covers the upper surface of the second well region between the second source structure and the second drain structure, and the second metal layer is located on the upper surface of the fourth dielectric layer.

[0015] Optionally, the first metal layer and the second metal layer are made of different materials.

[0016] Optionally, after forming the compressive stress layer and before removing the first dummy gate structure and the second dummy gate structure, the method further includes forming an interlayer dielectric layer covering an upper surface of the compressive stress layer.

[0017] Optionally, after forming the interlayer dielectric layer and before forming the first metal gate structure and the second metal gate structure, the method further includes removing the compressive stress layer and the interlayer dielectric layer directly above the first dummy gate structure and the second dummy gate structure.

[0018] The present invention also provides a semiconductor device, which is manufactured by using the above-mentioned method for manufacturing the semiconductor device.

[0019] As described above, the semiconductor device and the preparation method thereof of the present invention form a compressive stress layer on the upper surface of the semiconductor structure by improving the manufacturing process of the device. Since the height of the first source structure and the first drain structure protruding from the upper surface of the first well region is relatively high, the compressive stress layer covering the side walls of the first source structure and the first drain structure protruding from the first well region will squeeze the first source structure and the first drain structure. Then, through the combination of the first source structure, the first drain structure and the compressive stress layer, the channel stress of the device formed in the first well region is enhanced, and the performance of the device formed in the first well region is improved while having no effect on the performance of the device formed in the second well region, thereby improving the overall performance of the device and having a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The process flow chart of the method for manufacturing a semiconductor device of the present invention is shown.

[0021] Figure 2 The cross-sectional structure schematic diagram of the semiconductor structure of the semiconductor device manufacturing method of the present invention is shown.

[0022] Figure 3 It is a schematic diagram showing the cross-sectional structure after forming a compressive stress layer in the method for preparing a semiconductor device of the present invention.

[0023] Figure 4 It is a schematic diagram showing the cross-sectional structure after forming an interlayer dielectric layer in the method for preparing a semiconductor device of the present invention.

[0024] Figure 5 It is a schematic cross-sectional structure diagram of the method for manufacturing a semiconductor device of the present invention after removing the first dummy gate structure.

[0025] Figure 6 It is a schematic cross-sectional structure diagram of the method for manufacturing a semiconductor device of the present invention after forming a second metal gate structure.

[0026] Figure 7 It is a schematic diagram showing the cross-sectional structure after forming an insulating layer in the method for preparing a semiconductor device of the present invention.

[0027] Figure 8 It is a schematic diagram showing the cross-sectional structure after forming each electrode in the method for preparing the semiconductor device of the present invention.

[0028] Description of Figure Numbers

[0029] 1 Semiconductor structure

[0030] 11 Substrate

[0031] 12 First well region

[0032] 121 First Source Structure

[0033] 1211 The First Source Area

[0034] 122 First Drain Structure

[0035] 1221 First Drain

[0036] 123 First dummy gate structure

[0037] 124 first dielectric layer

[0038] 125 First dummy gate layer

[0039] 126 First side wall

[0040] 127 First Metal Gate Structure

[0041] 128 third dielectric layer

[0042] 129 First Metal Layer

[0043] 13 Second well region

[0044] 131 Second source structure

[0045] 132 Second Leakage Structure

[0046] 133 Second dummy gate structure

[0047] 134 second dielectric layer

[0048] 135 Second false gate layer

[0049] 136 Second side wall

[0050] 137 Second Metal Gate Structure

[0051] 138 fourth dielectric layer

[0052] 139 Second Metal Layer

[0053] 14 Isolation Structure

[0054] 2 Compressive stress layer

[0055] 3 Interlayer dielectric layer

[0056] 4 Insulation layer

[0057] 5 First source

[0058] 51 Second Source

[0059] 6 First drain

[0060] 61 Second drain

[0061] 7 First gate

[0062] 71 Second gate DETAILED DESCRIPTION

[0063] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] See also Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0065] Embodiment 1

[0066] This embodiment provides a method for preparing a semiconductor device, such as Figure 1 FIG. 1 is a process flow chart of the method for preparing the semiconductor device, comprising the following steps:

[0067] S1: providing a semiconductor structure including a semiconductor layer and a first dummy gate structure and a second dummy gate structure arranged at intervals, wherein the semiconductor layer includes at least one first conductive type first well and at least one second conductive type second well region located on an upper surface layer of the semiconductor layer, a second conductive type first source structure and a second conductive type first drain structure located on opposite sides of the first dummy gate structure are formed on an upper surface layer of the first well region, a first conductive type second source structure and a first conductive type second drain structure located on opposite sides of the second dummy gate structure are formed on an upper surface layer of the second well region, and the first dummy gate structure and the second dummy gate structure are located on upper surfaces of the first well region and the second well region, respectively;

[0068] S2: forming a compressive stress layer covering the upper surface of the semiconductor structure;

[0069] S3: removing the first dummy gate structure and forming a first metal gate structure, removing the second dummy gate structure and forming a second metal gate structure;

[0070] S4: Form a first source electrically connected to the first source structure, a first drain electrically connected to the first drain structure, a second source electrically connected to the second source structure, a second drain electrically connected to the second drain structure, a first gate electrically connected to the first metal gate structure, and a second gate electrically connected to the second metal gate structure.

[0071] See also Figures 2 to 3 , perform step S1 and step S2: provide a semiconductor structure 1 including a semiconductor layer and a first dummy gate structure 123 and a second dummy gate structure 133 arranged at intervals, the semiconductor layer including at least one first conductive type first well region 12 and at least one second conductive type second well region 13 located on the upper surface of the semiconductor layer, the upper surface of the first well region 12 is formed with a second conductive type first source structure 121 and a second conductive type first drain structure 122 located on opposite sides of the first dummy gate structure 123, the upper surface of the second well region 13 is formed with a first conductive type second source structure 131 and a first conductive type second drain structure 132 located on opposite sides of the second dummy gate structure 133, the first dummy gate structure 123 and the second dummy gate structure 133 are respectively located on the upper surfaces of the first well region 12 and the second well region 13; form a compressive stress layer 2 covering the upper surface of the semiconductor structure 1.

[0072] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type, that is, the device made in the first well region 12 is a P type device, and the device made in the second well region 13 is an N type device.

[0073] Specifically, Figure 2 As shown, it is a schematic diagram of the cross-sectional structure of the semiconductor structure 1. The semiconductor layer also includes a substrate 11. The first well region 12 and the second well region 13 are located on the upper surface layer of the substrate 11. The conductivity type of the substrate 11 can be the first conductivity type, the second conductivity type, or an intrinsic semiconductor.

[0074] Specifically, while ensuring device performance, the size, thickness, shape and doping concentration of the substrate 11 can be selected according to actual conditions.

[0075] Specifically, the first well region 12 and the second well region 13 can be spaced apart, or the second well region 13 can be located on the upper surface of the first well region 12, or the first well region 12 can be located on the upper surface of the second well region 13. When the first well region 12 and the second well region 13 are spaced apart, an isolation structure 14 is usually provided between the first well region 12 and the second well region 13. When the second well region 13 is located on the upper surface of the first well region 12, the first source structure 121, the first drain structure 122 and the first dummy gate structure 123 are spaced apart from the second well region 13. When the first well region 12 is located on the upper surface of the second well region 13, the second source structure 131, the second drain structure 132 and the second dummy gate structure 133 are spaced apart from the first well region 12.

[0076] It should be noted that the isolation structure 14 that usually isolates the first well region 12 and the second well region 13 is a commonly used shallow trench isolation structure. It can also be other suitable structures while ensuring device performance, and no excessive restrictions are imposed here.

[0077] Specifically, the first well region 12 and the second well region 13 are usually normal doping layers. Under the condition of ensuring device performance, the thickness, size, shape and doping concentration of the first well region 12 can be selected according to actual conditions; the thickness, size, shape and doping concentration of the second well region 13 can be selected according to actual conditions. Normal doping here is relative to light doping and heavy doping.

[0078] As an example, the first source structure 121 is embedded in the upper surface layer of the semiconductor layer and the upper surface of the first source structure 121 protrudes from the upper surface of the first well region 12, and the first drain structure 122 is embedded in the upper surface layer of the first well region 12 and the upper surface of the first drain structure 122 protrudes from the upper surface of the first well region 12.

[0079] Specifically, the first source structure 121 at least includes a second conductive type first source region 1211 whose bottom surface is lower than a preset distance from the upper surface of the first well region 12 , and the first drain structure 122 at least includes a second conductive type first drain region 1221 whose bottom surface is lower than a preset distance from the upper surface of the first well region 12 .

[0080] It should be noted that the first source region 1211 is usually located on the upper surface layer of the first source structure 121, and forms an ohmic contact with the first source electrode 5 formed subsequently, so the first source region 1211 needs to be heavily doped; the first drain region 1221 is usually located on the upper surface layer of the first drain structure 122, and forms an ohmic contact with the first drain electrode 6 formed subsequently, so the first drain region 1221 needs to be heavily doped.

[0081] Specifically, under the condition of ensuring device performance, the doping concentration and thickness of the first source region 1211 can be selected according to actual conditions; the doping concentration and thickness of the first drain region 1221 can be selected according to actual conditions.

[0082] As an example, the material of the first source structure 121 includes SiGe or other suitable semiconductor materials; the material of the first drain structure 122 includes SiGe or other suitable semiconductor materials. Preferably, the material of the first source structure 121 and the first drain structure 122 are both SiGe, that is, the device is a strained silicon device.

[0083] It should be noted that, usually in the process of manufacturing the first source structure 121 and the first drain structure 122, it is necessary to form a first groove and a second groove of a preset shape, preset size and preset depth on the upper surface of the first well region 12, and then form a first source structure 121 filling the first groove and a first drain structure 122 filling the second groove, and in the process of forming the first source structure 121 and the first drain structure 122, it is necessary to first form a single crystal SiGe layer filling the first groove and the second groove, and perform ion implantation on the upper surface of the single crystal SiGe layer to obtain a first source region 1211 located on the upper surface of the single crystal SiGe layer in the first groove and a first drain region 1221 located on the upper surface of the single crystal SiGe layer in the second groove.

[0084] Specifically, the method for forming the first groove includes dry etching, wet etching or other suitable methods; the method for forming the second groove includes dry etching, wet etching or other suitable methods. Preferably, a plasma etching process (dry etching) is combined with a wet etching process to simultaneously form sigma grooves with a special cross-sectional shape on two opposite sides of the first dummy gate structure 123, namely, the first groove and the second groove.

[0085] Specifically, while ensuring the performance of the device, the opening size, opening shape and depth of the first groove and the second groove can be selected according to actual conditions.

[0086] As an example, the first dummy gate structure 123 at least includes a first dielectric layer 124 located on the upper surface of the first well region 12 and a first dummy gate layer 125 located on the upper surface of the first dielectric layer 124 .

[0087] Specifically, the material of the first dielectric layer 124 includes silicon oxide, silicon nitride or other suitable dielectric materials; the material of the first dummy gate layer 125 includes polysilicon or other suitable materials.

[0088] It should be noted that a first side wall 126 for improving the reliability of the device is usually provided around the side wall of the first dummy gate structure 123. The first side wall 126 covers the side wall of the stacked structure formed by the first dummy gate layer 125 and the first dielectric layer 124. The material of the first side wall 126 includes silicon oxide, silicon nitride, silicon nitride oxide or other suitable dielectric materials.

[0089] Specifically, the top of the first spacer 126 is flush with the top surface of the first dummy gate layer 125. Under the condition of ensuring the performance of the device to be manufactured subsequently, the thickness of the first dielectric layer 124 can be selected according to the actual situation; the thickness, size and shape of the first dummy gate layer 125 can be selected according to the actual situation; the thickness of the first spacer 126 can be selected according to the actual situation. The thickness of the first dummy gate layer 125 refers to the distance from its upper surface to the lower surface, and the thickness of the first spacer 126 refers to the distance between the side of the first spacer 126 adjacent to the first dummy gate layer 125 and the side away from the first dummy gate layer 125.

[0090] It should be noted that, in an embedded SiGe device with a process of generally not more than 28 nm, the material of the second source structure 131 and the second drain structure 132 of the N-type device may be SiC, or may be the same as the material of the second well region 13, that is, ions are injected into the second well region 13 to form a second source region and a second drain region of opposite conductivity type to the second well region 13. In this embodiment, the upper surface of the second source structure 131 and the second drain structure 132 is flush with the upper surface of the second well region 13.

[0091] Specifically, the second source structure 131 and the second drain structure 132 usually need to form an ohmic contact with the second source and the second drain formed subsequently, so the second source structure 131 and the second drain structure 132 are both heavily doped regions. While ensuring the performance of the device, the thickness, shape, size and doping concentration of the second source structure 131 can be selected according to actual conditions; the thickness, shape, size and doping concentration of the second drain structure 132 can be selected according to actual conditions.

[0092] As an example, the second dummy gate structure 133 at least includes a second dielectric layer 134 located on the upper surface of the second well region 13 and a second dummy gate layer 135 located on the upper surface of the second dielectric layer 134 .

[0093] Specifically, the material of the second dielectric layer 134 includes silicon oxide, silicon nitride or other suitable dielectric materials; the material of the second dummy gate layer 135 includes polysilicon or other suitable materials.

[0094] It should be noted that a second side wall 136 is usually provided around the side wall of the second dummy gate structure 133 for improving the reliability of the device. The second side wall 136 covers the side wall of the stacked structure formed by the second dummy gate layer 135 and the second dielectric layer 134. The material of the second side wall 136 includes silicon oxide, silicon nitride, silicon nitride oxide or other suitable dielectric materials.

[0095] Specifically, the top of the second spacer 136 is flush with the top surface of the second dummy gate layer 135. Under the condition of ensuring the performance of the device to be manufactured subsequently, the thickness of the second dielectric layer 134 can be selected according to the actual situation; the thickness, size and shape of the second dummy gate layer 135 can be selected according to the actual situation; the thickness of the second spacer 136 can be selected according to the actual situation. The thickness of the second dummy gate layer 135 refers to the distance between its upper surface and lower surface, and the thickness of the second spacer 136 refers to the distance between the side adjacent to the first spacer 126 and the second dummy gate layer 135 and the side away from the second dummy gate layer 135.

[0096] Specifically, Figure 3 As shown, it is a schematic diagram of the cross-sectional structure after the compressive stress layer 2 is formed. The compressive stress layer 2 covers the exposed upper surfaces of the first well region 12 and the second well region 13 and the exposed surfaces of the first dummy gate structure 123 and the second dummy gate structure 133, and also covers the exposed surfaces of the first source structure 121, the first drain structure 122, the second source structure 131, and the second drain structure 132. The method for forming the compressive stress layer 2 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0097] As an example, the thickness range of the compressive stress layer 2 is For example, the thickness of the compressive stress layer 2 may be Preferably, the thickness of the compressive stress layer 2 is

[0098] Specifically, by making the thickness of the compressive stress layer 2 In this way, the performance of the device formed by the first well region 12 can be improved while avoiding affecting the overall performance of the device.

[0099] As an example, the material of the compressive stress layer 2 includes silicon nitride or other suitable stress materials.

[0100] Specifically, in the process of forming the compressive stress layer 2, the process parameters and the formation environment of the compressive stress layer 2 are controlled so that the stress type generated by the compressive stress layer 2 is compressive stress. For example, when the compressive stress layer 2 is a silicon nitride layer, a silicon nitride layer with compressive stress can be achieved by lowering the proportion of nitrogen source in the process of forming the silicon nitride layer. The silicon nitride layer with compressive stress can also be formed by a low-temperature deposition environment or a low radio frequency.

[0101] See also Figures 4 to 8, perform step S3 and step S4: remove the first dummy gate structure 123 and form a first metal gate structure 127, remove the second dummy gate structure 133 and form a second metal gate structure 137; form a first source 5 electrically connected to the first source structure 121, a first drain 6 electrically connected to the first drain structure 122, a second source 51 electrically connected to the second source structure 131, a second drain 61 electrically connected to the second drain structure 132, a first gate 7 electrically connected to the first metal gate structure 127, and a second gate 71 electrically connected to the second metal gate structure 137.

[0102] As an example, Figure 4 , which is a schematic diagram of the cross-sectional structure after the interlayer dielectric layer 3 is formed. After the compressive stress layer 2 is formed and before the first dummy gate structure 123 and the second dummy gate structure 133 are removed, the step of forming the interlayer dielectric layer 3 covering the upper surface of the compressive stress layer 2 is also included.

[0103] Specifically, the method of forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0104] Specifically, the upper surface of the interlayer dielectric layer 3 is flush with and not lower than the upper surface of the compressive stress layer 2 directly above the first dummy gate structure 123 and the second dummy gate structure 133 . The thickness of the interlayer dielectric layer 3 can be selected according to actual conditions while ensuring device performance.

[0105] As an example, after forming the interlayer dielectric layer 3 and before forming the first metal gate structure 127 , the process further includes removing the compressive stress layer 2 and the interlayer dielectric layer 3 directly above the first dummy gate layer 125 and the second dummy gate layer 135 .

[0106] Specifically, after removing the compressive stress layer 2 and the interlayer dielectric layer 3 directly above the first dummy gate structure 123 and the second dummy gate structure 133, the upper surface of the first dummy gate layer 125 and the second dummy gate layer 135, the upper surface of the remaining interlayer dielectric layer 3 and the exposed surface of the remaining compressive stress layer 2 are flush, and the method for removing the compressive stress layer 2 and the interlayer dielectric layer 3 directly above the first dummy gate structure 123 and the second dummy gate structure 133 includes dry etching, wet etching, chemical mechanical polishing or other suitable methods. Preferably, the interlayer dielectric layer 3 and the compressive stress layer 2 directly above the first dummy gate structure 123 and the second dummy gate structure 133 are removed by a chemical mechanical polishing process.

[0107] Specifically, Figure 5 , which is a schematic diagram of a cross-sectional structure after removing the first dummy gate structure 123, the method of removing the first dummy gate layer 125 in the first dummy gate structure 123 includes dry etching, wet etching or other suitable methods. Preferably, the first dummy gate layer 125 is removed by dry etching.

[0108] Specifically, after removing the first dielectric layer 124 in the first dummy gate structure 123, a first contact hole is formed whose bottom surface exposes the upper surface of the first well region 12. When the first sidewall 126 is provided on the periphery of the sidewall of the first dummy gate structure 123, the inner wall of the first contact hole is the first sidewall 126. When the first sidewall 126 is not provided on the periphery of the sidewall of the first dummy gate structure 123, the inner wall of the first contact hole is the interlayer dielectric layer 3. The method of removing the first dielectric layer 124 in the first dummy gate structure 123 includes dry etching, wet etching or other suitable methods. Preferably, the first dielectric layer 124 is removed by a dry etching process.

[0109] As an example, the first metal gate structure 127 includes at least a third dielectric layer 128 and a first metal layer 129 , the third dielectric layer 128 covers the upper surface of the first well region 12 between the first source structure 121 and the first drain structure 122 , and the first metal layer 129 is located on the upper surface of the third dielectric layer 128 .

[0110] It should be noted that after removing the first dielectric layer 124 and before forming the third dielectric layer 128 , a step of forming a first buffer layer is further included, and the first buffer layer at least covers the upper surface of the first well region 12 exposed by the bottom surface of the first contact hole.

[0111] Specifically, the first buffer layer is used to improve the interface state between the third dielectric layer 128 and the upper surface of the first well region 12 exposed by the bottom surface of the first contact hole. The material of the first buffer layer includes silicon oxynitride or other suitable dielectric materials.

[0112] Specifically, the first buffer layer also covers the inner wall of the first contact hole. Under the condition of ensuring device performance, the thickness of the first buffer layer can be selected according to actual conditions; the method for forming the first buffer layer can be selected according to actual conditions.

[0113] Specifically, the method of forming the third dielectric layer 128 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. Preferably, the third dielectric layer 128 is formed by an atomic layer deposition process.

[0114] Specifically, the method of forming the first metal layer 129 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0115] Specifically, the method of removing the second dummy gate layer 135 in the second dummy gate structure 133 includes dry etching, wet etching or other suitable methods. Preferably, the second dummy gate layer 135 is removed by dry etching.

[0116] Specifically, after removing the second dielectric layer 134 in the second dummy gate structure 133, a second contact hole is formed whose bottom surface exposes the upper surface of the second well region 13. When the second sidewall 136 is provided on the periphery of the sidewall of the second dummy gate structure 133, the inner wall of the second contact hole is the second sidewall 136. When the second sidewall 136 is not provided on the periphery of the sidewall of the second dummy gate structure 133, the inner wall of the second contact hole is the interlayer dielectric layer 3. The method for removing the second dielectric layer 134 in the second dummy gate structure 133 includes dry etching, wet etching or other suitable methods. Preferably, the second dielectric layer 134 is removed by dry etching.

[0117] As an example, Figure 6 As shown, it is a schematic diagram of the cross-sectional structure after the second metal gate structure 137 is formed. The second metal gate structure 137 includes at least a fourth dielectric layer 138 and a second metal layer 139. The fourth dielectric layer 138 covers the upper surface of the second well region 13 between the second source structure 131 and the second drain structure 132, and the second metal layer 139 is located on the upper surface of the fourth dielectric layer 138.

[0118] It should be noted that after removing the second dielectric layer 134 and before forming the fourth dielectric layer 138 , a step of forming a second buffer layer is further included, and the second buffer layer at least covers the upper surface of the second well region 13 exposed by the bottom surface of the second contact hole.

[0119] Specifically, the second buffer layer is used to improve the interface state between the fourth dielectric layer 138 and the upper surface of the second well region 13 exposed by the bottom surface of the second contact hole. The material of the second buffer layer includes silicon oxynitride or other suitable dielectric materials.

[0120] Specifically, the second buffer layer also covers the inner wall of the second contact hole. Under the condition of ensuring the device performance, the thickness of the second buffer layer can be selected according to the actual situation; the method for forming the second buffer layer can be selected according to the actual situation.

[0121] Specifically, the method of forming the third dielectric layer 128 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition or other suitable methods. Preferably, the third dielectric layer 128 is formed by an atomic layer deposition process.

[0122] Specifically, the method of forming the second metal layer 139 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0123] As an example, the first metal layer 129 and the second metal layer 139 are made of different materials, so that the first metal layer 129 has a work function matching the first well region 12 , and the second metal layer 139 has a work function matching the second well region 13 .

[0124] It should be noted that since the materials of the first metal layer 129 and the second metal layer 139 are different, the first metal gate structure 127 and the second metal gate structure 137 usually need to be formed in steps, and the formation order of the first metal gate structure 127 and the second metal gate structure 137 can be selected according to actual conditions.

[0125] Specifically, Figure 7 As shown, it is a schematic diagram of the cross-sectional structure after the insulating layer 4 is formed. After the first metal gate structure 127 and the second metal gate structure 137 are formed, and before the electrodes of the device are formed, it also includes the step of forming an insulating layer 4 covering the interlayer dielectric layer 3, the compressive stress layer 2, the first metal gate structure 127 and the second metal gate structure 137 to expose the upper surface.

[0126] Specifically, the method of forming the insulating layer 4 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0127] Specifically, the material of the insulating layer 4 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. The thickness of the insulating layer 4 can be selected according to actual conditions while ensuring the performance of the device.

[0128] Specifically, Figure 8 As shown, it is a schematic diagram of the cross-sectional structure after forming each electrode, and the method of forming each electrode (first source 5, first drain 6, first gate 7, second source 51, second drain 61 and second gate 71) includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0129] Specifically, before forming the interlayer dielectric layer 3, a compressive stress film layer of a preset thickness is directly formed on the upper surface of the semiconductor structure 1. In the metal gate device with a process of less than 28 nm, the first source structure 121 and the first drain structure 122 protruding from the first well region 12 have a larger size in the extension direction of the first metal gate structure 127, and the first source structure 121 and the first drain structure 122 are relatively high in height protruding from the upper surface of the first well region 12. After forming the first metal gate structure 127, the first source 5 and the first drain 6, the compressive stress layer 2 covering the side walls of the first source structure 121 and the first drain structure 122 protruding from the first well region 12 is used to compress the first source structure 121 and the first drain structure 122 respectively, so as to generate a large squeezing force on the first source structure 121 and the first drain structure 122, thereby increasing the channel stress in the arrangement direction of the first source structure 121 and the first drain structure 122, thereby improving the performance of the device in the first well region 12.

[0130] Specifically, since the second source structure 131 and the second drain structure 132 do not protrude from the upper surface of the second well region 13 or the height of the protrusion from the upper surface of the second well region 13 is relatively small, and after the second metal gate structure 137, the second source 51 and the second drain 61 are formed, the compressive stress layer 2 in this area is destroyed, and the stress exerted by the compressive stress layer 2 on the second source structure 131 and the second drain structure 132 is relatively small, the compressive stress layer 2 above the second well region 13 has no effect on the performance of the device formed in the second well region 13, thereby ensuring the performance of the device formed in the second well region 13.

[0131] The manufacturing method of the semiconductor device of the present embodiment improves the manufacturing process of the device to form a compressive stress layer 2 covering the upper surface of the semiconductor structure 1. After forming the first source 5, the first drain 6, the first metal gate structure 127, the second source 51, the second drain 61 and the second metal gate structure 137, based on the characteristics that the first source structure 121 and the first drain structure 122 protrude from the first well region 12 at a higher height, the compressive stress layer 2 covering the sidewalls of the first source structure 121 and the first drain structure 122 protruding from the first well region 12 is used to compress the first source structure 121 and the first drain structure 122 protruding from the first well region 12. The first source structure 121 and the first drain structure 122, and then the combination of the first source structure 121, the first drain structure 122 and the compressive stress layer 2 increase the channel stress of the device, thereby avoiding the problem that the channel stress of the device in the first well region 12 is insufficient and affects the performance of the device due to the formation of the first source 5, the first drain 6 and the first metal gate structure 127 and the small size of the first source structure 121 and the first drain structure 122. The formation of the compressive stress layer 2 has no effect on the performance of the device in the second well region 13, thereby improving the overall performance of the device.

[0132] Embodiment 2

[0133] This embodiment also provides a semiconductor device, such as Figure 8 , which is a schematic diagram of the cross-sectional structure of the semiconductor device, and the semiconductor device is manufactured by adopting the semiconductor device manufacturing method described above.

[0134] Specifically, the semiconductor device includes a semiconductor structure 1, a compressive stress layer 2, a first source 5, a first drain 6, a second source 51, a second drain 61, a first gate 7 and a second gate 71, wherein the semiconductor structure 1 includes a semiconductor layer and a first metal gate structure 127 and a second metal gate structure 137 arranged at intervals, the semiconductor layer includes at least one first conductive type first well and at least one second conductive type second well region 13 located on the upper surface of the semiconductor layer, the upper surface of the first well region 12 is formed with a second conductive type first source structure 121 and a second conductive type first drain structure 122 located on opposite sides of the first metal gate structure 127, and the upper surface of the second well region 13 is formed with a first conductive type second source structure 13 located on opposite sides of the second metal gate structure 137 1 and a first conductive type second drain structure 132, the first metal gate structure 127 is located on the upper surface of the first well region 12, and the second metal gate structure 137 is located on the upper surface of the second well region 13; the compressive stress layer 2 covers the upper surface of the semiconductor structure 1, and the compressive stress layer 2 at the first metal gate structure 127 and the second metal gate structure 137 does not cover the upper surfaces of the first metal gate structure 127 and the second metal gate structure 137; the first source 5 is electrically connected to the first source structure 121, the first drain 6 is electrically connected to the first drain structure 122, the second source 51 is electrically connected to the second source structure 131, the second drain 61 is electrically connected to the second drain structure 132, the first gate 7 is electrically connected to the first metal gate structure 127, and the second gate 71 is electrically connected to the second metal gate structure 137.

[0135] It should be noted that the semiconductor structure 1 in this embodiment is a structure in which the first dummy gate structure 123 and the second dummy gate structure 133 in the semiconductor structure 1 in the first embodiment are replaced by the first metal gate structure 127 and the second metal gate structure 137 respectively.

[0136] Specifically, the semiconductor layer also includes a substrate 11, a first well region 12 and a second well region 13 are located on the upper surface of the substrate 11, and the conductivity type of the substrate 11 can be the first conductivity type, or the second conductivity type or an intrinsic semiconductor.

[0137] Specifically, the first well region 12 and the second well region 13 may be spaced apart, or the first well region 12 may be located on the upper surface of the second well region 13 or the second well region 13 may be located on the upper surface of the first well region 12. In this embodiment, the first well region 12 and the second well region 13 are spaced apart by a preset distance.

[0138] It should be noted that, usually when the first well region 12 and the second well region 13 are arranged at intervals, an isolation structure 14 is also provided between the first well region 12 and the second well region 13 to achieve isolation between the devices in the first well region 12 and the devices in the second well region 13. While ensuring the performance of the device, the specific structure of the isolation structure 14 can be selected according to actual conditions.

[0139] Specifically, the material of the first source structure 121 includes SiGe or other suitable semiconductor materials, and the material of the first drain structure 122 includes SiGe or other suitable semiconductor materials. Preferably, the material of the first source structure 121 and the first drain structure 122 are both SiGe, that is, the device is a strained silicon device.

[0140] It should be noted that due to the characteristics of SiGe strain devices, the first source structure 121 and the first drain 6 are usually filled in two sigma grooves on both sides of the first metal gate structure 127, and the first source structure 121 and the first drain structure 122 protrude from the first well region 12 at a higher height. The upper surface layer of the first source structure 121 is provided with a first source region 1211 whose bottom surface is lower than the upper surface of the first well region 12 by a preset distance, and the upper surface layer of the first drain structure 122 is provided with a first drain region 1221 whose bottom surface is lower than the upper surface of the first well region 12 by a preset distance.

[0141] Specifically, while ensuring device performance, the distance between the upper surface of the first source structure 121 and the upper surface of the first well region 12 can be selected according to actual conditions; the cross-sectional size, cross-sectional shape and thickness of the first source structure 121 can be selected according to actual conditions; the cross-sectional size, cross-sectional shape and thickness of the first drain structure 122 can be selected according to actual conditions; the distance between the upper surface of the first drain structure 122 and the upper surface of the first well region 12 can be selected according to actual conditions; the distance between the bottom surface of the first source region 1211 and the upper surface of the first well region 12 can be selected according to actual conditions; the distance between the bottom surface of the first drain region 1221 and the upper surface of the first well region 12 can be selected according to actual conditions. In this embodiment, the relevant parameters of the first source structure 121 and the first drain structure 122 are the same.

[0142] Specifically, the second source structure 131 and the second drain structure 132 are usually heavily doped regions of the first conductivity type. While ensuring device performance, the cross-sectional size, cross-sectional shape and thickness of the second source structure 131 can be selected according to actual conditions; the cross-sectional shape and thickness of the second drain structure 132 can be selected according to actual conditions.

[0143] Specifically, the semiconductor structure 1 is also provided with a first side wall 126 covering the side wall of the first metal gate structure 127 and a second side wall 136 covering the side wall of the second metal gate structure 137. The first side wall 126 surrounds the first metal gate structure 127, and the upper surface of the first side wall 126 is flush with the upper surface of the first metal gate structure 127. The second side wall 136 surrounds the second metal gate structure 137, and the upper surface of the second side wall 136 is flush with the upper surface of the second metal gate structure 137. The compressive stress layer 2 covers a side of the first side wall 126 away from the side wall of the first metal gate structure 127 and a side of the second side wall 136 away from the side wall of the second metal gate structure 137.

[0144] Specifically, the first metal gate structure 127 includes a third dielectric layer 128 and a first metal layer 129, the third dielectric layer 128 at least covers the upper surface of the first well region 12 between the first source structure 121 and the first drain structure 122, and the first metal layer 129 covers the upper surface of the third dielectric layer 128. The second metal gate structure 137 includes a fourth dielectric layer 138 and a second metal layer 139, the fourth dielectric layer 138 at least covers the upper surface of the second well region 13 between the second source structure 131 and the second drain structure 132, and the second metal layer 139 covers the upper surface of the fourth dielectric layer 138.

[0145] Specifically, when a first side wall 126 and a second side wall 136 are provided in the semiconductor structure 1, the third dielectric layer 128 also wraps the side wall of the first metal layer 129, the first side wall 126 covers the side of the third dielectric layer 128 away from the side wall of the first metal layer 129, the fourth dielectric layer 138 also includes the side wall of the second metal layer 139, and the second side wall 136 covers the side of the fourth dielectric layer 138 away from the side wall of the second metal layer 139.

[0146] It should be noted that, usually, a first buffer layer and a second buffer layer are respectively provided between the third dielectric layer 128 and the first well region 12 and between the fourth dielectric layer 138 and the second well region 13. The first buffer layer is used to improve the interface state between the first well region 12 and the third dielectric layer 128, and the second buffer layer is used to improve the interface state between the fourth dielectric layer 138 and the second well region 13.

[0147] Specifically, the third dielectric layer 128 has a high K value, and the material of the third dielectric layer 128 includes tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium silicate or other suitable high-K dielectric materials; the fourth dielectric layer 138 has a high K value, and the material of the fourth dielectric layer 138 includes tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium silicate or other suitable high-K dielectric materials.

[0148] Specifically, the material of the first metal layer 129 is related to the conductivity type of the first well region 12. The Fermi level of the first metal layer 129 is close to the top of the valence band of the first well region 12 (P-type metal gate layer) to ensure the threshold voltage of the first metal gate structure 127. The material of the first metal layer 129 includes hafnium, zirconium, titanium, tantalum, aluminum, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, titanium nitride, tantalum nitride or other suitable conductive materials; the material of the second metal layer 139 is The upper surface is flush with the interlayer dielectric layer 3, and the material of the second metal layer 139 is related to the conductivity type of the second well region 13. The Fermi level of the second metal layer 139 is close to the valence band top (N-type metal gate layer) of the second well region 13 to ensure the threshold voltage of the second metal gate structure 137. The material of the second metal layer 139 includes hafnium, zirconium, titanium, tantalum, aluminum, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, titanium nitride, tantalum nitride or other suitable conductive materials.

[0149] Specifically, the material of the compressive stress layer 2 includes silicon nitride or other suitable materials. Preferably, the thickness is A thin silicon nitride layer is used as a compressive stress layer 2.

[0150] Specifically, the semiconductor device is further provided with an interlayer dielectric layer 3 and an insulating layer 4 stacked in sequence, the interlayer dielectric layer 3 covers the upper surface of the compressive stress layer 2 , and the upper surface of the interlayer dielectric layer 3 is flush with the upper surfaces of the first metal layer 129 and the second metal layer 139 .

[0151] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0152] Specifically, the insulating layer 4 covers the exposed upper surfaces of the interlayer dielectric layer 3, the first metal gate structure 127 and the second metal gate structure 137, the first source electrode 5 penetrates the insulating layer 4, the interlayer dielectric layer 3 and the compressive stress layer 2 directly above the first source structure 121 to be electrically connected to the first source structure 121, the first drain electrode 6 penetrates the insulating layer 4, the interlayer dielectric layer 3 and the compressive stress layer 2 directly above the first drain structure 122 to be electrically connected to the first drain structure 122, and the first gate electrode 7 penetrates the insulating layer directly above the first metal gate structure 127. 4, so as to be electrically connected to the first metal layer 129 in the first metal gate structure 127, the second source electrode 51 penetrates the insulating layer 4, the interlayer dielectric layer 3 and the compressive stress layer 2 just above the second source structure 131, so as to be electrically connected to the second source structure 131, the second drain electrode 61 penetrates the insulating layer 4, the interlayer dielectric layer 3 and the compressive stress layer 2 just above the second drain structure 132, so as to be electrically connected to the second drain structure 132, and the second gate electrode 71 penetrates the insulating layer 4 just above the second metal gate structure 137, so as to be electrically connected to the second metal layer 139.

[0153] Specifically, the material of each electrode includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.

[0154] Specifically, the semiconductor device is manufactured by adopting the semiconductor device preparation method described in Example 1, and the compressive stress layer 2 is used to squeeze the side walls of the first source structure 121 and the first drain structure 122 that protrude from the upper surface of the first well region 12, thereby increasing the channel stress of the device manufactured based on the first well region 12, thereby improving the performance of the semiconductor device formed in the first well region 12 in the device, while not affecting the performance of the device formed in the second well region 13, thereby improving the overall performance of the device.

[0155] The semiconductor device of this embodiment is manufactured by adopting the semiconductor device manufacturing method described in the first embodiment, thereby improving the performance of the semiconductor device formed in the first well region 12 of the device, while not affecting the performance of the device formed in the second well region 13 .

[0156] In summary, the semiconductor device and its preparation method of the present invention form a compressive stress layer on the upper surface of the semiconductor structure by improving the manufacturing method of the device. Based on the fact that the first source structure and the first drain structure protrude from the upper surface of the first well region at a relatively high height, the sidewalls covering the portion of the first source structure and the first drain structure protruding from the first well region are subjected to a relatively large extrusion force from the compressive stress layer. Then, the combination of the first source structure, the first drain structure and the compressive stress layer improves the channel stress on the device formed in the first well region, and improves the performance of the device made in the first well region while having no effect on the performance of the device formed in the second well region, thereby improving the overall performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0157] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: A semiconductor structure is provided, comprising a semiconductor layer and a first dummy gate structure and a second dummy gate structure arranged at intervals, wherein the semiconductor layer comprises at least one first conductive type first well region and at least one second conductive type second well region located on an upper surface layer of the semiconductor layer, a first source structure and a first drain structure located on opposite sides of the first dummy gate structure are formed on an upper surface layer of the first well region, a second source structure and a second drain structure located on opposite sides of the second dummy gate structure are formed on an upper surface layer of the second well region, and the first dummy gate structure and the second dummy gate structure are located on upper surfaces of the first well region and the second well region, respectively; forming a compressive stress layer covering the upper surface of the semiconductor structure; removing the first dummy gate structure and forming a first metal gate structure, and removing the second dummy gate structure and forming a second metal gate structure; A first source electrically connected to the first source structure, a first drain electrically connected to the first drain structure, a second source electrically connected to the second source structure, a second drain electrically connected to the second drain structure, a first gate electrically connected to the first metal gate structure, and a second gate electrically connected to the second metal gate structure are formed.

2. The method for preparing a semiconductor device according to claim 1, wherein: The first source structure is embedded in the upper surface layer of the semiconductor layer and the upper surface of the first source structure protrudes from the upper surface of the first well region. The first drain structure is embedded in the upper surface layer of the first well region and the upper surface of the first drain structure protrudes from the upper surface of the first well region.

3. The method for preparing a semiconductor device according to claim 2, wherein: The material of the first source structure includes SiGe; the material of the first drain structure includes SiGe.

4. The method for preparing a semiconductor device according to claim 1, wherein: The thickness range of the compressive stress layer is 5. The method for preparing a semiconductor device according to claim 1, wherein: The material of the compressive stress layer includes silicon nitride.

6. The method for preparing a semiconductor device according to claim 1, wherein: The first dummy gate structure at least includes a first dielectric layer located on the upper surface of the first well region and a first dummy gate layer located on the upper surface of the first dielectric layer; the second dummy gate structure at least includes a second dielectric layer located on the upper surface of the second well region and a second dummy gate layer located on the upper surface of the second dielectric layer; the first metal gate structure at least includes a third dielectric layer and a first metal layer, the third dielectric layer covers the upper surface of the first well region between the first source structure and the first drain structure, and the first metal layer is located on the upper surface of the third dielectric layer; The second metal gate structure at least includes a fourth dielectric layer and a second metal layer, the fourth dielectric layer covers the upper surface of the second well region between the second source structure and the second drain structure, and the second metal layer is located on the upper surface of the fourth dielectric layer.

7. The method for preparing a semiconductor device according to claim 6, wherein: The first metal layer and the second metal layer are made of different materials.

8. The method for preparing a semiconductor device according to claim 1, wherein: After forming the compressive stress layer and before removing the first dummy gate structure and the second dummy gate structure, the method further includes forming an interlayer dielectric layer covering the upper surface of the compressive stress layer.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: After forming the interlayer dielectric layer and before forming the first metal gate structure and the second metal gate structure, the method further includes removing the compressive stress layer and the interlayer dielectric layer directly above the first dummy gate structure and the second dummy gate structure.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by using the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

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