Radio frequency low-noise MOSFET transistor with buried layer structure and manufacturing method thereof

Abstract

The invention discloses a radio frequency low-noise MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a buried layer structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: injecting a buried layer in a substrate of a first active region; forming a shallow slot isolation region at the junction of the first active region and the second active region; forming a deep N well below the buried layer through injection; forming a shallow N well in the substrate around the position right above the deep N well through injection, wherein the shallow N well is overlapped with the edge of the deep N well; forming a P well in the substrate right above the deep N well through injection; manufacturing a grid electrode; injecting to form a source-drain contact region and an LDD region; and forming a side wall isolation structure and a metallization contact layer. According to the invention, double-layer substrate isolation is realized through the N-type buried layer below the P well and the deep N well, noise crosstalk of the P-type substrate caused by different bias voltages in a circuit is isolated, the value of random telegraph noise of a carrier and a trap defect in the transportation process is effectively suppressed, and the effect of suppressing low-frequency noise of a device is achieved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a radio frequency low-noise MOSFET transistor with a buried layer structure and a manufacturing method thereof. Background Art

[0002] In modern RF microwave integrated circuits, especially in high-precision analog integrated circuits for small signal processing, Germanium-Si Bi-CMOS technology or micro-nanoscale CMOS technology is commonly used to develop low-noise circuits such as low-noise amplifiers (LNA), high-precision analog-to-digital converters (ADC) and high-precision digital-to-analog converters (DAC), low-dropout linear regulators (LDO) and RF transceivers. Generally speaking, the noise source of the core component of the circuit, that is, the transistor, mainly comes from two aspects. One is the thermal noise generated by the circuit itself, where the thermal noise comes from the random fluctuation of carriers related to the current size in the circuit and is only related to the system current size and temperature, mainly including the thermal noise of the current MOSFET itself and the thermal noise of the MOSFET load resistor; the other is the "flicker" noise or 1 / f noise from the MOSFET transistor. Flicker noise is an intrinsic physical property of semiconductor devices, which is manifested as the fluctuation of semiconductor or metal conductivity and originates from the fluctuation of the number of carriers and / or mobility of the device. The interference of noise on the actual signal limits the minimum signal level of the device's actual operation and reduces the system's signal-to-noise ratio. In circuit design, in order to reduce system noise, especially to reduce "flicker" noise, designers usually use large MOSFETs to limit the flicker noise of transistors. However, using large MOSFETs also increases the channel length and channel width of the device, which undoubtedly increases the device's current, thereby increasing the system's background noise. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a radio frequency low-noise MOSFET transistor with a buried layer structure and a manufacturing method thereof.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure, comprising the following steps:

[0006] S1. providing a substrate, dividing a first active area and a second active area on the substrate, and implanting a buried layer into the substrate of the first active area;

[0007] S2, forming a shallow trench isolation region at the upper portion of the substrate corresponding to the junction of the first active region and the second active region;

[0008] S3, forming a deep N-well by implantation below the buried layer, wherein the horizontal size of the deep N-well is larger than the horizontal size of the buried layer;

[0009] S4, forming a shallow N-well by implantation in the substrate around the deep N-well, wherein the shallow N-well extends inward to contact the buried layer, thereby overlapping with the edge of the deep N-well; then forming a P-well by implantation in the substrate above the deep N-well;

[0010] S5, forming a P-type gate on the substrate surface above the shallow N-well, and forming an N-type gate on the substrate surface above the P-well; and implanting an N-type source-drain contact region, an NLDD region, a P-type source-drain contact region and a PLDD region on the substrate;

[0011] S6. Forming sidewall isolation structures around the P-type gate and the N-type gate respectively, and forming a metallized contact layer.

[0012] Furthermore, the doping type of the substrate is P-type doping, and the resistivity of the substrate is 10Ω.cm to 70Ω.cm; the doping type of the buried layer is N-type doping.

[0013] Furthermore, implanting the buried layer into the substrate comprises the following sub-steps:

[0014] S101, covering the surface of the substrate with a layer of photoresist, and photolithography out the implantation area of ​​the buried layer;

[0015] S102, injecting antimony ions or arsenic ions into the area photoetched in step S101, with an injection dose of 1e 15 cm -2 ~5e 15 cm -2 ;

[0016] S103, after the implantation is completed, a high temperature process is performed to form a buried layer, and the remaining photoresist on the substrate surface is removed.

[0017] Furthermore, the step S2 includes the following sub-steps:

[0018] S201, forming a thin oxide layer on the surface of the substrate by thermal oxidation, and then depositing a silicon nitride layer on the thin oxide layer;

[0019] S202, patterning the shallow trench region on the silicon nitride layer by photolithography, and selectively etching the thin oxide layer and the silicon nitride layer in the shallow trench region;

[0020] S203, removing the remaining photoresist on the surface of the substrate, and etching the substrate to form a shallow trench using the silicon nitride layer and the thin oxide layer reserved after etching as a hard mask;

[0021] S204, removing the silicon nitride layer and the thin oxide layer, and forming a linear oxide layer on the groove wall of the shallow trench by thermal oxidation;

[0022] S205, depositing a high-density plasma oxide layer on the substrate to backfill the shallow trench;

[0023] S206, using chemical mechanical polishing to achieve surface flattening, removing the high-density plasma oxide layer on the surface of the substrate, and the high-density plasma oxide layer remaining in the shallow trench forms a shallow trench isolation region.

[0024] Furthermore, in the step S2, before forming the shallow trench isolation region, epitaxial growth is performed on the substrate to form an epitaxial layer, the thickness of the epitaxial layer is 0.2 μm to 2 μm, and the doping type of the epitaxial layer is N-type doping.

[0025] Furthermore, the S3 step includes the following sub-steps:

[0026] S301, covering the substrate surface with a layer of photoresist, and photolithography out the injection region of the deep N well;

[0027] S302, using the remaining photoresist as a mask, using a high-energy ion implanter to perform ion implantation in the area photolithographed in step S301 to form a deep N well;

[0028] S303, removing the remaining photoresist on the substrate surface.

[0029] Furthermore, in the step S302, arsenic ions are implanted to form a deep N well, and the implantation dose is 6×10 12 cm -2 ~1.5×10 13 cm -2 .

[0030] Furthermore, the S4 step includes the following sub-steps:

[0031] S401, covering the substrate surface with a layer of photoresist, and photolithography out an injection region of a shallow N well;

[0032] S402, using the remaining photoresist as a mask, implanting into the area photolithographically formed in step S401 to form a shallow N well;

[0033] S403, covering the substrate surface with a layer of photoresist again, and photolithography out the injection area of ​​the P well;

[0034] S404, using the remaining photoresist as a mask, implanting into the area photolithographically formed in step S403 to form a P well;

[0035] S405, removing the remaining photoresist on the substrate surface.

[0036] Furthermore, in the step S402, phosphorus ion implantation is used to form a shallow N well, with an implantation energy of 400 keV and an implantation dose of 2×10 13 cm -2 In the step S404, boron ion implantation is used to form a P well, with an implantation energy of 250keV and an implantation dose of 2×10 13 cm -2 .

[0037] A radio frequency low noise MOSFET transistor with a buried layer structure, comprising a substrate, wherein a shallow trench isolation region is arranged on the upper part of the substrate, wherein the shallow trench isolation region divides the substrate into a first active region and a second active region; a buried layer and a deep N-well are formed by implantation in the substrate of the first active region; the buried layer is located directly above the deep N-well, and the horizontal dimension of the deep N-well is larger than the horizontal dimension of the buried layer; a shallow N-well is formed by implantation in the substrate around the deep N-well, wherein the shallow N-well extends inwardly to contact the buried layer, thereby overlapping with the edge of the deep N-well; a P-well is formed by implantation in the substrate directly above the deep N-well;

[0038] An N-type gate is arranged on the substrate surface above the P-well, and an N-type source-drain contact region is formed by injection around the area directly below the P-well corresponding to the N-type gate, and an NLDD region is formed by injection inside the N-type source-drain contact region; a P-type gate is arranged on the substrate surface above the shallow N-well, and a P-type source-drain contact region is formed by injection around the area directly below the shallow N-well corresponding to the P-type gate, and a PLDD region is formed by injection inside the P-type source-drain contact region; sidewall isolation structures are respectively wrapped on the sides of the P-type gate and the N-type gate, and a metal contact layer is respectively arranged on the surfaces of the N-type gate, the N-type source-drain contact region, the P-type gate and the P-type source-drain contact region.

[0039] In the present invention, a MOSFET transistor structure for suppressing low-frequency noise is formed by realizing double-layer substrate isolation through an N-type buried layer and a deep N-well below a P-well. The MOSFET transistor structure for suppressing low-frequency noise realizes complete isolation of the body structure of the NMOSFET through the buried layer and the shallow N-well around the deep N-well and the P-well, isolates the noise crosstalk caused by different bias voltages in the circuit of the P-type substrate, realizes a clean potential structure in the body of the NMOSFET, reduces the carrier concentration on the current transmission path, thereby reducing the capture and release process of carriers by silicon dioxide trap defects near the Si / SiO2 interface in the base region, and effectively suppresses the value of random telegraph noise of carriers and trap defects during the transport process, thereby achieving the effect of suppressing the low-frequency noise of the device. At the same time, the process of the MOSFET transistor structure for suppressing low-frequency noise is compatible with the existing SiGeBiCMOS manufacturing process, does not increase the process complexity and manufacturing cost, and is suitable for the circuit design of special requirements such as the development and production of low-noise amplifiers without requiring additional separate circuit-level design measures. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 The flowchart is a method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to an embodiment of the present invention.

[0042] Figure 2 Schematic diagram of implanting a buried layer into a substrate.

[0043] Figure 3 This is a schematic diagram of the structure after shallow trenches are formed by etching on the substrate.

[0044] Figure 4 Schematic diagram of the structure after a linear oxide layer is formed on the wall of the shallow trench.

[0045] Figure 5 Schematic diagram of the structure after a high-density plasma oxide layer is deposited on a substrate.

[0046] Figure 6 It is a schematic diagram of the structure after the shallow trench isolation area is formed.

[0047] Figure 7 Schematic diagram of implantation to form a deep N-well.

[0048] Figure 8 Schematic diagram of implantation to form a shallow N-well.

[0049] Fig. 9 Schematic diagram of the P-well formed by implantation.

[0050] Fig.10 Schematic diagram of the structure after the gate polycrystal is formed.

[0051] Fig.11 It is a schematic diagram of the structure after the film layer structure is formed.

[0052] Fig.12 It is a schematic structural diagram of an embodiment of a radio frequency low noise MOSFET transistor with a buried layer structure of the present invention.

[0053] Fig.13 A noise test comparison diagram of a conventional device and a device manufactured using the method of this embodiment

[0054] The accompanying drawings in the specification are numeraled as follows:

[0055] Substrate-100; thin oxide layer-101; silicon nitride layer-102; high-density plasma oxide layer-103; gate polycrystalline-104; metal contact layer-105; film layer structure-106; sidewall isolation structure-107; first active area-110; buried layer-111; deep N-well-112; P-well-113; N-type gate-114; N-type source-drain contact area-115; NLDD area-116; second active area-120; shallow N-well-123; P-type gate-124; P-type source-drain contact area-125; PLDD area-126; shallow trench-130; linear oxide layer-131; shallow trench isolation area-132; photoresist-200, 210, 220, 230. DETAILED DESCRIPTION

[0056] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0057] See also Figure 1 , Figure 1 This is a flow chart of an embodiment of a method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure of the present invention. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure of this embodiment includes the following steps:

[0058] S1. Provide a substrate 100, divide a first active area 110 and a second active area 120 on the substrate 100, and implant a buried layer 111 in the substrate 100 of the first active area 110. In this embodiment, the doping type of the substrate 100 is P-type doping, and the resistivity of the substrate 100 is 10Ω.cm to 70Ω.cm; the doping type of the buried layer 111 is N-type doping. The method of implanting the buried layer 111 in the substrate 100 may include the following sub-steps:

[0059] S101 , a layer of photoresist 200 is covered on the surface of the substrate 100 , and an implantation region of the buried layer 111 is formed by photolithography.

[0060] S102, please refer to Figure 2 , antimony ions or arsenic ions are injected into the area photolithographically formed in the previous step. The injection dose is appropriately selected according to the required breakdown voltage of the device. The injection dose is generally 1e 15 cm -2 ~5e 15 cm -2 .

[0061] S103 , after the implantation is completed, a high temperature process is performed to form a buried layer 111 , and the remaining photoresist 200 on the surface of the substrate 100 is removed.

[0062] S2. A shallow trench isolation region 132 is formed at the junction of the first active region 110 and the second active region 120 on the upper part of the substrate 100. Before forming the shallow trench isolation region 132, an epitaxial layer can be formed on the substrate 100 by epitaxial growth as required. The thickness of the epitaxial layer is appropriately selected according to the breakdown voltage of the bipolar device in the SiGe BiCMOS process, generally 0.2μm to 2μm. The doping type of the epitaxial layer is N-type doping. The epitaxial layer can be used as the collector region of the bipolar device. The epitaxial layer can be omitted when only the CMOS device is manufactured. Therefore, the epitaxial layer in this embodiment is not a necessary structure, but an optional structure.

[0063] This step may include the following sub-steps:

[0064] S201. A thin oxide layer 101 is formed on the surface of the substrate 100 (if an epitaxial layer is formed on the substrate 100 by epitaxial growth, the surface of the epitaxial layer is the surface of the substrate 100) by thermal oxidation. The thickness of the oxide layer is about 110 angstroms. Then, a silicon nitride layer 102 is deposited on the thin oxide layer 101. The thickness of the silicon nitride layer 102 is 1500 to 2500 angstroms.

[0065] S202 , patterning the shallow trench 130 region on the silicon nitride layer 102 by photolithography, and selectively etching the thin oxide layer 101 and the silicon nitride layer 102 in the shallow trench 130 region to form a hard mask layer through the thin oxide layer 101 and the silicon nitride layer 102 .

[0066] S203, please refer to Figure 3 , remove the remaining photoresist on the surface of the substrate 100, and use the silicon nitride layer 102 and the thin oxide layer 101 reserved after etching as a hard mask to etch and form a shallow trench 130 on the substrate 100.

[0067] S204, please refer to Figure 4 , remove the silicon nitride layer 102 and the thin oxide layer 101, and form a linear oxide layer 131 on the wall of the shallow trench 130 by thermal oxidation.

[0068] S205, please refer to Figure 5 , a high-density plasma oxide layer 103 is deposited on the substrate 100 , and the shallow trench 130 is backfilled.

[0069] S206, please refer to Figure 6 The surface is planarized by chemical mechanical polishing to remove the high-density plasma oxide layer 103 on the surface of the substrate 100. The high-density plasma oxide layer 103 remaining in the shallow trench 130 forms a shallow trench isolation region 132, which is used for electrical isolation and physical isolation between the first active region 110 and the second active region 120.

[0070] S3, forming a deep N well 112 by implantation below the buried layer 111, wherein the horizontal dimension of the deep N well 112 is larger than the horizontal dimension of the buried layer 111. This step may include the following sub-steps:

[0071] S301 , a layer of photoresist 210 is covered on the surface of the substrate 100 , and an implantation region of the deep N well 112 is formed by photolithography.

[0072] S302, please refer to Figure 7 , using the remaining photoresist 210 as a mask, ion implantation is performed in the area photolithographically formed in the previous step to form a deep N well 112. A high-energy ion implanter is required for the implantation of the deep N well 112 to ensure that the depth of the ion implantation meets the design requirements. In this embodiment, arsenic ion implantation is used to form the deep N well 112, and the implantation dose is 6×10 12 cm -2 ~1.5×10 13 cm -2 .

[0073] S303 , removing the remaining photoresist 210 on the surface of the substrate 100 .

[0074] S4, forming a shallow N well 123 by implantation in the substrate 100 around the deep N well 112, the shallow N well 123 extending inward to contact the buried layer 111, thereby overlapping with the edge of the deep N well 112; then forming a P well 113 by implantation in the substrate 100 directly above the deep N well 112. This step may include the following sub-steps:

[0075] S401 , a layer of photoresist 220 is covered on the surface of the substrate 100 , and exposure, development and etching are performed to photoetch out an implantation region of the shallow N well 123 .

[0076] S402, please refer to Figure 8 Using the remaining photoresist 220 as a mask, phosphorus ions are implanted in the area photolithographically formed in the previous step to form a shallow N well 123. The implantation energy is preferably 400 keV and the implantation dose is preferably 2×10 13 cm -2 .

[0077] S403 , removing the remaining photoresist 220 on the surface of the substrate 100 , covering the surface of the substrate 100 with a layer of photoresist 230 again, and performing exposure, development and etching to photoetch out the implantation region of the shallow P well 113 .

[0078] S404, please refer to Fig. 9 , using the remaining photoresist 230 as a mask, boron ion implantation is performed in the region photolithographically formed in step S403 to form a P well 113, the implantation energy is preferably 250 keV, and the implantation dose is preferably 2×10 13 cm -2 .

[0079] S405 , removing the remaining photoresist 230 on the surface of the substrate 100 .

[0080] The shallow N-well 123 and the P-well 113 are generally NMOSFET and PMOSFET of two voltages, 1.8V and 3.3V or 1.2V and 3.3V, according to the specific requirements of the SiGe BiCMOS process. Specifically, for the 1.8V and 3.3V or 1.2V and 3.3V devices, firstly, the 1.8V or 1.2V NMOSFET low-voltage P-type well photolithography and implantation are performed, and then the 1.8V or 1.2V PMOSFET low-voltage N-type well photolithography and implantation are performed; then the 3.3V NMOSFET high-voltage P-type well photolithography and implantation and the 3.3V PMOSFET high-voltage N-type well photolithography and implantation are performed. Finally, the deep N well 112 for making isolated NMOSFT is implanted, wherein the isolation deep N well 112 photolithography size must include a 1.8V or 1.2V NMOSFET low voltage P-type well or simultaneously include a 1.8V or 1.2V and 3.3V NMOSFET low voltage P-type well and a high voltage P-type well and must overlap with the N-type well in photolithography size to form a complete isolation of the P-type well. In particular, the deep N well 112 for making isolated NMOSFT must overlap with the N-type buried layer 111 structure in step S2 in photolithography pattern to form a high isolation structure in which the buried layer 111 is embedded in the deep N well 112.

[0081] S5, forming a P-type gate 124 on the surface of the substrate 100 above the shallow N-well 123, and forming an N-type gate 114 on the surface of the substrate 100 above the P-well 113; and implanting into the P-well 113 to form an N-type source-drain contact region 115, an NLDD region 116, a P-type source-drain contact region 125, and a PLDD region 126. This step may include the following sub-steps:

[0082] S501, please refer to Fig.10 First, a gate oxide layer is grown on the substrate 100 and a layer of polysilicon is deposited; then, the polysilicon is patterned by photolithography and etching, and a gate polycrystalline 104 is formed on the surface of the substrate 100 above the shallow N well 123 and the surface of the substrate 100 above the P well 113, respectively.

[0083] S502, please refer to Fig.11 , N-type impurities are implanted into the gate polycrystalline 104 above the P-well 113 to form an N-type gate 114, and at the same time, an N-type source-drain contact region 115 is formed by implantation around the area directly below the N-type gate 114 in the P-well 113, and an NLDD region 116 is formed by implantation on the inner side of the N-type source-drain contact region 115.

[0084] S503, please continue reading Fig.11, P-type impurities are implanted into the gate polycrystalline 104 above the shallow N-well 123 to form a P-type gate 124. At the same time, a P-type source-drain contact region 125 is formed by implantation around the area directly below the P-type gate 124 in the shallow N-well 123, and a PLDD region 126 is formed by implantation on the inner side of the P-type source-drain contact region 125.

[0085] The specific manufacturing processes of the above-mentioned gate polycrystalline 104, N-type gate 114, N-type source and drain contact area 115, NLDD area 116, P-type gate 124, P-type source and drain contact area 125 and PLDD area 126 are all conventional processes, and there is no obvious difference from the existing manufacturing process, so they will not be repeated here.

[0086] S6. Please refer to Fig.12 , forming a sidewall isolation structure 107 around the P-type gate 124 and the N-type gate 114, and completing the back-end metal wiring process of the HBT device (Heterojunction Bipolar Transistor) to form a metallized contact layer. This step may include the following sub-steps:

[0087] When forming the sidewall isolation structure 107, an oxide layer, silicon nitride and an oxide layer are sequentially deposited on the surface of the substrate 100 to form a film structure 106. On the sidewalls of the gate (including the N-type gate 114 and the P-type gate 124), due to the good conformality of the oxide layer, silicon nitride and oxide layer thin film deposition of the film structure 106, the thickness of the film structure 106 on both sides of the gate is much higher than that of the flat surface area. Dry anisotropic etching is used to cleanly etch the oxide layer, silicon nitride and oxide layer thin film in the film structure 106 deposited on the surface, leaving the sidewall isolation structure 107 on the sidewalls of the N-type gate 114 and the P-type gate 124. The above are all conventional processes, which are not significantly different from the existing manufacturing process and will not be described in detail here.

[0088] The back-end metal wiring process of the HBT device mainly includes: depositing an ILD dielectric layer on the surface of the substrate 100, and performing chemical mechanical polishing and flattening on the ILD dielectric layer; on the ILD dielectric layer, hole etching and tungsten plug filling are performed at the positions corresponding to the source and drain regions of the MOSFET, and at the positions of the emitter, base and collector of the device, respectively, to form contact hole tungsten plugs, and then flattening is performed; in particular, the difference between this embodiment and the conventional process is that in order to effectively ensure the high-speed performance of the HBT device, the emitter and collector contact holes of the HBT device do not use conventional square holes, but use long strip-shaped slot holes to increase the through-hole current carrying capacity; finally, a metallization process is performed on the surface according to the conventional semiconductor process to form a metal contact layer 105 on the surface of the N-type gate 114, the N-type source and drain contact area 115, the P-type gate 124 and the P-type source and drain contact area 125, so as to achieve good metal contact of the gate, source and drain. Except for changing the shape of the contact holes from square holes to slot holes that are all long strips, the rest are conventional processes with no significant difference from the existing manufacturing process, which will not be described in detail here.

[0089] Fig.13 This is a noise test comparison diagram of a conventional device and a device manufactured using the method of this embodiment. Fig.13 It can be seen that the overall noise level of the MOSFET transistor structure for suppressing low-frequency noise is 1-2 orders of magnitude lower than that of the standard device, so the noise suppression structure proposed in the present invention can achieve good results.

[0090] It should be noted that the MOSFET transistor described in the present invention can be either an NMOSFET transistor or a PMOSFET transistor, which is not limited here.

[0091] In this embodiment, an N-type buried layer structure specifically used for SiGe HBT bipolar devices is embedded into a deep N-well structure in an ultra-high-speed SiGe BiCMOS process. In a conventional RF CMOS process, the NMOSFET in the RF MOSFET device isolates the P-well 113 of the NMOSFET device through the deep N-well 112. Since the substrate 100 is P-type silicon, the deep N-well 112 has a high injection energy and a large injection depth, thereby isolating the P-well 113 of the NMOSFET from the P-type substrate 100, forming a reverse-biased PN junction to prevent leakage current from coupling from the substrate 100 into the P-well 113 of the NMOSFET. In this embodiment, not only the isolation of the deep N-well 112 is included, but also the N-type buried layer 111 that only appears in the SiGe HBT bipolar device is stacked with the deep N-well 112, effectively realizing the double-layer isolation of the NMOSFET device. Moreover, since the doping concentration of the N-type buried layer 111 is relatively high, the new isolation structure is unlikely to have an impurity inversion effect under actual working conditions, thereby ensuring the isolation of the NMOSFET by the deep N-well 112 and blocking the influence of substrate defects and crosstalk signals on the NMOSFET. In addition, the buried layer process is formed before the NMOSFET well process. The high temperature heat annealing for the buried layer 111 during the formation of the buried layer 111 effectively repairs the impurity defects in the active area of ​​the final device. At the same time, during the high temperature annealing process, the proper upward expansion of the impurities in the buried layer 111 effectively complements the impurity distribution at the bottom of the P well 113 of the NMOSFET device. Since the impurity types of the buried layer 111 and the P well 113 are opposite, a PN junction mutation junction is formed at the bottom of the well, and the high concentration side of the mutation junction is located in the lower N-type region, which is conducive to the convergence of the 3 sigma distribution at the end of the Gaussian distribution of the impurities in the P well 113 of the NMOSFET device, optimizes the comprehensive impurity distribution of the NMOSFET device area, is conducive to improving the consistency and repeatability of the electrical performance of the NMOSFET device and reducing the parameter mismatch between devices, further improves the radio frequency performance of the isolated NMOSFET, and improves the overall performance of the process. At the same time, the process of suppressing low-frequency noise does not increase the process complexity and manufacturing cost. The radio frequency low-noise MOSFET transistor structure with a buried layer structure is suitable for the development and production of circuit designs with special requirements such as low-noise amplifiers without requiring additional separate circuit-level design measures.

[0092] Please continue reading Fig.12 , Fig.12The schematic diagram of the structure of an embodiment of a radio frequency low noise MOSFET transistor with a buried layer structure of the present invention. The radio frequency low noise MOSFET transistor with a buried layer structure of the present embodiment includes a substrate 100, and a shallow trench isolation region 132 is provided on the upper part of the substrate 100, and the shallow trench isolation region 132 divides the substrate 100 into a first active region 110 and a second active region 120. A buried layer 111 and a deep N well 112 are formed by implantation in the substrate 100 of the first active region 110; the buried layer 111 is located directly above the deep N well 112, and the horizontal size of the deep N well 112 is larger than the horizontal size of the buried layer 111. A shallow N well 123 is formed by implantation in the substrate 100 around the deep N well 112, and the shallow N well 123 extends inwardly to contact the buried layer 111, thereby overlapping with the edge of the deep N well 112; a P well 113 is formed by implantation in the substrate 100 directly above the deep N well 112.

[0093] In this embodiment, the doping type of the substrate 100 is P-type doping, and the resistivity of the substrate 100 is 10Ω.cm to 70Ω.cm; the doping type of the buried layer 111 is N-type doping. The buried layer 111 must be located below the P-well 113 and above the deep N-well 112, and the buried layer 111 must be in contact with the shallow N-well 123 around it, so that the buried layer 111, as a layer of high N-type doping concentration, and the surrounding shallow N-well 123 structure together realize the isolation of the NMOSFET body P-well 113 and the bottom P-type substrate 100. Above the XY plane formed by the deep N-well 112, the isolation of the P-substrate 100 and the P-well 113 is realized by the dual structure of the deep N-well 112 and the N-type buried layer 111, which effectively realizes the crosstalk and coupling of noise signals generated by the voltage fluctuation of the P-type substrate 100 due to the voltage bias of different parts of the circuit.

[0094] An N-type gate 114 is provided on the surface of the substrate 100 above the P-well 113. An N-type source-drain contact region 115 is formed by implantation around the area directly below the N-type gate 114 corresponding to the P-well 113. An NLDD region 116 is formed by implantation inside the N-type source-drain contact region 115. A P-type gate 124 is provided on the surface of the substrate 100 above the shallow N-well 123. A P-type source-drain contact region 125 is formed by implantation around the area directly below the P-type gate 124 corresponding to the shallow N-well 123. A PLDD region 126 is formed by implantation inside the P-type source-drain contact region 125. Sidewall isolation structures 107 are respectively wrapped around the sides of the P-type gate 124 and the N-type gate 114. A metal contact layer 105 is respectively provided on the surfaces of the N-type gate 114, the N-type source-drain contact region 115, the P-type gate 124 and the P-type source-drain contact region 125.

[0095] In this embodiment, the NMOSFET transistor structure is isolated from the P-type substrate 100 by the N-type buried layer 111 and the deep N-well 112 under the P-well 113. At the same time, the N-type buried layer 111 and the deep N-well 112 realize double-layer isolation to further isolate the crosstalk and influence of the substrate 100, forming a MOSFET transistor structure that suppresses low-frequency noise, reduces the carrier recombination rate near the Si / SiO2 interface in the channel region, and suppresses the value of random telegraph noise of carriers and trap defects during transport, thereby achieving the effect of suppressing the low-frequency noise of the device; at the same time, the process of the MOSFET transistor structure that suppresses low-frequency noise is compatible with the existing SiGe BiCMOS manufacturing process.

[0096] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure, characterized in that: The following steps are involved: S1. providing a substrate, dividing a first active area and a second active area on the substrate, and implanting a buried layer into the substrate of the first active area; S2, forming a shallow trench isolation region at the upper portion of the substrate corresponding to the junction of the first active region and the second active region; S3, forming a deep N-well by implantation below the buried layer, wherein the horizontal size of the deep N-well is larger than the horizontal size of the buried layer; S4, forming a shallow N-well by implantation in the substrate around the deep N-well, wherein the shallow N-well extends inwardly to contact the buried layer, thereby overlapping with the edge of the deep N-well; Then, a P well is formed in the substrate directly above the deep N well by implantation; S5, manufacturing a P-type gate on the surface of the substrate above the shallow N-well, and manufacturing an N-type gate on the surface of the substrate above the P-well; and implanting on the substrate to form an N-type source-drain contact region, an NLDD region, a P-type source-drain contact region and a PLDD region; S6. Forming sidewall isolation structures around the P-type gate and the N-type gate respectively, and forming a metallized contact layer.

2. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 1, characterized in that: The doping type of the substrate is P-type doping, and the resistivity of the substrate is 10Ω.cm to 70Ω.cm; the doping type of the buried layer is N-type doping.

3. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 1 or 2, characterized in that: Implanting the buried layer into the substrate comprises the following sub-steps: S101, covering the surface of the substrate with a layer of photoresist, and photolithography out the implantation area of ​​the buried layer; S102, injecting antimony ions or arsenic ions into the area photoetched in step S101, with an injection dose of 1e 15 cm -2 ~5e 15 cm -2 ; S103, after the implantation is completed, a high temperature process is performed to form a buried layer, and the remaining photoresist on the substrate surface is removed.

4. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 3, characterized in that: The S2 step includes the following sub-steps: S201, forming a thin oxide layer on the surface of the substrate by thermal oxidation, and then depositing a silicon nitride layer on the thin oxide layer; S202, patterning the shallow trench region on the silicon nitride layer by photolithography, and selectively etching the thin oxide layer and the silicon nitride layer in the shallow trench region; S203, removing the remaining photoresist on the surface of the substrate, and etching the substrate to form a shallow trench using the silicon nitride layer and the thin oxide layer reserved after etching as a hard mask; S204, removing the silicon nitride layer and the thin oxide layer, and forming a linear oxide layer on the groove wall of the shallow trench by thermal oxidation; S205, depositing a high-density plasma oxide layer on the substrate to backfill the shallow trench; S206, using chemical mechanical polishing to achieve surface flattening, removing the high-density plasma oxide layer on the surface of the substrate, and the high-density plasma oxide layer remaining in the shallow trench forms a shallow trench isolation region.

5. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 4, characterized in that: In the step S2, before forming the shallow trench isolation region, epitaxial growth is performed on the substrate to form an epitaxial layer, the thickness of the epitaxial layer is 0.2 μm to 2 μm, and the doping type of the epitaxial layer is N-type doping.

6. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 4, characterized in that: The S3 step includes the following sub-steps: S301, covering the substrate surface with a layer of photoresist, and photolithography out the injection region of the deep N well; S302, using the remaining photoresist as a mask, using a high-energy ion implanter to perform ion implantation in the area photolithographed in step S301 to form a deep N well; S303, removing the remaining photoresist on the substrate surface.

7. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 6, characterized in that: In the step S302, arsenic ions are implanted to form a deep N well, and the implantation dose is 6×10 12 cm -2 ~1.5×10 13 cm -2 .

8. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 7, characterized in that: The S4 step includes the following sub-steps: S401, covering the substrate surface with a layer of photoresist, and photolithography out an injection region of a shallow N well; S402, using the remaining photoresist as a mask, implanting into the area photolithographically formed in step S401 to form a shallow N well; S403, covering the substrate surface with a layer of photoresist again, and photolithography out the injection area of ​​the P well; S404, using the remaining photoresist as a mask, implanting into the area photolithographically formed in step S403 to form a P well; S405, removing the remaining photoresist on the substrate surface.

9. The method for manufacturing a radio frequency low noise MOSFET transistor with a buried layer structure according to claim 8, characterized in that: In the step S402, phosphorus ion implantation is used to form a shallow N well, with an implantation energy of 400 keV and an implantation dose of 2×10 13 cm -2 ; In the step S404, boron ion implantation is used to form a P well, with an implantation energy of 250 keV and an implantation dose of 2×10 13 cm -2 .

10. A radio frequency low noise MOSFET transistor with a buried layer structure, characterized in that: The invention comprises a substrate, wherein a shallow trench isolation region is arranged on the upper part of the substrate, wherein the shallow trench isolation region divides the substrate into a first active region and a second active region; a buried layer and a deep N-well are formed by implantation in the substrate of the first active region; the buried layer is located directly above the deep N-well, and the horizontal dimension of the deep N-well is larger than the horizontal dimension of the buried layer; a shallow N-well is formed by implantation in the substrate around the deep N-well, wherein the shallow N-well extends inwardly to contact the buried layer, thereby overlapping with the edge of the deep N-well; A P well is formed in the substrate directly above the deep N well by implantation; An N-type gate is arranged on the substrate surface above the P-well, and an N-type source-drain contact region is formed by injection around the area directly below the P-well corresponding to the N-type gate, and an NLDD region is formed by injection inside the N-type source-drain contact region; a P-type gate is arranged on the substrate surface above the shallow N-well, and a P-type source-drain contact region is formed by injection around the area directly below the shallow N-well corresponding to the P-type gate, and a PLDD region is formed by injection inside the P-type source-drain contact region; sidewall isolation structures are respectively wrapped on the sides of the P-type gate and the N-type gate, and a metal contact layer is respectively arranged on the surfaces of the N-type gate, the N-type source-drain contact region, the P-type gate and the P-type source-drain contact region.

Images