Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device and the semiconductor device, and the method comprises the steps: etching a part of a second interlayer dielectric layer and a part of a first interlayer dielectric layer to form a first-type groove at the side of a gate structure, and etching a part of the first interlayer dielectric layer to form a second-type groove above the gate structure; the second interlayer dielectric layer is etched, a convex part structure, a first wiring groove and a second wiring groove are formed, one side of the convex part structure is the first wiring groove, and the other side of the convex part structure is the second wiring groove; etching the first interlayer dielectric layer and the second interlayer dielectric layer, and rubbing the first type of groove and the second type of groove until the first type of groove is connected with the metal silicide of the semiconductor structure and the second type of groove is connected with the gate oxide layer of the gate structure; filling a part of the second-type groove to form a metal gate, and simultaneously filling the first-type groove and a part of the second-type groove to form a contact plug; and filling the first wiring groove and the second wiring groove to form a metal layer.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a manufacturing method of a semiconductor device and a semiconductor device. Background Art

[0002] In the manufacturing of complementary metal oxide semiconductor (CMOS), the molding quality of gate and contact holes is an important factor affecting the yield and reliability of devices. In the process of gate and contact holes, etching and polishing cause depressions on the surface of the contact etch stop layer and uneven surface of the dielectric layer. In addition, in the process of gate and contact holes, metal residues may exist after the gate is polished, thereby increasing the possibility of contact hole disconnection and gate short circuit. In addition, in the process of gate and contact holes, the surface of the metal gate may bulge due to the pattern load, thereby increasing the turn-on voltage of the metal gate. Therefore, the molding yield of the process of gate and contact holes is low, resulting in low device reliability. Summary of the invention

[0003] The object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device, which can improve the molding yield of CMOS semiconductor devices and improve the reliability of the device.

[0004] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a method for manufacturing a semiconductor device, comprising the following steps: A semiconductor structure is provided, the semiconductor structure comprising a substrate and a gate structure, wherein the gate structure is disposed on the substrate; forming a first interlayer dielectric layer on the semiconductor structure, and forming a second interlayer dielectric layer on the first interlayer dielectric layer; Etching a portion of the second interlayer dielectric layer and a portion of the first interlayer dielectric layer to form a first type of trench on the side of the gate structure, and etching a portion of the first interlayer dielectric layer to form a second type of trench on the gate structure; Etching the second interlayer dielectric layer to form a convex structure, a first wiring groove and a second wiring groove, wherein one side of the convex structure is the first wiring groove, and the other side of the convex structure is the second wiring groove; Etching the first interlayer dielectric layer and the second interlayer dielectric layer to deepen the first type of trench and the second type of trench until the first type of trench is connected to the metal silicide of the semiconductor structure and the second type of trench is connected to the gate oxide layer of the gate structure; Filling a portion of the second type trench to form a metal gate, and simultaneously filling the first type trench and a portion of the second type trench to form a contact plug; and The first wiring trench and the second wiring trench are filled to form a metal layer.

[0005] In one embodiment of the present invention, the step of forming the first interlayer dielectric layer includes: forming a protective layer on the semiconductor structure, forming a first interlayer dielectric layer on the protective layer; and The first interlayer dielectric layer is ground until the first interlayer dielectric layer is flush with the nitride layer of the gate structure, wherein the nitride layer covers the polysilicon layer of the gate structure.

[0006] In one embodiment of the present invention, after forming the second interlayer dielectric layer, a stacked structure is formed on the second interlayer dielectric layer, wherein the stacked structure includes a protective layer, an anti-reflection layer and a first photoresist layer.

[0007] In one embodiment of the present invention, in the step of etching to form the first type of grooves and the second type of grooves, the orthographic projection of the etching window of the first type of grooves on the substrate overlaps with the functional area of ​​the semiconductor structure, and the orthographic projection of the etching window of the second type of grooves on the substrate overlaps with the polysilicon layer of the gate structure.

[0008] In one embodiment of the present invention, the width of the etching window for forming the second type of trenches is greater than the width of the etching layer window for forming the first type of trenches.

[0009] In one embodiment of the present invention, the step of forming the first wiring trench and the second wiring trench comprises: Etching the second interlayer dielectric layer between adjacent first-type trenches to form the first wiring trenches; and At the same time, a portion of the second interlayer dielectric layer located between the first type of trench and the second type of trench is etched to form the second wiring trench, and a convex structure is formed between the first type of trench and the second type of trench.

[0010] In one embodiment of the present invention, in the step of forming the first type of trench and the second type of trench, the bottom of the first type of trench is formed in the middle of the first interlayer dielectric layer, and the bottom of the second type of trench is formed in the middle of the second interlayer dielectric layer.

[0011] In one embodiment of the present invention, after forming the first type of grooves and the second type of grooves, a photoresist pattern is formed in the first type of grooves and the second type of grooves, and on the second interlayer dielectric layer between the first type of grooves and the second type of grooves.

[0012] In one embodiment of the present invention, in the step of forming the metal layer, after the first wiring groove and the second wiring groove are filled, the metal layer is ground until the metal layer is flush with the surface of the protrusion structure.

[0013] The present invention provides a semiconductor device, comprising: A semiconductor structure, comprising a substrate and a gate structure, wherein the gate structure is disposed on the substrate; A first interlayer dielectric layer is disposed on the semiconductor structure; A second interlayer dielectric layer is disposed on the first interlayer dielectric layer, wherein the second interlayer dielectric layer includes a convex structure, one side of the convex structure is a first wiring groove, and the other side of the convex structure is a second wiring groove; A plurality of first-type trenches, passing through the first interlayer dielectric layer and the second interlayer dielectric layer, connected to the metal silicide of the semiconductor structure, wherein the first-type trenches are connected to the first wiring trenches; A second type of trench, passing through the first interlayer dielectric layer and connected to the gate oxide layer of the gate structure, wherein the second type of trench is connected to the second wiring trench; a metal gate, filling the second type of trench and covering the gate oxide layer; a contact plug filled in the first type trench and the second type trench and connected to the metal gate or the metal silicide; and A metal layer is filled in the first wiring trench and the second wiring trench and is connected to the contact plug.

[0014] As described above, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, and its unexpected technical effect is that in the process of forming the gate and the contact hole, not only metal residue is avoided, but also over-etching and non-preset depressions can be avoided, so the metal gate has a high forming yield, and the defects caused by the polishing process and the load effect to the gate forming and the contact hole forming can be reduced, thereby improving the yield of the gate and contact hole forming process, thereby improving the reliability of the semiconductor device. The method for manufacturing a semiconductor device and the semiconductor device provided by the present invention have low process complexity and high manufacturing efficiency.

[0015] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 FIG. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0018] Figure 2 FIG. 4 is a schematic diagram of a structure for forming an etching stop layer in one embodiment of the present invention.

[0019] Figure 3 It is a schematic diagram of the structure of depositing a first interlayer dielectric layer in one embodiment of the present invention.

[0020] Figure 4 Schematic diagram of the structure after the first interlayer dielectric layer is ground in one embodiment of the present invention.

[0021] Figure 5 FIG. 4 is a schematic diagram of forming a stacking structure in one embodiment of the present invention.

[0022] Figure 6 FIG. 1 is a schematic diagram of a structure for forming a photolithography groove in an embodiment of the present invention.

[0023] Figure 7 It is a schematic diagram of the structure of forming the first type of grooves and the second type of grooves in one embodiment of the present invention.

[0024] Figure 8 FIG. 4 is a schematic diagram of a structure for forming a second photoresist layer in one embodiment of the present invention.

[0025] Fig. 9 FIG. 4 is a schematic diagram of a structure for forming a second photoresist pattern in one embodiment of the present invention.

[0026] Fig.10 FIG. 4 is a schematic diagram of a structure for forming a convex structure in one embodiment of the present invention.

[0027] Fig.11 FIG. 4 is a schematic diagram of a device structure after the second photoresist pattern is removed in one embodiment of the present invention.

[0028] Fig.12 Schematic diagram of the structure of the first type of groove and the second type of groove after deepening in one embodiment of the present invention.

[0029] Fig.13 Schematic diagram of the structure of the second type of groove after deepening in one embodiment of the present invention.

[0030] Fig.14FIG. 1 is a schematic diagram of the structure of a metal layer, a metal gate and a contact plug in one embodiment of the present invention.

[0031] Fig.15 Schematic diagram of the structure of the metal layer, metal gate and contact plug after grinding process in one embodiment of the present invention.

[0032] In the figure: 100, semiconductor structure; 110, substrate; 111, deep well region; 112, first well region; 113, second well region; 114, first doped region; 115, second doped region; 116, metal silicide; 120, gate structure; 121, gate oxide layer; 122, polysilicon layer; 123, sidewall structure; 1231, nitride layer; 200, protection layer; 300, first interlayer dielectric layer; 400, A second interlayer dielectric layer; 410, a protective layer; 420, a first anti-reflection layer; 430, a second anti-reflection layer; 440, a convex structure; 500, a first photoresist layer; 510, a photolithography groove; 520, a first type of groove; 530, a second type of groove; 600, a second photoresist layer; 610, a second photoresist pattern; 620, a first wiring groove; 630, a second wiring groove; 700, a metal layer; 710, a contact plug. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The semiconductor device provided by the present invention comprises a metal gate. The semiconductor device provided by the present invention may be one or more of semiconductor devices such as a field effect transistor (FET), a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), a high-speed and high-efficiency rectifier diode (HED), a constant voltage diode, a high-frequency diode, a light-emitting diode (LED), a gate light-closed thyristor (GTO), a light-triggered thyristor (LTT), a thyristor, a charge coupled device (CCD image sensor), a digital signal processor (DSP), a photo relay (Photo Relay) or a microprocessor (Micro Processor). In this embodiment, the semiconductor device is a CMOS semiconductor device.

[0035] See also Figure 1 As shown, in the method for manufacturing a semiconductor device provided by the present invention, a semiconductor structure 100 is first provided. The semiconductor structure 100 includes a substrate 110. The substrate 110 is, for example, a silicon substrate for forming the semiconductor structure 100. The substrate 110 may include a substrate and a silicon layer disposed on the substrate. The substrate may be, for example, silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium arsenide (GaAs), lithium aluminate (LiAlO 2) and other semiconductor substrate materials. Phosphorus ions or arsenic ions can be implanted in the silicon layer of the substrate 110 to form a deep well region 111 and multiple well regions and doped regions. Among them, multiple well regions, such as the first well region 112 and the second well region 113, are all located above the deep well region 111. In this embodiment, the doping ions of the first well region 112 and the second well region 113 are different. Specifically, the first well region 112 can be a P well, and the second well region 113 can be an N well. Continue to inject multiple ions into the well region to form the source region and drain region of the semiconductor structure 100. And ions can be injected into the well region, and the concentration of the injected ions can be adjusted to form a heavily doped region or a lightly doped region, etc., which is not specifically limited in the present invention. In this embodiment, for example, a first doped region 114 is formed in the first well region 112. For example, a second doped region 115 is formed in the second well region 113. It should be noted that the present invention does not limit the type and structure of the doped region. For example, the first doping region 114 is a doping structure with a rectangular cross section, and the second doping region 115 is sigma doped. Then, a metal silicide 116 is formed on the top of the first doping region 114 and the second doping region 115 by a metal silicide process.

[0036] See also Figure 1 As shown, in one embodiment of the present invention, the semiconductor structure 100 includes a gate structure 120. The gate structure 120 is disposed on the substrate 110, and the gate structure 120 is disposed between the source region and the drain region of the semiconductor structure 100. Among them, the gate structure 120 includes a gate oxide layer 121, a polysilicon layer 122 and a sidewall structure 123. In this embodiment, the gate oxide layer 121 is disposed on the substrate 110. It should be noted that the accompanying drawings do not show the multilayer structure of the gate oxide layer 121. In this embodiment, the gate oxide layer 121 can be a stacked structure of an oxide and a high-K dielectric layer. For example, the gate oxide layer 121 includes a hafnium dioxide layer and a titanium nitride layer. Among them, the polysilicon layer 122 is disposed on the gate oxide layer 121. The sidewall structure 123 is coated on the outside of the polysilicon layer 122 and the gate oxide layer 121. In this embodiment, the sidewall structure 123 includes at least one silicon nitride layer, and at least one silicon oxide layer. The silicon nitride layer is coated on the outside of the polysilicon layer 122 and the gate oxide layer 121, and the silicon oxide layer is arranged on the silicon nitride layer. The silicon nitride layer can be Figure 1 The nitride layer 1231 is shown.

[0037] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, a protective layer 200 is formed on the semiconductor structure 100. In this embodiment, silicon nitride is deposited on the substrate 110, the gate structure 120, and the metal silicide 116 by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD), thereby forming a protective layer 200 in a thin film shape to protect the semiconductor structure 100 from being damaged by the process in subsequent processes. The protective layer 200 covers the semiconductor structure 100.

[0038] See also Figure 2 and Figure 3 As shown, in one embodiment of the present invention, a first interlayer dielectric layer 300 is formed on the protective layer 200. In this embodiment, silicon oxide is deposited on the protective layer 200 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming the first interlayer dielectric layer 300. The thickness of the first interlayer dielectric layer 300 is greater than the height of the gate structure 120. Specifically, the first interlayer dielectric layer 300 covers the gate structure 120. It should be noted that, as shown in FIG. Figure 3 As shown, when the first interlayer dielectric layer 300 is formed, the surface of the first interlayer dielectric layer 300 is uneven. Specifically, the area of ​​the first interlayer dielectric layer 300 covering the gate structure 120 is higher than the area covering the substrate 110, and the area of ​​the first interlayer dielectric layer 300 covering the gate structure 120 is higher than the area covering the metal silicide 116.

[0039] See also Figure 3 and Figure 4 As shown, in one embodiment of the present invention, the surface of the first interlayer dielectric layer 300 is ground to expose the sidewall structure 123 covering the polysilicon layer 122, and the surface of the first interlayer dielectric layer 300 is flush with the surface of the nitride layer 1231. In this embodiment, the nitride layer 1231 is a layer of silicon nitride directly covering the polysilicon layer 122 in the sidewall structure 123. And the nitride layer 1231 is the innermost layer of the sidewall structure 123. In this embodiment, the first interlayer dielectric layer 300 and part of the sidewall structure 123 are processed by chemical mechanical polishing (CMP). Specifically, the nitride layer 1231 covering the top of the polysilicon layer 122 is used as a polishing stop layer, and part of the first interlayer dielectric layer 300 and part of the sidewall structure 123 are ground and removed. The part of the sidewall structure 123 removed is the part of the sidewall structure 123 located above the nitride layer 1231 on the top of the polysilicon layer 122. At this time, the surfaces of the first interlayer dielectric layer 300 and the nitride layer 1231 are flush with each other.

[0040] See also Figures 4 to 6 As shown, in one embodiment of the present invention, after grinding the first interlayer dielectric layer 300, a stacked structure is formed on the first interlayer dielectric layer 300. In this embodiment, borophospho silicate glass (BPSG) is deposited on the first interlayer dielectric layer 300 by chemical vapor deposition or plasma enhanced chemical vapor deposition, thereby forming a second interlayer dielectric layer 400. Then, a protective layer 410 is formed on the second interlayer dielectric layer 400. The protective layer 410 is an APF film, and the material is amorphous carbon. Then, a plurality of photolithography auxiliary layers are formed on the protective layer 410. In this embodiment, the photolithography auxiliary layer includes a first anti-reflection layer 420 and a second anti-reflection layer 430. The anti-reflection layer is an ARC film (Anti-Reflection Coating, ARC). Then, a photoresist is spin-coated on the second anti-reflection layer 430 to form a first photoresist layer 500. The first photoresist layer 500 is patterned by exposure etching and the like to form a plurality of photolithography grooves 510, and the first photoresist layer 500 is converted into a first photoresist pattern. In the present embodiment, the orthographic projection of a portion of the photolithography grooves 510 on the gate structure 120 is located on the polysilicon layer 122, and the orthographic projection of another portion of the photolithography grooves 510 on the substrate 110 is located on the metal silicide 116. The groove width of the photolithography grooves 510 located on the polysilicon layer 122 is greater than the groove width of the photolithography grooves 510 located on the metal silicide 116. It should be noted that the present invention does not limit the groove bottom of the photolithography grooves 510. In the present embodiment, the groove bottom of the photolithography grooves 510 may be the first anti-reflection layer 420.

[0041] See also Figure 6 and Figure 7As shown, in one embodiment of the present invention, the first photoresist pattern is used as a mask, and a portion of the first anti-reflection layer 420, a portion of the protective layer 410, a portion of the second interlayer dielectric layer 400, and a portion of the first interlayer dielectric layer 300 are removed by dry etching to form a first type of groove 520 and a second type of groove 530. In this embodiment, under the same etching environment and the same etching object, since the groove width of the photolithography groove 510 located on the metal silicide 116 is smaller, the etching depth is larger, and the first interlayer dielectric layer 300 is directly etched, thereby forming the first type of groove 520. However, the groove width of the photolithography groove 510 located on the polysilicon layer 122 is larger, so the etching depth is smaller, and only the second interlayer dielectric layer 400 is etched, thereby forming the second type of groove 530. The groove width of the second type of groove 530 is greater than the groove width of the first type of groove 520. In this embodiment, when the first type of groove 520 is formed, the etching is stopped at any position of the first interlayer dielectric layer 300. For example, etching can be stopped when etching reaches the middle of the first interlayer dielectric layer 300 to form the first type of trench 520 and the second type of trench 530. After the first type of trench 520 and the second type of trench 530 are formed, the first photoresist pattern, the first anti-reflection layer 420, the second anti-reflection layer 430 and the protective layer 410 are washed away to expose the second interlayer dielectric layer 400.

[0042] See also Figures 7 to 9 As shown, in one embodiment of the present invention, the first type of trench 520 and the second type of trench 530 are filled with photoresist to form a second photoresist layer 600. In this embodiment, after the photoresist fills the first type of trench 520 and the second type of trench 530, the photoresist continues to accumulate and forms a film structure on the second interlayer dielectric layer 400, as shown in FIG. Figure 8 As shown, a second photoresist layer 600 is formed. Then, the second photoresist layer 600 is processed by exposure and development, etc., to form a second photoresist pattern 610. When patterning the second photoresist layer 600, a portion of the photoresist located in the first type of groove 520 and the second type of groove 530 is retained, and a portion of the photoresist located on the second interlayer dielectric layer 400 is retained. In this embodiment, the second photoresist pattern 610 is located on the second interlayer dielectric layer 400, in the first type of groove 520, or in the second type of groove 530.

[0043] See also Figures 9 to 11As shown, in one embodiment of the present invention, the second photoresist pattern 610 is used as a mask layer to remove part of the second interlayer dielectric layer 400, form the first wiring groove 620 and the second wiring groove 630, and form the convex structure 440. In this embodiment, the second photoresist pattern 610 retained in the first type of groove 520 and the second type of groove 530 can protect this part of the first type of groove 520 and the second type of groove 530 from being affected by etching. On the second interlayer dielectric layer 400, the area not covered by the second photoresist pattern 610 is etched until the top surface of the second photoresist pattern 610 located in the first type of groove 520 and the second type of groove 530 is etched, thereby forming the first wiring groove 620 and the second wiring groove 630. The bottom of the first wiring groove 620 is connected to the top surface of the second photoresist pattern 610 located in the first type of groove 520 and the second type of groove 530. In the present embodiment, while forming the first wiring groove 620, a plurality of stepped convex structures 440 are formed on the top of the second interlayer dielectric layer 400. In the present embodiment, the orthographic projection of the first wiring groove 620 on the substrate 110 connects the source of the first device and the drain of the second device. The first device and the second device are adjacent. The orthographic projection of the second wiring groove 630 on the gate structure 120 overlaps with the polysilicon layer 122. In the present embodiment, the orthographic projection of the second wiring groove 630 on the gate structure 120 covers the polysilicon layer 122. Then, the second photoresist pattern 610 is removed to expose the first type of groove 520 and the second type of groove 530. In the present embodiment, the first wiring groove 620 connects the first type of groove 520 of different devices. The second wiring groove 630 connects the second type of groove 530.

[0044] See also Fig.11 and Fig.12 As shown, in one embodiment of the present invention, the first type of trench 520 is deepened so that the first type of trench 520 extends to the top surface of the metal silicide 116. The second type of trench 530 is deepened so that the second type of trench 530 extends to the top surface of the polysilicon layer 122. In this embodiment, the top surface of the metal silicide 116 is used as an etching stop layer, and the first interlayer dielectric layer 300 is etched to deepen the first type of trench 520. At the same time, the top surface of the polysilicon layer 122 is used as an etching stop layer, and the second interlayer dielectric layer 400 is etched to deepen the second type of trench 530. It should be noted that in this etching step, exposing the surface of the metal silicide 116 is used as an etching stop signal, so that a portion of the polysilicon layer 122 can be etched more.

[0045] See also Fig.12 and Fig.13As shown, in one embodiment of the present invention, the polysilicon layer 122 is etched away to continue deepening the second type of trench 530 until the polysilicon layer 122 is completely removed. In this embodiment, the polysilicon layer 122 is removed by wet etching. In another embodiment of the present invention, in the step of deepening the first type of trench 520, after the surface of the metal silicide 116 is exposed, the polysilicon layer 122 can be continuously etched until the polysilicon layer 122 is removed. Since the materials of the metal silicide 116 and the polysilicon layer 122 are completely different, in the step of removing the polysilicon layer 122, the surface of the metal silicide 116 can still be undamaged.

[0046] See also Figure 1 , Figures 13 to 15 As shown, in one embodiment of the present invention, the first type of trench 520 and the second type of trench 530 are filled to form a metal interconnection structure and a metal gate 800. The surface of the metal interconnection structure is ground so that the top surface of the metal interconnection structure is flush with the top surface of the convex structure 440. In this embodiment, the first type of trench 520, the second type of trench 530, the first wiring trench 620 and the second wiring trench 630 are filled with metal materials by chemical vapor deposition or sputtering, such as copper-aluminum alloy and tungsten, so as to form a metal gate 800 in the second type of trench 530, form a contact plug 710 in the first type of trench 520 and the first wiring trench 620, and form a metal layer 700 in the second wiring trench 630. The metal gate 800 is arranged on the gate oxide layer 121. After the first wiring trench 620 and the second wiring trench 630 are filled, the metal material continues to accumulate to increase the thickness of the metal layer 700. At this time, the metal layer 700 is electrically connected to the metal gate 800. In this embodiment, the metal layer 700 is thinned by chemical mechanical polishing until the surface of the metal layer 700 is flush with the top surface of the convex structure 440. At this time, the metal layer 700 is electrically connected to the source of one device and the drain of another device, and the metal gate 800 is led out separately. In this embodiment, in order to ensure that the convex structure 440 can play a good separation role, part of the convex structure 440 can be removed during polishing, so that the surface of the convex structure 440 is flush with the surface of the metal layer 700, and the semiconductor device structure of the present invention is formed. For easy identification, Fig.15 8 shows the structure of the metal gate 800. In the present invention, the metal gate 800, the contact plug 710 and the metal layer 700 are formed in the same step and the materials used are the same.

[0047] The present invention provides a method for manufacturing a semiconductor device and a semiconductor device, wherein a first type of groove is formed on the side of a gate structure by etching a portion of a second interlayer dielectric layer and a portion of a first interlayer dielectric layer, and a second type of groove is formed above the gate structure by etching a portion of the first interlayer dielectric layer. The second interlayer dielectric layer is etched to form a convex structure, a first wiring groove and a second wiring groove, wherein one side of the convex structure is the first wiring groove and the other side of the convex structure is the second wiring groove. The first interlayer dielectric layer and the second interlayer dielectric layer are etched to deepen the first type of groove and the second type of groove until the first type of groove is connected to the metal silicide of the semiconductor structure and the second type of groove is connected to the gate oxide layer of the gate structure. A portion of the second type of groove is filled to form a metal gate, and the first type of groove and a portion of the second type of groove are filled to form a contact plug. And the first wiring groove and the second wiring groove are filled to form a metal layer. The unexpected technical effect of the present invention is that in the process of forming the gate and the contact hole, not only metal residue is avoided, but also over-etching and non-preset depressions can be avoided, so the metal gate has a high forming yield, and the defects caused by the polishing process and the load effect to the gate forming and the contact hole forming can be reduced, thereby improving the yield of the gate and contact hole forming process, thereby improving the reliability of the semiconductor device. The manufacturing method and semiconductor device provided by the present invention have low process complexity and high manufacturing efficiency.

[0048] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: A semiconductor structure is provided, the semiconductor structure comprising a substrate and a gate structure, wherein the gate structure is disposed on the substrate; forming a first interlayer dielectric layer on the semiconductor structure, and forming a second interlayer dielectric layer on the first interlayer dielectric layer; Etching a portion of the second interlayer dielectric layer and a portion of the first interlayer dielectric layer to form a first type of trench on the side of the gate structure, and etching a portion of the first interlayer dielectric layer to form a second type of trench on the gate structure; Etching the second interlayer dielectric layer to form a convex structure, a first wiring groove and a second wiring groove, wherein one side of the convex structure is the first wiring groove, and the other side of the convex structure is the second wiring groove; Etching the first interlayer dielectric layer and the second interlayer dielectric layer to deepen the first type of trench and the second type of trench until the first type of trench is connected to the metal silicide of the semiconductor structure and the second type of trench is connected to the gate oxide layer of the gate structure; Filling a portion of the second type of trench to form a metal gate, and simultaneously filling the first type of trench and a portion of the second type of trench to form a contact plug; as well as The first wiring trench and the second wiring trench are filled to form a metal layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The step of forming the first interlayer dielectric layer comprises: forming a protective layer on the semiconductor structure, forming a first interlayer dielectric layer on the protective layer; and The first interlayer dielectric layer is ground until the first interlayer dielectric layer is flush with the nitride layer of the gate structure, wherein the nitride layer covers the polysilicon layer of the gate structure.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that: After forming the second interlayer dielectric layer, a stacked structure is formed on the second interlayer dielectric layer, wherein the stacked structure includes a protective layer, an anti-reflection layer and a first photoresist layer.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the step of etching to form the first type of grooves and the second type of grooves, the orthographic projection of the etching window of the first type of grooves on the substrate overlaps with the functional area of ​​the semiconductor structure, and the orthographic projection of the etching window of the second type of grooves on the substrate overlaps with the polysilicon layer of the gate structure.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The width of the etching window for forming the second type of trench is greater than the width of the etching layer window for forming the first type of trench.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The step of forming the first wiring trench and the second wiring trench comprises: Etching the second interlayer dielectric layer between adjacent first-type trenches to form the first wiring trenches; and At the same time, a portion of the second interlayer dielectric layer located between the first type of trench and the second type of trench is etched to form the second wiring trench, and a convex structure is formed between the first type of trench and the second type of trench.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the step of forming the first type trench and the second type trench, the bottom of the first type trench is formed in the middle of the first interlayer dielectric layer, and the bottom of the second type trench is formed in the middle of the second interlayer dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that: After forming the first type of grooves and the second type of grooves, a photoresist pattern is formed in the first type of grooves and the second type of grooves, and on the second interlayer dielectric layer between the first type of grooves and the second type of grooves.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In the step of forming the metal layer, after the first wiring groove and the second wiring groove are filled, the metal layer is ground until the metal layer is flush with the surface of the protrusion structure.

10. A semiconductor device, characterized in that: include: A semiconductor structure, comprising a substrate and a gate structure, wherein the gate structure is disposed on the substrate; A first interlayer dielectric layer is disposed on the semiconductor structure; A second interlayer dielectric layer is disposed on the first interlayer dielectric layer, wherein the second interlayer dielectric layer includes a convex structure, one side of the convex structure is a first wiring groove, and the other side of the convex structure is a second wiring groove; A plurality of first-type trenches, passing through the first interlayer dielectric layer and the second interlayer dielectric layer, connected to the metal silicide of the semiconductor structure, wherein the first-type trenches are connected to the first wiring trenches; A second type of trench, passing through the first interlayer dielectric layer and connected to the gate oxide layer of the gate structure, wherein the second type of trench is connected to the second wiring trench; a metal gate, filling the second type of trench and covering the gate oxide layer; A contact plug filled in the first type of trench and the second type of trench and connected to the metal gate or the metal silicide; as well as A metal layer is filled in the first wiring trench and the second wiring trench and is connected to the contact plug.

Images