HEMT (High Electron Mobility Transistor) cascade device

Abstract

The invention belongs to the technical field of semiconductors, and discloses an HEMT cascade device which comprises a GaN chip and an MOS chip, the GaN chip comprises a matching capacitor, a first source electrode, a first drain electrode, a first gate electrode, a substrate, a laminated structure, a first dielectric layer and a second dielectric layer, the substrate, the laminated structure, the first dielectric layer and the second dielectric layer are sequentially arranged from bottom to top, and the surface of the matching capacitor comprises a matching capacitor electrode. The first source electrode, the first drain electrode and the first gate electrode are all located in the first dielectric layer and the second dielectric layer, the matching capacitor is located above the second dielectric layer, and at least part of the orthographic projection of the matching capacitor on the substrate coincides with the orthographic projection of the first drain electrode on the substrate. And the matching capacitor electrode is used for connecting the matching capacitor with a third gate electrode of the HEMT cascade type device during packaging. According to the HEMT cascade type device, the matching capacitor is designed on the upper layer of the conventional GaN chip, and the matching capacitor is connected with the third gate electrode of the cascade type device during packaging, so that the Cgd of the HEMT cascade type device is increased, and the switching speed adjustment of the device is facilitated.

Description

[0001] This application is a divisional application of the invention patent application with application date of September 24, 2024, application number 202411328309.3, and invention name “A GaN chip and its preparation method, HEMT cascade device and its packaging method”. Technical Field

[0002] The present invention belongs to the field of semiconductor technology, and in particular relates to a HEMT cascade device. Background Art

[0003] There are two main types of AlGaN / GaN HEMT devices: cascade type and enhancement type. Among them, enhancement type devices mainly use P-GaN, which has many problems such as weak gate, high resistivity, reliability risks, and high dynamic resistance. The cascade type device uses a depletion-type GaN device and a low-voltage MOS for cascading. At this time, the drive is completely determined by the low-voltage MOS, which has high reliability. At the same time, the resistivity of GaN can be controlled at the optimal level, and the parasitic parameters introduced by the low-voltage MOS are very small, making the overall device show high performance. At present, cascaded GaN power devices have been widely used in various types of switching power supplies, especially in industrial and automotive categories, and have certain advantages.

[0004] However, the C gd The capacitance is mainly composed of the depletion mode GaN C ds And low voltage MOS C gd Series formation, since the depletion-type GaN is a planar structure, its C ds Often much smaller than the C of low voltage MOS gd , so the C of the cascade device gd Mainly composed of GaN C ds Since the C of the cascaded device gd The width of the Miller platform is the main factor affecting the switching speed (tr, tf). The above situation will cause the switching speed of the cascade device to be too fast, which may cause vibration in practical applications, reduce efficiency, increase electromagnetic radiation, and even cause machine crashes. Therefore, how to effectively optimize the C of the cascade device is a key issue. gd , which is an urgent problem to be solved in the current promotion of cascade devices.

[0005] The main solutions currently available for the above problems are as follows:

[0006] (1) Increasing the C of depletion-mode GaN ds :But this solution will bring significant hidden dangers, namely, leading to C ds _GaN / (C ds _MOS+C gdThe increase of this ratio will lead to abnormal shutdown transient waveform, mainly because the low-voltage MOS distribution voltage increases and reaches avalanche, thus causing reliability risks for the entire cascade device.

[0007] (2) Increase the C of low voltage MOS gd :However, due to the C gd It is the C of low voltage MOS gd With GaN C ds In series, usually the C gd Much larger than GaN’s C ds , further increase the C of the low voltage MOS gd The effect on the series capacitance is very small, that is, the improvement effect is not obvious.

[0008] (3) Increase the driving resistance (main method): reduce the charging and discharging speed of the capacitor by limiting the current through resistance, but this will increase the driving loss and reduce the efficiency of the whole machine.

[0009] (4) External C gd Capacitor: This solution has a long external loop and is prone to oscillation.

[0010] In summary, the industry has made great efforts to optimize the C of cascade devices. gd There is no unified and effective solution to the problem yet. Summary of the invention

[0011] In view of this, in order to overcome the defects of the prior art, the purpose of the present invention is to provide a HEMT cascade device. On the basis of a conventional GaN chip, a matching capacitor is designed on the upper layer of the chip, and the matching capacitor is connected to the gate electrode of the HEMT cascade device during packaging, which is beneficial to increase the C gd , which is helpful to improve a series of problems caused by the excessively fast switching speed of HEMT cascade devices in practical applications.

[0012] The present invention provides a GaN chip, comprising a matching capacitor, a first source electrode, a first drain electrode, a first gate electrode, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top, wherein the surface of the matching capacitor comprises a matching capacitor electrode, the first source electrode, the first drain electrode, and the first gate electrode are all located in the first dielectric layer and the second dielectric layer, the matching capacitor is located above the second dielectric layer, the orthographic projection of the matching capacitor on the substrate at least partially overlaps with the orthographic projection of the first drain electrode on the substrate, and the matching capacitor electrode is used to connect the matching capacitor to the third gate electrode of a HEMT cascade device during packaging.

[0013] By designing a matching capacitor on the GaN chip, the size of the matching capacitor can be adjusted according to the size of the overlap area of ​​the orthographic projection of the matching capacitor on the substrate and the orthographic projection of the first drain electrode on the substrate, and the matching capacitor is connected to the gate electrode of the MOS chip through the matching capacitor electrode and the bonding wire during packaging, which is beneficial to increase the C of the HEMT cascade device. gd ; At the same time, the C of HEMT cascade devices can be selectively adjusted gs , and the C of the MOS chip gd , which ultimately helps to adjust the switching speed of HEMT cascade devices.

[0014] According to some preferred implementation aspects of the present invention, it further includes a first source electrode extension electrode and a first drain electrode extension electrode, wherein the first source electrode extension electrode and the first drain electrode extension electrode are both located in the stacked structure and the first dielectric layer.

[0015] According to some preferred implementation aspects of the present invention, the first source electrode extension electrode is connected to the first source electrode and is located below the first source electrode, and the first drain electrode extension electrode is connected to the first drain electrode and is located below the first drain electrode.

[0016] According to some preferred implementation aspects of the present invention, the matching capacitor includes a first part, a first connecting part and a second part, one end of the first connecting part is connected to the first part, and the other end of the first connecting part is connected to the second part.

[0017] According to some preferred implementation aspects of the present invention, the orthographic projection of the first portion on the substrate is within the range of the orthographic projection of the first drain electrode on the substrate. In some embodiments of the present invention, the first portion of the matching capacitor is designed above the first drain electrode. At this time, the lower electrode of the matching capacitor includes the first drain electrode of the GaN chip. Since the drain electrode (first drain electrode) of the GaN chip is the drain electrode (third drain electrode) of the final HEMT cascade device, when the HEMT cascade device is packaged, when the upper electrode of the matching capacitor (matching capacitor electrode) is connected to the gate electrode (third gate electrode) of the HEMT cascade device, the C brought by the matching capacitor is introduced. gd , which helps to adjust the C of HEMT cascade devices gd , thereby effectively adjusting the switching speed of the HEMT cascade device.

[0018] According to some preferred implementation aspects of the present invention, a portion of the orthographic projection of the first portion on the substrate is located within the range of the orthographic projection of the first drain electrode on the substrate, and a portion of the orthographic projection of the first portion on the substrate is located within the range of the orthographic projection of the first gate electrode on the substrate. In some embodiments of the present invention, the first portion of the matching capacitor is made wider so that a portion of it falls on the first drain electrode and a portion of it falls on the first gate electrode. At this time, the lower electrode of the matching capacitor includes the first drain electrode and the first gate electrode of the GaN chip. Because the drain electrode (first drain electrode) of the GaN chip is the drain electrode (third drain electrode) of the final HEMT cascade device, and the gate electrode (first gate electrode) of the GaN chip is the source electrode (third source electrode) of the final HEMT cascade device, when the HEMT cascade device is packaged, when the upper electrode of the matching capacitor is connected to the gate electrode (third gate electrode) of the HEMT cascade device, the C gd On the basis of the HEMT cascade device, the C gs , which is beneficial to adjust the C of HEMT cascade devices gd , realize switching speed adjustment; can also control the driving speed; control C gs With MOS chip C gd The ratio of makes the gate of the HEMT cascade device float and the drain voltage rises, and the gate terminal, as the middle point of the series capacitor, will not have the problem of false start-up caused by excessive voltage floating, and the system is more stable.

[0019] According to some preferred implementation aspects of the present invention, the matching capacitor also includes a third part and a second connecting part, one end of the second connecting part is connected to the second part, the other end of the second connecting part is connected to the third part, and the orthographic projection of the third part on the substrate is located within the range of the orthographic projection of the first source electrode on the substrate.

[0020] Preferably, in some other embodiments of the present invention, the first part of the matching capacitor is designed to be above the first drain electrode, and the third part is designed to be on the first source electrode. In this case, the lower electrode of the matching capacitor includes the first drain electrode and the first source electrode of the GaN chip. Since the drain electrode (first drain electrode) of the GaN chip is the drain electrode (third drain electrode) of the final HEMT cascade device, and the source electrode (first source electrode) of the GaN chip is connected to the drain electrode (second drain electrode) of the MOS chip in the HEMT cascade device, when the HEMT cascade device is packaged, when the upper electrode of the matching capacitor is connected to the gate electrode (third gate electrode) of the HEMT cascade device, when C is introduced gd On the basis of the MOS chip, the C gd capacitor, which is helpful to adjust the C gd , realize the adjustment of switching speed; it can also adjust the C of MOS chipgd , further adjust the C of the HEMT cascade device gd , to achieve fine-tuning of its switching speed; in addition, the C gd With GaN chip C ds The ratio of 20V to 20V makes the voltage division of the MOS chip controlled at the moment of shutdown, and it will not avalanche or even stay away from the avalanche range.

[0021] Preferably, in some other embodiments of the present invention, the first part of the matching capacitor is designed to be above the first drain electrode and the first gate electrode, and the third part is designed to be on the first source electrode. In this case, the lower electrode of the matching capacitor includes the first drain electrode, the first gate electrode and the first source electrode of the GaN chip. Since the drain electrode (first drain electrode) of the GaN chip is the drain electrode (third drain electrode) of the final HEMT cascade device, the gate electrode (first gate electrode) of the GaN chip is the source electrode (third source electrode) of the final HEMT cascade device, and the source electrode (first source electrode) of GaN is connected to the drain electrode (second drain electrode) of the MOS chip in the HEMT cascade device, when the HEMT cascade device is packaged, when the upper electrode of the matching capacitor is connected to the gate electrode (third gate electrode) of the HEMT cascade device, when C is introduced gd On the basis of the HEMT cascade device, the C gs , and also increased the C gd , which is beneficial to adjust the C gd , realize the adjustment of switching speed; can control the driving speed; control the C gs With MOS chip C gd The ratio of 100% to 100% makes it possible for the HEMT cascade device to be in a state of gate floating and drain voltage rising, with the gate end acting as the middle point of the series capacitor, without the problem of false start-up caused by excessive voltage floating, making the system more stable. It is also beneficial to adjust the C of the MOS chip. gd , further adjust the C of the HEMT cascade device gd , thereby achieving fine-tuning of the switching speed of the cascade device; it is beneficial to adjust the C gd With GaN chip C ds The ratio of 20V to 20V makes the voltage division of the MOS chip controlled at the moment of shutdown, and it will not avalanche or even stay away from the avalanche range.

[0022] According to some preferred implementation aspects of the present invention, the matching capacitor electrode is located on the second portion, and an area of ​​the matching capacitor electrode is smaller than an area of ​​the second portion.

[0023] The present invention also provides a method for preparing the GaN chip as described above, comprising the following steps:

[0024] Performing epitaxial growth of nitride on the substrate to sequentially form a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer, wherein the nucleation layer, the buffer layer, the channel layer, the barrier layer and the cap layer constitute a stacked structure;

[0025] Etching is performed on the capping layer of the stacked structure to form a source electrode ohmic hole and a drain electrode ohmic hole;

[0026] Filling metal in the source electrode ohmic hole and the drain electrode ohmic hole and performing annealing treatment to form a first source electrode extension electrode and a first drain electrode extension electrode respectively;

[0027] Depositing a first dielectric layer above the first source electrode extension electrode and the first drain electrode extension electrode, and etching a source electrode hole, a drain electrode hole, and a gate electrode hole;

[0028] Filling metal on the first dielectric layer and etching away excess metal to form a first source electrode, a first drain electrode and a first gate electrode;

[0029] Depositing a second dielectric layer on the first source electrode, the first drain electrode and the first gate electrode, and etching a source electrode opening window, a drain electrode opening window and a gate electrode opening window;

[0030] Filling metal on the second dielectric layer and etching excess metal to form a matching capacitor; obtaining the GaN chip.

[0031] The present invention further provides a HEMT cascade device, comprising a MOS chip and a GaN chip as described above. The HEMT cascade device of the present invention further comprises a frame and a substrate. The HEMT cascade device is formed by cascading a GaN chip and a MOS chip in a source-gate co-connected manner, and a side of the substrate of the GaN chip away from the stacked structure is connected to the frame. Furthermore, the MOS chip is arranged on the front side of the substrate, and the GaN chip and the substrate are both arranged on the third source electrode of the HEMT cascade device; the first source electrode of the GaN chip is electrically connected to the substrate, the first drain electrode of the GaN chip is electrically connected to the third drain electrode of the HEMT cascade device, the first gate electrode of the GaN chip is electrically connected to the third source electrode of the HEMT cascade device, and the matching capacitor of the GaN chip is electrically connected to the third gate electrode of the HEMT cascade device. The second source electrode of the MOS chip is electrically connected to the third source electrode of the HEMT cascade device, the second gate electrode of the MOS chip is electrically connected to the third gate electrode of the HEMT cascade device, and the second drain electrode of the MOS chip is bonded to a side of the substrate away from the frame to achieve electrical connection. The middle layer of the substrate is an insulating layer, and the front and back surfaces of the substrate are both conductive layers.

[0032] The present invention also provides a packaging method for a HEMT cascade device, wherein the MOS chip comprises a second source electrode, a second drain electrode, and a second gate electrode, and the HEMT cascade device comprises a third source electrode, a third drain electrode, and a third gate electrode, and the packaging method comprises the following steps:

[0033] The GaN chip and the substrate are attached to the mounting area of ​​the frame, and the MOS chip is attached to the substrate; the second drain electrode is attached to a side of the substrate away from the frame;

[0034] The first drain electrode is connected to the third drain electrode, the first gate electrode is connected to the third source electrode, the first source electrode is connected to the surface of the substrate, and the matching capacitor is connected to the third gate electrode;

[0035] The second source electrode is connected to the third source electrode, and the second gate electrode is connected to the third gate electrode; thus completing the packaging of the HEMT cascade device.

[0036] In the present invention, the package shape of the HEMT cascade device can be DFN, TO, TOLL, TOLT, SOP or any other shape with three or more pins. For the HEMT cascade device, it includes at least three electrodes, namely, a third source electrode, a third drain electrode, and a third gate electrode, and the third source electrode also serves as a patch area.

[0037] Due to the adoption of the above technical solution, compared with the prior art, the present invention is beneficial in that: the present invention increases the C of the HEMT cascade device by designing a matching capacitor on the upper layer of a conventional GaN chip and connecting it to the third gate electrode of the HEMT cascade device during packaging. gd , which is conducive to adjusting the switching speed of the device, thereby improving the problems of oscillation, reduced efficiency, increased electromagnetic radiation, and even machine crash caused by the excessive switching speed of HEMT cascade devices in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a cross-sectional schematic diagram after the stacked structure is formed in step 1 of the preparation method of Example 5 of the present invention;

[0040] Figure 2 It is a cross-sectional schematic diagram after the source electrode ohmic hole and the drain electrode ohmic hole are formed in step 2 of the preparation method of Example 5 of the present invention;

[0041] Figure 3 It is a cross-sectional schematic diagram after forming a first source electrode extension electrode and a first drain electrode extension electrode in step 2 of the preparation method of embodiment 5 of the present invention;

[0042] Figure 4 It is a cross-sectional schematic diagram after forming the first dielectric layer, the source electrode hole, the drain electrode hole and the gate electrode hole in step 3 of the preparation method of embodiment 5 of the present invention;

[0043] Figure 5 It is a cross-sectional schematic diagram after forming a first source electrode, a first drain electrode and a first gate electrode in step 4 of the preparation method of embodiment 5 of the present invention;

[0044] Figure 6 It is a cross-sectional schematic diagram after forming a second dielectric layer and a source electrode opening window, a drain electrode opening window and a gate electrode opening window in step 5 of the preparation method of embodiment 5 of the present invention;

[0045] Figure 7 It is a cross-sectional schematic diagram of the GaN chip in Example 1 of the present invention and a cross-sectional schematic diagram after the matching capacitor is formed in step 6 of the preparation method of Example 5;

[0046] Figure 8 is a schematic cross-sectional view of a GaN chip in Embodiment 2 of the present invention;

[0047] Fig. 9 is a schematic cross-sectional view of a GaN chip in Example 3 of the present invention;

[0048] Fig.10 is a schematic cross-sectional view of a GaN chip in Example 4 of the present invention;

[0049] Fig.11 Schematic diagram of the top view of the GaN chip in Example 1 of the present invention;

[0050] Fig.12 Schematic diagram of the top view of the GaN chip in Embodiment 2 of the present invention;

[0051] Fig.13 Schematic diagram of the top view of the GaN chip in Example 3 of the present invention;

[0052] Fig.14 Schematic diagram of the top view of the GaN chip in Example 4 of the present invention;

[0053] Fig.15 Schematic diagram of the top view of the HEMT cascade device in Embodiments 1 to 4 of the present invention;

[0054] Fig.16Schematic diagram of the top view of the HEMT cascade device in Comparative Example 1 of the present invention;

[0055] Fig.17 is an equivalent circuit diagram of the HEMT cascade device in Example 1 of the present invention;

[0056] Fig.18 is an equivalent circuit diagram of the HEMT cascade device in Example 2 of the present invention;

[0057] Fig.19 is an equivalent circuit diagram of a HEMT cascade device in Example 3 of the present invention;

[0058] Fig. 20 is an equivalent circuit diagram of a HEMT cascade device in Example 4 of the present invention;

[0059] Fig.21 It is a double pulse test simulation switching curve of the HEMT cascade device in Comparative Example 1 of the present invention;

[0060] Fig. 22 It is a double pulse test simulation switching curve of the HEMT cascade device in Example 1 of the present invention;

[0061] Wherein, the accompanying drawings are marked as follows:

[0062] GaN chip-10, substrate-1, nucleation layer-21, buffer layer-22, channel layer-23, barrier layer-24, cap layer-25, source electrode ohmic hole-251, drain electrode ohmic hole-252, first source electrode extension electrode-253, first drain electrode extension electrode-254, first source electrode-3, first drain electrode-4, first dielectric layer-5, source electrode hole-51, drain electrode hole-52, gate electrode hole-53, second dielectric layer-6, source electrode opening window-61, drain electrode opening window -62, gate electrode window-63, matching capacitor-64, matching capacitor electrode-641, first part-642, second part-643, third part-644, first connecting part-645, second connecting part-646, first gate electrode-7, MOS chip-20, second source electrode-201, second drain electrode-202, second gate electrode-203, frame-30, substrate-40, third source electrode-501, third drain electrode-502, third gate electrode-503, bonding wire-60. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0064] The GaN chip 10 of the present invention comprises a matching capacitor 64, a first source electrode 3, a first drain electrode 4, a first gate electrode 7, and a substrate 1, a stacked structure, a first dielectric layer 5, and a second dielectric layer 6 arranged in sequence from bottom to top. The surface of the matching capacitor 64 comprises a matching capacitor electrode 641. The stacked structure comprises a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a cap layer 25 arranged in sequence from bottom to top. A two-dimensional electron gas is formed at the interface between the channel layer 23 and the barrier layer 24. The first source electrode 3, the first drain electrode 4, and the first gate electrode 7 are all located in the first dielectric layer 5 and the second dielectric layer 6, the matching capacitor 64 is located above the second dielectric layer 6, and the matching capacitor electrode 641 is used to connect the matching capacitor 64 to the third gate electrode 503 of the HEMT cascade device during packaging.

[0065] Furthermore, the GaN chip 10 of the present invention further includes a first source electrode extension electrode 253 and a first drain electrode extension electrode 254, both of which are located in the barrier layer 24, the cap layer 25 and the first dielectric layer 5. The first source electrode extension electrode 253 is connected to the first source electrode 3 and is located below the first source electrode 3, and the first drain electrode extension electrode 254 is connected to the first drain electrode 4 and is located below the first drain electrode 4.

[0066] Furthermore, in some embodiments of the present invention, the matching capacitor 64 includes a first part 642, a first connecting part 645 and a second part 643, one end of the first connecting part 645 is connected to the first part 642, and the other end of the first connecting part 645 is connected to the second part 643, and the orthographic projection of the first part 642 on the substrate 1 is located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1, that is, the first part 642 of the matching capacitor 64 is designed to be above the first drain electrode 4.

[0067] Furthermore, in some embodiments of the present invention, the matching capacitor 64 includes a first part 642, a first connecting part 645 and a second part 643, one end of the first connecting part 645 is connected to the first part 642, and the other end of the first connecting part 645 is connected to the second part 643, a portion of the orthographic projection of the first part 642 on the substrate 1 is located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1, and a portion of the orthographic projection of the first part 642 on the substrate 1 is located within the range of the orthographic projection of the first gate electrode 7 on the substrate 1, that is, a portion of the first part 642 of the matching capacitor 64 is designed above the first drain electrode 4, and a portion of the first part 642 is designed above the first gate electrode 7.

[0068] Furthermore, in some embodiments of the present invention, the matching capacitor 64 includes a first part 642, a second part 643, a third part 644, a first connecting part 645 and a second connecting part 646, one end of the first connecting part 645 is connected to the first part 642, the other end of the first connecting part 645 is connected to the second part 643, one end of the second connecting part 646 is connected to the second part 643, the other end of the second connecting part 646 is connected to the third part 644, the orthographic projection of the first part 642 on the substrate 1 is located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1, and the orthographic projection of the third part 644 on the substrate 1 is located within the range of the orthographic projection of the first source electrode 3 on the substrate 1, that is, the first part 642 of the matching capacitor 64 is designed to be above the first drain electrode 4, and the third part 644 is designed to be above the first source electrode 3.

[0069] Further, in some embodiments of the present invention, the matching capacitor 64 includes a first portion 642, a second portion 643, a third portion 644, a first connecting portion 645 and a second connecting portion 646, one end of the first connecting portion 645 is connected to the first portion 642, the other end of the first connecting portion 645 is connected to the second portion 643, one end of the second connecting portion 646 is connected to the second portion 643, and the other end of the second connecting portion 646 is connected to the third portion 644; a portion of the orthographic projection of the first portion 642 on the substrate 1 is located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1, a portion of the orthographic projection of the first portion 642 on the substrate 1 is located within the range of the orthographic projection of the first gate electrode 7 on the substrate 1, and an orthographic projection of the third portion 644 on the substrate 1 is located within the range of the orthographic projection of the first source electrode 3 on the substrate 1, that is, a portion of the first portion 642 of the matching capacitor 64 is designed above the first drain electrode 4, a portion of the first portion 642 is designed above the first gate electrode 7, and the third portion 644 is designed above the first source electrode 3.

[0070] By designing a matching capacitor 64 on the GaN chip 10 and connecting the matching capacitor 64 to the second gate electrode 203 of the MOS chip 20 through the matching capacitor electrode 641 and the bonding wire 60 during packaging, it is beneficial to increase the C of the HEMT cascade device. gd .

[0071] The present invention further provides a HEMT cascade device, which includes a MOS chip 20 and the GaN chip 10 as described above. The HEMT cascade device can be formed by cascading the MOS chip 20 and the GaN chip 10 in a source-gate co-connected manner.

[0072] Embodiment 1 Device structure

[0073] like Fig.15 As shown, the HEMT cascade device in this embodiment includes a GaN chip 10, a MOS chip 20, a substrate 40 and a frame 30. Figure 7 and Fig.11 As shown, the GaN chip 10 includes a matching capacitor 64, a first source electrode 3, a first drain electrode 4, a first gate electrode 7, and a substrate 1, a stacked structure, a first dielectric layer 5, and a second dielectric layer 6 arranged from bottom to top. The stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a cap layer 25 arranged from bottom to top. A two-dimensional electron gas is formed at the interface between the channel layer 23 and the barrier layer 24. The MOS chip 20 includes a second source electrode 201, a second drain electrode 202, and a second gate electrode 203; the HEMT cascade device has a third source electrode 501, a third drain electrode 502, and a third gate electrode 503. The middle layer of the substrate 40 is an insulating layer, and the front and back surfaces of the substrate 40 are both conductive layers. The MOS chip 20 is arranged on the front surface of the substrate 40, and the GaN chip 10 and the substrate 40 are both arranged on the third source electrode 501.

[0074] Further, the first source electrode 3, the first drain electrode 4 and the first gate electrode 7 are all located in the first dielectric layer 5 and the second dielectric layer 6; the surface of the matching capacitor 64 includes a matching capacitor electrode 641, the matching capacitor 64 is located above the second dielectric layer 6, and the matching capacitor electrode 641 is used to connect the matching capacitor 64 to the third gate electrode 503 during packaging. The GaN chip 10 also includes a first source electrode extension electrode 253 and a first drain electrode extension electrode 254, the first source electrode extension electrode 253 is arranged corresponding to the first source electrode 3, the first drain electrode extension electrode 254 is arranged corresponding to the first drain electrode 4, and the first source electrode extension electrode 253 and the first drain electrode extension electrode 254 are both located in the barrier layer 24, the cap layer 25 and the first dielectric layer 5; the first source electrode extension electrode 253 is connected to the first source electrode 3 and is located below the first source electrode 3, and the first drain electrode extension electrode 254 is connected to the first drain electrode 4 and is located below the first drain electrode 4.

[0075] Further, the matching capacitor 64 in the GaN chip 10 of the present embodiment includes a first portion 642, a first connecting portion 645 and a second portion 643, one end of the first connecting portion 645 is connected to one end of the first portion 642, the other end of the first connecting portion 645 is connected to one end of the second portion 643, the width of the first portion 642 is greater than the width of the first connecting portion 645; the orthographic projection of the first portion 642 on the substrate 1 is only located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1. In the present embodiment, the capacitance of the designed matching capacitor 64 is 5pF.

[0076] Furthermore, when the device is packaged, the side of the substrate 1 of the GaN chip 10 away from the stacked structure is electrically connected to the frame 30 through silver glue, the first source electrode 3 is electrically connected to the substrate 40 through the bonding wire 60, the first drain electrode 4 is electrically connected to the third drain electrode 502 through the bonding wire 60, the first gate electrode 7 is electrically connected to the third source electrode 501 through the bonding wire 60, and the matching capacitor 64 is electrically connected to the third gate electrode 503 through the matching capacitor electrode 641 and the bonding wire 60; the second source electrode 201 is electrically connected to the third source electrode 501 through the bonding wire 60, the second gate electrode 203 is electrically connected to the third gate electrode 503 through the bonding wire 60, and the second drain electrode 202 is bonded to the side of the substrate 40 away from the frame 30 to achieve electrical connection between the two.

[0077] The equivalent circuit diagram of the HEMT cascade device in this embodiment is as follows: Fig.17 As shown, by designing the first portion 642 of the matching capacitor 64 above the first drain electrode 4, the matching capacitor electrode 641 is used as the upper electrode of the matching capacitor 64. At this time, the lower electrode of the matching capacitor 64 includes the first drain electrode 4 of the GaN chip 10. In the HEMT cascade device, since the first drain electrode 4 is the final third drain electrode 502, when the HEMT cascade device is packaged, when the matching capacitor electrode 641 is connected to the third gate electrode 503, the C brought by the matching capacitor 64 is introduced. gd , which helps to adjust the C of HEMT cascade devices gd , thereby effectively adjusting the switching speed of the HEMT cascade device.

[0078] Embodiment 2 Device structure

[0079] like Fig.15 As shown, the HEMT cascade device in this embodiment includes a GaN chip 10, a MOS chip 20, a substrate 40 and a frame 30. Figure 8 and Fig.12As shown, the GaN chip 10 includes a matching capacitor 64, a first source electrode 3, a first drain electrode 4, a first gate electrode 7, and a substrate 1, a stacked structure, a first dielectric layer 5, and a second dielectric layer 6 arranged from bottom to top. The stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a cap layer 25 arranged from bottom to top. A two-dimensional electron gas is formed at the interface between the channel layer 23 and the barrier layer 24. The MOS chip 20 includes a second source electrode 201, a second drain electrode 202, and a second gate electrode 203; the HEMT cascade device has a third source electrode 501, a third drain electrode 502, and a third gate electrode 503. The middle layer of the substrate 40 is an insulating layer, and the front and back surfaces of the substrate 40 are both conductive layers. The MOS chip 20 is arranged on the front surface of the substrate 40, and the GaN chip 10 and the substrate 40 are both arranged on the third source electrode 501.

[0080] Further, the first source electrode 3, the first drain electrode 4 and the first gate electrode 7 are all located in the first dielectric layer 5 and the second dielectric layer 6; the surface of the matching capacitor 64 includes a matching capacitor electrode 641, the matching capacitor 64 is located above the second dielectric layer 6, and the matching capacitor electrode 641 is used to connect the matching capacitor 64 to the third gate electrode 503 during packaging. The GaN chip 10 also includes a first source electrode extension electrode 253 and a first drain electrode extension electrode 254, the first source electrode extension electrode 253 is arranged corresponding to the first source electrode 3, the first drain electrode extension electrode 254 is arranged corresponding to the first drain electrode 4, and the first source electrode extension electrode 253 and the first drain electrode extension electrode 254 are both located in the barrier layer 24, the cap layer 25 and the first dielectric layer 5; the first source electrode extension electrode 253 is connected to the first source electrode 3 and is located below the first source electrode 3, and the first drain electrode extension electrode 254 is connected to the first drain electrode 4 and is located below the first drain electrode 4.

[0081] Furthermore, the matching capacitor 64 in the GaN chip 10 of the present embodiment includes a first part 642, a first connecting part 645 and a second part 643, one end of the first connecting part 645 is connected to one end of the first part 642, the other end of the first connecting part 645 is connected to one end of the second part 643, and the width of the first part 642 is greater than the width of the first connecting part 645; a part of the orthographic projection of the first part 642 on the substrate 1 is located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1, and a part of the orthographic projection of the first part 642 on the substrate 1 is located within the range of the orthographic projection of the first gate electrode 7 on the substrate 1.

[0082] Furthermore, when the device is packaged, the side of the substrate 1 of the GaN chip 10 away from the stacked structure is electrically connected to the frame 30 through silver glue, the first source electrode 3 is electrically connected to the substrate 40 through the bonding wire 60, the first drain electrode 4 is electrically connected to the third drain electrode 502 through the bonding wire 60, the first gate electrode 7 is electrically connected to the third source electrode 501 through the bonding wire 60, and the matching capacitor 64 is electrically connected to the third gate electrode 503 through the matching capacitor electrode 641 and the bonding wire 60; the second source electrode 201 is electrically connected to the third source electrode 501 through the bonding wire 60, the second gate electrode 203 is electrically connected to the third gate electrode 503 through the bonding wire 60, and the second drain electrode 202 is bonded to the side of the substrate 40 away from the frame 30 to achieve electrical connection between the two.

[0083] The equivalent circuit diagram of the HEMT cascade device in this embodiment is as follows: Fig.18 As shown, by designing a part of the first portion 642 of the matching capacitor 64 above the first drain electrode 4, and a part of the first portion 642 above the first gate electrode 7, the matching capacitor electrode 641 is used as the upper electrode of the matching capacitor 64. At this time, the lower electrode of the matching capacitor 64 includes the first drain electrode 4 and the first gate electrode 7 of the GaN chip 10. In the HEMT cascade device, since the first drain electrode 4 is the final third drain electrode 502 and the first gate electrode 7 is the final third source electrode 501, when the HEMT cascade device is packaged, when the matching capacitor electrode 641 is connected to the third gate electrode 503, the C gd On the basis of the HEMT cascade device, the C gs , which is beneficial to adjust the C of HEMT cascade devices gd , realize the adjustment of switching speed; at the same time, it can also control the driving speed and control C gs With MOS chip 20 C gd The ratio of makes the gate of the HEMT cascade device float and the drain voltage rises, and the gate terminal, as the middle point of the series capacitor, will not have the problem of false start-up caused by excessive voltage floating, making the system more stable.

[0084] Embodiment 3 Device structure

[0085] like Fig.15 As shown, the HEMT cascade device in this embodiment includes a GaN chip 10, a MOS chip 20, a substrate 40 and a frame 30. Fig. 9 and Fig.13As shown, the GaN chip 10 includes a matching capacitor 64, a first source electrode 3, a first drain electrode 4, a first gate electrode 7, and a substrate 1, a stacked structure, a first dielectric layer 5, and a second dielectric layer 6 arranged from bottom to top. The stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a cap layer 25 arranged from bottom to top. A two-dimensional electron gas is formed at the interface between the channel layer 23 and the barrier layer 24. The MOS chip 20 includes a second source electrode 201, a second drain electrode 202, and a second gate electrode 203; the HEMT cascade device has a third source electrode 501, a third drain electrode 502, and a third gate electrode 503. The middle layer of the substrate 40 is an insulating layer, and the front and back surfaces of the substrate 40 are both conductive layers. The MOS chip 20 is arranged on the front surface of the substrate 40, and the GaN chip 10 and the substrate 40 are both arranged on the third source electrode 501.

[0086] Further, the first source electrode 3, the first drain electrode 4 and the first gate electrode 7 are all located in the first dielectric layer 5 and the second dielectric layer 6; the surface of the matching capacitor 64 includes a matching capacitor electrode 641, the matching capacitor 64 is located above the second dielectric layer 6, and the matching capacitor electrode 641 is used to connect the matching capacitor 64 to the third gate electrode 503 during packaging. The GaN chip 10 also includes a first source electrode extension electrode 253 and a first drain electrode extension electrode 254, the first source electrode extension electrode 253 is arranged corresponding to the first source electrode 3, the first drain electrode extension electrode 254 is arranged corresponding to the first drain electrode 4, and the first source electrode extension electrode 253 and the first drain electrode extension electrode 254 are both located in the barrier layer 24, the cap layer 25 and the first dielectric layer 5; the first source electrode extension electrode 253 is connected to the first source electrode 3 and is located below the first source electrode 3, and the first drain electrode extension electrode 254 is connected to the first drain electrode 4 and is located below the first drain electrode 4.

[0087] Further, the matching capacitor 64 in the GaN chip 10 of the present embodiment includes a first portion 642, a second portion 643, a third portion 644, a first connecting portion 645, and a second connecting portion 646. One end of the first connecting portion 645 is connected to one end of the first portion 642, the other end of the first connecting portion 645 is connected to one end of the second portion 643, one end of the second connecting portion 646 is connected to the other end of the second portion 643, and the other end of the second connecting portion 646 is connected to one end of the third portion 644. The width of the first connecting portion 645 is equal to the width of the second connecting portion 646, the width of the first portion 642 is greater than the width of the first connecting portion 645, and the width of the third portion 644 is greater than the width of the second connecting portion 646. The orthographic projection of the first portion 642 on the substrate 1 is only located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1, and the orthographic projection of the third portion 644 on the substrate 1 is only located within the range of the orthographic projection of the first source electrode 3 on the substrate 1.

[0088] Furthermore, when the device is packaged, the side of the substrate 1 of the GaN chip 10 away from the stacked structure is electrically connected to the frame 30 through silver glue, the first source electrode 3 is electrically connected to the substrate 40 through the bonding wire 60, the first drain electrode 4 is electrically connected to the third drain electrode 502 through the bonding wire 60, the first gate electrode 7 is electrically connected to the third source electrode 501 through the bonding wire 60, and the matching capacitor 64 is electrically connected to the third gate electrode 503 through the matching capacitor electrode 641 and the bonding wire 60; the second source electrode 201 is electrically connected to the third source electrode 501 through the bonding wire 60, the second gate electrode 203 is electrically connected to the third gate electrode 503 through the bonding wire 60, and the second drain electrode 202 is bonded to the side of the substrate 40 away from the frame 30 to achieve electrical connection between the two.

[0089] The equivalent circuit diagram of the HEMT cascade device in this embodiment is as follows: Fig.19 As shown, the first part 642 of the matching capacitor 64 is designed above the first drain electrode 4, the third part 644 is designed above the first source electrode 3, and the matching capacitor electrode 641 is used as the upper electrode of the matching capacitor 64. At this time, the lower electrode of the matching capacitor 64 includes the first drain electrode 4 and the first source electrode 3 of the GaN chip 10. In the HEMT cascade device, since the first drain electrode 4 is the final third drain electrode 502 and the first source electrode 3 is connected to the second drain electrode 202, when the HEMT cascade device is packaged, when the matching capacitor electrode 641 is connected to the third gate electrode 503, the C gd On the basis of the MOS chip 20, the C gd capacitor, which is helpful to adjust the C gd , to adjust the switching speed; it can also adjust the C of the MOS chip 20 gd , further adjust the C of the HEMT cascade device gd , to achieve fine-tuning of its switching speed; in addition, in this embodiment, the C of the MOS chip 20 can also be adjusted gd With GaN chip 10 C ds The ratio of 20 to 25 makes the voltage division of the MOS chip 20 controlled at the moment of shutdown, and does not avalanche, or even stays away from the avalanche range.

[0090] Embodiment 4 Device structure

[0091] like Fig.15 As shown, the HEMT cascade device in this embodiment includes a GaN chip 10, a MOS chip 20, a substrate 40 and a frame 30. Fig.10 and Fig.14As shown, the GaN chip 10 includes a matching capacitor 64, a first source electrode 3, a first drain electrode 4, a first gate electrode 7, and a substrate 1, a stacked structure, a first dielectric layer 5, and a second dielectric layer 6 arranged from bottom to top. The stacked structure includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24, and a cap layer 25 arranged from bottom to top. A two-dimensional electron gas is formed at the interface between the channel layer 23 and the barrier layer 24. The MOS chip 20 includes a second source electrode 201, a second drain electrode 202, and a second gate electrode 203; the HEMT cascade device has a third source electrode 501, a third drain electrode 502, and a third gate electrode 503. The middle layer of the substrate 40 is an insulating layer, and the front and back surfaces of the substrate 40 are both conductive layers. The MOS chip 20 is arranged on the front surface of the substrate 40, and the GaN chip 10 and the substrate 40 are both arranged on the third source electrode 501.

[0092] Further, the first source electrode 3, the first drain electrode 4 and the first gate electrode 7 are all located in the first dielectric layer 5 and the second dielectric layer 6; the surface of the matching capacitor 64 includes a matching capacitor electrode 641, the matching capacitor 64 is located above the second dielectric layer 6, and the matching capacitor electrode 641 is used to connect the matching capacitor 64 to the third gate electrode 503 during packaging. The GaN chip 10 also includes a first source electrode extension electrode 253 and a first drain electrode extension electrode 254, the first source electrode extension electrode 253 is arranged corresponding to the first source electrode 3, the first drain electrode extension electrode 254 is arranged corresponding to the first drain electrode 4, and the first source electrode extension electrode 253 and the first drain electrode extension electrode 254 are both located in the barrier layer 24, the cap layer 25 and the first dielectric layer 5; the first source electrode extension electrode 253 is connected to the first source electrode 3 and is located below the first source electrode 3, and the first drain electrode extension electrode 254 is connected to the first drain electrode 4 and is located below the first drain electrode 4.

[0093] Further, the matching capacitor 64 in the GaN chip 10 of the present embodiment includes a first portion 642, a second portion 643, a third portion 644, a first connecting portion 645, and a second connecting portion 646. One end of the first connecting portion 645 is connected to one end of the first portion 642, the other end of the first connecting portion 645 is connected to one end of the second portion 643, one end of the second connecting portion 646 is connected to the other end of the second portion 643, and the other end of the second connecting portion 646 is connected to one end of the third portion 644. The width of the first connecting portion 645 is equal to the width of the second connecting portion 646, the width of the first portion 642 is greater than the width of the first connecting portion 645, and the width of the third portion 644 is greater than the width of the second connecting portion 646. A portion of the orthographic projection of the first portion 642 on the substrate 1 is located within the range of the orthographic projection of the first drain electrode 4 on the substrate 1 , a portion of the orthographic projection of the first portion 642 on the substrate 1 is located within the range of the orthographic projection of the first gate electrode 7 on the substrate 1 , and the orthographic projection of the third portion 644 on the substrate 1 is only located within the range of the orthographic projection of the first source electrode 3 on the substrate 1 .

[0094] Furthermore, when the device is packaged, the side of the substrate 1 of the GaN chip 10 away from the stacked structure is electrically connected to the frame 30 through silver glue, the first source electrode 3 is electrically connected to the substrate 40 through the bonding wire 60, the first drain electrode 4 is electrically connected to the third drain electrode 502 through the bonding wire 60, the first gate electrode 7 is electrically connected to the third source electrode 501 through the bonding wire 60, and the matching capacitor 64 is electrically connected to the third gate electrode 503 through the matching capacitor electrode 641 and the bonding wire 60; the second source electrode 201 is electrically connected to the third source electrode 501 through the bonding wire 60, the second gate electrode 203 is electrically connected to the third gate electrode 503 through the bonding wire 60, and the second drain electrode 202 is bonded to the side of the substrate 40 away from the frame 30 to achieve electrical connection between the two.

[0095] The equivalent circuit diagram of the HEMT cascade device in this embodiment is as follows: Fig. 20 As shown, by designing a part of the first part 642 of the matching capacitor 64 above the first drain electrode 4, a part of the first part 642 is designed above the first gate electrode 7, and the third part 644 is designed on the first source electrode 3, the matching capacitor electrode 641 is used as the upper electrode of the matching capacitor 64. At this time, the lower electrode of the matching capacitor 64 includes the first drain electrode 4, the first gate electrode 7 and the first source electrode 3 of the GaN chip 10. In the HEMT cascade device, since the first drain electrode 4 is the final third drain electrode 502, the first gate electrode 7 is the final third source electrode 501, and the first source electrode 3 is connected to the second drain electrode 202, when the HEMT cascade device is packaged, when the matching capacitor electrode 641 is connected to the third gate electrode 503, when C is introduced gd On the basis of the HEMT cascade device, the C gs , and also increased the C of the MOS chip 20gd , which is beneficial to adjust the C gd , to adjust the switching speed; it can also control the driving speed and control the C gs With MOS chip 20 C gd The ratio of 20 makes the gate of the HEMT cascade device float and the drain voltage rise, so that the gate terminal, as the middle point of the series capacitor, will not cause the problem of false start due to excessive voltage floating, making the system more stable. It can also be adjusted by adjusting the C of the MOS chip 20 gd , further adjust the C of the HEMT cascade device gd , thereby achieving fine-tuning of the switching speed of the cascade device; the C gd With GaN chip 10 C ds The ratio of 20 to 25 makes the voltage division of the MOS chip 20 controlled at the moment of shutdown, and does not avalanche, or even stays away from the avalanche range.

[0096] Comparative Example 1 Device Structure

[0097] like Fig.16 As shown, the HEMT cascade device in this comparative example includes a GaN chip 10, a MOS chip 20, a substrate 40 and a frame 30. The difference between the device structure in this comparative example and that in Example 1 is that the GaN chip 10 in this comparative example does not have a matching capacitor 64, and when the device is packaged, only the second gate electrode 203 is electrically connected to the third gate electrode 503, and there is no matching capacitor 64.

[0098] Specifically, in this comparative example, the side of the substrate 1 of the GaN chip 10 away from the stacked structure is electrically connected to the frame 30 through silver glue, the first source electrode 3 is electrically connected to the substrate 40 through the bonding wire 60, the first drain electrode 4 is electrically connected to the third drain electrode 502 through the bonding wire 60, and the first gate electrode 7 is electrically connected to the third source electrode 501 through the bonding wire 60; the second source electrode 201 is electrically connected to the third source electrode 501 through the bonding wire 60, the second drain electrode 202 is bonded to the side of the substrate 40 away from the frame 30 to achieve electrical connection between the two, and the second gate electrode 203 is electrically connected to the third gate electrode 503 through the bonding wire 60.

[0099] Example 5 Preparation method

[0100] This embodiment provides a method for preparing the GaN chip 10 in the above-mentioned embodiments 1 to 4, which specifically includes the following steps:

[0101] Step 1: Figure 1As shown, nitride epitaxial growth is performed on the substrate 1 to sequentially form a nucleation layer 21, a buffer layer 22, a channel layer 23, a barrier layer 24 and a cap layer 25, and the nitride material includes GaN, AlGaN, AlN, AlGaNInN, SiN and other group III nitride materials. The nucleation layer 21, the buffer layer 22, the channel layer 23, the barrier layer 24 and the cap layer 25 form a stacked structure, thereby forming a complete semiconductor epitaxial layer structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 23 and the barrier layer 24 to generate a conductive channel.

[0102] The substrate 11 is one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, germanium, diamond, sapphire or any other material capable of growing group III nitride materials.

[0103] Step 2: If Figure 2 As shown, patterned etching is performed on the cap layer 25 to form a source electrode ohmic hole 251 and a drain electrode ohmic hole 252, and metal is filled in the source electrode ohmic hole 251 and the drain electrode ohmic hole 252. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, AlSiCu, and W. The filling method includes evaporation, sputtering, etc., and patterned stripping or etching is used to form a specific structure, and annealing is performed to form an ohmic contact, so as to form a first source electrode extension electrode 253 and a first drain electrode extension electrode 254, respectively. Figure 3 shown.

[0104] Step 3: deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 on the first source electrode extension electrode 253 and the first drain electrode extension electrode 254 to form a first dielectric layer 5, and etch out a source electrode hole 51, a drain electrode hole 52, and a gate electrode hole 53, such as Figure 4 shown.

[0105] Step 4: Fill the first dielectric layer 5 with metal, the metal includes one or more combinations of Cu, Ag, Sn, Pb, PbSn, Ti, Al, AlCu, AlSiCu, TiN, and the filling method includes evaporation, sputtering, etc. Cooperate with patterned stripping or etching to form a specific structure, etch away excess metal, and form the first source electrode 3, the first drain electrode 4 and the first gate electrode 7, such as Figure 5 shown.

[0106] Step 5: Deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 on the first source electrode 3, the first drain electrode 4, and the first gate electrode 7 to form a second dielectric layer 6, and etch a source electrode opening window 61, a drain electrode opening window 62, and a gate electrode opening window 63, as shown in FIG. Figure 6 shown.

[0107] Step 6: Figure 7 , Figure 8 , Fig. 9 or Fig.10 As shown, metal is filled on the second dielectric layer 6, and the metal includes one or more combinations of Cu, Ag, Sn, Pb, PbSn, Ti, Al, AlCu, AlSiCu, and TiN, and the filling method includes evaporation, sputtering, etc. A specific structure is formed by patterned stripping or etching, and the excess metal is etched away to form a matching capacitor 64, thereby obtaining a GaN chip 10.

[0108] Embodiment 6 Packaging method

[0109] This embodiment provides a method for packaging the HEMT cascade device in the above-mentioned embodiments 1 to 4, which specifically includes the following steps:

[0110] Step 1: Use the third source electrode 501 on the frame 30 as the patch area, attach the GaN chip 10 and the substrate 40 to the patch area of ​​the frame 30, attach the MOS chip 20 to the substrate 40 and make the second drain electrode 202 fit with the side of the substrate 40 away from the frame 30 to achieve electrical connection between the second drain electrode 202 and the substrate 40.

[0111] Step 2: Connect the first drain electrode 4 to the third drain electrode 502 through the bonding wire 60, connect the first gate electrode 7 to the third source electrode 501 through the bonding wire 60, connect the first source electrode 3 to the surface of the substrate 40 through the bonding wire 60, and connect the matching capacitor electrode 641 on the matching capacitor 64 to the third gate electrode 503 through the bonding wire 60.

[0112] Step 3: Connect the second source electrode 201 and the third source electrode 501 via the bonding wire 60 , and connect the second gate electrode 203 and the third gate electrode 503 via the bonding wire 60 , thereby completing the packaging of the HEMT cascade device.

[0113] In this embodiment, the package shape of the HEMT cascade device can be any one of DFN, TO, TOLL, TOLT, SOP or any other shapes with three pins or more.

[0114] Example 7 Results and Discussion

[0115] The double pulse test was performed on the HEMT cascade devices in Comparative Example 1 and Example 1, and the results were as follows: Fig.21 (Comparative Example 1) and Fig. 22 The double pulse test simulation switch curve shown in (Example 1) is Figure 21 to Figure 22 It can be seen that when a matching capacitor 64 is designed in Example 1 (C gd=5pF), the switching speed can be effectively adjusted. Compared with comparative example 1, the turn-on time tf in embodiment 1 is effectively extended by 45%, which further illustrates that the design of the matching capacitor 64 can increase the C of the HEMT cascade device. gd , which is beneficial to achieve the switching speed adjustment of the device.

[0116] The above embodiments of the present invention are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A HEMT cascade device, comprising a MOS chip, a GaN chip, a substrate and a frame, characterized in that: The GaN chip includes a matching capacitor, a first source electrode, a first source electrode extension electrode, a first drain electrode, a first drain electrode extension electrode, a first gate electrode, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top; the surface of the matching capacitor includes a matching capacitor electrode, the first source electrode extension electrode is arranged corresponding to the first source electrode, and the first drain electrode extension electrode is arranged corresponding to the first drain electrode; the matching capacitor is adjusted by adjusting the overlapping area of ​​the orthographic projection of the matching capacitor on the substrate and the orthographic projection of the first drain electrode on the substrate; The HEMT cascade device further comprises at least a third source electrode, a third drain electrode and a third gate electrode. The third source electrode is used as a patch area when the HEMT cascade device is packaged. The matching capacitor is connected to the third gate electrode through the matching capacitor electrode.

2. The HEMT cascade device according to claim 1, characterized in that: The matching capacitor electrode is used as the upper electrode of the matching capacitor, and the lower electrode of the matching capacitor includes at least the first drain electrode; the material of the matching capacitor is a combination of one or more of Cu, Ag, Sn, Pb, PbSn, Ti, Al, AlCu, AlSiCu, and TiN.

3. The HEMT cascade device according to claim 2, characterized in that: The matching capacitor includes a first portion, a first connecting portion, and a second portion. The first portion is located above the first drain electrode, and an orthographic projection of the first portion on the substrate is located within the range of an orthographic projection of the first drain electrode on the substrate.

4. The HEMT cascade device according to claim 3, characterized in that: The lower electrode of the matching capacitor includes the first drain electrode.

5. The HEMT cascade device according to claim 2, characterized in that: The matching capacitor includes a first part, a first connecting part, and a second part, a part of the first part is located above the first drain electrode, a part of the first part is located above the first gate electrode, a part of the orthographic projection of the first part on the substrate is located within the range of the orthographic projection of the first drain electrode on the substrate, and a part of the orthographic projection of the first part on the substrate is located within the range of the orthographic projection of the first gate electrode on the substrate.

6. The HEMT cascade device according to claim 5, characterized in that: The lower electrode of the matching capacitor includes the first drain electrode and a first gate electrode.

7. The HEMT cascade device according to claim 4 or 6, characterized in that: Two ends of the first connecting portion are respectively connected to the first portion and the second portion, and a width of the first portion is greater than a width of the first connecting portion.

8. The HEMT cascade device according to claim 2, characterized in that: The matching capacitor includes a first part, a second part, a third part, a first connecting part and a second connecting part, the first part is located above the first drain electrode, the third part is located above the first source electrode, the orthographic projection of the first part on the substrate is located within the range of the orthographic projection of the first drain electrode on the substrate, and the orthographic projection of the third part on the substrate is located within the range of the orthographic projection of the first source electrode on the substrate.

9. The HEMT cascade device according to claim 8, characterized in that: The lower electrode of the matching capacitor includes the first drain electrode and a first source electrode.

10. The HEMT cascade device according to claim 2, characterized in that: The matching capacitor includes a first part, a second part, a third part, a first connecting part, and a second connecting part, a part of the first part is located above the first drain electrode, a part of the first part is located above the first gate electrode, the third part is located above the first source electrode, a part of the orthographic projection of the first part on the substrate is located within the range of the orthographic projection of the first drain electrode on the substrate, a part of the orthographic projection of the first part on the substrate is located within the range of the orthographic projection of the first gate electrode on the substrate, and the orthographic projection of the third part on the substrate is located within the range of the orthographic projection of the first source electrode on the substrate.

11. The HEMT cascade device according to claim 10, characterized in that: The lower electrode of the matching capacitor includes the first drain electrode, a first gate electrode and a first source electrode.

12. The HEMT cascade device according to claim 9 or 11, characterized in that: One end of the first connecting portion is connected to one end of the first portion, the other end of the first connecting portion is connected to one end of the second portion, one end of the second connecting portion is connected to the other end of the second portion, and the other end of the second connecting portion is connected to one end of the third portion; the width of the first connecting portion is equal to the width of the second connecting portion, the width of the first portion is greater than the width of the first connecting portion, and the width of the third portion is greater than the width of the second connecting portion.

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