Integrated power field effect transistor

Abstract

The invention discloses an integrated power field effect transistor which comprises a gate structure layer, a conductive structure layer, an epitaxial layer and a substrate layer which are arranged in a stacked mode in the first direction, the conductive structure layer comprises a first conductive structure region, a JFET region and a second conductive structure region, the JFET region is arranged between the first conductive structure region and the second conductive structure region in the second direction, and the first conductive structure region is arranged between the first conductive structure region and the second conductive structure region. A first channel region and a Schottky contact layer are arranged in the first conductive structure region, the Schottky contact layer, the first channel region and the JFET region are sequentially connected in the second direction, and the Schottky contact layer is arranged on the surface, close to the gate structure layer, of the first conductive structure region; wherein the substrate layer, the epitaxial layer and the JFET region have a first conductive type, the first conductive structure region has a second conductive type, and the second conductive structure region has the first conductive type and the second conductive type. According to the integrated power field effect transistor, the influence of an internal body diode can be reduced, and the integrated power field effect transistor has relatively high power density and reliability.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to an integrated power field effect transistor. Background Art

[0002] Among semiconductor devices, SiC MOSFET (SiC Metal Oxide Semiconductor Field Effect Transistor) power devices have excellent dynamic characteristics, and their faster switching speed can make their dynamic power consumption lower. However, there is a natural body diode in SiC MOSFET, and the presence of the body diode can cause crystal defects in the device and lead to bipolar degradation effects, which will increase additional power consumption after long-term use.

[0003] Among the current solutions, the bipolar degradation effect is usually alleviated by integrating an SBD structure or an LBD device into an integrated SiC MOSFET. However, the SiC MOSFET power device with an integrated SBD structure has a large leakage current, which may cause short-circuit failure and avalanche failure, affecting the overall reliability. The SiC MOSFET power device with an integrated LBD device has a high on-voltage and a large reverse recovery current, resulting in a low power density of the device. Summary of the invention

[0004] The present application provides an integrated power field effect transistor, which can reduce the influence of an internal body diode and has high power density and reliability.

[0005] The present application provides an integrated power field effect transistor, which includes a gate structure layer, a conductive structure layer, an epitaxial layer and a substrate layer stacked along a first direction, the conductive structure layer includes a first conductive structure region, a JFET region and a second conductive structure region, the JFET region is arranged between the first conductive structure region and the second conductive structure region in the second direction, the first conductive structure region has a first channel region and a Schottky contact layer, the Schottky contact layer, the first channel region and the JFET region are connected in sequence in the second direction, and the Schottky contact layer is arranged on the surface of the first conductive structure region close to the gate structure layer; wherein the substrate layer, the epitaxial layer and the JFET region have a first conductivity type, the first conductive structure region has a second conductivity type, and the second conductive structure region has a first conductivity type and a second conductivity type.

[0006] As above, the integrated power field effect transistor, wherein the first conductive structure region also includes a first well region and a first doped region, the first channel region and the first doped region are arranged at intervals along the second direction, at least part of the first well region is connected between the conductive structure region and the first doped region, and the Schottky contact layer is connected to and covers the surface of the first well region close to the gate structure layer.

[0007] As above integrated power field effect transistor, wherein the gate structure layer includes a first gate, the first gate is conductively connected to both the JFET region and the first channel region, and a portion of the Schottky contact layer is arranged on the surface of the first channel region close to the gate structure layer and is conductively connected to the first gate.

[0008] In the above integrated power field effect transistor, the first channel region has a channel length L in the second direction, and the channel length L has a value range of: 0.3 μm≤L≤1 μm.

[0009] In the above integrated power field effect transistor, the doping concentration of the first doping region is higher than the doping concentration of the first well region, and the doping concentration of the first channel region is lower than the doping concentration of the first well region.

[0010] In the above integrated power field effect transistor, along the first direction, the width of the first channel region is smaller than the width of the first well region, and the width of the first doped region is the same as the width of the first well region.

[0011] As above, the integrated power field effect transistor, wherein the second conductive structure region includes a second well region, a second channel region, a second doping region and a third doping region, and within the conductive structure layer, the second channel region, the second doping region and the third doping region are all arranged on a side close to the gate structure layer, the second well region is arranged on a side close to the epitaxial layer, and the second channel region, the second doping region and the third doping region are arranged in sequence along the second direction; wherein the second doping region is of the first conductive type, and the second channel region, the third doping region and the second well region are all of the second conductive type.

[0012] In the above integrated power field effect transistor, the gate structure layer further includes a second gate, and the second gate is conductively connected to the JFET region, the second channel region and the second doping region.

[0013] In the above integrated power field effect transistor, the doping concentrations of the second doping region and the third doping region are both higher than that of the second well region, and the doping concentration of the second channel region is lower than that of the second well region.

[0014] The integrated power field effect transistor as above, wherein the integrated power field effect transistor also includes a first electrode layer, the first electrode layer includes an electrode layer body, a first connecting portion and a second connecting portion, the electrode layer body is a plate-like structure perpendicular to the first direction, the first connecting portion and the second connecting portion are arranged at intervals along the second direction, the gate structure layer is accommodated between the first connecting portion and the second connecting portion, a portion of the first connecting portion is conductively connected to the Schottky contact layer, another portion of the first connecting portion is conductively connected to the first doped region and forms an ohmic contact, and the second connecting portion is conductively connected to the second conductive structure region.

[0015] The integrated power field effect transistor of the present application includes a gate structure layer, a conductive structure layer, an epitaxial layer and a substrate layer stacked along a first direction, the conductive structure layer includes a first conductive structure region, a JFET region and a second conductive structure region, the JFET region is arranged in the first conductive structure region and the second conductive structure region in the second direction, wherein the surface of the first conductive structure region has a Schottky contact layer, and the first conductive structure region is made of a semiconductor material of the second conductive type, which can form a unipolar device together with the Schottky contact layer, thereby alleviating the bipolar degradation effect and improving the overall power density of the integrated power field effect transistor; and between the Schottky contact layer and the JFET region, the first conductive structure region also has a first channel region, the first channel region can form a potential barrier between the Schottky contact layer and the JFET region, when the device as a whole is in a forward conduction or blocking state, the existence of the potential barrier can reduce the leakage current, thereby ensuring the overall reliability of the integrated power field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 It is a schematic diagram of the overall structure of the integrated power field effect transistor according to an embodiment of the present application;

[0018] Figure 2 A schematic diagram of different structural regions of an integrated power field effect transistor according to an embodiment of the present application;

[0019] Figure 3 An equivalent circuit diagram of an integrated power field effect transistor according to an embodiment of the present application;

[0020] Figure 4 A test circuit diagram for testing the integrated power field effect transistor of an embodiment of the present application;

[0021] Figure 5 A reverse recovery characteristic curve diagram of the integrated power field effect transistor of an embodiment of the present application;

[0022] Figure 6 It is a third quadrant conduction characteristic curve diagram of the integrated power field effect transistor according to an embodiment of the present application.

[0023] Description of Figure Numbers:

[0024] 10. Gate structure layer; 11. First gate; 12. Second gate; 20. Conductive structure layer; 21. First conductive structure region; 211. First channel region; 212. Schottky contact layer; 213. First well region; 214. First doped region; 22. JFET region; 23. Second conductive structure region; 231. Second well region; 232. Second channel region; 233. Second doped region; 234. Third doped region; 30. Epitaxial layer; 40. Substrate layer; 50. First electrode layer; 51. Electrode layer body; 52. First connecting portion; 53. Second connecting portion; 60. Second electrode layer;

[0025] 100, body diode area; 200, SSBR area; 300, conventional MOSFET area;

[0026] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0027] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0028] In SiC MOSFET devices, due to their own structure, there is a natural body diode, the reverse conduction voltage of the body diode is about 2.7V, which is much larger than that of SiC MOSFET, and when SiC MOSFET works in the third quadrant, the reverse recovery current and reverse recovery charge of the body diode will be larger, resulting in greater power consumption during the dead time. In addition, the presence of the body diode will cause crystal defects in the device, resulting in a bipolar degradation effect, which will also increase additional power consumption after long-term use.

[0029] In the current solution, the bipolar degradation effect is usually alleviated by integrating SBD (Schottky Barrier Diode) structure or LBD (Low Barrier Diode) devices in the integrated SiC MOSFET. However, the SiC MOSFET power device with integrated SBD structure has a lower on-voltage and a larger leakage current, which will cause short-circuit failure and avalanche failure, affecting the overall reliability; while the SiC MOSFET power device with integrated LBD device has a higher on-voltage and a larger reverse recovery current, resulting in a lower power density of the device.

[0030] In order to solve the comprehensive problems arising from the above-mentioned solutions, an integrated power field effect transistor is provided in an embodiment of the present application, which can reduce the influence of the internal body diode and has high power density and reliability. The following is a detailed description of the integrated power field effect transistor in the embodiment of the present application.

[0031] like Figures 1 to 6 As shown, an embodiment of the present application provides an integrated power field effect transistor, which includes a gate structure layer 10, a conductive structure layer 20, an epitaxial layer 30 and a substrate layer 40 stacked along a first direction X, the conductive structure layer 20 includes a first conductive structure area 21, a JFET area 22 and a second conductive structure area 23, the JFET area 22 is arranged between the first conductive structure area 21 and the second conductive structure area 23 in the second direction Y, the first conductive structure area 21 has a first channel area 211 and a Schottky contact layer 212, the Schottky contact layer 212, the first channel area 211 and the JFET area 22 are connected in sequence in the second direction Y, and the Schottky contact layer 212 is arranged on the surface of the first conductive structure area 21 close to the gate structure layer 10; wherein the substrate layer 40, the epitaxial layer 30 and the JFET area 22 have a first conductivity type, the first conductive structure area 21 has a second conductivity type, and the second conductive structure area 23 has a first conductivity type and a second conductivity type.

[0032] Among them, in the embodiment of the present application, the first conductivity type is N-type, that is, the epitaxial layer 30, the substrate layer 40 and the JFET region 22 are all formed of N-type semiconductor materials, and the second conductivity type is P-type, that is, the first conductive structure region 21 is formed of P-type semiconductor materials, and the second conductive structure region 23 has both N-type semiconductor regions and P-type semiconductor regions. It should be noted that the first conductivity type can also be set to P-type and the second conductivity type can be set to N-type.

[0033] In a specific implementation, the integrated power field effect transistor further includes a first electrode layer 50 and a second electrode layer 60. The first electrode layer 50 is disposed on one side of the gate structure layer 10 as the source of the integrated power field effect transistor, and the second electrode layer 60 is disposed on one side of the substrate layer 40 as the drain of the integrated power field effect transistor. When a forward voltage is applied to the gate structure layer 10, a channel is formed in the first channel region 211 of the first conductive structure region 21. At this time, the voltage difference between the first electrode layer 50 and the second electrode layer 60 can drive the current from the second electrode layer 60 to sequentially pass through the substrate layer 40, the epitaxial layer 30, the JFET region 22, the first channel region 211 and the Schottky contact layer 212 to the first electrode layer 50.

[0034] In the embodiment of the present application, the integrated power field effect transistor includes a gate structure layer 10, a conductive structure layer 20, an epitaxial layer 30 and a substrate layer 40 stacked along a first direction X, the conductive structure layer 20 includes a first conductive structure region 21, a JFET region 22 and a second conductive structure region 23, the JFET region 22 is arranged in the first conductive structure region 21 and the second conductive structure region 23 in the second direction Y, wherein the surface of the first conductive structure region 21 has a Schottky contact layer 212, and the first conductive structure region 21 is made of a semiconductor material of the second conductivity type, It can form a unipolar device together with the Schottky contact layer 212, thereby alleviating the bipolar degradation effect and improving the overall power density of the integrated power field effect transistor; and between the Schottky contact layer 212 and the JFET region 22, the first conductive structure region 21 also has a first channel region 211, and the first channel region 211 can form a potential barrier between the Schottky contact layer 212 and the JFET region 22. When the device as a whole is in a forward conduction or blocking state, the existence of the potential barrier can reduce the leakage current, thereby ensuring the overall reliability of the integrated power field effect transistor.

[0035] The integrated power field effect transistor of the embodiment of the present application, wherein the first conductive structure region 21 also includes a first well region 213 and a first doping region 214, the first channel region 211 and the first doping region 214 are arranged at intervals along the second direction Y, at least part of the first well region 213 is connected between the conductive structure region and the first doping region 214, and the Schottky contact layer 212 is connected to and covers the surface of the first well region 213 close to the gate structure layer 10.

[0036] In a specific implementation, the first doped region 214 and the first channel region 211 of the first conductive structure region 21 are both arranged on the side of the first conductive structure region 21 close to the gate structure layer 10, so that both can form contact with the first electrode layer 50 or the gate structure layer 10; and at least part of the first well region 213 is provided between the first doped region 214 and the first channel region 211, so at least part of the first well region 213 is also provided on the side of the first conductive structure region 21 close to the gate structure layer 10, and forms a Schottky contact with the first electrode layer 50 through the Schottky contact layer 212 covering its surface, so that the overall forward voltage drop of the device is lower, the switching speed is faster, and the response speed is higher.

[0037] The integrated power field effect transistor of the embodiment of the present application, wherein the gate structure layer 10 includes a first gate 11, the first gate 11 is conductively connected to the JFET region 22 and the first channel region 211, and a portion of the Schottky contact layer 212 is arranged on the surface of the first channel region 211 close to the gate structure layer 10 and is conductively connected to the first gate 11.

[0038] In a specific implementation, part of the Schottky contact layer 212 is connected to the first channel region 211, and the other part of the Schottky contact layer 212 is conductively connected to the first well region 213. Since the first channel region 211 and the first well region 213 are both of the first conductivity type, they can form a unipolar structure with the Schottky contact layer 212. In the unipolar structure, there is no storage effect of carriers, and only electrons work, which can have a faster reverse recovery speed, thereby avoiding the occurrence of bipolar degradation effects, and further avoiding the increase in the overall on-resistance of the device and the increase in forward voltage caused by the bipolar degradation phenomenon.

[0039] The first gate 11 is arranged correspondingly to the JFET region 22 and the first channel region 211 and is conductively connected to each other. When a forward voltage is applied to the first gate 11, a channel that connects the JFET region 22 and the first well region 213 can be formed in the first channel region 211, thereby realizing the opening of the first conductive structure region 21.

[0040] Relative to the first conductive structure region 21, the gate structure layer 10 only covers the first channel region 211 to control the formation of a channel in the first channel region 211, and the gate structure layer 10 is staggered with the first well region 213 in the second direction Y and does not cover the surface of the first well region 213, so that the first well region 213 can cover the Schottky contact layer 212, and the first well region 213 is conductively connected to the first electrode layer 50 through the Schottky contact layer 212, thereby forming a SSBR structure (Super SchottkyBarrier Rectifier).

[0041] The integrated power field effect transistor of the embodiment of the present application, wherein the second conductive structure region 23 includes a second well region 231, a second channel region 232, a second doping region 233 and a third doping region 234. In the conductive structure layer 20, the second channel region 232, the second doping region 233 and the third doping region 234 are all arranged on a side close to the gate structure layer 10, the second well region 231 is arranged on a side close to the epitaxial layer 30, and the second channel region 232, the second doping region 233 and the third doping region 234 are arranged in sequence along the second direction Y; wherein the second doping region 233 is of the first conductive type, and the second channel region 232, the third doping region 234 and the second well region 231 are all of the second conductive type.

[0042] In a specific implementation, the conductivity type of the second doping region 233 is N-type, the conductivity types of the second well region 231, the second channel region 232 and the third doping region 234 are all P-type, and the second channel region 232, the second doping region 233 and the third doping region 234 are all arranged on a side close to the gate structure layer 10, and the second well region 231 is arranged on a side close to the epitaxial layer 30, so that a conventional MOSFET structure is formed in the second conductive structure region 23.

[0043] like Figure 2 and Figure 3 As shown, in the integrated power field effect transistor of the embodiment of the present application, by combining the first conductive structure region 21 and the second conductive structure region 23 in the conductive structure layer 20, a structure as shown in FIG. Figure 2 The composite structure of the body diode region 100, the SSBR region 200 and the conventional MOSFET region 300 is shown. Figure 3 In the equivalent circuit diagram shown, the body diode formed by the body diode region 100, the SSBR structure formed by the SSBR region 200, and the conventional MOSFET structure formed by the conventional MOSFET region 300 can be connected in parallel between the source and the drain. By setting the SSBR structure, the body diode can be short-circuited, thereby reducing the influence of the body diode on the circuit conduction.

[0044] When performing a reverse recovery characteristic test on the integrated power field effect transistor of the embodiment of the present application, it is necessary to use the following Figure 4 The test circuit shown, in the test circuit, the MOSFET of the embodiment of the present application is connected in parallel with the inductor, and is connected in series with the conventional MOSFET used for testing between the DC power supply and the ground, the pulse component and the gate resistor are connected in series between the conventional MOSFET and the DC power supply, wherein the conventional MOSFET is a low-side MOSFET, and the MOSFET in the embodiment of the present application is a high-side MOSFET.

[0045] When testing, the first pulse of the pulse device is turned on, and the current flows through the gate resistor of the load and then flows through the low-side MOSFET. After the first pulse ends, the low-side MOSFET is turned off, and the current is turned on at the diode of the high-side MOSFET to form a freewheeling loop; after the second pulse is turned on, the current flows through the freewheeling diode, and reverse recovery occurs. By testing the reverse recovery process of the diode of the high-side MOSFET, the following can be obtained: Figure 5 The reverse recovery characteristic curve in.

[0046] Figure 5 The reverse recovery characteristic curve of the conventional MOSFET and the reverse recovery characteristic curve of the MOSFET with SSBR structure in the embodiment of the present application are included in the test of both. Figure 4 The test circuit and test method are the same. Figure 5 As shown, the reverse recovery time of the two is the same, but the maximum reverse recovery current of the traditional MOSFET is 129A, and the maximum reverse recovery current of the MOSFET with the SSBR structure in the embodiment of the present application is 28A, which is much smaller than the maximum reverse recovery current of the traditional MOSFET. Therefore, the reverse recovery characteristic of the MOSFET with the SSBR structure is better, its power consumption when working in the third quadrant is lower, and the power density of the overall device is higher.

[0047] In the integrated power field effect transistor of the embodiment of the present application, the first channel region 211 has a channel length L in the second direction Y, and the channel length L has a value range of: 0.3 μm≤L≤1 μm.

[0048] In specific implementation, the channel length L of the first channel region 211 ranges from 0.3μm to 1μm. Within this range, the channel length L is up to 1μm, which can ensure that the on-state voltage drop of the device is less than 2.7V and is easier to form a current path, thereby ensuring that the device has a higher switching speed and lower power consumption.

[0049] exist Figure 6 The static simulation diagram of the integrated power field effect transistor working in the third quadrant is shown in FIG. The three line segments respectively show the on-state voltage drop of the traditional MOSFET structure, the on-state voltage drop of the MOSFET structure in the embodiment of the present application when the channel length L is 0.3 μm, and the on-state voltage drop of the MOSFET structure in the embodiment of the present application when the channel length L is 0.5 μm. Figure 6It can be seen that the conventional MOSFET structure has the largest on-state voltage drop of 2.7 V; the MOSFET structure of the present application with a channel length L of 0.5 μm has a smaller on-state voltage drop of 1.8 V; the MOSFET structure of the present application with a channel length L of 0.3 μm has the smallest on-state voltage drop of 1.4 V. Therefore, setting the channel length L to 0.3 μm can make the on-state voltage drop in the third quadrant reach about 50% of that of the conventional MOSFET structure.

[0050] In the integrated power field effect transistor of the embodiment of the present application, the doping concentration of the first doping region 214 is higher than the doping concentration of the first well region 213 , and the doping concentration of the first channel region 211 is lower than the doping concentration of the first well region 213 .

[0051] The doping concentration of the first doping region 214 is set to a heavy doping concentration. When the first electrode layer 50 contacts the first doping region 214 of the metal structure, the requirement of low contact resistance can be met, thereby forming an ohmic contact, so that the energy loss is small when the current passes through the ohmic contact position, and the overall efficiency of the device is higher.

[0052] Optionally, the doping concentration of the first channel region 211 may be the same as the doping concentration of the first well region 213 , which can also achieve the effect of the SSBR structure on the MOSFET and ensure the power density and reliability of the MOSFET.

[0053] like Figure 1 As shown, the integrated power field effect transistor of the embodiment of the present application, wherein along the first direction X, the width of the first channel region 211 is smaller than the width of the first well region 213 , and the width of the first doped region 214 is the same as the width of the first well region 213 .

[0054] Setting the width of the first doped region 214 to be the same as the width of the first well region 213 can improve the overall robustness of the integrated power field effect transistor, that is, can ensure the stable operation of the device.

[0055] Optionally, the width of the first doped region 214 may be smaller than the width of the first well region 213 , which can also achieve the effect of the SSBR structure on the MOSFET and ensure the power density and reliability of the MOSFET.

[0056] like Figure 1 As shown, in the integrated power field effect transistor of the embodiment of the present application, the gate structure layer 10 further includes a second gate 12 , and the second gate 12 is conductively connected to the JFET region 22 , the second channel region 232 and the second doping region 233 .

[0057] In a specific implementation, the second gate 12 is conductively connected to the JFET region 22 , the second channel region 232 and the second doping region 233 . When a forward voltage is applied to the second gate 12 , a channel that connects the JFET region 22 and the second doping region 233 can be formed in the second channel region 232 , thereby realizing the opening of the second conductive structure region 23 .

[0058] Specifically, the portion of the gate structure layer 10 corresponding to the second gate 12 covers the surface of part of the JFET region 22, the surface of the second channel region 232 and the surface of part of the second doping region 233 to achieve conductive connection with the JFET region 22, the second channel region 232 and the second doping region 233, so that when the second gate 12 is turned on, a complete current path is formed between the JFET region 22, the second channel region 232 and the second doping region 233.

[0059] like Figure 1 As shown, in the integrated power field effect transistor of the embodiment of the present application, the doping concentrations of the second doping region 233 and the third doping region 234 are both higher than the second well region 231 , and the doping concentration of the second channel region 232 is lower than the second well region 231 .

[0060] In specific implementation, the doping concentration of the second doping region 233 is relatively high, and an N+ region can be formed, with the P- region of the second channel region 232 and the P+ region of the third doping region 234 on both sides thereof. The above second doping region 233, the second channel region 232 and the third doping region 234 are all formed in the P-type region of the second well region 231, thereby forming a traditional MOSFET structure.

[0061] Optionally, the doping concentration of the second channel region 232 may be the same as the doping concentration of the second well region 231 , and a conventional MOSFET structure can also be formed.

[0062] Specifically, the width of the third doped region 234 in the first direction X is the same as the overall width of the second conductive structure region 23 , and its larger width can improve the overall robustness of the integrated power field effect transistor, that is, can ensure the stable operation of the device.

[0063] Furthermore, at the third doping region 234 , there is also a body diode in the integrated power field effect transistor. However, under the effect of the SSBR structure in the embodiment of the present application, the bipolar degradation phenomenon caused by the body diode here can also be alleviated.

[0064] like Figure 1As shown, an integrated power field effect transistor of an embodiment of the present application, wherein the first electrode layer 50 includes an electrode layer body 51, a first connecting portion 52 and a second connecting portion 53, the electrode layer body 51 is a plate-like structure perpendicular to the first direction X, the first connecting portion 52 and the second connecting portion 53 are arranged at intervals along the second direction Y, the gate structure layer 10 is accommodated between the first connecting portion 52 and the second connecting portion 53, a portion of the first connecting portion 52 is conductively connected to the Schottky contact layer 212, another portion of the first connecting portion 52 is conductively connected to the first doping region 214 and forms an ohmic contact, and the second connecting portion 53 is conductively connected to the second conductive structure region 23.

[0065] In a specific implementation, the first connection portion 52 and the second connection portion 53 of the first electrode layer 50 can respectively connect the first conductive structure area 21 and the second conductive structure area 23 to the electrode layer body 51, thereby forming a Figure 3 The SSBR structure shown is connected in parallel with the MOSFET structure, thereby reducing the impact of the body diode on the overall device and alleviating the bipolar degradation phenomenon.

[0066] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0067] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. An integrated power field effect transistor, characterized in that: It comprises a gate structure layer, a conductive structure layer, an epitaxial layer and a substrate layer stacked along a first direction, the conductive structure layer comprises a first conductive structure region, a JFET region and a second conductive structure region, the JFET region is arranged between the first conductive structure region and the second conductive structure region in the second direction, the first conductive structure region has a first channel region and a Schottky contact layer, the Schottky contact layer, the first channel region and the JFET region are connected in sequence in the second direction, and the Schottky contact layer is arranged on a surface of the first conductive structure region close to the gate structure layer; The substrate layer, the epitaxial layer and the JFET region have a first conductivity type, the first conductive structure region has a second conductivity type, and the second conductive structure region has a first conductivity type and a second conductivity type.

2. The integrated power field effect transistor according to claim 1, characterized in that: The first conductive structure region also includes a first well region and a first doped region. The first channel region and the first doped region are arranged at intervals along the second direction. At least part of the first well region is connected between the conductive structure region and the first doped region. The Schottky contact layer is connected to and covers the surface of the first well region close to the gate structure layer.

3. The integrated power field effect transistor according to claim 1, characterized in that: The gate structure layer includes a first gate, which is conductively connected to both the JFET region and the first channel region. Part of the Schottky contact layer is disposed on a surface of the first channel region close to the gate structure layer and conductively connected to the first gate.

4. The integrated power field effect transistor according to claim 3, characterized in that: The first channel region has a channel length L in the second direction, and the channel length L has a value range of: 0.3 μm≤L≤1 μm.

5. The integrated power field effect transistor according to claim 2, characterized in that: The doping concentration of the first doping region is higher than the doping concentration of the first well region, and the doping concentration of the first channel region is lower than the doping concentration of the first well region.

6. The integrated power field effect transistor according to claim 2, characterized in that: Along the first direction, the width of the first channel region is smaller than the width of the first well region, and the width of the first doping region is the same as the width of the first well region.

7. The integrated power field effect transistor according to claim 1, characterized in that: The second conductive structure region includes a second well region, a second channel region, a second doping region and a third doping region. In the conductive structure layer, the second channel region, the second doping region and the third doping region are all arranged on a side close to the gate structure layer, the second well region is arranged on a side close to the epitaxial layer, and the second channel region, the second doping region and the third doping region are arranged in sequence along the second direction; The second doping region is of the first conductivity type, and the second channel region, the third doping region and the second well region are all of the second conductivity type.

8. The integrated power field effect transistor according to claim 7, characterized in that: The gate structure layer further includes a second gate, and the second gate is conductively connected to the JFET region, the second channel region, and the second doping region.

9. The integrated power field effect transistor according to claim 7, characterized in that: The doping concentrations of the second doping region and the third doping region are both higher than that of the second well region, and the doping concentration of the second channel region is lower than that of the second well region.

10. The integrated power field effect transistor according to claim 2, characterized in that: The integrated power field effect transistor also includes a first electrode layer, which includes an electrode layer body, a first connecting portion and a second connecting portion. The electrode layer body is a plate-like structure perpendicular to the first direction, and the first connecting portion and the second connecting portion are arranged at intervals along the second direction. The gate structure layer is accommodated between the first connecting portion and the second connecting portion. A portion of the first connecting portion is conductively connected to the Schottky contact layer, and another portion of the first connecting portion is conductively connected to the first doped region and forms an ohmic contact. The second connecting portion is conductively connected to the second conductive structure region.

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