Electrostatic discharge protection device with low capacitance

Abstract

The invention relates to an electrostatic discharge protection device with low capacitance. A diode for an ESD protection device is described. The diode has a low capacitance. In an example, a semiconductor device (100) includes: a substrate; an n-type epitaxial layer (110) on the n-type substrate in a first region of the n-type substrate; and a p-type epitaxial layer (115) on the n-type epitaxial layer, with an interface (111) between the n-type epitaxial layer and the p-type epitaxial layer. The p-type epitaxial layer (115) has a first concentration of p-type dopant throughout the p-type epitaxial layer. Moreover, the semiconductor device (100) comprises: a p-type dopant profile across the interface (111), the p-type dopant profile having a first peak concentration of p-type dopant greater than the first concentration; and an n-type dopant profile across the interface (111), the n-type dopant profile having a second peak concentration of n-type dopant. The second peak concentration is substantially the same as the first peak concentration.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and more particularly to low capacitance electrostatic discharge (ESD) diodes. Background Art

[0002] Integrated circuits (ICs) can be subjected to ESD events, which typically occur when the IC is in contact with or close to another object. An ESD protection device can be coupled to the IC to provide a current path to protect the IC during an ESD event. The ESD protection device will need to be able to safely dissipate high currents without causing damage. During normal operation of the IC, the ESD protection device is inactive so as not to interfere with normal operation. Although the ESD protection device is inactive (e.g., a diode under reverse bias conditions), its presence tends to increase the parasitic capacitance of the IC. The ESD protection device will need to have a low capacitance. Summary of the invention

[0003] The present disclosure describes an ESD protection device including a diode with low capacitance. This summary is not an exhaustive overview of the present disclosure. Instead, the main purpose of the summary is to present some concepts of the present disclosure in a simplified form as a prelude to a more detailed description that is presented later.

[0004] In some examples, a semiconductor device includes: an n-type substrate; an n-type epitaxial layer on the n-type substrate in a first region of the n-type substrate; a p-type epitaxial layer on the n-type epitaxial layer, the n-type epitaxial layer and the p-type epitaxial layer having an interface therebetween, the p-type epitaxial layer having a first concentration of a p-type dopant throughout the p-type epitaxial layer; a p-type dopant distribution across the interface, the p-type dopant distribution having a first peak concentration of the p-type dopant greater than the first concentration; and an n-type dopant distribution across the interface, the n-type dopant distribution having a second peak concentration of the n-type dopant, the second peak concentration being substantially the same as the first peak concentration.

[0005] In some examples, a method includes growing an n-type epitaxial layer on an n-type substrate. The method also includes implanting a p-type dopant in a second region of the n-type epitaxial layer. The method also includes implanting an n-type dopant in a first region of the n-type epitaxial layer that is different from the second region. The method also includes: growing a p-type epitaxial layer on the n-type substrate so that an interface is formed between the n-type epitaxial layer and the p-type epitaxial layer in the first region, wherein: the p-type epitaxial layer in the first region contains a first concentration of p-type dopant throughout the p-type epitaxial layer; a p-type dopant distribution is formed across the interface due to growing the p-type epitaxial layer, the p-type dopant distribution has a first peak concentration of p-type dopant greater than the first concentration; and an n-type dopant distribution is formed across the interface due to implanting the n-type dopant and growing the p-type epitaxial layer, the n-type dopant distribution has a second peak concentration of n-type dopant, the second peak concentration being substantially the same as the first peak concentration.

[0006] In some instances, a semiconductor device includes: a substrate of a first conductivity type; a first epitaxial layer of the first conductivity type, which is located on the substrate in a first region of the substrate; a second epitaxial layer of the second conductivity type, which is on the first epitaxial layer, having an interface between the first epitaxial layer and the second epitaxial layer, the second epitaxial layer having a first concentration of a dopant of the second conductivity type throughout the second epitaxial layer; a first dopant distribution of the second conductivity type dopant across the interface, the first dopant distribution having a first peak concentration of the second conductivity type dopant greater than the first concentration; and a second dopant distribution of the first conductivity type dopant across the interface, the second dopant distribution having a second peak concentration of the first conductivity type dopant, the second peak concentration being substantially the same as the first peak concentration. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a semiconductor device in the described example;

[0008] Figure 2 is a detailed view of a dopant profile of a semiconductor device in the described example; and

[0009] Figures 3A to 3F The process steps for manufacturing a semiconductor device in the described example are shown. DETAILED DESCRIPTION

[0010] The present disclosure is described with reference to the accompanying drawings. The components in the figures are not drawn to scale. In fact, the emphasis is on clearly illustrating the overall features and principles of the present disclosure. Many specific details and relationships are set forth with reference to the examples of the figures to provide an understanding of the present disclosure. The figures and examples are not intended to limit the scope of the present disclosure to such examples, but other examples are possible by means of interchange or modification of at least some of the described or illustrated elements. In addition, where the elements of the present disclosure may be partially or completely implemented using known components, certain parts of such components that promote an understanding of the present disclosure are described, and detailed descriptions of other parts of such components are omitted to avoid confusing the present disclosure.

[0011] As used herein, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms in the description and claims are not necessarily intended to indicate the time or other priority ordering of such elements. In addition, considering the orientation shown in the figures, terms such as "front", "back", "top", "bottom", "above", "below", "vertical", "horizontal", "lateral", "downward", "upward", "upper", "lower" are used to refer to the relative direction or position of features in the semiconductor device. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than other features. The terms used in this way are interchangeable in appropriate circumstances, so that examples of the technology described herein can, for example, operate in other orientations compared to those shown or otherwise described herein. In the following discussion and claims, the terms "including", "includes", "having", "has", "with" or variations thereof are intended to be inclusive in a manner similar to the term "comprising", and should therefore be interpreted as meaning "including but not limited to". Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0012] Various structures disclosed herein can be formed using semiconductor processing techniques. Layers comprising a variety of materials can be formed on a substrate (e.g., a semiconductor wafer), for example, using deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating), thermal processing techniques (e.g., oxidation, nitridation, epitaxy), and / or other suitable techniques. Similarly, portions of a layer can be selectively removed, for example, using etching techniques (e.g., plasma (or dry) etching, wet etching), chemical mechanical planarization, and / or other suitable techniques, some of which can be combined with photolithography steps. The conductivity (or resistivity) of a substrate (or a region of a substrate) can be controlled by doping techniques using various chemical species (which can also be referred to as dopants, dopant atoms, etc.), including but not limited to boron, gallium, indium, arsenic, phosphorus, or antimony. Doping can be performed during the initial formation or growth of a substrate (or an epitaxial layer grown on a substrate) by ion implantation or other suitable doping techniques.

[0013] Diodes are used in a variety of ESD protection devices. A silicon controlled rectifier (SCR) or bipolar avalanche associated with one or more pn junctions provides a low resistance current-voltage (IV) characteristic suitable for ESD protection. For example, a bidirectional ESD protection device includes a diode (e.g., D2) coupled to another diode (e.g., D1). Figure 1 ) combined back-to-back diodes (e.g., D1-Z1 diodes with a common anode, such as Figure 1 ). As described in more detail herein, the D2 diode may be configured to have a relatively low capacitance by forming its pn junction at an interface between a lightly doped p-type layer (e.g., p-type epitaxial layer 115) and a lightly doped n-type layer (e.g., n-type epitaxial layer 110) so as to reduce the parasitic capacitance of the bidirectional ESD protection device.

[0014] In some examples, prior to forming a lightly doped p-type layer on the lightly doped n-type layer, certain regions of the lightly doped n-type layer may be doped (e.g., implanted) to include a relatively high concentration of a dopant (e.g., a p-type dopant such as boron). When the lightly doped p-type layer is formed (e.g., epitaxially grown) on the lightly doped n-type layer, dopants present in the lightly doped n-type layer (e.g., implanted boron) may outgas from the lightly doped n-type layer into the processing chamber and then subsequently deposit in other regions of the lightly doped n-type layer. This phenomenon may be referred to as "auto-doping."

[0015] Due to the incorporation of undesirable dopants at the interface (e.g., the pn junction of the D2 diode) during at least the initial stages of forming the lightly doped p-type layer, the dopant concentration (e.g., boron concentration) may increase at or near the interface between the lightly doped p-type layer and the lightly doped n-type layer. Such an increase in dopant concentration causes an increase in the capacitance (e.g., junction capacitance) of the D2 diode because the increase in dopant concentration reduces the width of the depletion layer formed across the interface (which may be referred to as the metallurgical junction of the pn junction). In some instances, autodoping may increase the junction capacitance to two times (2 times) or more of the expected capacitance in the absence of the autodoping effect. In some instances, the processing temperature for forming the lightly doped p-type layer may be decreased to reduce outgassing so that autodoping may be reduced. Although such a reduction in processing temperature may facilitate achieving the expected capacitance of the D2 diode, another device parameter of the bidirectional ESD protection device may be reduced, such as the holding voltage (V HOLD ), breakdown voltage (V BR ) and others.

[0016] The present disclosure describes methods for compensating (or reducing) undesirable effects of auto-doping (e.g., increased capacitance) and semiconductor devices manufactured based on the methods. In some examples, blanket implantation of dopants may be performed to introduce dopants at or near the surface of a lightly doped n-type layer. The implanted dopants have a conductivity type opposite to that of the dopants that cause the auto-doping effect. For example, considering a p-type dopant (e.g., boron) that can auto-dope the surface of a lightly doped n-type layer, an n-type dopant (e.g., phosphorus, arsenic) may be implanted into the lightly doped n-type layer. In this way, the increased boron concentration at the interface between the n-type lightly doped layer and the p-type lightly doped layer may be compensated (e.g., at least partially offset) by the implanted phosphorus / arsenic concentration. Therefore, the depletion layer across the metallurgical junction may have a width consistent with the designed processing conditions (e.g., the dopant concentration in the n-type lightly doped layer and the p-type lightly doped layer without auto-doping) to provide the desired junction capacitance, thereby alleviating undesirable effects of auto-doping, such as increased junction capacitance values.

[0017] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 in the described example. The semiconductor device 100 includes an n-type substrate 105. The substrate 105 may be, for example, a portion of a bulk silicon wafer. The dynamic resistance of the semiconductor device 100 may be primarily determined by the dopant density in the substrate 105 (or the resistivity of the substrate 105). The n-type substrate 105 may have a resistivity greater than 1×10 18 cm -3 In some examples, the n-type substrate 105 may have an average dopant density exceeding 4×10 19 cm -3 The average dopant density.

[0018] Semiconductor device 100 includes a lightly doped n-type layer 110 disposed on substrate 105. In some examples, n-type layer 110 can be crystalline silicon doped with phosphorus. n-type layer 110 can be 1 micrometer (μm) to 10 micrometers thick. In some examples, n-type layer 110 has a thickness of less than 1×10 16 cm -3 In some examples, the n-type layer 110 may have an average dopant density greater than 1×10 16 cm -3 ,like Figure 2 105 (e.g., including dopants diffused from substrate 105 and / or dopants incorporated during formation of n-type layer 110), but less than the average dopant density of substrate 105. N-type layer 110 may be an epitaxial layer formed on substrate 105. Thus, n-type layer 110 may be referred to as an n-type epitaxial layer, an n-type epi-layer, an n-epi layer, etc.

[0019] Semiconductor device 100 includes a lightly doped p-type layer 115 disposed on or above n-type layer 110. In some examples, p-type layer 115 may be crystalline silicon doped with boron. P-type layer 115 may be 3 microns to 8 microns thick. In some examples, p-type layer 115 may have a thickness of approximately 1×10 15 cm -3 In some examples, the p-type layer 115 may have an average dopant density between 1×10 13 cm -3 With 1×10 16 cm -3 The p-type layer 115 may be an epitaxial layer formed on the n-type layer 110. Thus, the p-type layer 115 may be referred to as a p-type epitaxial layer, a p-type epi-layer, a p-epi layer, etc. The p-type layer 115 has a surface (e.g., a top surface) 116.

[0020] The semiconductor device 100 includes a first region 120 where a diode is located. Figure 1 As indicated in FIG. 1 , the diode in the first region 120 may be referred to as a D2 diode, which includes a pn junction formed at an interface 111 between the n-epi layer 110 and the p-epi layer 115. The semiconductor device 100 also includes a second region 125 where two diodes are located, the diodes being connected back-to-back in a series configuration. Figure 1, the diodes in the second region 125 may be referred to as the D1 diode and the Z1 diode. The D1 diode includes a pn junction formed at an interface 138 between the n-type region 135 and the p-type epi layer 115. The Z1 diode includes a pn junction formed at an interface 131 between the p-type buried layer 130 and the n-type layer 110. The p-type epi layer 115 below the n-type region 135 and the p-type buried layer 130 forms a common anode for the D1 diode and the Z1 diode.

[0021] The semiconductor device 100 includes an isolation structure 140 that laterally surrounds a first region 120 for a D2 diode and a second region 125 for a D1-Z1 diode. In some examples, the isolation structure 140 can be a deep trench isolation structure having a dielectric liner 141 and a trench fill 142. In some examples, the trench fill can be polysilicon (which can also be referred to as polysilicon) on the dielectric liner 141, such as Figure 1 Described in.

[0022] The p-type buried layer 130 is located in the second region 125 (not present in the first region 120 ), and extends from the p-type layer 115 to the n-type layer 110 without penetrating the n-type layer 110 . Figure 1 In FIG. 1 , the original surface of the n-type layer 110 in the second region 125 is depicted in dotted lines within the p-type buried layer 130. The p-type buried layer 130 may have a thickness greater than 1×10 17 cm -3 The p-type buried layer 130 extends laterally across the second region 125, such as Figure 1 Described in.

[0023] The n-type doping region 135 is located in the p-type layer 115 of the second region 125, and the n-type doping region extends to the top surface 116 of the p-type layer 115. The n-type doping region 135 may have a thickness of, for example, 1×10 16 cm -3 to 3×10 19 cm -3 The n-type region 135 may include an inner portion 136 and an outer portion 137, the outer portion having a lower dopant density than the inner portion 136. The lighter doped outer portion 137 contacts the p-type epitaxial layer 115, and the heavier doped inner portion 136 is within the lighter doped outer portion 137. The lighter doped outer portion 137 may have, for example, 1×10 16 cm -3 to 1×10 17 cm -3 The more heavily doped inner portion 136 may have, for example, 1×10 17 cm -3 to 5×10 19cm -3 The average dopant density.

[0024] A p-type doped region 145 is disposed in the p-type epi layer 115 of the first region 120, the p-type doped region extending to the top surface 116 of the p-type epi layer 115. The p-type doped region 145 extends across the first region 120, such as Figure 1 The p-type region 145 may have at least 1×10 17 cm -3 The average dopant density of Z1 diode can be reduced and the desired low resistance contact can be provided for D2 diode. Substrate 105 can form a common cathode for D2 diode and Z1 diode.

[0025] The first terminal 160 of the semiconductor device 100 is electrically connected to the n-type region 135 of the D1 diode and the p-type region 145 of the D2 diode, as shown in FIG. Figure 1 The first terminal 160 may be integrated into the semiconductor device 100, or may be a separate external connection, such as a wire bond or a bump bond. The second terminal 165 is electrically connected to the substrate 105, such as Figure 1 1 , which in some examples may be solder or a conductive die attach material. During operation of the semiconductor device 100, a voltage excursion that is positive on the first terminal 160 relative to the second terminal 165 forward biases the D2 diode, and thus shunts current through the D2 diode. A voltage excursion that is negative on the first terminal 160 relative to the second terminal 165 forward biases the D1 diode and causes a breakdown in the Z1 diode, and thus shunts current through the D1-Z1 diode.

[0026] As described herein, the semiconductor device 100 includes three different pn junctions, namely, the D1 diode has a first pn junction formed at the interface 138, the Z1 diode has a second pn junction formed at the interface 131, and the D2 diode has a third pn junction formed at the interface 111, respectively. The first junction at the interface 138 can be configured to provide a relatively low capacitance for the semiconductor device 100 in view of the lighter doped outer portion 137 in contact with the p-type layer 115. The second junction at the interface 131 can be configured to provide a desired breakdown voltage for the semiconductor device 100 in view of the p-type buried layer 130 in contact with the n-type layer 110. The third pn junction at the interface 111 can be configured to provide a relatively low capacitance for the semiconductor device 100 in view of the lighter doped p-type layer 115 in contact with the n-type layer 110.

[0027] The capacitance of the D2 diode is determined by the dopant density of the n-type layer 110 and the p-type layer 115 at the third pn junction at the interface 111. In some examples, the capacitance of the D2 diode can be comparable to the first pn junction at the interface 138. In some examples, as shown in FIG. Figures 3A to 3C Described in more detail, dopants present in p-type buried layer 130 may outgas (e.g., into an epitaxial processing chamber) during an epitaxial processing step to form p-type layer 115, and then subsequently deposit on n-type layer 110, such that the dopant density at or near interface 111 increases, e.g., “auto-doping” p-type layer 115 and n-type layer 110 at or near interface 111. Auto-doping may adversely increase the capacitance of the D2 diode, as described herein.

[0028] The semiconductor device 100 includes a dopant disposed at or near the interface 111, for example, to mitigate the auto-doping effect. The dopant may be an implanted dopant and have a conductivity type opposite to that of the dopant causing the auto-doping effect. For example, given that a p-type dopant (e.g., boron from the p-type buried layer 130) may auto-dope the p-type layer 115 and the n-type layer 110 at or near the interface 111, an n-type dopant (e.g., phosphorus, arsenic, antimony) may be implanted into the n-type layer 110. In this way, an increased boron concentration at or near the interface 111 between the n-type layer 110 and the p-type layer 115 may be compensated (e.g., at least partially offset) by the implanted phosphorus (or arsenic / antimony) concentration. Thus, the depletion layer across the metallurgical junction may have a width consistent with the processing conditions (e.g., dopant concentrations in the n-type lightly doped layer 110 and the p-type lightly doped layer 115) designed to provide the desired capacitance of the D2 diode. In this way, undesirable increases in junction capacitance due to autodoping may be mitigated. Figure 1 The framed region 170 includes the interface 111 between the n-type layer 110 and the p-type layer 115, and further details of the framed region 170 are referred to in Figure 2 Give a description.

[0029] Figure 2 Detailed view of a dopant profile of a semiconductor device (e.g., semiconductor device 100) in the described example. The dopant profile is taken across line AA extending across framed region 170, which includes portions of p-epi layer 115 and n-epi layer 110. Figure 1 The interface 111 shown in FIG. The substrate 105 may have a thickness greater than 1×10 19 cm -3 As described above. Also, the n-epi layer 110 may have an n-type dopant having a concentration greater than 1×10 16 cm -3 The average concentration of Figure 2 The p-epi layer 115 may have a p-type dopant having a concentration of about 8×10 14 cm -3 The concentration, such as Figure 2 The dopant concentration profile 215 of the p-epi layer 115 shows that the p-type dopant is substantially uniformly distributed throughout the p-epi layer 115, for example, the dopant concentration profile 215 is substantially flat, as shown in FIG. Figure 2 As shown in .

[0030] Figure 2 Also shown is a dopant concentration profile 220 of a p-type dopant. The p-type dopant of the concentration profile 220 may be the result of auto-doping, such as outgassing of boron present in the p-type buried layer 130 in the second region 125 and disposed in the first region 120, as described with reference to FIG. Figure 3C In other words, the p-type dopant of the concentration profile 220 originates from the p-type buried layer 130 in the second region 125 (or the region 378 containing the p-type dopant, as shown in FIG. Figure 3A 111). The p-type dopant profile of concentration profile 220 may span (across) interface 111. In addition, the p-type dopant profile has a peak concentration of p-type dopant greater than the concentration of p-epi layer 115. In some examples, the peak concentration of the p-type dopant may be at least five (5) times that of p-epi layer 115. In some examples, the peak concentration of profile 220 is located at interface 111.

[0031] Figure 2 Also shown is a dopant concentration profile 225 of an n-type dopant (e.g., phosphorus). Dopant concentration profile 225 may include n-type dopants from multiple sources. Dopant concentration profile 225 may include n-type dopants diffused from substrate 105, as depicted by phosphorus concentration profile 225b. Additionally, dopant concentration profile 225 may include n-type dopants implanted into n-epi layer 110, as depicted by phosphorus concentration profile 225a. Implantation may be performed prior to forming (e.g., epitaxially growing) p-epi layer 115 to compensate for auto-doping effects, such as due to the p-type dopant of concentration profile 220. Figure 2 In the exemplary embodiment shown in FIG. 2 , the n-type dopant of concentration profile 225 a corresponds to a concentration of 2×10 12 cm -2 In other examples, arsenic can be implanted at 150 keV at 3×10 12 cm -2 dose implanted.

[0032] The implantation conditions for the concentration profile 225a may vary based on various processing conditions, such as the p-type dopant concentration in region 378, the epitaxial growth processing conditions for the p-epi layer 115, the species to be implanted to form the desired dopant concentration profile 225a to mitigate auto-doping effects, and others. In some examples, phosphorus may be implanted at an implantation energy of approximately between 30 keV and 200 keV at a density of approximately between 1×10 11 cm -2 With 1×10 13 cm -2 Similarly, in some examples, arsenic may be implanted at a dose of approximately between 1×10 11 cm -2 With 1×10 13 cm -2 The dose was implanted between .

[0033] The n-type dopant profile of concentration profile 225a may span (across) interface 111, for example, due to the incorporation of implanted n-type dopants into p-epi layer 115 during p-epi layer formation. The n-type dopant profile of concentration profile 225a may span interface 111, wherein a peak concentration of the n-type dopant is substantially the same as a peak concentration of the p-type dopant profile of concentration profile 220. In this manner, p-type dopants incorporated into first region 120 due to auto-doping may be compensated by the n-type dopant of concentration profile 225a. In some examples, the peak concentration of concentration profile 225a is located at interface 111. Furthermore, at or near interface 111, the peak concentration of concentration profile 225a may be greater than the dopant concentration of n-epi layer 110 in the absence of the n-type dopant of concentration profile 225a, for example, the concentration of the n-type dopant present at or near interface 111.

[0034] FIG. 3A to FIG. 3F Processing steps for fabricating a semiconductor device (eg, semiconductor device 100 ) in the described example are shown. Figure 3A An n-type layer 110 is shown formed on a substrate 105, for example using an epitaxial process. An n-type dopant present in the substrate 105, such as phosphorus (or possibly arsenic or antimony), may diffuse into the n-type layer 110 during the epitaxial process, as shown. Figure 2 2 (eg, dopant concentration profile 225 b ). Additional n-type dopants, such as phosphorus and / or arsenic, may be introduced into the n-type layer 110 (eg, in-situ doped n-type layer 110 ) during the epitaxial process.

[0035] Figure 3AIt is also shown that a pad oxide layer 372 may be formed on the n-type layer 110. The pad oxide layer 372 may be formed by thermal oxidation and may be 5 nanometers to 50 nanometers thick. The pad oxide layer 372 protects the surface of the n-type layer 110 during subsequent processing. A first implant mask 374 is formed over the pad oxide layer 372, which exposes the second region 125 to form the p-type buried layer 130. The first implant mask 374 covers the first region 120 for the D2 diode. The first implant mask 374 may include a photoresist formed by a photolithography process and may include a hard mask material, such as silicon dioxide or silicon nitride. P-type dopants 376, such as boron and possibly gallium or indium, are implanted into the n-type layer 110 in the second region 125 not covered by the first implant mask 374 to form a region 378 implanted with p-type dopants 376 in the n-type layer 110 below the pad oxide layer 372. The pad oxide layer 372 can reduce the access of the implanted p-type dopant 376, which can advantageously provide a more reproducible dopant profile in the p-type buried layer 130 and thus provide a more consistent breakdown voltage for the Z1 diode. The p-type dopant 376 can have a 3×10 13 cm -2 or larger doses to provide greater than 1×10 17 cm -3 The peak dopant density.

[0036] Figure 3B The first implant mask 374 is shown removed after the p-type dopant 376 is implanted. Figure 3B Also shown is an n-type dopant 380, such as phosphorus or arsenic (or antimony), implanted into the n-type layer 110 after the first implant mask 374 is removed. The n-type dopant 380 corresponds to the reference Figure 2 The n-type dopant of the dopant concentration profile 225a is depicted (without subsequent diffusion of the implanted n-type dopant). In some examples, implanting the n-type dopant 380 may include implanting the n-type dopant 380 at 80 keV at 3×10 12 cm -2 Phosphorus implanted at a dose of 3×10 12 cm -2 The dose of arsenic implanted is Figure 3B , the implant process may be a blanket implant process without an implant mask. Considering that the dosage of the p-type dopant 376 in the region 378 (corresponding to the p-type buried layer 130) is approximately ten (10) times the dosage of the n-type dopant 380, the n-type dopant 380 implanted in the region 378 may not adversely affect the desired electrical characteristics of the p-type buried layer 130. In some examples, an implant mask may be formed to open the first region 120 (while covering the second region 125) before implanting the n-type dopant 380.

[0037] An annealing process may be performed to activate the implanted p-type dopants 376 and the implanted n-type dopants 380 in the implanted regions 378. The annealing process may be a rapid thermal process, heating the substrate 105 (and the n-type layer 110) to a temperature of 1000° C. to 1050° C. for 20 seconds to 60 seconds for one example, or may be a boiler anneal, heating the substrate 105 and the n-type layer 110 to a temperature of 850° C. to 950° C. for 30 minutes to 120 minutes for another example. The pad oxide layer 372 is then removed, for example, by a dilute buffered aqueous solution of hydrofluoric acid.

[0038] Figure 3C The p-type layer 115 is shown formed on the n-type layer 110, for example, using an epitaxial process. A p-type dopant, such as boron, may be introduced (eg, in-situ doped) into the p-type layer 115 during the epitaxial process to provide approximately 1×10 15 cm -3 During the epitaxial process for forming the p-type layer 115, the p-type dopant of the implanted region 378 diffuses upward into the p-type layer 115 and diffuses downward to extend into the n-type layer 110 to form the p-type buried layer 130. The p-type dopant of the p-type buried layer 130 counter-dopes the portion of the n-type layer 110 in the second region 125. FIG. 3C to FIG. 3F In FIG. 1 , the original surface of the n-type layer 110 is depicted in the p-type buried layer 130 by a dotted line.

[0039] Figure 3C Also shown is a framed region 170, which includes the interface 111, the p-epi layer 115, and a portion of the n-epi layer 110. The dopant profile across line AA passing through the framed region 170 can be compared to the reference Figure 2 In other words, although the dopant profile of the framed region 170 may be slightly different from the reference region 170 immediately after the epitaxial process of growing the p-type layer 115 is completed, the dopant profile of the framed region 170 may be slightly different from the reference region 170. Figure 2 described dopant profiles (e.g., due to additional thermal cycling experienced by the dopant during subsequent processing steps), but reference is made to Figure 2 The general characteristics of the dopant profile described apply to the dopant profile presented across the framed region 170 after the epitaxial process of growing the p-type layer 115 is completed.

[0040] Figure 3D Another pad oxide layer 382 is shown to be formed over the top surface 116 of the p-type layer 115 to protect the p-type layer 115 during subsequent processing. The pad oxide layer 382 may be similar to the reference Figure 3A A second implant mask 384 is formed over the second pad oxide layer 382 to expose an area in the second region 125 to form a reference Figure 1The n-type region 135 is depicted. A second implant mask 384 covers the first region 120 for the D2 diode. The second implant mask 384 may include a photoresist formed by a photolithography process.

[0041] A first set of n-type dopants 386 (e.g., phosphorus, arsenic, or antimony) is implanted into the p-type layer 115 in the areas exposed by the second implant mask 384 to form a first n-type implant region 388 in the p-type layer 115 directly below the pad oxide 382. The first set of n-type dopants 386 may have a density of, for example, 1×10 15 cm -2 to 1×10 16 cm -2 The total dose and energy delivered to an average depth of 50 nm to 200 nm provide a reference Figure 1 The n-type dopant 390 of the more heavily doped inner portion 136 of the n-type region 135 is depicted. A second set of n-type dopants 390 (e.g., phosphorus, arsenic, or antimony) is implanted into the p-type layer 115 in the areas exposed by the second implant mask 384 to form a second n-type implant region 392 in the p-type layer 115 directly below the first n-type implant region 388. The second set of n-type dopants 390 may have, for example, 1×10 13 cm -2 to 1×10 14 cm -2 Total dose and energy of 250keV to 600keV for phosphorus, for example, to provide a reference Figure 1 The n-type dopant of the more lightly doped inner portion 137 of the n-type region 135 is depicted. Subsequently, the second implant mask 384 is removed.

[0042] refer to Figure 3E A third implantation mask 394 is formed on the pad oxide layer 382 to expose the first region 120 for Figure 1 The third implant mask 394 covers the second region 125 for the D1-Z1 diode. The third implant mask 394 may be similar to Figure 3D A set of p-type dopants 396 are implanted into the p-type layer 115 in the areas exposed by the third implant mask 394 to form a p-type implant region 398 in the p-type layer 115 directly below the pad oxide 382. The p-type dopant 396 may have a density of, for example, 1×10 15 cm -2 to 1×10 16 cm -2 Subsequently, the third implant mask 394 is removed. In some examples, a thermal cycle may be performed to activate the dopants in the implant regions 388, 392, and 398, respectively.

[0043] refer to Figure 3F, an isolation structure 140 is formed through the p-type layer 115 and the n-type layer 110, extending into the substrate 105. The isolation structure 140 laterally surrounds the first region 120 for the D2 diode and the second region 125 for the D1-Z1 diode, respectively. The isolation structure 140 can be formed by etching an isolation trench through the p-type layer 115, the n-type layer 110 and into the substrate 105. Subsequently, a dielectric liner 141 is formed on the trench. In some examples, the dielectric liner 141 includes a thermal oxide layer grown on the sidewalls and bottom of the isolation trench.

[0044] Subsequently, trench fill 142 is formed on dielectric liner 141. In some examples, trench fill 142 includes a polysilicon layer formed on dielectric liner 141 extending into the isolation trench. In some examples, polysilicon trench fill 142 may be referred to as a field plate. Polysilicon (and in some cases, dielectric liner 141) may be removed from above top surface 116 of p-type layer 115, for example, by an etch-back process and / or a chemical mechanical polishing (CMP) process, leaving isolation structure 140. In some examples, thermal cycles associated with forming dielectric liner 141 activate and diffuse the dielectric liner 141. Figure 3E The implanted n-type dopants in the first n-type implant region 388 and the second n-type implant region 392 are respectively formed to form the more heavily doped inner portion 136 and the more lightly doped inner portion 137 of the n-type region 135. Furthermore, the thermal cycle activates and diffuses Figure 3E The implanted p-type dopant in the p-type implant region 398 is formed to form the p-type region 145. An optional heat-driven process (eg, a boiler anneal) may be performed before or after the formation of the isolation structure 140 to further diffuse the implanted n-type dopant and the implanted p-type dopant.

[0045] The formation of semiconductor device 100 continues by forming electrical connections to substrate 105, n-type region 135, and p-type region 145 to provide Figure 1 structure.

[0046] The various embodiments described above have been described by way of example only and not limitation. Numerous changes to the embodiments may be made according to the description without departing from the spirit or scope of the description. For example, although the above reference Figures 1 to 3FThe described examples include various semiconductor layers (e.g., n-epi layers, p-epi layers) and doped regions (e.g., n-doped regions, p-doped regions) based on an n-type substrate, but the description is not limited thereto. In some examples, the described semiconductor devices can be manufactured based on a p-type substrate in combination with various doped regions of opposite polarity, such as the exchange of acceptor (p-type) and donor (n-type) dopant atoms. In addition, although in the illustrated embodiments, various features or components have been shown as having a particular arrangement or configuration, other arrangements and configurations are also possible. In addition, aspects of the technology of the present invention described in the context of the example embodiments may also be combined or removed in other embodiments. Therefore, the breadth and scope of the description are not limited by any of the above-described embodiments.

Claims

1. A semiconductor device comprising: n-type substrate; an n-type epitaxial layer located on the n-type substrate in a first region of the n-type substrate; a p-type epitaxial layer on the n-type epitaxial layer, the n-type epitaxial layer and the p-type epitaxial layer having an interface therebetween, the p-type epitaxial layer having a first concentration of a p-type dopant throughout the p-type epitaxial layer; a p-type dopant profile across the interface, the p-type dopant profile having a first peak concentration of the p-type dopant greater than the first concentration; as well as An n-type dopant profile is provided across the interface, the n-type dopant profile having a second peak concentration of the n-type dopant, the second peak concentration being substantially the same as the first peak concentration.

2. The semiconductor device according to claim 1, wherein: The first peak concentration is located at the interface; and The second peak concentration is located at the interface. 3 . The semiconductor device of claim 1 , wherein the first peak concentration is at least five (5) times greater than the first concentration.

4. The semiconductor device according to claim 1, wherein: The n-type epitaxial layer comprises a second concentration of an n-type dopant at the interface; and The second peak concentration is greater than the second concentration. 5 . The semiconductor device of claim 1 , wherein the interface corresponds to a metallurgical junction of a pn diode formed by the n-type epitaxial layer and the p-type epitaxial layer. 6 . The semiconductor device of claim 1 , wherein the p-type epitaxial layer includes a p-type doped region proximate a surface of the p-type epitaxial layer.

7. The semiconductor device according to claim 1, wherein the p-type epitaxial layer is a first portion of the p-type epitaxial layer corresponding to the first region of the n-type substrate, the semiconductor device further comprising: a p-type buried layer partially extending into the n-type epitaxial layer in the second region of the n-type substrate; as well as A second portion of the p-type epitaxial layer is on the p-type buried layer, wherein the second portion of the p-type epitaxial layer includes an n-type doped region proximate to a surface of the second portion of the p-type epitaxial layer.

8. The semiconductor device according to claim 7, wherein: The n-type doped region and the second portion of the p-type epitaxial layer form a first pn diode; and The p-type buried layer and the n-type epitaxial layer form a second pn diode, wherein the second portion of the p-type epitaxial layer and the p-type buried layer form a common anode for the first pn diode and the second pn diode.

9. The semiconductor device according to claim 8, wherein: The n-type epitaxial layer and the first portion of the p-type epitaxial layer form a third pn diode; and The n-type substrate forms a common cathode for the second pn diode and the third pn diode.

10. A method comprising: growing an n-type epitaxial layer on an n-type substrate; implanting a p-type dopant in the second region of the n-type epitaxial layer; implanting an n-type dopant in a first region of the n-type epitaxial layer different from the second region; and A p-type epitaxial layer is grown on the n-type substrate so that an interface is formed between the n-type epitaxial layer and the p-type epitaxial layer in the first region, wherein: The p-type epitaxial layer in the first region includes a first concentration of p-type dopant throughout the p-type epitaxial layer; a p-type dopant profile formed across the interface as a result of growing the p-type epitaxial layer, the p-type dopant profile having a first peak concentration of the p-type dopant greater than the first concentration; and An n-type dopant profile is formed across the interface as a result of implanting the n-type dopant and growing the p-type epitaxial layer, the n-type dopant profile having a second peak concentration of the n-type dopant that is substantially the same as the first peak concentration.

11. The method according to claim 10, wherein: The first peak concentration is located at the interface; and The second peak concentration is located at the interface.

12. The method of claim 10, wherein the first peak concentration is at least five (5) times greater than the first concentration.

13. The method of claim 10, wherein: The n-type epitaxial layer comprises a second concentration of an n-type dopant at the interface; and The second peak concentration is greater than the second concentration. 14 . The method of claim 10 , wherein the interface corresponds to a metallurgical junction of a pn diode formed by the n-type epitaxial layer and the p-type epitaxial layer in the first region.

15. The method of claim 10, wherein the p-type dopant profile formed across the interface originates from the p-type dopant implanted in the second region of the n-type epitaxial layer.

16. A semiconductor device comprising: a substrate of a first conductivity type; A first epitaxial layer of the first conductivity type, located on the substrate in a first region of the substrate; A second epitaxial layer of a second conductivity type, which is on the first epitaxial layer, has an interface between the first epitaxial layer and the second epitaxial layer, and the second epitaxial layer has a first concentration of a dopant of the second conductivity type throughout the second epitaxial layer; a first dopant profile of a second conductivity type dopant across the interface, the first dopant profile having a first peak concentration of the second conductivity type dopant greater than the first concentration; as well as A second dopant profile of the first conductivity type dopant across the interface, the second dopant profile having a second peak concentration of the first conductivity type dopant, the second peak concentration being substantially the same as the first peak concentration.

17. The semiconductor device according to claim 16, wherein: The first peak concentration is located at the interface; and The second peak concentration is located at the interface.

18. The semiconductor device of claim 16, wherein the first peak concentration is at least five (5) times greater than the first concentration.

19. The semiconductor device according to claim 16, wherein: The first epitaxial layer includes a second concentration of the first conductivity type dopant at the interface; and The second peak concentration is greater than the second concentration.

20. The semiconductor device of claim 16, wherein the interface corresponds to a metallurgical junction of a diode formed by the first epitaxial layer and the second epitaxial layer.

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