Image sensing device including test pattern

Abstract

The invention relates to an image sensing device including a test pattern. An image sensing apparatus includes: a plurality of first upper signal lines respectively connected to a plurality of first pixel transistors located in different rows of a pixel array; a first test line commonly connected to the plurality of first upper signal lines; a first test pad configured to provide a first test signal to the first test line; and a first test transistor connected to the first test line and the first test pad. During a test operation, a first test signal is provided to a plurality of first pixel transistors located in different rows of a pixel array through a first test transistor, a first test line, and a plurality of first upper signal lines.

Description

Technical Field

[0001] The technology and implementation disclosed in this patent document generally relate to an image sensing device, and more particularly, to an image sensing device including a test pattern for testing defects of a signal line. Background Art

[0002] Image sensing devices are used in electronic devices to convert optical images into electrical signals. Image sensing devices can be roughly classified into CCD (Charge Coupled Device) image sensing devices and CMOS (Complementary Metal Oxide Semiconductor) image sensing devices.

[0003] CCD image sensing devices can be driven more easily than CCD image sensing devices. In addition, CMOS image sensing devices are compatible with CMOS manufacturing technology, resulting in reduced production costs. In recent years, CMOS image sensing devices have been intensively studied and rapidly used. Summary of the invention

[0004] According to an embodiment of the disclosed technology, an image sensing device may include: a plurality of first upper signal lines, which are respectively connected to a plurality of first pixel transistors located in different rows of a pixel array; a first test line, which is commonly connected to the plurality of first upper signal lines; a first test pad, which is configured to provide a first test signal to the first test line; and a first test transistor, which is connected to the first test line and the first test pad. During a test operation, the first test signal may be provided to the plurality of first pixel transistors located in different rows of the pixel array through the first test transistor, the first test line, and the plurality of first upper signal lines.

[0005] In some implementations, each of the plurality of first pixel transistors may be any one of a reset transistor, a select transistor, a transfer transistor, and a gain conversion transistor.

[0006] In some implementations, the image sensing device may further include: a plurality of first lower signal lines, which are respectively connected to the plurality of first upper signal lines. The plurality of first pixel transistors, the plurality of first upper signal lines and the first test line may be disposed in the first substrate, and the plurality of first lower signal lines may be disposed in a second substrate located below the first substrate.

[0007] In some implementations, the pixel array may further include a plurality of second pixel transistors disposed in different rows.

[0008] In some implementations, the pixel array may further include: a plurality of second upper signal lines, respectively connected to a plurality of second pixel transistors; a second test line, commonly connected to the plurality of second upper signal lines; a second test pad, configured to provide a second test signal to the second test line; and a second test transistor, connected to the second test line and the second test pad.

[0009] In some implementations, the first test transistor and the second test transistor may be activated at the same timing point.

[0010] In some implementations, the first test transistor and the second test transistor may be activated at different timing points.

[0011] In some implementations, the first upper signal lines may be respectively connected to a plurality of first pixel transistors located in the same row of the pixel array.

[0012] In some implementations, the image sensing device may further include: a plurality of first lower signal lines respectively connected to the plurality of first upper signal lines, wherein a first control signal for controlling the first pixel transistor is provided to the plurality of first pixel transistors. The plurality of first pixel transistors are located in any row of the pixel array through any first lower signal line and any first upper signal line. Any first upper signal line is connected to any first lower signal line and is located in any row of the pixel array.

[0013] In some implementations, the first test line may be located below the first upper signal line and may be located in the same substrate as the first upper signal line.

[0014] According to another embodiment of the disclosed technology, an image sensing device may include: a plurality of first pixel transistors located in any row included in a pixel array; a first upper signal line connected to the plurality of first pixel transistors and located in a first substrate; a first test line connected to the first upper signal line and located in the first substrate; a first lower signal line connected to the first upper signal line and located in a second substrate below the first substrate; and a first test transistor connected to the first lower signal line and a first test pad. During a sensing operation, a first control signal for the first pixel transistor may be provided to the plurality of first pixel transistors via the first lower signal line and the first upper signal line. During a test operation, a first test signal provided via the first test pad may be provided to the plurality of first pixel transistors without passing through the first lower signal line.

[0015] In some other implementations, a plurality of first pixel transistors located in different rows of the pixel array may be respectively connected to a plurality of first upper signal lines, wherein the plurality of first upper signal lines are commonly connected to the first test line.

[0016] In some other implementations, each of the plurality of first pixel transistors may be any one of a reset transistor, a select transistor, a transfer transistor, and a gain conversion transistor.

[0017] In some other implementations, the first test line may be located below the first upper signal line and may be located in the same substrate as the first upper signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0019] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0020] Figure 2 is a diagram showing an example of a portion of a pixel array based on some implementations of the disclosed technology.

[0021] Figure 3 is a diagram showing an example of a detailed structure of a pixel array based on some implementations of the disclosed technology.

[0022] Figure 4 is a cross-sectional diagram illustrating an example of a pixel array based on some implementations of the disclosed technology.

[0023] Figure 5 and Figure 6 is a diagram illustrating an example of a method of operating a test transistor based on some implementations of the disclosed technology. DETAILED DESCRIPTION

[0024] When the manufacturing process of the CMOS image sensing device is completed, a probe test may be performed to determine whether a signal line included in the CMOS image sensing device is defective. The location of the defective signal line may be confirmed by the probe test, but when the probe test for the signal line cannot be performed due to the layout structure of the substrate, it may be difficult to confirm the location of the defective signal line. This patent application discloses a design of a CMOS image sensing device so that a test pattern can easily test and confirm the location of a physical defect in a signal line.

[0025] This patent document provides implementations and examples of image sensing devices including test patterns for testing defects in signal lines, which can be used in a configuration to substantially solve one or more technical or engineering problems and alleviate limitations and disadvantages encountered in some other image sensing device designs. Some implementations of the disclosed technology relate to a test pad for directly applying power to a signal line to easily confirm the location of a defect in the signal line. Recognizing the above problems, the image sensing device may include a test pad for directly providing a test signal to a signal line disposed in a substrate to be tested, so that the image sensing device can easily confirm the location of a defect in the signal line using the test pad. In addition to the signal line to which the drive signal of the pixel transistor is applied, the image sensing device may include a separate test line, so that a test signal can be provided to the signal line to be tested for defect inspection without passing through the signal line to which the drive signal is applied.

[0026] Various embodiments of the disclosed technology are directed to an image sensing device capable of easily confirming the position of a defect in a signal line.

[0027] Various embodiments of the disclosed technology are directed to a test pad for directly applying power to a signal line to easily confirm a location of a defect in the signal line.

[0028] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

[0029] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. Although the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof are illustrated as examples in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0030] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0031] In the following description, detailed descriptions of related known configurations or functions contained herein will be omitted to avoid obscuring the subject matter.

[0032] The terms used herein are only for describing specific embodiments and are not intended to limit the disclosed technology. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form. It will be further understood that the terms "include" and / or "comprising" when used in this specification specify the presence of the constituent elements, steps, operations and / or components, but do not exclude the presence or addition of one or more other constituent elements, steps, operations and / or their components. The term "and / or" may include a combination of multiple items or any one of multiple items.

[0033] Figure 1 is a block diagram illustrating an image sensing device 100 based on some implementations of the disclosed technology.

[0034] Reference Figure 1 , the image sensing device 100 may include a pixel array 110 , a row driver 120 , a correlated double sampler (CDS) 130 , an analog-to-digital converter (ADC) 140 , an output buffer 150 , a column driver 160 , and a timing controller 170 . Figure 1 The components of image sensing device 100 shown are discussed merely as examples, and this patent document encompasses numerous other alterations, substitutions, variations, modifications, and modifications.

[0035] The pixel array 110 may include a plurality of unit imaging pixels arranged in rows and columns. In one example, the plurality of unit imaging pixels may be arranged in a two-dimensional pixel array including rows and columns.

[0036] The plurality of unit imaging pixels may convert optical signals into electrical signals, each of the unit imaging pixels may include a plurality of photoelectric conversion elements, and the photoelectric conversion elements may be commonly connected to at least a specific transistor.

[0037] Pixel array 110 may receive driving signals including row selection signals, pixel reset signals, and transfer signals from row driver 120. Upon receiving the driving signals, corresponding imaging pixels in pixel array 110 may be activated to perform operations corresponding to the row selection signals, pixel reset signals, and transfer signals.

[0038] Row driver 120 may activate pixel array 110 to perform specific operations on imaging pixels in corresponding rows based on command and control signals provided by controller circuitry such as timing controller 170 .

[0039] In some implementations, row driver 120 may select one or more imaging pixels arranged in one or more rows of pixel array 110. Row driver 120 may generate row selection signals to select one or more rows among a plurality of rows.

[0040] The row driver 120 may sequentially activate a pixel reset signal for resetting the imaging pixels corresponding to at least one selected row and a transmission signal for the pixels corresponding to at least one selected row. Therefore, as analog signals generated by the respective imaging pixels of the selected row, the reference signal and the image signal may be sequentially transmitted to the CDS 130.

[0041] The reference signal may be an electrical signal provided to the CDS 130 when a sensing node (e.g., a floating diffusion node) of an imaging pixel is reset, and the image signal may be an electrical signal provided to the CDS 130 when photocharges generated by the imaging pixel are accumulated in the sensing node. The reference signal indicating the unique reset noise of each pixel and the image signal indicating the intensity of the incident light may be collectively referred to as a pixel signal as needed.

[0042] CMOS image sensors may use correlated double sampling (CDS) to remove undesired offset values ​​(called fixed pattern noise) of pixels by sampling the pixel signal twice to remove the difference between the two samples. In one example, correlated double sampling (CDS) may remove undesired offset values ​​of pixels by comparing the pixel output voltages obtained before and after the photocharges generated by the incident light are accumulated in the sensing node so that only the pixel output voltage based on the incident light may be measured. In some embodiments of the disclosed technology, CDS 130 may sequentially sample and hold the voltage levels of the reference signal and the image signal provided to each of the plurality of column lines from the pixel array 110. That is, CDS 130 may sample and hold the voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 110.

[0043] In some implementations, the CDS 130 may transmit the reference signal and the image signal of each column to the ADC 140 as a correlated double sampling signal based on a control signal from the timing controller 170 .

[0044] ADC 140 is used to convert the analog CDS signal into a digital signal. In some implementations, ADC 140 may be implemented as a ramp comparison ADC. The ramp comparison ADC may include a comparator circuit for comparing the analog pixel signal with a reference signal (e.g., a ramp signal that ramps up or down) and a timer for performing counting until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, ADC 140 may convert the correlated double sampling signal generated by CDS 130 for each column into a digital signal and output the digital signal.

[0045] The ADC 140 may include a plurality of column counters. Each column of the pixel array 110 is connected to the column counter, and image data may be generated by converting a correlated double sampling signal received from each column into a digital signal using the column counter. In another embodiment of the disclosed technology, the ADC 140 may include a global counter to convert a correlated double sampling signal corresponding to a column into a digital signal using a global code provided from the global counter.

[0046] The output buffer 150 may temporarily hold the column-based image data provided from the ADC 140 to output the image data. In one example, the image data provided from the ADC 140 to the output buffer 150 may be temporarily stored in the output buffer 150 based on a control signal of the timing controller 170. The output buffer 150 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device 100 and other devices.

[0047] The column driver 160 may select a column of the output buffer upon receiving a control signal from the timing controller 170, and sequentially output the image data temporarily stored in the selected column of the output buffer 150. In some implementations, upon receiving an address signal from the timing controller 170, the column driver 160 may generate a column selection signal based on the address signal and select a column of the output buffer 150, thereby outputting the image data as an output signal from the selected column of the output buffer 150.

[0048] The timing controller 170 may control operations of the row driver 120 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0049] The timing controller 170 may provide a clock signal required for the operation of each component of the image sensing device 100, a control signal for timing control, and an address signal for selecting a row or column to the row driver 120, the column driver 160, and the output buffer 150. In an embodiment of the disclosed technology, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0050] Figure 2 is a diagram showing an example of a portion of a pixel array 110 based on some implementations of the disclosed technology.

[0051] Figure 2A unit pixel region 10, at least one bonding region 20 located near the unit pixel region 10, and at least one pad region 30 located near the unit pixel region 10 are shown as included in the pixel array 110. For example, at least one bonding region 20 is located at one side of the unit pixel region 10. For example, at least one pad region 30 is located at one side of the bonding region, such that the bonding region 20 is located between the unit pixel region 10 and the pad region 30. As discussed further later, the bonding region 20 and the pad region may be positioned around the unit pixel region 10.

[0052] Reference Figure 2 The pixel array 110 may include a structure in which a plurality of substrate layers are stacked. For example, the plurality of substrate layers may include a semiconductor layer and an interlayer insulating layer formed above the semiconductor layer.

[0053] For example, the semiconductor layer may be or may include a single crystal silicon substrate. The semiconductor layer may be a P-type or N-type bulk substrate, may be a substrate formed by growing a P-type or N-type epitaxial layer on a P-type bulk substrate, or may be a substrate formed by growing a P-type or N-type epitaxial layer on an N-type bulk substrate.

[0054] Source / drain regions of a photoelectric conversion element or a pixel transistor for converting incident light into photocharges may be provided within the semiconductor layer.

[0055] The interlayer insulating layer may be or may include a layer including an insulating material such as silicon oxide or silicon nitride, and may serve as a region where a signal line including a metal interconnection is provided or a gate of a pixel transistor is formed.

[0056] The metal interconnection disposed in the interlayer insulating layer may include a metal such as copper (Cu), tungsten (W), or aluminum (Al). The detailed vertical stacking structure of the pixel array 110 will be referred to in detail. Figure 4 Detailed description.

[0057] The unit pixel region 10 may be or may include a region where a plurality of photoelectric conversion elements, a plurality of pixel transistors, and a floating diffusion region are disposed. The unit pixel may be a minimum unit of a pixel layout repeatedly arranged within the unit pixel region 10 .

[0058] The photoelectric conversion element may be a region that generates photocharges in response to incident light received by the photoelectric conversion element, and may be formed by doping an impurity region in a semiconductor layer. Each photoelectric conversion element may be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0059] The pixel transistor may be a transistor that processes a pixel signal corresponding to the photoelectric conversion element. As an example, each pixel transistor may be any one of a transfer transistor, a selection transistor, a reset transistor, or a gain conversion transistor.

[0060] The bonding region 20 may refer to a region where elements (eg, signal lines, etc.) arranged in a plurality of layers of the pixel array 110 are electrically connected to each other.

[0061] The bonding area 20 may include an upper bonding metal layer disposed in an upper layer (i.e., a first substrate layer) and a lower bonding metal layer disposed in a lower layer (i.e., a second substrate layer). Signal lines and the like included in each of the upper layer and the lower layer may be electrically connected to each other according to a bonding method of the bonding metal. The bonding metal may include, for example, aluminum (Al), copper (Cu), or tungsten (W).

[0062] In addition, the bonding region 20 may include a signal line extending from the unit pixel region 10. The signal line provided in the first substrate layer and the signal line provided in the second substrate layer may be connected to each other through a bonding metal.

[0063] The pad area 30 may refer to an area where a plurality of input / output (I / O) pads (PAD) are arranged. The input / output (I / O) pads may be a means for providing an external signal to the pixel array 110 or a means for outputting a pixel signal to the outside.

[0064] The external signal provided to the input / output (I / O) pad may be transmitted to the pixel transistor or the like through the signal line provided in the plurality of layers and the bonding area 20. The external signal may be or may include, for example, a control signal for each pixel transistor or a test signal for determining whether a defect occurs in the signal line.

[0065] The control signal received through the input / output (I / O) pad can be transmitted to the pixel transistor through the lower signal line set in the lower layer (i.e., the second substrate layer) of the pixel array 110, the bonding area, and the upper signal line set in the upper layer (i.e., the first substrate layer).

[0066] In some implementations, additional test pads may be provided in the pad region 30. The test pads may be pads that receive test signals from an external test device. The test signals may be provided to signal lines included in the pixel array 110 through the test pads and the test lines.

[0067] Although for the sake of convenience, Figure 2 The bonding region 20 and the pad region 30 are shown to be disposed on the left and right sides of the unit pixel region 10, but the positions and shapes of the bonding region 20 and the pad region 30 are not limited to Figure 2 implementation method.

[0068] In an example, the bonding region 20 and the pad region 30 may be selectively located at the upper side, the lower side, the left side, and the right side of the unit pixel region 10. For example, the bonding region 20 and the pad region 30 may be arranged to surround the unit pixel region 10 according to a layout shape, or may be located at any one of the upper side, the lower side, the left side, and the right side of the unit pixel region 10.

[0069] A semiconductor device based on some implementations of the disclosed technology may include a test pad and a test line so that the semiconductor device may perform a defect test on signal lines respectively connected to pixel transistors of the pixel array 110 .

[0070] More specifically, the test line may be provided in an upper layer (i.e., the first substrate layer) of the pixel array 110 and may be connected to an upper signal line provided in the upper layer. Since the test signal may be provided to the upper signal line through the test line, the semiconductor device may easily identify whether a defect occurs in the upper signal line without applying a control signal to the pixel transistor.

[0071] In some implementations, one test line may be commonly connected to upper signal lines connected to pixel transistors of the same type disposed in the pixel array 110 .

[0072] Pixel transistors of the same type may refer to transistors that perform the same function during a sensing operation of an image sensing device.

[0073] In addition, the semiconductor device includes a test line so that a test signal is supplied to the upper signal line without passing through the lower signal line. As a result, the semiconductor device can find out whether a defect occurs at the lower signal line or the upper signal line.

[0074] The image sensing device can identify (or specify) a row where a defect occurs in the upper signal line within the pixel array 110 by providing a control signal to the pixel transistor. In addition, the image sensing device provides a test signal to the test line so that the image sensing device can specify (or identify) a defective pixel transistor having a defective upper signal line among a plurality of pixel transistors arranged in the row direction.

[0075] Figure 3 is a diagram showing an example of a detailed structure of a pixel array 110 based on some implementations of the disclosed technology.

[0076] exist Figure 3 , the unit pixel region 10a, the bonding region 20a, and the pad region 30a are specifically shown in detail.

[0077] Figure 3 The unit pixel region 10a and the bonding region 20a shown in FIG. 1 may be arranged in one substrate layer (eg, a first substrate layer). Figure 3The constituent components in the illustrated unit pixel region 10 a and the bonding region 20 a may be components included in an upper layer (ie, a first substrate layer) among a plurality of semiconductor layers included in the pixel array 110 .

[0078] Figure 3 Components that are vertically connected to each other in the embodiment can be connected by vertical through holes.

[0079] Reference Figure 3 , the unit pixel region 10a may include a plurality of unit pixels (PX1, PX2, PX3, PX4).

[0080] A plurality of unit pixels ( PX1 , PX2 , PX3 , PX4 ) may be arranged in a matrix shape within the unit pixel region 10 a .

[0081] Reference Figure 3 , the first unit pixel (PX1) and the second unit pixel (PX2) may be arranged in a first row (ROW1) included in the unit pixel region 10a, and the third unit pixel (PX3) and the fourth unit pixel (PX4) may be arranged in a second row (ROW2) included in the unit pixel region 10a.

[0082] For the convenience of description, Figure 3 Only four unit pixels (PX1, PX2, PX3, PX4) and two rows (ROW1, ROW2) are shown. The number of unit pixels and the number of rows included in the unit pixels may be modified in various ways. For example, the unit pixel region 10a may include more than 4 unit pixels and more than 2 rows. Figure 3 In the example shown, a first set of upper signal lines MT1-1 to MT8-1 and a second set of upper signal lines MT1-2 to MT8-2 are provided. The first set of upper signal lines MT1-1 to MT8-1 are included in a first row, and the second set of upper signal lines MT1-2 to MT8-2 are included in a second row.

[0083] because Figure 3 The unit pixels (PX1, PX2, PX3, PX4) shown are basically the same in structure, so the structure of the unit pixel will be described below based on the structure of the first unit pixel (PX1), and its redundant description will be omitted herein for simplicity.

[0084] The first unit pixel (PX1) may include a first drive transistor (DX1), a first selection transistor (SX1), a first reset transistor (RX1), a first gain conversion transistor (DCGX1), and four transfer transistors (TX1-1, TX2-1, TX3-1, TX4-1).

[0085] The first unit pixel (PX1) may include a first floating diffusion region (FD1) receiving photocharges from a photoelectric conversion element (not shown), and the first floating diffusion region (FD1) may be connected to a floating diffusion boosting signal line (MT8-1).

[0086] The first unit pixel (PX1) may further include a first capacitance element (CAP1) connected to the first floating diffusion region (FD1) through the first gain conversion transistor (DCGX1) to change the storage capacity of the first floating diffusion region (FD1).

[0087] The transfer transistors (TX1-1, TX2-1, TX3-1, TX4-1) may correspond to photoelectric conversion elements (not shown), respectively. In this case, the first unit pixel (PX1) may include four photoelectric conversion elements.

[0088] The four photoelectric conversion elements are only examples, and the number of photoelectric conversion elements included in the unit pixel may be modified differently. For example, instead of four photoelectric conversion elements, the unit pixel may include two photoelectric conversion elements, or may include eight photoelectric conversion elements arranged in a (2×4) matrix. In the example, the unit pixel may include the same number of transfer transistors as the number of photoelectric conversion elements.

[0089] Each photoelectric conversion element may generate photocharges corresponding to incident light. The generated photocharges may be transferred to the first floating diffusion region (FD1) through each transfer transistor (eg, TX1-1).

[0090] The first drive transistor (DX1) may amplify a voltage change corresponding to the photocharge transferred to the first floating diffusion region (FD1). A gate terminal of the first drive transistor (DX1) may contact one end of the first floating diffusion region (FD1).

[0091] The first selection transistor (SX1) may determine whether to output a pixel signal corresponding to the amplified voltage. The first selection transistor (SX1) may be connected to one end of the first driving transistor (DX1).

[0092] The first reset transistor (RX1) may remove photo charges from the first unit pixel (PX1) and may reset the first unit pixel (PX1) to a pixel voltage.

[0093] The first gain conversion transistor (DCGX1) may be connected between the first floating diffusion region (FD1) and the first capacitance element (CAP1), and may adjust the capacitance of the first floating diffusion region (FD1).

[0094] The first capacitive element (CAP1) is merely an example configuration and may be omitted according to an embodiment. In addition, instead of the first capacitive element (CAP1), a separate transistor (eg, a blooming transistor, etc.) may be provided within the unit pixel.

[0095] The eighth upper signal line (MT8-1) connected to the first floating diffusion region (FD1) and the second floating diffusion region (FD2) may be a signal line for providing a boost voltage to the first floating diffusion region (FD1) and the second floating diffusion region (FD2). The above description is provided mainly for the first unit pixel in the first row, and a similar description is applicable to the second to fourth unit pixels in the pixel array. When the above description is applied to the unit pixels in the second row, the upper signal lines MT1-2 to MT8-2 of the second set may be connected to the components of the unit pixels in the second row.

[0096] The unit pixels ( PX1 , PX2 , PX3 , PX4 ) may be repeatedly arranged in a row direction and a column direction.

[0097] Pixel transistors respectively included in unit pixels located in one row and performing the same function during a sensing operation may be connected in common to any one of the upper signal lines ( MT1 - 1 ˜ MT8 - 2 ).

[0098] For example, selection transistors that perform the same function during a sensing operation and are located in the same row of the same pixel array are connected to corresponding upper signal lines. For example, a first selection transistor (SX1) included in a first unit pixel (PX1) and a second selection transistor (SX2) included in a second unit pixel (PX2) may be commonly connected to a first upper signal line (MT1-1).

[0099] For example, transfer transistors that perform the same function during a sensing operation and are located in the same row of the same pixel array are connected to the corresponding upper signal line. For example, a first transfer transistor (TX1-1) included in a first unit pixel (PX1) belonging to a first row (ROW1) and a second transfer transistor (TX1-2) included in a second unit pixel (PX2) belonging to the first row (ROW1) may be commonly connected to a second upper signal line (MT2-1).

[0100] The first to eighth upper signal lines (MT1-1 to MT8-1) arranged in the first row (ROW1) may be provided in an upper layer (i.e., a first substrate layer) among a plurality of semiconductor layers included in the pixel array 110. The first to eighth upper signal lines (MT1-1 to MT8-1) arranged in the first row (ROW1) may be signal lines for transmitting control signals for pixel transistors (e.g., SX1, RX1, TX1-1, TX2-1, TX3-1, TX4-1, DCGX1, etc.), or may be signal lines for transmitting a boosted voltage to a floating diffusion region (e.g., FD1, etc.).

[0101] The upper signal lines (MT1-1 ∼ MT8-2) may be disposed in an interlayer insulating layer disposed in the first substrate, and may include a metal such as copper (Cu), tungsten (W), or aluminum (Al).

[0102] The remaining pixel transistors or floating diffusion regions other than the driving transistor (eg, DX1) may be connected to the upper signal lines (MT1-1 ∼ MT8-2).

[0103] The number of upper signal lines (MT1-1 to MT8-1) included in one row (eg, ROW1) may be determined based on the number of elements (eg, transistors or floating diffusion regions, etc.) included in each unit pixel (eg, PX1).

[0104] From the row driver ( Figure 1 The control signal for the pixel transistor (e.g., SX1, SX2) received by the upper signal line 120 in the pixel array 110 may be transmitted to the upper signal line (e.g., MT-1) through the lower signal line (not shown) and the control contact (e.g., BC1) included in the lower layer (i.e., the second substrate layer) among the plurality of semiconductor layers included in the pixel array 110. The upper signal line (e.g., MT1-1) may transmit the received control signal to the connected pixel transistor (e.g., SX1, SX2).

[0105] Each control connector (BC1-BC16) can be arranged on the pixel array ( Figure 1 A connector that connects elements (eg, upper signal lines and lower signal lines) in each of a plurality of substrates included in 110) to each other.

[0106] The test lines (T1 to T8) included in the bonding region 20a may be commonly connected to the plurality of upper signal lines (MT1-1 to MT8-2).

[0107] For example, the first test line (T1) may be commonly connected to the first upper signal line (MT1-1) disposed in the first row (ROW1) and the first upper signal line (MT1-2) disposed in the second row (ROW2).

[0108] In an example, the first test line ( T1 ) may be commonly connected to all first upper signal lines (eg, MT1 - 1 , MT1 - 2 , etc.) connected to selection transistors ( SX1 , SX2 , SX3 , SX4 , etc.) included in the unit pixel region 10 a .

[0109] In an example, the second test line (T2) may be commonly connected to all second upper signal lines (MT2-1, MT2-2, etc.) connected to all first transfer transistors (TX1-1, TX1-2, TX1-3, TX1-4, etc.) included in the unit pixel region 10a.

[0110] Since the test line (eg, T1) is commonly connected to a plurality of upper signal lines (eg, MT1-1, MT1-2), the test signals received through the test line may be commonly connected to the upper signal lines (eg, MT1-1, MT1-2).

[0111] As described previously, pixel transistors located in the same row may receive the same control signal. Therefore, when there is a defect in the upper signal line, the row in which the error has occurred may be identified (or specified) based on the pixel signals output for each row.

[0112] In addition, since the test signal is included in the unit pixel region 10a and is simultaneously transmitted to multiple upper signal lines (e.g., MT1-1, MT1-2) connected to pixel transistors configured to perform the same function during a sensing operation, it is easy to identify (or specify) which upper signal line located in the same row is defective.

[0113] The test lines (T1 to T8) may be connected to different test pads (TP1 to TP8), and a test voltage may be provided to each test pad.

[0114] During a sensing operation, upper signal lines (eg, MT1 - 1 , MT6 - 1 ) connected to pixel transistors (eg, SX1 , RX1 , etc.) configured to perform different functions may receive different test signals.

[0115] Whether to supply the test voltage to each test pad may be determined according to the on / off state of the test transistor (TTX1 to TTX8).

[0116] In some implementations, the on / off states of the test transistors ( TTX1 ˜ TTX8 ) may be determined by one test enable signal, or may be determined by different test enable signals respectively applied to the test transistors ( TTX1 ˜ TTX8 ).

[0117] The test lines (T1-T8) can be connected to the test transistors (TTX1-TTX8) through the test connectors (BT1-BT8) through the wires located in the second substrate layer.

[0118] The test pads (P1-P8) and the test lines (T1-T8) may be short-circuited or open-circuited depending on whether the test transistors (TTX1-TTX8) are turned on or off.

[0119] Since the test transistors (TTX1~TTX8) determine whether the test pads (P1~P8) and the test lines (T1~T8) are short-circuited or open-circuited, the test transistors (TTX1~TTX8) can perform defect tests separately for different types of pixel transistors and prevent the test voltage from being applied to these pixel transistors during the sensing operation.

[0120] Figure 4 is a cross-sectional diagram illustrating an example of a pixel array 110 based on some implementations of the disclosed technology.

[0121] Figure 4 1 is a cross-sectional view of a pixel array 110 including a first substrate layer (PIXEL) and a second substrate layer (LOGIC).

[0122] The first substrate layer (PIXEL) may be a layer including a photoelectric conversion element, a pixel transistor, etc., and may be referred to as a pixel layer. The second substrate layer (LOGIC) may be a region including a peripheral circuit electrically connected to the elements included in the first substrate layer (PIXEL), and may be referred to as a logic layer.

[0123] The first substrate layer (PIXEL) may include a first semiconductor layer (SUB1) and a first interlayer insulating layer (IL1).

[0124] The first semiconductor layer (SUB1) may be or may include a single crystal silicon substrate. The first semiconductor layer (SUB1) may be or may include a P-type or N-type bulk substrate, may be or may include a substrate formed by growing a P-type or N-type epitaxial layer on a P-type bulk substrate, or may be or may include a substrate formed by growing a P-type or N-type epitaxial layer on an N-type bulk substrate.

[0125] The first interlayer insulating layer ( IL1 ) may be or may include a layer including an insulating material such as silicon oxide or silicon nitride.

[0126] In an example, the second substrate layer (LOGIC) may include a second semiconductor layer (SUB2) and a second interlayer insulating layer (IL2).

[0127] In an example, similar to the first semiconductor layer (SUB1), the second semiconductor layer (SUB2) may be or may include a P-type or N-type bulk substrate, may be or may include a substrate formed by growing a P-type or N-type epitaxial layer on a P-type bulk substrate, or may be or may include a substrate formed by growing a P-type or N-type epitaxial layer on an N-type bulk substrate.

[0128] The second interlayer insulating layer (IL2) may be or may include a layer including an insulating material such as silicon oxide or silicon nitride.

[0129] The pixel transistor (eg, SX1) may be disposed in the first semiconductor layer (SUB1). More specifically, the source / drain regions of the pixel transistor may be formed in the first semiconductor layer (SUB1).

[0130] The upper signal line (MT1-1) and the test line (T1) may be formed in the first interlayer insulating layer (IL1). Figure 4 As shown, the test line (T1) can be set below the upper signal line (MT1-1).

[0131] The upper signal line (MT1-1) can be connected to the lower signal line (MD1-1) provided in the second substrate layer (LOGIC) through the control connector (BC1). The lower signal line (MD1-1) can be connected to a pad for applying a control signal to the pixel transistor.

[0132] The test line (T1) can be connected to a lower test line (T1') provided in the second substrate layer (LOGIC) through a test connector (BT1). The lower test line (T1') can be connected to a test pad through a test transistor.

[0133] Reference Figure 4 During a sensing operation of the image sensing device, a control signal may be transmitted to a pixel transistor (eg, SX1) via a lower signal line (eg, MD1-11), a control connector (eg, BC1), and an upper signal line (eg, MT1-1).

[0134] In addition, during a test operation of the image sensing device, a test signal may be transmitted to an upper signal line (eg, MT1-1) through a lower test line (eg, T1'), a test tap (eg, BT1), and a test line (eg, T1).

[0135] Figure 5 and Figure 6 is a diagram illustrating an example of a method of operating a test transistor based on some implementations of the disclosed technology.

[0136] Reference Figure 5, information about whether to transmit test signals (TX1_TS, TX2_TS, TX3_TS, TX4_TS, SX_TS, RX_TS, DCGX_TS, FBX_TS) for each test pad to the test line (T_TX1, T_TX2, T_TX3, T_TX4, T_SX, T_RX, T_DCGX, T_FBX) can be determined based on the on / off state of the test transistor (TX1_TT, TX2_TT, TX3_TT, TX4_TT, SX_TT, RX_TT, DCGX_TT, FBX_TT).

[0137] Figure 5 The test transistors (TX1_TT, TX2_TT, TX3_TT, TX4_TT, SX_TT, RX_TT, DCGX_TT, FBX_TT) shown may correspond to Figure 3 The test transistors (TTX1, TTX2, TTX3, TTX4, TTX5, TTX6, TTX7, TTX8) are shown.

[0138] like Figure 5 As shown, when the test enable signals (TEST_EN) respectively provided to different test transistors are the same signal, the test signals (TX1_TS, TX2_TS, TX3_TS, TX4_TS, SX_TS, RX_TS, DCGX_TS, FBX_TS) can be provided to the test lines (T_TX1, T_TX2, T_TX3, T_TX4, T_SX, T_RX, T_DCGX, T_FBX) only when the test enable signals are activated. Therefore, during the remaining operations other than the test operation, the test signals can be prevented from being provided to the pixel transistors or the floating diffusion region.

[0139] Figure 5 The test lines shown (T_TX1, T_TX2, T_TX3, T_TX4, T_SX, T_RX, T_DCGX, T_FBX) can correspond to Figure 3 Test lines shown (T1, T2, T3, T4, T5, T6, T7, T8).

[0140] For example, when the test enable signal (TEST_EN) is activated, the test transistor (FBX_TT) for the floating diffusion boost signal may be activated and the test signal (FBX_TS) for the floating diffusion boost signal line may be provided to the floating diffusion region through the test line (T_FBX).

[0141] and Figure 3 When the test enable signal (TEST_EN) is activated, the eighth test transistor (corresponding to Figure 3TTX8 and FBX_TT in can be activated and the eighth test pad ( Figure 3 The test signal (corresponding to FBX_TS) provided by the eighth test line (corresponding to Figure 3 T8 and T_FBX) in are provided as floating diffusion areas.

[0142] like Figure 6 As shown, different test enable signals (TX1_TEST_EN, TX2_TEST_EN, TX3_TEST_EN, TX4_TEST_EN, SX_TEST_EN, RX_TEST_EN, DCGX_TEST_EN, FBX_TEST_EN) can be provided to the test transistors (TX1_TT, TX2_TT, TX3_TT, TX4_TT, SX_TT, RX_TT, DCGX_TT, FBX_TEST_EN), respectively.

[0143] Figure 6 The test transistors (TX1_TT, TX2_TT, TX3_TT, TX4_TT, SX_TT, RX_TT, DCGX_TT, FBX_TT) can correspond to Figure 3 Test transistors (TTX1, TTX2, TTX3, TTX4, TTX5, TTX6, TTX7, TTX8).

[0144] For example, when a test enable signal (FBX_TEST_EN) for a floating diffusion boost signal line is activated, a test transistor (FBX_TT) for the floating diffusion boost signal line may be activated, and a test signal (FBX_TS) for the floating diffusion boost signal line may be provided to the floating diffusion region through a test line (T_FBX).

[0145] like Figure 6 As shown, when the test enable signals (TX1_TEST_EN, TX2_TEST_EN, TX3_TEST_EN, TX4_TEST_EN, SX_TEST_EN, RX_TEST_EN, DCGX_TEST_EN, FBX_TEST_EN) respectively provided to different test transistors (TX1_TT, TX2_TT, TX3_TT, TX4_TT, SX_TT, RX_TT, DCGX_TT, FBX_TEST_EN) are different from each other, test signals (TX1_TS, TX2_TS, TX3_TS, TX4_TS, SX_TS, RX_TS, DCGX_TS, FBX_TS) can be provided to the test lines (T_TX1, T_TX2, T_TX3, T_TX4, T_SX, T_RX, T_DCGX, T_FBX), respectively.

[0146] As is apparent from the above description, an image sensing device based on some implementations of the disclosed technology includes a test pad for directly providing a test signal to a signal line disposed in a substrate to be tested, so that the image sensing device can easily confirm the location of a defect in the signal line using the test pad.

[0147] In addition to signal lines that apply drive signals to pixel transistors, image sensing devices based on some implementations of the disclosed technology include separate test lines, so that test signals are provided to the signal lines to be tested for defect inspection without passing through the signal lines to which the drive signals are applied.

[0148] The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized from the above-mentioned patent documents.

[0149] Those skilled in the art will appreciate that the disclosed technology can be implemented in a specific manner other than that described herein. In addition, claims not explicitly stated in the appended claims may be stated as a combination of embodiments or included as new claims through subsequent amendments after filing an application.

[0150] Although several exemplary embodiments are described, it should be understood that modifications and / or enhancements to the disclosed embodiments, as well as other embodiments, may be devised based on what is described and / or illustrated in this patent document.

[0151] CROSS-REFERENCE TO RELATED APPLICATIONS

[0152] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0133368, filed on October 6, 2023, the disclosure of which is incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a pixel array comprising pixel cells that generate photocharges in response to incident light, the pixel cells comprising a plurality of first pixel transistors located in different rows of the pixel array; a plurality of first upper signal lines, wherein the plurality of first upper signal lines are respectively connected to the plurality of first pixel transistors; a first test line separated from the plurality of first upper signal lines and commonly connected to the plurality of first upper signal lines; a first test pad connected to the first test line and providing a first test signal to the first test line; as well as a first test transistor connected to the first test line and the first test pad and activating or deactivating a test operation by selectively supplying the first test signal to the first test line, During the test operation, the first test signal is provided to the plurality of first pixel transistors located in different rows of the pixel array through the first test transistor, the first test line and the plurality of first upper signal lines.

2. The image sensing device according to claim 1, wherein: Each of the plurality of first pixel transistors is a reset transistor, a selection transistor, a transfer transistor, or a gain conversion transistor.

3. The image sensing device according to claim 1, further comprising: a plurality of first lower signal lines, the plurality of first lower signal lines being respectively connected to the plurality of first upper signal lines, wherein the plurality of first pixel transistors, the plurality of first upper signal lines and the first test line are arranged in a first substrate included in the pixel array; and The plurality of first lower signal lines are disposed in a second substrate located below the first substrate.

4. The image sensing device according to claim 1, wherein: The pixel array further comprises: A plurality of second pixel transistors are provided in rows different from each other.

5. The image sensing device according to claim 4, wherein: The pixel array further comprises: a plurality of second upper signal lines, wherein the plurality of second upper signal lines are respectively connected to the plurality of second pixel transistors; a second test line, the second test line being commonly connected to the plurality of second upper signal lines; a second test pad, the second test pad providing a second test signal to the second test line; and A second test transistor is connected to the second test line and the second test pad.

6. The image sensing device according to claim 5, wherein: The first test transistor and the second test transistor are activated at the same time.

7. The image sensing device according to claim 5, wherein: The first test transistor and the second test transistor are activated at different times from each other.

8. The image sensing device according to claim 1, wherein: The pixel unit further includes an additional first pixel transistor located in the same row of the pixel array as one of the plurality of first pixel transistors, and One first upper signal line of the plurality of first upper signal lines is connected to the one first pixel transistor of the plurality of first pixel transistors and the additional first pixel transistor.

9. The image sensing device according to claim 1, further comprising: a plurality of first lower signal lines, the plurality of first lower signal lines being respectively connected to the plurality of first upper signal lines, In which, a first control signal for controlling the first pixel transistor is provided to multiple first pixel transistors located in any row of the pixel array through any first lower signal line and any first upper signal line located in any row of the pixel array and connected to any first lower signal line.

10. The image sensing device according to claim 1, wherein: The first test line is located below the first upper signal line and is located in the same substrate as the first upper signal line.

11. The image sensing device according to claim 1, wherein: The pixel array includes a first substrate and a second substrate disposed to overlap each other.

12. An image sensing device, comprising: a pixel array disposed in the first substrate layer and receiving incident light and generating photocharges in response to the incident light; a plurality of first pixel transistors, the plurality of first pixel transistors being located in any row included in the pixel array; a first upper signal line connected to the plurality of first pixel transistors and located in the first substrate layer; a first test line connected to the first upper signal line and located in the first substrate layer; a first lower signal line connected to the first upper signal line and located in a second substrate layer below the first substrate layer; as well as a first test transistor connected to the first lower signal line and a first test pad, wherein the first test line, the first test transistor and the first test pad are provided to test the plurality of first pixel transistors, and wherein, during a sensing operation, a first control signal for the first pixel transistor is provided to the plurality of first pixel transistors through the first lower signal line and the first upper signal line, and During a test operation, a first test signal provided through the first test pad is provided to the plurality of first pixel transistors without passing through the first lower signal line.

13. The image sensing device according to claim 12, further comprising: An additional first pixel transistor is located in a row different from the arbitrary row and connected to a first upper signal line different from the first upper signal line.

14. The image sensing device according to claim 13, wherein: The different first upper signal line is connected to the first test line, and the first test signal is provided to the additional first pixel transistor.

15. The image sensing device according to claim 13, wherein: A second control signal different from the first control signal is provided to the additional first pixel transistor.

16. The image sensing device according to claim 12, wherein: Each of the plurality of first pixel transistors is a reset transistor, a selection transistor, a transfer transistor, or a gain conversion transistor.

17. The image sensing device according to claim 12, wherein: The first test line is located below the first upper signal line and is located in the same substrate as the first upper signal line.

18. The image sensing device according to claim 12, further comprising: A second pixel transistor is located in the arbitrary row and connected to a first upper signal line different from the first upper signal line.

19. The image sensing device according to claim 18, wherein: A second test signal different from the first test signal is provided to the second pixel transistor.

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