Display device and electronic device with same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes: a display panel including a display area, the display area including sub-pixels, and in which are defined: a sensing area including sub-pixels and an optical sensor for providing a sensing signal corresponding to an amount of received light to a readout line; and a non-sensing region including sub-pixels; a readout circuit for receiving a sensing signal through a readout line; and a connection portion electrically connecting the readout line to the readout circuit. A connection line connecting the readout line and the connection portion to each other is located in the non-sensing area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0132552 filed in the Korean Intellectual Property Office on October 5, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device including an optical sensor and an electronic device having the display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, etc. has increased. In addition, the display device can sense the fingerprint of the user using an optical sensor and can perform a user authentication function.

[0005] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] One or more embodiments of the present disclosure may relate to a display device in which a readout line and a connection portion are connected to each other through a connection line provided in a non-sensing region.

[0007] One or more embodiments of the present disclosure may relate to an electronic device including the display device.

[0008] According to one or more embodiments of the present disclosure, a display device includes: a display panel including a display area, the display area including sub-pixels, and the display area defines: a sensing area including sub-pixels and an optical sensor configured to provide a sensing signal corresponding to the amount of received light to a readout line; and a non-sensing area including sub-pixels; a readout circuit configured to receive the sensing signal through the readout line; and a connecting portion electrically connecting the readout line to the readout circuit. A connecting line connecting the readout line and the connecting portion to each other is located in the non-sensing area.

[0009] In an embodiment, the readout line may extend in a first direction; the display area may include a first display area and a second display area, the first display area being adjacent to the connection portion in the first direction; and the connection line may connect the readout line of the second display area to the connection portion.

[0010] In an embodiment, the readout line may extend in a first direction; the connecting line may include a first connecting line and a second connecting line; the first connecting line may extend in a second direction intersecting the first direction and may be connected to the readout line through a first line contact hole; and the second connecting line may extend in the first direction and may be connected to the first connecting line through a second line contact hole.

[0011] In an embodiment, the first connection lines and the second connection lines may form a mesh structure.

[0012] In an embodiment, the connection line may also include a third connection line and a fourth connection line; the third connection line may extend in the second direction and may be connected to the second connection line through a third line contact hole; and the fourth connection line may extend in the first direction and may be connected to the third connection line through a fourth line contact hole.

[0013] In an embodiment, the readout line may be located at the same layer as that of the second connection line.

[0014] In an implementation, the first connection line may be located at the same layer as that of the third connection line.

[0015] In an embodiment, the connecting portion may include a first connecting region and a second connecting region spaced apart from the first connecting region; the readout line may extend in a first direction; the display area may include a first display area and a second display area, the first display area being adjacent to the first connecting region and the second connecting region in the first direction; and the connecting line may connect the readout line of the second display area to the connecting portion.

[0016] In an embodiment, a width of a first end of the connection portion adjacent to the display area may be longer than a width of a second end of the connection portion connected to the readout circuit.

[0017] In an embodiment, the sub-pixel may include a light emitting element and a pixel driving circuit; the optical sensor may include a light receiving element and a sensor driving circuit; the sensing area may include a first area including the pixel driving circuit, and a second area adjacent to the first area and including the sensor driving circuit; and the non-sensing area may include a first area including the pixel driving circuit, and a third area adjacent to the first area.

[0018] In an embodiment, the pixel driving circuit may include a first pixel transistor configured to generate a driving current; the first pixel transistor may include a portion of a conductive pattern; and a width of the conductive pattern in the third region may be wider than a width of the conductive pattern in the second region.

[0019] In an embodiment, the pixel driving circuit may include a second pixel transistor configured to write a data voltage in response to a write gate signal; the second pixel transistor may include a portion of a conductive pattern; and a width of the conductive pattern in the third region may be wider than a width of the conductive pattern in the second region.

[0020] In an embodiment, the pixel driving circuit may include a storage capacitor configured to store a data voltage; the storage capacitor may include a portion of the conductive pattern; and at least a portion of the conductive pattern may be located in the third region.

[0021] In an embodiment, the sensor driving circuit may be configured to be initialized with a reset voltage; and the conductive pattern configured to receive the reset voltage may overlap at least a portion of the readout line.

[0022] In an embodiment, at least a portion of the conductive pattern configured to receive the reset voltage may overlap the first region.

[0023] In an implementation, the conductive pattern configured to receive the reset voltage may have a mesh structure.

[0024] In an embodiment, the pixel driving circuit may be configured to receive a data voltage through a data line; the sensor driving circuit may be configured to receive a reset voltage through a reset voltage line; and the reset voltage line may be located between the data line and the readout line in the third region.

[0025] In an embodiment, the width of the connection line may increase as the length of the connection line increases.

[0026] According to one or more embodiments of the present disclosure, a display device includes: a display panel including a display area, the display area including sub-pixels, and the display area is defined as follows: a sensing area including sub-pixels and an optical sensor, the optical sensor configured to provide a sensing signal corresponding to the amount of received light to a readout line; and a non-sensing area including sub-pixels; a readout circuit configured to receive the sensing signal through the readout line; a first connection portion electrically connecting the readout line to the readout circuit; and a second connection portion electrically connecting the readout line to the readout circuit and spaced apart from the first connection portion. A connection line connecting the readout line to the first connection portion and the second connection portion to each other may be located in the non-sensing area.

[0027] According to one or more embodiments of the present disclosure, an electronic device includes: a processor configured to provide input image data to a display device; a display device configured to display an image based on the input image data; and a power supply configured to supply power to the display device. The display device includes: a display panel including a display area, the display area including sub-pixels, and the display area is defined with: a sensing area including sub-pixels and an optical sensor, the optical sensor configured to provide a sensing signal corresponding to the amount of received light to a readout line; and a non-sensing area including sub-pixels; a readout circuit configured to receive the sensing signal through the readout line; and a connecting portion electrically connecting the readout line to the readout circuit. The connecting line connecting the readout line and the connecting portion to each other may be located in the non-sensing area.

[0028] According to one or more embodiments of the present disclosure, a display device having a minimized or reduced dead zone may be provided by connecting a readout line and a connection portion to each other via a connection line disposed in a non-sensing region.

[0029] However, aspects and features of the present disclosure are not limited to those described above. Additional aspects and features will be set forth in part in the following detailed description with reference to the accompanying drawings, and in part may be apparent therefrom, or may be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of exemplary non-limiting embodiments with reference to the accompanying drawings.

[0031] Figure 1 A block diagram of a display device according to one or more embodiments of the present disclosure is shown.

[0032] Figure 2 Shows Figure 1 A circuit diagram of an example of a sub-pixel of a display device.

[0033] Figure 3 Shows Figure 1 A circuit diagram of an example of an optical sensor of a display device.

[0034] Figure 4 Shows Figure 1 Examples of sensing areas and non-sensing areas of a display device.

[0035] Figure 5 Shows Figure 1 An example of a first display area and a second display area of ​​a display device.

[0036] Figure 6 Shows the settings in Figure 1An example of a readout line in a first display area of ​​a display device.

[0037] Figure 7 Shows the settings in Figure 1 An example of a readout line in a second display area of ​​a display device.

[0038] Figures 8 to 23 Shows Figure 1 Layout diagram of an example of a sensing area of ​​a display device.

[0039] Figures 24 to 39 Shows Figure 1 Layout diagram of an example of a non-sensing area of ​​a display device.

[0040] Fig.40 An example of a readout line provided in a second display area of ​​a display device according to one or more embodiments of the present disclosure is shown.

[0041] Fig.41 Examples of a sensing area and a non-sensing area of ​​a display device according to one or more embodiments of the present disclosure are shown.

[0042] Fig.42 Shows Fig.41 An example of a first display area and a second display area of ​​a display device.

[0043] Fig.43 Shows the settings in Fig.41 An example of a readout line in a first display area of ​​a display device.

[0044] Fig.44 Shows the settings in Fig.41 An example of a readout line in a second display area of ​​a display device.

[0045] Fig.45 Examples of a sensing area and a non-sensing area of ​​a display device according to one or more embodiments of the present disclosure are shown.

[0046] Fig.46 Shows Fig.45 An example of a first display area and a second display area of ​​a display device.

[0047] Fig.47 Shows the settings in Fig.45 An example of a readout line in a first display area of ​​a display device.

[0048] Fig.48 Shows the settings in Fig.45 An example of a readout line in a second display area of ​​a display device.

[0049] Fig.49Examples of a sensing area and a non-sensing area of ​​a display device according to one or more embodiments of the present disclosure are shown.

[0050] Fig.50 Shows Fig.49 An example of a first display area and a second display area of ​​a display device.

[0051] Fig.51 Shows the settings in Fig.49 An example of a readout line in a first display area of ​​a display device.

[0052] Fig.52 Shows the settings in Fig.49 An example of a readout line in a second display area of ​​a display device.

[0053] Fig.53 A layout diagram of a first conductive layer, a first active layer, and a second conductive layer of a display device according to one or more embodiments of the present disclosure is shown.

[0054] Fig.54 A layout diagram of a third conductive layer of a display device according to one or more embodiments of the present disclosure is shown.

[0055] Fig.55 A layout diagram of a sixth conductive layer of a display device according to one or more embodiments of the present disclosure is shown.

[0056] Fig.56 Shows Fig.55 Layout diagram of the seventh conductive layer of a display device.

[0057] Fig.57 A layout diagram of a sixth conductive layer of a display device according to an embodiment of the present disclosure is shown.

[0058] Fig.58 Shows Fig.57 Layout diagram of the seventh conductive layer of a display device.

[0059] Fig.59 A layout diagram of a sixth conductive layer of a display device according to one or more embodiments of the present disclosure is shown.

[0060] Fig.60 A block diagram of an electronic device according to one or more embodiments of the present disclosure is shown.

[0061] Fig.61 Shows the Fig.60 The electronic device is implemented as an example of a smart phone.

[0062] Fig.62 It shows Fig.60An example in which the electronic device is implemented as a tablet personal computer. DETAILED DESCRIPTION

[0063] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always represent the same elements. However, the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments illustrated herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals represent the same elements, and therefore, redundant descriptions thereof may not be repeated.

[0064] When a specific embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0065] In the accompanying drawings, for clarity, the relative size, thickness and ratio of elements, layers and regions can be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below", "below", "lower", "below", "above", "upper" etc. can be used in this article to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It will be understood that, in addition to the orientations depicted in the accompanying drawings, spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "below" or "below" of other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can cover both upper and lower orientations. The device can have another orientation (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly.

[0066] In the drawings, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0067] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may be referred to as the second element, second component, second region, second layer or second part.

[0068] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to another element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to the other layer, region, or element with one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0069] The terms used herein are used for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "includes", "including", "has", "have", and "having" specify the existence of the features, wholes, steps, operations, elements and / or parts described, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or their combinations. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. For example, the statement "A and / or B" means A, B, or A and B. Statements such as "at least one of..." modify the entire element list when after the element list, rather than modifying the individual elements in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0070] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. In addition, when describing embodiments of the present disclosure, the use of "may" means "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0071] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0072] Figure 1 A block diagram of a display device according to one or more embodiments of the present disclosure is shown.

[0073] exist Figure 1 For ease of illustration, connecting lines and connecting parts that are described in more detail below are not shown.

[0074] refer to Figure 1 , the display device may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a data driver 400, an emission driver 500, a readout circuit 600, and a reset driver 700. In an embodiment, the drive controller 200 and the data driver 400 may be integrated together on a single chip. In an embodiment, the drive controller 200, the data driver 400, and the readout circuit 600 may be integrated together into one chip.

[0075] The display panel 100 may include a display area DA for displaying an image, and a non-display area NDA disposed adjacent to the display area DA. In an embodiment, the gate driver 300 and the emission driver 500 may be installed in the non-display area NDA.

[0076] The display panel 100 may include a plurality of pixel gate lines PGL, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of sub-pixels SP electrically connected to the pixel gate lines PGL, the data lines DL, and the emission lines EL. The pixel gate lines PGL and the emission lines EL may extend in a direction crossing the data lines DL.

[0077] The display panel 100 may include a plurality of sensing gate lines SGL, a reset line RSL, a plurality of readout lines RL, and a plurality of optical sensors LS electrically connected to the sensing gate lines SGL, the reset lines RSL, and the readout lines RL.

[0078] In this embodiment, the sensing gate line SGL is Figure 1 3 is shown as being connected to the gate driver 300, but the present disclosure is not limited thereto. For example, the display panel driver may further include a separate driver that drives the sensing gate line SGL.

[0079] In this embodiment, the reset line RSL is Figure 1 3 is shown as being connected to the reset driver 700, but the present disclosure is not limited thereto. For example, the reset line RSL may be driven by a separate driver that drives the gate driver 300, the emission driver 500, or the sensing gate line SGL instead of the reset driver 700.

[0080] The drive controller 200 may receive input image data IMG and an input control signal CONT from a processor (e.g., a graphics processing unit (GPU), etc.). For example, the input image data IMG may include red image data, green image data, and blue image data. In an embodiment, the input image data IMG may also include white image data. For another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0081] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , a fifth control signal CONT5 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0082] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and may output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0083] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and may output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0084] The driving controller 200 may receive input image data IMG and an input control signal CONT to generate a data signal DATA. The driving controller 200 may output the data signal DATA to the data driver 400.

[0085] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT, and may output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0086] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the readout circuit 600 based on the input control signal CONT, and may output the fourth control signal CONT4 to the readout circuit 600 .

[0087] The driving controller 200 may generate a fifth control signal CONT5 for controlling the operation of the reset driver 700 based on the input control signal CONT, and may output the fifth control signal CONT5 to the reset driver 700 .

[0088] The gate driver 300 may generate a gate signal for driving the pixel gate line PGL and the sensing gate line SGL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the pixel gate line PGL and the sensing gate line SGL. For example, the gate driver 300 may sequentially output the gate signal to the pixel gate line PGL and the sensing gate line SGL.

[0089] The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200. The data driver 400 may generate a data voltage obtained by converting the data signal DATA into an analog voltage. The data driver 400 may output the data voltage to the data line DL.

[0090] The emission driver 500 may generate emission signals for driving the emission lines EL in response to the third control signal CONT3 received from the driving controller 200. The emission driver 500 may output the emission signals to the emission lines EL. For example, the emission driver 500 may sequentially output the emission signals to the emission lines EL.

[0091] In response to the fourth control signal CONT4 received from the drive controller 200, the readout circuit 600 may generate sensing information based on the sensing signal received from the readout line RL. For example, the sensing information may correspond to a fingerprint image. The processor or the drive controller 200 may use the sensing information provided from the readout circuit 600 to perform a user authentication function.

[0092] The reset driver 700 may provide a reset signal to the reset line RSL in response to a fifth control signal CONT5 received from the driving controller 200. In an embodiment, the reset driver 700 may be commonly connected to all optical sensors LS through the reset line RSL. In another embodiment, the reset driver 700 may be connected to each of the optical sensors LS through a plurality of reset lines RSL.

[0093] The sub-pixel SP may include a light emitting element. The light emitting element may be a light emitting diode. The light emitting element may include an organic light emitting diode, an inorganic light emitting diode and / or a quantum dot / quantum well light emitting diode. The light emitting element may emit light in one of the first color, the second color and the third color.

[0094] The optical sensor LS may include a light receiving element. In an embodiment, the light receiving element may be a photodiode. In another embodiment, the light receiving element may be composed of a phototransistor.

[0095] The light emitted from the light emitting element may be reflected by the user's fingerprint to be applied to the light receiving element adjacent to the light emitting element. In addition, the optical sensor LS may generate a sensing signal corresponding to the amount of light applied to the light receiving element. The processor or the drive controller 200 may distinguish between the valleys and ridges of the fingerprint according to the intensity of the sensing signal, and may obtain an image of the user's fingerprint.

[0096] Figure 2 Shows Figure 1 A circuit diagram of an example of a sub-pixel of a display device.

[0097] refer to Figure 2 , the sub-pixel SP may include a light emitting element EE and a pixel driving circuit PC for driving the light emitting element EE.

[0098] The pixel driving circuit PC may include a first pixel transistor TP1 (e.g., a driving transistor), which includes a control electrode connected to the first pixel node PN1, a first electrode connected to the second pixel node PN2, and a second electrode connected to the third pixel node PN3. The pixel driving circuit PC may also include a second pixel transistor TP2, which includes a control electrode receiving a write gate signal GW, a first electrode receiving a data voltage VDATA, and a second electrode connected to the second pixel node PN2. The pixel driving circuit PC may also include a third pixel transistor TP3, which includes a control electrode receiving a compensation gate signal GC, a first electrode connected to the third pixel node PN3, and a second electrode connected to the first pixel node PN1. The pixel driving circuit PC may also include a fourth pixel transistor TP4, which includes a control electrode receiving an initialization gate signal GI, a first electrode receiving a first initialization voltage VINT, and a second electrode connected to the first pixel node PN1. The pixel driving circuit PC may also include a fifth pixel transistor TP5, which includes a control electrode receiving an emission signal EM, a first electrode receiving a first power supply voltage ELVDD (e.g., a high power supply voltage), and a second electrode connected to the second pixel node PN2. The pixel driving circuit PC may further include a sixth pixel transistor TP6, which includes a control electrode receiving an emission signal EM, a first electrode connected to a third pixel node PN3, and a second electrode connected to a fourth pixel node PN4. The pixel driving circuit PC may further include a seventh pixel transistor TP7, which includes a control electrode receiving a bias gate signal GB (or a write gate signal GW[N-1] of a previous pixel row), a first electrode receiving a second initialization voltage VAINT (e.g., an anode initialization voltage), and a second electrode connected to the fourth pixel node PN4. The pixel driving circuit PC may further include a storage capacitor CST, which includes a first electrode receiving a first power supply voltage ELVDD and a second electrode connected to the first pixel node PN1. The light emitting element EE may include a first electrode (e.g., an anode electrode) connected to the fourth pixel node PN4, and a second electrode (e.g., a cathode electrode) for receiving a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0099] However, the present disclosure is not limited to Figure 2 For example, each of the sub-pixels SP may have a 3T1C structure including three transistors and one capacitor, a 5T2C structure including five transistors and two capacitors, a 7T1C structure including seven transistors and one capacitor, and / or a 9T1C structure including nine transistors and one capacitor.

[0100] The first pixel transistor TP1, the second pixel transistor TP2, the fifth pixel transistor TP5, the sixth pixel transistor TP6, and the seventh pixel transistor TP7 can be implemented as p-channel metal oxide semiconductor (PMOS) transistors. In this case, the low voltage level can be an activation level, and the high voltage level can be a non-activation level. For example, when the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor can be turned on. For example, when the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor can be turned off.

[0101] The third pixel transistor TP3 and the fourth pixel transistor TP4 can be implemented as n-channel metal oxide semiconductor (NMOS) transistors. In this case, the high voltage level can be an activation level, and the low voltage level can be a non-activation level. For example, when the signal applied to the control electrode of the NMOS transistor has a high voltage level, the NMOS transistor can be turned on. For example, when the signal applied to the control electrode of the NMOS transistor has a low voltage level, the NMOS transistor can be turned off.

[0102] However, the present disclosure is not limited thereto. For example, the first pixel transistor TP1, the second pixel transistor TP2, and the fifth pixel transistor TP5, the sixth pixel transistor TP6, and the seventh pixel transistor TP7 may be implemented as NMOS transistors. For example, the third pixel transistor TP3 and the fourth pixel transistor TP4 may be implemented as PMOS transistors.

[0103] For example, in the initialization period, the initialization gate signal GI may have an activation level, and the fourth pixel transistor TP4 may be turned on. Therefore, the first initialization voltage VINT may be applied to the first pixel node PN1. In other words, the control electrode (eg, storage capacitor CST) of the first pixel transistor TP1 may be initialized.

[0104] For example, in the data writing period, the writing gate signal GW and the compensation gate signal GC may have an activation level, and the second pixel transistor TP2 and the third pixel transistor TP3 may be turned on. Therefore, the data voltage VDATA may be written to the storage capacitor CST.

[0105] For example, in the anode initialization period, the bias gate signal GB may have an activation level and the seventh pixel transistor TP7 may be turned on. Therefore, the second initialization voltage VAINT may be applied to the first electrode (eg, anode electrode) of the light emitting element EE.

[0106] For example, in the light emission period, the emission signal EM may have an activation level, and the fifth pixel transistor TP5 and the sixth pixel transistor TP6 may be turned on. Therefore, the first power supply voltage ELVDD is applied to the first pixel transistor TP1 to generate a drive current, and the drive current may be applied to the light emitting element EE. In other words, the light emitting element EE may emit light having a brightness corresponding to the drive current.

[0107] Figure 3 Shows Figure 1 A circuit diagram of an example of an optical sensor of a display device.

[0108] refer to Figure 1 and Figure 3 , the optical sensor LS may include a light receiving element OPD, and a sensor driving circuit LC that drives the light receiving element OPD.

[0109] The sensor driving circuit LC may include a first sensing transistor TS1 that generates a sensing signal, and a second sensing transistor TS2 that provides the sensing signal to the readout line RL in response to the sensing gate signal GS. The light receiving element OPD is connected to the control node of the first sensing transistor TS1. The optical sensor LS may further include a third sensing transistor TS3 that initializes the control node of the first sensing transistor TS1 in response to the reset signal RS. For example, the sensing signal may be a current generated by the first sensing transistor TS1.

[0110] For example, the first sensing transistor TS1 includes a control electrode connected to the first sensing node SN1, a first electrode for receiving the common voltage VCOM, and a second electrode connected to the first electrode of the second sensing transistor TS2. The second sensing transistor TS2 includes a control electrode for receiving a sensing gate signal GS, a first electrode connected to the second electrode of the first sensing transistor TS1, and a second electrode connected to the readout line RL. The light receiving element OPD may include a first electrode connected to the first sensing node SN1 and a second electrode for receiving the bias voltage VBIAS. The third sensing transistor TS3 may include a control electrode for receiving a reset signal RS, a first electrode for receiving a reset voltage VRST, and a second electrode connected to the first sensing node SN1.

[0111] In an embodiment, the first and second sensing transistors TS1 and TS2 may be implemented as PMOS transistors, and the third sensing transistor TS3 may be implemented as an NMOS transistor. However, the present disclosure is not limited thereto.

[0112] For example, in the reset period, the reset signal RS may have an activation level, and the sensing gate signal GS may have a non-activation level. Therefore, the third sensing transistor TS3 may be turned on, and the second sensing transistor TS2 may be turned off. In addition, the reset voltage VRST may be applied to the first sensing node SN1. In other words, the first sensing node SN1 and the first electrode of the light receiving element OPD may be initialized.

[0113] For example, in the light receiving period, the reset signal RS and the sensing gate signal GS may have a non-activated level. Therefore, the second sensing transistor TS2 and the third sensing transistor TS3 may be turned off. In addition, when light is applied, the light receiving element OPD generates a current in a direction toward the first sensing node SN1, and the voltage of the first sensing node SN1 may be reduced. Therefore, the intensity of the sensing signal generated in the sensing conduction period described in more detail below may vary. In addition, because the amount of light applied to the light receiving element OPD varies according to the valleys and ridges of the fingerprint, the intensity of the sensing signal may vary according to the valleys and ridges of the fingerprint.

[0114] For example, in the sensing on period, the reset signal RS may have an inactive level, and the sensing gate signal GS may have an active level. Therefore, the second sensing transistor TS2 may be turned on, and the third sensing transistor TS3 may be turned off. In addition, the first sensing transistor TS1 may generate a sensing signal corresponding to its gate-source voltage. The sensing signal may be applied to the readout circuit 600 through the readout line RL.

[0115] In an embodiment, the common voltage VCOM may be the second initialization voltage VAINT. In an embodiment, the bias voltage VBIAS may be the second power supply voltage ELVSS.

[0116] In an embodiment, the sensing gate signal GS may be the writing gate signal GW. In this case, the pixel gate line PGL to which the writing gate signal GW is applied may be the same as the sensing gate line SGL to which the sensing gate signal GS is applied.

[0117] Figure 4 Shows Figure 1 Examples of sensing areas and non-sensing areas of a display device.

[0118] refer to Figures 1 to 4 , the display area DA may include a sensing area SA including a sub-pixel SP and an optical sensor LS, and a non-sensing area NSA including the sub-pixel SP. For example, the display area DA may include a pixel driving circuit PC and a sensor driving circuit LC, while the non-sensing area NSA may include the pixel driving circuit PC and may not include the sensor driving circuit LC.

[0119] The non-sensing area NSA may be adjacent to the connection portion FO in the first direction DR1. The sensing area SA may be adjacent to the non-sensing area NSA in the first direction DR1. For example, the non-sensing area NSA may be formed between the sensing area SA and the connection portion FO.

[0120] The display device may include a connection portion FO electrically connecting the readout line RL to the readout circuit 600. The connection portion FO may electrically connect not only the readout line RL to the readout circuit 600 but also the data line DL to the data driver 400.

[0121] In an embodiment, a width W1 of a first surface (e.g., a first end) of the connection portion FO adjacent to the display area DA may be longer than a width W2 of a second surface (e.g., a second end) thereof connected to the readout circuit 600 (or the data driver 400). The width of the readout circuit 600 (or the data driver 400) may be narrower (e.g., very narrow) than the width of the display area DA. Therefore, the connection portion FO may allow the readout line RL (or the data line DL) of the display area DA to be properly connected to the readout circuit 600 (or the data driver 400).

[0122] Figure 5 Shows Figure 1 An example of a first display area and a second display area of ​​a display device. Figure 6 Shows the settings in Figure 1 An example of a readout line in a first display area of ​​a display device. Figure 7 Shows the settings in Figure 1 An example of a readout line in a second display area of ​​a display device.

[0123] refer to Figures 1 to 7 , the readout line RL extends in the first direction DR1. The display area DA includes a first display area DA1 and a second display area DA2, wherein the first display area DA1 is adjacent to the connection portion FO in the first direction DR1. The connection lines CL1 and CL2 may connect the readout line RL of the second display area DA2 to the connection portion FO.

[0124] The readout line RL of the first display area DA1 may extend in the first direction DR1 to be directly connected to the connection portion FO. However, the readout line RL of the second display area DA2 may be connected to the connection portion FO using additional wiring. Therefore, the readout line RL of the second display area DA2 may be connected to the connection portion FO through the connection lines CL1 and CL2.

[0125] The connection lines CL1 and CL2 connecting the readout line RL and the connection part FO to each other may be disposed in the non-sensing area NSA. When the connection lines CL1 and CL2 are disposed in the sensing area SA, coupling may occur between the connection lines CL1 and CL2 and the sensor driving circuit LC. In this case, the sensing signal may be distorted, and the accuracy of sensing by the optical sensor LS may be deteriorated.

[0126] For example, the readout line RL extends in the first direction DR1. The connection lines CL1 and CL2 include a first connection line CL1 and a second connection line CL2. The first connection line CL1 may extend in the second direction DR2 crossing the first direction DR1 and may be connected to the readout line RL through the first line contact hole LCNT1. The second connection line CL2 may extend in the first direction DR1 and may be connected to the first connection line CL1 through the second line contact hole LCNT2. For example, the second connection line CL2 may be connected to the connection portion FO.

[0127] In an embodiment, the readout line RL, the first connection line CL1, and the second connection line CL2 may be formed in different layers from each other. In an embodiment, the first line contact hole LCNT1 and the second line contact hole LCNT2 may be a channel contact hole and / or a via contact hole. For example, when an organic film is disposed between the readout line RL and the first connection line CL1, the first line contact hole LCNT1 may be a channel contact hole. As another example, when an inorganic film is disposed between the readout line RL and the first connection line CL1, the first line contact hole LCNT1 may be a via contact hole. As another example, when an organic film and an inorganic film are disposed between the readout line RL and the first connection line CL1, the first line contact hole LCNT1 may include both a channel contact hole and a via contact hole. For example, when an organic film is disposed between the first connection line CL1 and the second connection line CL2, the second line contact hole LCNT2 may be a channel contact hole. As another example, when an inorganic film is disposed between the first connection line CL1 and the second connection line CL2, the second line contact hole LCNT2 may be a via contact hole. As another example, when the organic film and the inorganic film are disposed between the first and second connection lines CL1 and CL2 , the second line contact hole LCNT2 may include both a channel contact hole and a via contact hole.

[0128] Figures 8 to 23 Shows Figure 1 Layout diagram of an example of a sensing area of ​​a display device.

[0129] refer to Figures 2 to 4 and Figure 8The sensing area SA may include a first area R1 including a pixel driving circuit PC and a second area R2 adjacent to the first area R1 and including a sensor driving circuit LC. The display device may include a first conductive layer 310 , a first active layer 320 , and a second conductive layer 330 .

[0130] The first conductive layer 310 and the second conductive layer 330 may include metals, alloys, conductive metal oxides, transparent conductive materials, etc. These may be used alone or in any suitable combination with each other.

[0131] The first active layer 320 may include a metal oxide semiconductor (eg, indium gallium zinc oxide (IGZO)), an inorganic semiconductor (eg, amorphous silicon or polycrystalline silicon), or an organic semiconductor.

[0132] The first conductive layer 310 may include a 1-1th conductive pattern 311. A portion of the 1-1th conductive pattern 311 may form a back gate electrode of the first pixel transistor TP1.

[0133] The first active layer 320 may be disposed on the first conductive layer 310. The first active layer 320 may include a 1-1th active pattern 321 and a 1-2th active pattern 322. The second conductive layer 330 may be disposed on the first active layer 320. The second conductive layer 330 may include a 2-1th conductive pattern 331, a 2-2nd conductive pattern 332, and a 2-3rd conductive pattern 333.

[0134] The 1-1 active pattern 321 and the portion of the 2-1 conductive pattern 331 that overlaps the 1-1 active pattern 321 may configure the second pixel transistor TP2, the seventh pixel transistor TP7, and the second sensing transistor TS2 (e.g., the control electrodes of the second pixel transistor TP2, the seventh pixel transistor TP7, and the second sensing transistor TS2). For example, the 2-1 conductive pattern 331 may be a pixel gate line PGL to which a write gate signal GW is applied.

[0135] Portions of the 1-1 active pattern 321 and the 2-2 conductive pattern 332 overlapping the 1-1 active pattern 321 may configure the first pixel transistor TP1 (eg, a control electrode of the first pixel transistor TP1 ).

[0136] The portions of the 1-1 active pattern 321 and the 2-3 conductive pattern 333 that overlap the 1-1 active pattern 321 may configure the fifth pixel transistor TP5 and the sixth pixel transistor TP6 (e.g., the control electrodes of the fifth pixel transistor TP5 and the sixth pixel transistor TP6). For example, the 2-3 conductive pattern 333 may be an emission line EL to which an emission signal EM is applied.

[0137] Portions of the 1-2 th active pattern 322 and the 2-4 th conductive pattern 334 overlapping the 1-2 th active pattern 322 may configure the first sensing transistor TS1 (eg, a control electrode of the first sensing transistor TS1 ).

[0138] The 1-2 th active pattern 322 and a portion of the 2-1 th conductive pattern 331 overlapping the 1-2 th active pattern 322 may configure the second sensing transistor TS2 (eg, a control electrode of the second sensing transistor TS2 ).

[0139] refer to Figures 2 to 4 and Figures 8 to 10 , the display device may include a third conductive layer 340 .

[0140] The third conductive layer 340 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. These may be used alone or in any suitable combination with each other.

[0141] The third conductive layer 340 may be disposed on the second conductive layer 330. The third conductive layer 340 may include a 3-1st conductive pattern 341, a 3-2nd conductive pattern 342, a 3-3rd conductive pattern 343, and a 3-4th conductive pattern 344.

[0142] The 3-1st conductive pattern 341 and the 2-2nd conductive pattern 332 may configure a storage capacitor CST. The 3-2nd conductive pattern 342 may be a reset line RSL to which a reset signal RS is applied. The 3-3rd conductive pattern 343 may be a pixel gate line PGL to which a compensation gate signal GC is applied. The 3-4th conductive pattern 344 may be a pixel gate line PGL to which an initialization gate signal GI is applied.

[0143] refer to Figures 2 to 4 and Figures 8 to 12 , the display device may include a second active layer 350 .

[0144] The second active layer 350 may include a metal oxide semiconductor (eg, indium gallium zinc oxide), an inorganic semiconductor (eg, amorphous silicon or polycrystalline silicon), or an organic semiconductor.

[0145] The second active layer 350 may be disposed on the third conductive layer 340. The second active layer 350 may include a 2-1st active pattern 351 and a 2-2nd active pattern 352.

[0146] refer to Figures 2 to 4 and Figures 8 to 14 , the display device may include a fourth conductive layer 410 .

[0147] The fourth conductive layer 410 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. These may be used alone or in any suitable combination with each other.

[0148] The fourth conductive layer 410 may be disposed on the second active layer 350. The fourth conductive layer 410 may include a 4-1st conductive pattern 411, a 4-2nd conductive pattern 412, and a 4-3rd conductive pattern 413.

[0149] The 4-1st conductive pattern 411 and the 3-2nd conductive pattern 342 may be connected to each other through a channel contact hole and / or a via contact hole in the display area DA or the non-display area NDA. The 4-2nd conductive pattern 412 and the 3-3rd conductive pattern 343 may be connected to each other through a channel contact hole and / or a via contact hole in the display area DA or the non-display area NDA. The 4-3rd conductive pattern 413 and the 3-4th conductive pattern 344 may be connected to each other through a channel contact hole and / or a via contact hole in the display area DA or the non-display area NDA.

[0150] The 4-1st conductive pattern 411 may be a reset line RSL to which a reset signal RS is applied. The 4-2nd conductive pattern 412 may be a pixel gate line PGL to which a compensation gate signal GC is applied. The 4-3rd conductive pattern 413 may be a pixel gate line PGL to which an initialization gate signal GI is applied.

[0151] The 2-1st active pattern 351 and a portion of the 4-2nd conductive pattern 412 overlapping the 2-1st active pattern 351 (or a portion of the 3-3rd conductive pattern 343 overlapping the 2-1st active pattern 351 ) may configure the third pixel transistor TP3 (eg, a control electrode of the third pixel transistor TP3 ).

[0152] The 2-1st active pattern 351 and a portion of the 4-3rd conductive pattern 413 overlapping the 2-1st active pattern 351 (or a portion of the 3-4th conductive pattern 344 overlapping the 2-1st active pattern 351 ) may configure the fourth pixel transistor TP4 (eg, a control electrode of the fourth pixel transistor TP4 ).

[0153] The 2-2nd active pattern 352 and a portion of the 4-1st conductive pattern 411 overlapping the 2-2nd active pattern 352 (or a portion of the 3-2nd conductive pattern 342 overlapping the 2-2nd active pattern 352 ) may configure the third sensing transistor TS3 (eg, a control electrode of the third sensing transistor TS3 ).

[0154] The display device may include a first contact hole CNT1. The first contact hole CNT1 may connect the second active layer 350 to a fifth conductive layer (eg, Fig.16420 in the figure). For example, the first contact hole CNT1 may be a channel contact hole and / or a via contact hole. For example, the first contact hole CNT1 may connect the second active layer 350 to a fifth conductive layer (eg, Fig.16 420 in the above table).

[0155] refer to Fig.15 , the display device may include a second contact hole CNT2. The second contact hole CNT2 may connect the first active layer 320, the second conductive layer 330, and the third conductive layer 340 to the fifth conductive layer 420, which will be described in more detail below. For example, the second contact hole CNT2 may be a channel contact hole and / or a via contact hole.

[0156] refer to Figures 2 to 4 and Figures 8 to 17 , the display device may include a fifth conductive layer 420 .

[0157] The fifth conductive layer 420 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. These may be used alone or in any suitable combination with each other.

[0158] The fifth conductive layer 420 may be disposed on the fourth conductive layer 410. The fifth conductive layer 420 may include a 5-1st conductive pattern 421, a 5-2nd conductive pattern 422, a 5-3rd conductive pattern 423, a 5-4th conductive pattern 424, a 5-5th conductive pattern 425, a 5-6th conductive pattern 426, a 5-7th conductive pattern 427, a 5-8th conductive pattern 428, and a 5-9th conductive pattern 429.

[0159] The 5-1st conductive pattern 421 may be a reset voltage line to which a reset voltage VRST is applied. The 5-6th conductive pattern 426 may be an anode initialization voltage line to which a second initialization voltage VAINT is applied. The 5-7th conductive pattern 427 may be a gate initialization voltage line to which a first initialization voltage VINT is applied.

[0160] The 5-2nd conductive pattern 422 may configure the second electrode of the sixth pixel transistor TP6 or the first electrode of the light emitting element EE. The 5-3rd conductive pattern 423 may configure the first electrode of the fifth pixel transistor TP5. The 5-4th conductive pattern 424 may configure the first electrode of the third pixel transistor TP3, the second electrode of the first pixel transistor TP1, or the first electrode of the sixth pixel transistor TP6. The 5-5th conductive pattern 425 may configure the second electrode of the storage capacitor CST, the control electrode of the first pixel transistor TP1, or the second electrode of the fourth pixel transistor TP4. The 5-8th conductive pattern 428 may configure the second electrode of the third sensing transistor TS3 or the first electrode of the light receiving element OPD. The 5-9th conductive pattern 429 may form the second electrode of the second sensing transistor TS2 or the readout line RL.

[0161] The display device may include a third contact hole CNT3. The third contact hole CNT3 may connect the fifth conductive layer 420 to a sixth conductive layer (eg, Fig.18 430), a seventh conductive layer (eg, Fig. 20 440) or an eighth conductive layer (eg, Fig. 22 450 in the figure). When the third contact hole CNT3 connects the fifth conductive layer 420 to the seventh conductive layer (eg, Fig. 20 440) or the eighth conductive layer 450, the third contact hole CNT3 may be connected to the fourth contact hole CNT4 (see Fig.18 For example, the third contact hole CNT3 may be a channel contact hole and / or a via contact hole.

[0162] refer to Figures 2 to 4 and Figures 8 to 19 , the display device may include a sixth conductive layer 430 .

[0163] The sixth conductive layer 430 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. These may be used alone or in any suitable combination with each other.

[0164] The sixth conductive layer 430 may be disposed on the fifth conductive layer 420. The sixth conductive layer 430 may include a 6-1st conductive pattern 431, a 6-2nd conductive pattern 432, a 6-3rd conductive pattern 433, a 6-4th conductive pattern 434, a 6-5th conductive pattern 435, and a 6-6th conductive pattern 436.

[0165] The 6-1st conductive pattern 431 may be a first power supply voltage line to which a first power supply voltage ELVDD is applied. The 6-3rd conductive pattern 433 may be a data line DL to which a data voltage VDATA is applied. The 6-4th conductive pattern 434 may be a readout line RL to which a sensing signal is applied. The 6-5th conductive pattern 435 may be a reset voltage line to which a reset voltage VRST is applied. For example, the 6-5th conductive pattern 435 may be connected to the 5-1st conductive pattern 421 through the third contact hole CNT3.

[0166] The 6-2nd conductive pattern 432 may configure the second electrode of the sixth pixel transistor TP6 or the first electrode of the light emitting element EE. For example, the 6-2nd conductive pattern 432 may be connected to the 5-2nd conductive pattern 422 through the third contact hole CNT3.

[0167] The 6-6th conductive pattern 436 may configure the second electrode of the third sensing transistor TS3 or the first electrode of the light receiving element OPD. For example, the 6-6th conductive pattern 436 may be connected to the 5-8th conductive pattern 428 through the third contact hole CNT3.

[0168] The display device may include a fourth contact hole CNT4. The fourth contact hole CNT4 may connect the sixth conductive layer 430 to a seventh conductive layer (eg, Fig. 20 440) or an eighth conductive layer (eg, Fig. 22 450 in the figure). When the fourth contact hole CNT4 connects the sixth conductive layer 430 to the eighth conductive layer (eg, Fig. 22 450 in FIG. 4), the fourth contact hole CNT4 may be connected to the fifth contact hole CNT5 (see FIG. 450 in FIG. 450 ) which will be described in more detail below. Fig. 20 ). For example, the fourth contact hole CNT4 may be a channel contact hole and / or a via contact hole.

[0169] refer to Figures 2 to 4 and Figures 8 to 21 , the display device may include a seventh conductive layer 440 .

[0170] The seventh conductive layer 440 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. These may be used alone or in any suitable combination with each other.

[0171] The seventh conductive layer 440 may be disposed on the sixth conductive layer 430. The seventh conductive layer 440 may include a 7-1st conductive pattern 441.

[0172] The 7-1st conductive pattern 441 may be a reset voltage line to which a reset voltage VRST is applied. The 7-1st conductive pattern 441 may overlap at least a portion of the readout line RL. For example, the 7-1st conductive pattern 441 may overlap the 6-4th conductive pattern 434. When a portion of the 6-4th conductive pattern 434 overlaps with the 7-1st conductive pattern 441, the influence of coupling on the 6-4th conductive pattern 434 (for example, the influence of coupling on the sensing signal) may be reduced.

[0173] The display device may include a fifth contact hole CNT5. The fifth contact hole CNT5 may connect the fourth contact hole CNT4 to the eighth conductive layer 450 which will be described in more detail below. For example, the fifth contact hole CNT5 may be a channel contact hole and / or a via contact hole.

[0174] refer to Figures 2 to 4 and Figures 8 to 23 , the display device may include an eighth conductive layer 450 .

[0175] The eighth conductive layer 450 may include metal, alloy, conductive metal oxide, transparent conductive material, etc. These may be used alone or in any suitable combination with each other.

[0176] The eighth conductive layer 450 may be disposed on the seventh conductive layer 440. The eighth conductive layer 450 may include an 8-1st conductive pattern 451a, 451b, and 451c, and an 8-2nd conductive pattern 452.

[0177] The 8-1st conductive patterns 451a, 451b and 451c may configure the second electrode of the sixth pixel transistor TP6 or the first electrode of the light emitting element EE. For example, the 8-1st conductive patterns 451a, 451b and 451c may be connected to the 6-2nd conductive pattern 432 through the fourth contact hole CNT4 and the fifth contact hole CNT5.

[0178] In an embodiment, the 8-1st conductive pattern 451a can be configured to be a first electrode of a light-emitting element EE presenting a first color, the 8-1st conductive pattern 451b can be configured to be a first electrode of a light-emitting element EE presenting a second color, and the 8-1st conductive pattern 451c can be configured to be a first electrode of a light-emitting element EE presenting a third color.

[0179] The 8-2nd conductive pattern 452 may configure the second electrode of the third sensing transistor TS3 or the first electrode of the light receiving element OPD. For example, the 8-2nd conductive pattern 452 may be connected to the 6-6th conductive pattern 436 through the fourth contact hole CNT4 and the fifth contact hole CNT5.

[0180] Figures 24 to 39 Shows Figure 1Layout diagram of an example of a non-sensing area of ​​a display device.

[0181] The non-sensing region according to the present embodiment may have the same or substantially the same configuration as that of the sensing region described above, except for the third region R3. Figures 24 to 39 , the same figure numerals and reference numerals are used to denote constituent elements that are the same or substantially the same (or similar) as those described above, and thus, redundant descriptions may not be repeated.

[0182] refer to Figures 2 to 4 as well as Figure 24 to Figure 26 , the non-sensing area NSA may include a first area R1 including a pixel driving circuit PC, and a third area R3 adjacent to the first area R1. The third area R3 corresponds to the second area R2 described above, but may not include the sensor driving circuit LC. Therefore, the third area R3 may not include the 1-2 active pattern (e.g., Figure 8 322) and the 2nd to 4th conductive patterns (e.g., Figure 8 334).

[0183] refer to Figures 2 to 4 and Figures 24 to 31 The third region R3 corresponds to the second region R2 described above, but may not include the sensor driving circuit LC. Therefore, the third region R3 may not include the 2-2 active pattern (eg, Fig.11 352 in ).

[0184] refer to Figures 2 to 4 and Figures 24 to 33 The third region R3 corresponds to the second region R2 described above, but may not include the sensor driving circuit LC. Therefore, the third region R3 may not include the 5th-8th conductive pattern 428 and the 5th-9th conductive pattern 429.

[0185] refer to Figures 2 to 4 and Figures 24 to 35 The third region R3 corresponds to the second region R2 described above, but may not include the sensor driving circuit LC. Therefore, the third region R3 may not include the 6-6 conductive pattern 436.

[0186] In addition, since the third region R3 does not include the sensor driving circuit LC, the third region R3 can sufficiently ensure a space for the readout line RL (for example, a space for the 6-4th conductive pattern 434) when compared with the second region R2. Therefore, the third region R3 can include more readout lines RL (for example, the 6-4th conductive pattern 434) when compared with the second region R2.

[0187] Furthermore, since the third region R3 does not include the sensor driving circuit LC, the influence of coupling on the readout line RL (eg, the influence of coupling on the sensing signal) may be reduced.

[0188] In the present embodiment, the third region R3 is illustrated as including three 6-4th conductive patterns 434 , but the present disclosure is not limited to the number of 6-4th conductive patterns 434 shown in the drawings.

[0189] refer to Figures 2 to 4 and Figures 24 to 39 The third region R3 corresponds to the second region R2 described above, but may not include the sensor driving circuit LC. Therefore, the third region R3 may not include the 8-2nd conductive pattern 452.

[0190] In an embodiment, the size of the first region R1 in the sensing area SA may be smaller than the size of the first region R1 in the non-sensing area NSA. Since the non-sensing area NSA does not include the sensor driving circuit LC, the size of the third region R3 may be smaller than the size of the second region R2. In addition, as the size of the third region R3 decreases, the size of the first region R1 in the non-sensing area NSA may increase.

[0191] In an embodiment, the number of the readout lines RL (eg, the 6 - 4 th conductive pattern 434 ) disposed in the third region R3 may increase as the resolution of the display panel 100 increases.

[0192] Fig.40 An example of a readout line provided in a second display area of ​​a display device according to one or more embodiments of the present disclosure is shown.

[0193] Since the display device according to the present embodiment may have the same structure as the above reference except for the readout line RL and the connection lines CL1 and CL2, Figure 1 The configuration of the display device described is the same or substantially the same configuration, and thus the same reference numerals and reference numerals are used to denote constituent elements that are the same or substantially the same (or similar) as those described above. Therefore, a redundant description may not be repeated.

[0194] refer to Fig.40 , the first connection line CL1 and the second connection line CL2 may form a grid structure. For example, the first connection line CL1 may extend in the second direction DR2. For example, the second connection line CL2 may extend in the first direction DR1. For example, the first connection line CL1 may extend to cross or intersect with the second connection line CL2.

[0195] The readout line RL and the first connection line CL1 may form a grid structure. For example, the readout line RL may extend in the first direction DR1. For example, the first connection line CL1 may extend in the second direction DR2. For example, the readout line RL may extend to cross or intersect with the first connection line CL1.

[0196] Fig.41 Examples of a sensing area and a non-sensing area of ​​a display device according to one or more embodiments of the present disclosure are shown.

[0197] Because in addition to the sensing area SA, the non-sensing area NSA, the readout line RL, and the connection lines CL1, CL2, CL3, and CL4 (see Fig.44 ), the display device according to this embodiment may have the same Figure 1 The configuration of the display device described is the same or substantially the same configuration, and thus the same reference numerals and reference numerals are used to denote constituent elements that are the same or substantially the same (or similar) as those described above. Therefore, a redundant description may not be repeated.

[0198] refer to Figures 1 to 3 and Fig.41 , the non-sensing area NSA may be adjacent to the connection portion FO in the first direction DR1. The non-sensing area NSA may be formed to surround the sensing area SA (eg, around the periphery of the sensing area SA).

[0199] Fig.42 Shows Fig.41 An example of a first display area and a second display area of ​​a display device. Fig.43 Shows the settings in Fig.41 An example of a readout line in a first display area of ​​a display device. Fig.44 Shows the settings in Fig.41 An example of a readout line in a second display area of ​​a display device.

[0200] refer to Figures 1 to 3 and Figure 41 to Figure 44 , the connection lines CL1, CL2, CL3, and CL4 connecting the readout line RL and the connection part FO to each other may be disposed in the non-sensing area NSA. When the connection lines CL1, CL2, CL3, and CL4 are disposed in the sensing area SA, coupling may occur between the connection lines CL1, CL2, CL3, and CL4 and the sensor driving circuit LC. In this case, the sensing signal may be distorted, and the accuracy of sensing performed by the optical sensor LS may be deteriorated.

[0201] For example, the readout line RL may extend in the first direction DR1. The connection lines CL1, CL2, CL3, and CL4 may include a first connection line CL1, a second connection line CL2, a third connection line CL3, and a fourth connection line CL4. The first connection line CL1 may extend in a second direction DR2 intersecting the first direction DR1, and may be connected to the readout line RL through a first line contact hole LCNT1. The second connection line CL2 may extend in the first direction DR1, and may be connected to the first connection line CL1 through a second line contact hole LCNT2. The third connection line CL3 may extend in the second direction DR2, and may be connected to the second connection line CL2 through a third line contact hole LCNT3. The fourth connection line CL4 may extend in the first direction DR1, and may be connected to the third connection line CL3 through a fourth line contact hole LCNT4. For example, the fourth connection line CL4 may be connected to the connection portion FO.

[0202] In an embodiment, the fourth connection line CL4 may form a mesh structure with the third connection line CL3. In an embodiment, the third connection line CL3 may form a mesh structure with the second connection line CL2. In an embodiment, the second connection line CL2 may form a mesh structure with the first connection line CL1. In an embodiment, the first connection line CL1 may form a mesh structure with the readout line RL.

[0203] In an embodiment, the readout line RL may be formed at the same layer as the layer of the second connection line CL2 (e.g., therein). In an embodiment, the first connection line CL1 may be formed at the same layer as the layer of the third connection line CL3 (e.g., therein). In an embodiment, the fourth connection line CL4 may be formed at a layer different from the layers of the readout line RL and the first connection line CL1, the second connection line CL2, and the third connection line CL3 (e.g., therein). However, the present disclosure is not limited thereto, and the layers in which the connection lines CL1, CL2, CL3, and CL4 and the readout line RL are formed may be variously modified as needed or desired.

[0204] In an embodiment, the first line contact hole LCNT1, the second line contact hole LCNT2, the third line contact hole LCNT3 and the fourth line contact hole LCNT4 may be a channel contact hole and / or a via contact hole. For example, when the organic film is disposed between the second connection line CL2 and the third connection line CL3, the third line contact hole LCNT3 may be a channel contact hole. When the inorganic film is disposed between the second connection line CL2 and the third connection line CL3, the third line contact hole LCNT3 may be a via contact hole. When the organic film and the inorganic film are disposed between the second connection line CL2 and the third connection line CL3, the third line contact hole LCNT3 may include both a channel contact hole and a via contact hole. For example, when the organic film is disposed between the third connection line CL3 and the fourth connection line CL4, the fourth line contact hole LCNT4 may be a channel contact hole. When the inorganic film is disposed between the third connection line CL3 and the fourth connection line CL4, the fourth line contact hole LCNT4 may be a via contact hole. When the organic film and the inorganic film are disposed between the third and fourth link lines CL3 and CL4 , the fourth line contact hole LCNT4 may include both a channel contact hole and a via contact hole.

[0205] As the length of the connection lines CL1, CL2, CL3, and CL4 increases, the width of the connection lines CL1, CL2, CL3, and CL4 may increase. The load of each connection line CL1, CL2, CL3, or CL4 may vary according to the length of the connection lines CL1, CL2, CL3, and CL4. In other words, the intensity of the sensing signal may vary according to the connection lines CL1, CL2, CL3, and CL4. Therefore, as the length of the connection lines CL1, CL2, CL3, and CL4 increases, the display device may minimize or reduce the load difference between the connection lines CL1, CL2, CL3, and CL4 by setting a line with a wider width.

[0206] For example, the first connection line CL1 may become longer as it goes outward. In this case, the width of the first connection line CL1 may become wider toward the outside.

[0207] For example, the second connection line CL2 may become longer as it goes outward. In this case, the width of the second connection line CL2 may become wider toward the outside.

[0208] For example, the closer the fourth connection line CL4 is to the central portion of the connection portion FO, the longer the fourth connection line CL4 may become. In this case, the width of the fourth connection line CL4 may become wider toward the central portion of the connection portion FO.

[0209] In an embodiment, the lengths of the connected connection lines CL1, CL2, CL3, and CL4 may be increasingly longer toward the outside. In this case, the widths of the first connection line CL1, the second connection line CL2, the third connection line CL3, and the fourth connection line CL4 may be increasingly wider toward the outside.

[0210] Fig.45 Examples of a sensing area and a non-sensing area of ​​a display device according to one or more embodiments of the present disclosure are shown. Fig.46 Shows Fig.45 An example of a first display area and a second display area of ​​a display device. Fig.47 Shows the settings in Fig.45 An example of a readout line in a first display area of ​​a display device. Fig.48 Shows the settings in Fig.45 An example of a readout line in a second display area of ​​a display device.

[0211] Since the display device according to the present embodiment may have the same Fig.41 The configuration of the display device in FIG. 1 is the same or substantially the same configuration, and therefore the same reference numerals and reference signs are used to represent the same or substantially the same (or similar) constituent elements as those described above. Therefore, redundant descriptions may not be repeated.

[0212] refer to Figures 1 to 3 and Figures 45 to 48 The connection portion FO may include a first connection region FR1 and a second connection region FR2 spaced apart from the first connection region FR1. The display area DA may include a first display area DA1 and a second display area DA2, wherein the first display area DA1 is adjacent to the first connection region FR1 and the second connection region FR2 in the first direction DR1.

[0213] The connection portion FO may include a first connection region FR1 and a second connection region FR2 connecting the readout line RL to the readout circuit 600. In an embodiment, the connection portion FO may connect the data line DL to the data driver 400 in a region other than the first connection region FR1 and the second connection region FR2. In another embodiment, the connection portion FO may connect the data line DL to the data driver 400 through a region formed at a layer different from (e.g., in) the layers of the first connection region FR1 and the second connection region FR2.

[0214] Fig.49 Examples of a sensing area and a non-sensing area of ​​a display device according to one or more embodiments of the present disclosure are shown. Fig.50 Shows Fig.49An example of a first display area and a second display area of ​​a display device. Fig.51 Shows the settings in Fig.49 An example of a readout line in a first display area of ​​a display device. Fig.52 Shows the settings in Fig.49 An example of a readout line in a second display area of ​​a display device.

[0215] Because the display device according to the present embodiment may have the same structure as the above reference numerals except for the first connection portion FO1 and the second connection portion FO2. Fig.41 The configuration of the display device described is the same or substantially the same configuration, and thus the same reference numerals and reference numerals are used to denote constituent elements that are the same or substantially the same (or similar) as those described above. Therefore, a redundant description may not be repeated.

[0216] refer to Figures 1 to 3 and Figures 45 to 48 , the display device may include a first connection portion FO1 and a second connection portion FO2, the first connection portion FO1 electrically connecting the readout line RL to the readout circuit 600, and the second connection portion FO2 electrically connecting the readout line RL to the readout circuit 600. The second connection portion FO2 may be spaced apart from the first connection portion FO1. In an embodiment, a width W1 of a first surface (e.g., a first end) of the first connection portion FO1 and the second connection portion FO2 adjacent to the display area DA may be longer than a width W2 of a second surface (e.g., a second end) of the first connection portion FO1 and the second connection portion FO2 connected to the readout circuit 600.

[0217] The readout line RL may extend in the first direction DR1. The display area DA may include a first display area DA1 and a second display area DA2, wherein the first display area DA1 is adjacent to the first connection portion FO1 and the second connection portion FO2 in the first direction DR1. Connection lines CL1, CL2, CL3, and CL4 may connect the readout line RL of the second display area DA2 to the first connection portion FO1 and the second connection portion FO2.

[0218] The readout line RL of the first display area DA1 may extend in the first direction DR1 to be directly connected to the first connection portion FO1 and the second connection portion FO2. However, the readout line RL of the second display area DA2 may be connected to the first connection portion FO1 and the second connection portion FO2 using additional wiring. Therefore, the readout line RL of the second display area DA2 may be connected to the first connection portion FO1 and the second connection portion FO2 through the connection lines CL1, CL2, CL3, and CL4.

[0219] Fig.53A layout diagram of a first conductive layer, a first active layer, and a second conductive layer of a display device according to one or more embodiments of the present disclosure is shown.

[0220] Because the display device according to the present embodiment may have the same Figure 1 The configuration of the display device in FIG. 1 is the same or substantially the same configuration, and therefore the same reference numerals and reference signs are used to represent the same or substantially the same (or similar) constituent elements as those described above. Therefore, redundant descriptions may not be repeated.

[0221] refer to Figure 8 and Fig.53 , the width of the 1-1st conductive pattern 311 in the third region R3 may be wider than the width of the 1-1st conductive pattern 311 in the second region R2. The third region R3 may have sufficient additional space compared to the second region R2. Therefore, by increasing the width of the 1-1st conductive pattern 311 in the third region R3, the resistance of the 1-1st conductive pattern 311 in the third region R3 may be reduced.

[0222] The width of the 2-1st conductive pattern 331 in the third region R3 may be wider than the width of the 2-1st conductive pattern 331 in the second region R2. The third region R3 may have sufficient additional space compared to the second region R2. Therefore, by increasing the width of the 2-1st conductive pattern 331 in the third region R3, the resistance of the 2-1st conductive pattern 331 in the third region R3 may be reduced.

[0223] Fig.54 A layout diagram of a third conductive layer of a display device according to one or more embodiments of the present disclosure is shown.

[0224] Because the display device according to the present embodiment may have the same structure as the above reference except for the 3-1st conductive pattern 341 in the third region R3. Figure 1 The configuration of the display device described is the same or substantially the same configuration, and thus the same reference numerals and reference numerals are used to denote constituent elements that are the same or substantially the same (or similar) as those described above. Therefore, a redundant description may not be repeated.

[0225] refer to Fig. 9 and Fig.54, at least a portion of the 3-1st conductive pattern 341 may be included in the third region R3. The third region R3 may have sufficient additional space compared to the second region R2. Therefore, the 3-1st conductive patterns 341 adjacent to the third region R3 may be connected to each other through the third region R3. In other words, by connecting the 3-1st conductive patterns 341 to each other in the third region R3, the resistance of the 3-1st conductive pattern 341 may be reduced.

[0226] Fig.55 A layout diagram of a sixth conductive layer of a display device according to one or more embodiments of the present disclosure is shown. Fig.56 Shows Fig.55 Layout diagram of the seventh conductive layer of a display device.

[0227] Because the display device according to the present embodiment may have the same structure as the above reference pattern except for the 6-5th conductive pattern 435, the 6-8th conductive pattern 438, and the 7-1st conductive pattern 441 in the third region R3. Figure 1 The configuration of the display device described is the same or substantially the same configuration, and thus the same reference numerals and reference numerals are used to denote constituent elements that are the same or substantially the same (or similar) as those described above. Therefore, a redundant description may not be repeated.

[0228] refer to Fig.18 , Fig.33 , Fig.55 and Fig.56 , the display device may include a 6-8th conductive pattern 438. At least a portion of the 6-8th conductive pattern 438 may overlap the first region R1. The 6-8th conductive pattern 438 may be connected to the 5-1st conductive pattern 421 and the 7-1st conductive pattern 441. In other words, the reset voltage VRST may be applied to the 6-8th conductive pattern 438.

[0229] For example, the 6th to 8th conductive patterns 438 may be disposed in one of the first region R1 adjacent to the third region R3 in the second direction DR2 and the first region R1 adjacent to the third region R3 in a direction opposite to the second direction DR2.

[0230] In an embodiment, the 6-5th conductive pattern 435 may not be connected to the 7-1st conductive pattern 441 in the third region R3. In other words, the fourth contact hole CNT4 connecting the 6-5th conductive pattern 435 to the 7-1st conductive pattern 441 may be provided in the second region R2.

[0231] Fig.57 A layout diagram of a sixth conductive layer of a display device according to one or more embodiments of the present disclosure is shown. Fig.58 Shows Fig.57Layout diagram of the seventh conductive layer of a display device.

[0232] Because the display device according to the present embodiment may have the same Figure 1 The configuration of the display device in FIG. 1 is the same or substantially the same configuration, and therefore the same reference numerals and reference signs are used to represent the same or substantially the same (or similar) constituent elements as those described above. Therefore, redundant descriptions may not be repeated.

[0233] refer to Fig.18 , Fig.33 , Fig.57 and Fig.58 , the display device may include a 6-8th conductive pattern 438. At least a portion of the 6-8th conductive pattern 438 may overlap the first region R1. The 6-8th conductive pattern 438 may be connected to the 5-1st conductive pattern 421 and the 7-1st conductive pattern 441. In other words, the reset voltage VRST may be applied to the 6-8th conductive pattern 438.

[0234] The 6th to 8th conductive patterns 438 may form a mesh structure. For example, the 6th to 8th conductive patterns 438 may be disposed in the first region R1 adjacent to the third region R3 in the second direction DR2 and in the first region R1 adjacent to the third region R3 in a direction opposite to the second direction DR2.

[0235] In an embodiment, the 6-5th conductive pattern 435 may not be connected to the 7-1st conductive pattern 441 in the third region R3. In other words, the fourth contact hole CNT4 connecting the 6-5th conductive pattern 435 to the 7-1st conductive pattern 441 may be provided in the second region R2.

[0236] Fig.59 A layout diagram of a sixth conductive layer of a display device according to one or more embodiments of the present disclosure is shown.

[0237] Because the display device according to the present embodiment may have the same structure as the above reference except for the 6-5th conductive pattern 435 in the third region R3. Figure 1 The configuration of the display device described is the same or substantially the same configuration, and thus the same reference numerals and reference numerals are used to denote constituent elements that are the same or substantially the same (or similar) as those described above. Therefore, a redundant description may not be repeated.

[0238] refer to Figures 1 to 3 and Fig.59, the 6-3rd conductive pattern 433 may be a data line DL to which a data voltage VDATA is applied. The 6-4th conductive pattern 434 may be a readout line RL to which a sensing signal is applied. The 6-5th conductive pattern 435 may be a reset voltage line to which a reset voltage VRST is applied.

[0239] The reset voltage line may be disposed between the data line DL and the readout line RL in the third region R3. For example, the 6-5th conductive pattern 435 may be disposed between the 6-3rd conductive pattern 433 and the 6-4th conductive pattern 434. Therefore, since the reset voltage line is disposed between the data line DL and the readout line RL, interference between the data line DL and the readout line RL (e.g., influence of coupling between the data line DL and the readout line RL) may be minimized or reduced.

[0240] Fig.60 A block diagram of an electronic device according to one or more embodiments of the present disclosure is shown. Fig.61 Shows the Fig.60 The electronic device is implemented as an example of a smart phone. Fig.62 Shows Fig.60 An example in which the electronic device is implemented as a tablet personal computer.

[0241] refer to Figure 60 to Figure 62 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device (or I / O device) 1040, a power supply 1050, and a display device 1060. For example, the display device 1060 may be the above reference Figure 1 In addition, the electronic device 1000 may also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or with other systems. In an embodiment, as Fig.61 and Fig.62 As shown, the electronic device 1000 can be implemented as a smart phone or a tablet personal computer. However, the present disclosure is not limited thereto, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a vehicle navigation device, a computer display screen, a laptop computer, a head-mounted display device, etc.

[0242] The processor 1010 can perform specific calculations or tasks. In some embodiments, the processor 1010 can be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 can be connected to other components through an address bus, a control bus, and a data bus. In some embodiments, the processor 1010 can also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0243] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include one or more suitable nonvolatile memory devices (such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and / or ferroelectric random access memory (FRAM) devices) and / or one or more suitable volatile memory devices (such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and / or mobile DRAM devices).

[0244] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0245] The input / output device 1040 may include one or more suitable input devices (such as a keyboard, a keypad, a touch pad, a touch screen, a mouse, etc.) and one or more suitable output devices (such as a speaker, a printer, etc.). In some embodiments, the display device 1060 may be included in the input / output device 1040.

[0246] The power supply 1050 may supply power for the operation of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0247] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 may be an organic light-emitting display device or a quantum dot light-emitting display device, but the present disclosure is not limited thereto. The display device 1060 may be connected to other components via a bus or other communication links.

[0248] The embodiments of the present disclosure described above can be applied to a display device and an electronic device including the display device. For example, the embodiments of the present disclosure can be applied to a digital television (TV), a 3D TV, a mobile phone, a smart phone, a tablet computer, a virtual reality (VR) device, a personal computer, a home electronic device, a laptop computer, a personal digital assistant (PDA), a personal multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0249] The above are examples of some embodiments of the present disclosure, and should not be interpreted as limiting them. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made to the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it will be understood that the above are examples of various exemplary embodiments, and should not be interpreted as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included in the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: The display panel comprises a display area, the display area comprises sub-pixels, and the display area is defined as follows: a sensing region including the sub-pixel and an optical sensor configured to provide a sensing signal corresponding to an amount of received light to a readout line; as well as a non-sensing area including the sub-pixel; a readout circuit configured to receive the sensing signal through the readout line; as well as a connecting portion electrically connecting the readout line to the readout circuit, wherein a connection line connecting the readout line and the connection portion to each other is located in the non-sensing region.

2. The display device according to claim 1, wherein: The readout line extends in a first direction; The display area includes a first display area and a second display area, the first display area being adjacent to the connecting portion in the first direction; as well as The connection line connects the readout line of the second display area to the connection portion.

3. The display device according to claim 1, wherein: The readout line extends in a first direction; The connecting wires include a first connecting wire and a second connecting wire; The first connection line extends in a second direction crossing the first direction and is connected to the readout line through a first line contact hole; and The second connection line extends in the first direction and is connected to the first connection line through a second wire contact hole.

4. The display device according to claim 3, wherein: The first connection lines and the second connection lines form a grid structure.

5. The display device according to claim 3, wherein: The connecting wires further include a third connecting wire and a fourth connecting wire; The third connection line extends in the second direction and is connected to the second connection line through a third line contact hole; and The fourth connection line extends in the first direction and is connected to the third connection line through a fourth line contact hole.

6. The display device according to claim 5, wherein: The readout line is located at the same layer as that of the second connection line.

7. The display device according to claim 5, wherein: The first connection line is located at the same layer as that of the third connection line.

8. The display device according to claim 1, wherein: The connecting portion includes a first connecting region and a second connecting region spaced apart from the first connecting region; The readout line extends in a first direction; The display area includes a first display area and a second display area, the first display area is adjacent to the first connection area and the second connection area in the first direction; as well as The connection line connects the readout line of the second display area to the connection portion.

9. The display device according to claim 1, wherein: A width of a first end of the connection portion adjacent to the display region is longer than a width of a second end of the connection portion connected to the readout circuit.

10. The display device according to claim 1, wherein: The sub-pixel includes a light-emitting element and a pixel driving circuit; The optical sensor includes a light receiving element and a sensor driving circuit; The sensing area includes a first area including the pixel driving circuit, and a second area adjacent to the first area and including the sensor driving circuit; and The non-sensing area includes the first area including the pixel driving circuit and a third area adjacent to the first area.

11. The display device according to claim 10, wherein: The pixel driving circuit includes a first pixel transistor configured to generate a driving current; The first pixel transistor includes a portion of a conductive pattern; and A width of the conductive pattern in the third region is wider than a width of the conductive pattern in the second region.

12. The display device according to claim 10, wherein: The pixel driving circuit includes a second pixel transistor configured to write a data voltage in response to a write gate signal; The second pixel transistor includes a portion of a conductive pattern; and A width of the conductive pattern in the third region is wider than a width of the conductive pattern in the second region.

13. The display device according to claim 10, wherein: The pixel driving circuit includes a storage capacitor configured to store a data voltage; The storage capacitor includes a portion of a conductive pattern; and At least a portion of the conductive pattern is located in the third region.

14. The display device according to claim 10, wherein: The sensor driving circuit is configured to be initialized with a reset voltage; and A conductive pattern configured to receive the reset voltage overlaps at least a portion of the readout line.

15. The display device according to claim 14, wherein: At least a portion of the conductive pattern configured to receive the reset voltage overlaps the first region.

16. The display device according to claim 14, wherein: The conductive pattern configured to receive the reset voltage has a mesh structure.

17. The display device according to claim 10, wherein: The pixel driving circuit is configured to receive a data voltage through a data line; The sensor driving circuit is configured to receive a reset voltage via a reset voltage line; as well as The reset voltage line is located between the data line and the readout line in the third region.

18. The display device according to claim 1, wherein: The width of the connection line increases as the length of the connection line increases.

19. A display device comprising: The display panel comprises a display area, the display area comprises sub-pixels, and the display area is defined as follows: a sensing region including the sub-pixel and an optical sensor configured to provide a sensing signal corresponding to an amount of received light to a readout line; as well as a non-sensing area including the sub-pixel; a readout circuit configured to receive the sensing signal through the readout line; a first connection portion electrically connecting the readout line to the readout circuit; as well as a second connection portion electrically connecting the readout line to the readout circuit and spaced apart from the first connection portion, Wherein, a connection line connecting the readout line and the first connection portion and the second connection portion to each other is located in the non-sensing area.

20. Electronic devices, including: a processor configured to provide input image data to a display device; The display device is configured to display an image based on the input image data; as well as a power supply configured to supply power to the display device, Wherein, the display device comprises: The display panel comprises a display area, the display area comprises sub-pixels, and the display area is defined as follows: a sensing area including the sub-pixel and an optical sensor configured to provide a sensing signal corresponding to an amount of received light to a readout line; and a non-sensing area including the sub-pixel; a readout circuit configured to receive the sensing signal through the readout line; and a connecting portion electrically connecting the readout line to the readout circuit, wherein a connection line connecting the readout line and the connection portion to each other is located in the non-sensing region.

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