Display substrate and display device

Abstract

The embodiment of the invention provides a display substrate and a display device, and relates to the technical field of display. The display substrate comprises a substrate base plate, wherein the substrate base plate comprises a first edge and a second edge adjacent to the first edge, and the length of the first edge is larger than that of the second edge; the sub-pixels are arranged on one side of the substrate, the sub-pixels are arranged in an array mode in the first direction and the second direction, the sub-pixels in the same pixel row are arranged in the second direction, and the sub-pixels in the same pixel column are arranged in the first direction; the multiple grid lines are arranged on one side of the substrate, extend in the second direction and are electrically connected with the sub-pixels in one pixel row, and the grid lines are configured to transmit grid driving signals to the sub-pixels; the data lines are arranged on one side of the substrate, the data lines extend in the first direction, one data line is electrically connected with at least part of the sub-pixels in one pixel column, and the data lines are configured to transmit data voltage signals to the sub-pixels. The power consumption of the display substrate can be effectively reduced, and the user experience is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the development of science and technology, the application of organic light-emitting diode (OLED) display technology is becoming more and more widespread. OLED is driven by electric field, and organic semiconductor materials and luminescent materials emit light through carrier injection and recombination. Each pixel in the OLED display can emit light independently without backlight support, with high contrast, high brightness, wide color gamut and color saturation; at the same time, the screen structure of OLED display is simple and thin, which can bring different visual experience to users. Summary of the invention

[0003] The present application provides a display substrate and a display device, which are used to improve the problem of high power consumption of display panels in the prior art.

[0004] According to one aspect of the present application, a display substrate is provided, comprising:

[0005] A substrate, comprising a first side and a second side adjacent to the first side, wherein the length of the first side is greater than the length of the second side;

[0006] A plurality of sub-pixels are arranged on one side of the substrate, the plurality of sub-pixels are arranged in an array in a first direction and a second direction, the sub-pixels in the same pixel row are arranged along the second direction, the sub-pixels in the same pixel column are arranged along the first direction, the first direction is parallel to the extension direction of the second side, and the second direction is parallel to the extension direction of the first side;

[0007] A plurality of gate lines are arranged on one side of the substrate, the gate lines extend along the second direction and are electrically connected to the sub-pixels in a pixel row, and the gate lines are configured to transmit gate drive signals to the sub-pixels;

[0008] A plurality of data lines are arranged on one side of the base substrate, the data lines extend along a first direction, one data line is electrically connected to at least part of the sub-pixels in a pixel column, and the data line is configured to transmit data voltage signals to the sub-pixels.

[0009] In a possible implementation, the base substrate includes a display area, a first peripheral area, and a second peripheral area, the first peripheral area is located on a side of the display area facing the first side, the second peripheral area is located on a side of the display area facing the second side, and a plurality of sub-pixels are arranged in the display area; the display substrate further includes:

[0010] At least one gate driving circuit is arranged in the second peripheral area, the gate driving circuit includes a plurality of cascaded shift registers, the gate line extends to the second peripheral area and is electrically connected to a shift register of one level.

[0011] In a possible implementation, the first peripheral area is provided with a binding area, the binding area is configured to bind the display driver chip, the binding area includes a data pin, and the data line extends to the binding area and is electrically connected to a data pin.

[0012] In another possible implementation, the above-mentioned multiple data lines include a first data line and a second data line; the first peripheral area is provided with at least two binding areas, the at least two binding areas include a first sub-binding area and a second sub-binding area, the first data line extends to the first sub-binding area and is electrically connected to the data pin in the first sub-binding area, and the second data line extends to the second sub-binding area and is electrically connected to the data pin in the second sub-binding area.

[0013] In yet another possible implementation, the first sub-binding area and the second sub-binding area are located on the same side of the display area, or on two opposite sides of the display area.

[0014] In another possible implementation, the above-mentioned multiple sub-pixels include a first pixel column and a second pixel column arranged alternately in the second direction; the sub-pixels of the first pixel column are green sub-pixels, and the second pixel column includes red sub-pixels and blue sub-pixels, and the red sub-pixels and the blue sub-pixels are arranged alternately along the first direction.

[0015] In another possible implementation, the sub-pixels in the same first pixel column are electrically connected to the same first data line, and the sub-pixels in the same second pixel column are electrically connected to the same second data line.

[0016] In another possible implementation, the red sub-pixels in the same second pixel column are electrically connected to the same first data line, and the blue sub-pixels in the same second pixel column are electrically connected to the same second data line.

[0017] In another possible implementation, the green sub-pixels in the same first pixel column are electrically connected to the same first data line or the same second data line; or,

[0018] The green sub-pixels located in odd-numbered rows in the first pixel column are electrically connected to the same first data line, and the green sub-pixels located in even-numbered rows in the first pixel column are electrically connected to the same second data line; or,

[0019] The green sub-pixels in the even-numbered rows of the first pixel column are electrically connected to the same first data line, and the green sub-pixels in the odd-numbered rows of the first pixel column are electrically connected to the same second data line.

[0020] In another possible implementation, the binding area includes a clock pin;

[0021] The display substrate also includes multiple clock signal lines, which are arranged in the second peripheral area; the clock signal lines extend along the first direction and are electrically connected to the multi-stage shift register, and the clock signal lines are configured to transmit clock signals to the shift register; the clock signal lines extend to the first peripheral area and are electrically connected to the clock pins.

[0022] According to another aspect of an embodiment of the present application, a display device is provided. The device includes the display substrate shown in the first aspect of the present application.

[0023] The beneficial effects of the technical solution provided by this application are:

[0024] The display substrate and display device provided by the present application can be provided with a plurality of gate lines on one side of the base substrate, the gate lines extending along the second direction and electrically connected to the sub-pixels in a pixel row, and the sub-pixels in the same pixel row are arranged along the second direction; at the same time, a plurality of data lines are provided on one side of the base substrate, the data lines extending along the first direction, and one data line is electrically connected to at least part of the sub-pixels in a pixel column; wherein the base substrate includes a first side and a second side adjacent to the first side, the first direction is parallel to the extension direction of the second side, and the second direction is parallel to the extension direction of the first side; since the length of the first side is greater than the length of the second side, each gate line is electrically connected to the sub-pixels in a pixel row, so the gate lines extend along the long sides of the display substrate, and the number of stages of the shift registers connected to the gate lines is relatively reduced, which can effectively reduce the logic power consumption of the gate drive circuit, thereby reducing the power consumption of the display substrate and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1-1 A schematic diagram of a light emitting control signal of a gate driving circuit provided in an embodiment of the present application;

[0027] Figure 1-2 A schematic diagram of a row scanning signal of a gate driving circuit provided in an embodiment of the present application;

[0028] Figure 1-3 A schematic diagram of the sub-pixel arrangement of a display substrate provided in an embodiment of the present application;

[0029] Figure 2A schematic diagram of the structure of a display substrate provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of a gate driving circuit in a display substrate provided in an embodiment of the present application;

[0031] Figure 4 A circuit diagram of a pixel driving circuit in a display substrate provided in an embodiment of the present application;

[0032] Figure 5-1 A partial schematic diagram of a gate driving circuit in a display substrate provided in an embodiment of the present application;

[0033] Figure 5-2 Another partial schematic diagram of a gate driving circuit in a display substrate provided in an embodiment of the present application;

[0034] Figure 6 A schematic diagram of binding a display driver chip in a display substrate provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of the structure of a binding area in a display substrate provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of the structure of a binding area in another display substrate provided in an embodiment of the present application;

[0037] Fig. 9 A schematic diagram of the structure of the sub-pixel arrangement in the display area of ​​a display substrate provided in an embodiment of the present application;

[0038] Fig.10 A schematic diagram of a local structure of a sub-pixel in a display area of ​​a display substrate provided in an embodiment of the present application;

[0039] Fig.11 A schematic diagram of a partial structure of a sub-pixel in a display area of ​​another display substrate provided in an embodiment of the present application;

[0040] Fig.12 A schematic diagram of the local structure of a sub-pixel in a display area of ​​another display substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0042] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0043] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0044] First, the terms involved in this application are explained:

[0045] Active-matrix organic light-emitting diode (AMOLED): A display technology. OLED is a term that describes a specific type of thin-film display technology: organic electroluminescent display; AM (active matrix) refers to the underlying pixel addressing technology. AMOLED technology is primarily used in smartphones and continues to evolve toward low power, low cost, and large size. AMOLED is gaining adoption in smartphones because it has a wider viewing angle, higher refresh rate, and thinner size than traditional LCD displays used in most phones.

[0046] GOA (Gate On Array): refers to the integration of gate drive on the array substrate, which can realize the progressive scanning drive function of the liquid crystal panel. In traditional active matrix liquid crystal displays, the row scanning signal is realized by an external integrated circuit, and the use of GOA drive means that the row scanning drive circuit is manufactured using the same process as the thin film transistor on the basis of only providing a few control signals from the external circuit, so as to realize the progressive scanning drive function. Therefore, the use of GOA drive saves integrated circuits related to scanning drive and reduces the production cost of liquid crystal displays.

[0047] At present, with the development of AMOLED display screens, they are gradually applied to the fields of gaming phones and gaming displays. The requirements for refresh rates are becoming more and more extreme, such as 120Hz, 144Hz, etc., and the resolution of the display screens is higher. Therefore, at high refresh rates, the logic power consumption of some GOA circuits is higher.

[0048] At the same time, the gate driving circuit in the AMOLED display substrate is arranged on the long side of the display substrate, and the gate driving circuit includes a multi-level GOA unit, each gate line extends along the short side and is electrically connected to the first-level GOA unit; the binding area of ​​the display driver chip is arranged on the short side of the display substrate, and multiple data lines extend along the long side and are electrically connected to the binding area; the long side of the display substrate also includes a clock signal line for providing a gate line driving signal for the pixel row in the display area. The inventor found that since each gate line has a parasitic capacitance with the corresponding GOA unit, the clock signal line will be attenuated during the transmission from top to bottom, such as Figure 1-1 The light emitting control signal output by the EM GOA (light emitting gate drive circuit) is shown as follows: Figure 1-2 The figure shows the row scan signal output by P-gateGOA. Figure 1-1 and Figure 1-2 It can be seen that as the number of pixel rows increases, the gate line charging voltage of the pixel row scanned later is insufficient, and the output voltage signal is deformed.

[0049] like Figure 1-3 The figure shows a schematic diagram of the sub-pixel arrangement of the display substrate. The sub-pixels are divided into green pixel columns and red and blue pixel columns. The inventors also found that when the display driver chip drives the row scan, due to the larger luminous energy of the blue sub-pixel, the data voltage of the red and blue pixel columns will jump back and forth, causing the logic power consumption of the display driver chip to increase.

[0050] Based on the above technical problems, some embodiments of the present application are provided with a plurality of gate lines on one side of the substrate, the gate lines extending along the second direction and being electrically connected to the sub-pixels in a pixel row; at the same time, a plurality of data lines are provided on one side of the substrate, the data lines extending along the first direction, and one data line is electrically connected to at least part of the sub-pixels in a pixel column; wherein the substrate includes a first side and a second side adjacent to the first side, the first direction is parallel to the extension direction of the second side, and the second direction is parallel to the extension direction of the first side; since the length of the first side is greater than the length of the second side, each gate line is electrically connected to the sub-pixels in a pixel row, so the gate lines extend along the long side of the display substrate, and the number of stages of the shift registers connected to the gate lines is relatively reduced, which can effectively reduce the logic power consumption of the gate drive circuit, thereby reducing the power consumption of the display substrate and improving the user experience.

[0051] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0052] In an embodiment of the present application, a display substrate is provided, such as Figure 2As shown, it may include a substrate 101 , a plurality of sub-pixels 102 , a plurality of gate lines 103 and a plurality of data lines 104 .

[0053] Among them, the base substrate 101 includes a first edge 1011 and a second edge 1012 adjacent to the first edge 1011, and the length of the first edge 1011 is greater than the length of the second edge 1012; the above-mentioned base substrate 101 includes a display area 1013, a first peripheral area 1014 and a second peripheral area 1015, the first peripheral area 1014 is located on the side of the display area 1013 facing the first edge 1011, the second peripheral area 1015 is located on the side of the display area 1013 facing the second edge 1012, and multiple sub-pixels are arranged in the display area 1013.

[0054] like Figure 2 As shown, the base substrate 101 includes two long sides (i.e., the first side 1011) and two short sides (i.e., the second side 1012), and the display area 1013 is respectively provided with a first peripheral area 1014 on one side facing the two long sides, and the display area 1013 is respectively provided with a second peripheral area 1015 on one side facing the two short sides; the adjacent first peripheral area 1014 and second peripheral area 1015 are separated by a dotted line.

[0055] A plurality of sub-pixels 102 are disposed on one side of the substrate 101, and the plurality of sub-pixels 102 are arranged in an array in a first direction and a second direction. The sub-pixels 102 in the same pixel row are arranged along the second direction, and the sub-pixels 102 in the same pixel column are arranged along the first direction. The first direction is parallel to the extension direction of the second side 1012, and the second direction is parallel to the extension direction of the first side 1011.

[0056] Optionally, the sub-pixel may include a light emitting device and a pixel driving circuit for driving the light emitting device to emit light; Figure 4 As shown, the pixel driving circuit may include a driving subcircuit, a data temporary storage subcircuit, a writing subcircuit, a compensation subcircuit and a light emitting control subcircuit. Among them, the driving subcircuit may include a transistor M0, the data temporary storage subcircuit may store a capacitor C1, the writing subcircuit may include a third transistor M3, the compensation subcircuit may include a second transistor M2, and the light emitting control subcircuit may include a fifth transistor M5 and a sixth transistor M6. The pixel driving circuit may also include a reset subcircuit, and the reset subcircuit may include a first transistor M1. The pixel circuit is a 7T1C pixel circuit using LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide) technology, wherein the second transistor M2 and the first transistor M1 are N-type transistors such as NMOS tubes, and the other transistors are P-type transistors such as PMOS tubes.

[0057] A plurality of gate lines 103 are disposed on one side of the base substrate 101 . The gate lines 103 extend along the second direction and are electrically connected to the sub-pixels 102 in a pixel row. The gate lines 103 are configured to transmit gate driving signals to the sub-pixels 102 .

[0058] A plurality of data lines 104 are disposed on one side of the base substrate 101 . The data lines 104 extend along a first direction. One data line 104 is electrically connected to at least some of the sub-pixels 102 in a pixel column. The data line 104 is configured to transmit a data voltage signal to the sub-pixel 102 .

[0059] The embodiment of the present application can be achieved by setting a plurality of gate lines on one side of the substrate, the gate lines extending along the second direction and electrically connected to the sub-pixels in a pixel row, and the sub-pixels in the same pixel row are arranged along the second direction; at the same time, setting a plurality of data lines on one side of the substrate, the data lines extending along the first direction, and one data line electrically connected to at least part of the sub-pixels in a pixel column; wherein the substrate substrate includes a first side and a second side adjacent to the first side, the first direction is parallel to the extension direction of the second side, and the second direction is parallel to the extension direction of the first side; since the length of the first side is greater than the length of the second side, each gate line is electrically connected to the sub-pixels in a pixel row, so the gate lines extend along the long sides of the display substrate, and the number of stages of the shift registers connected to the gate lines is relatively reduced, which can effectively reduce the logic power consumption of the gate drive circuit, thereby reducing the power consumption of the display substrate and improving the user experience.

[0060] A possible implementation method is provided in the embodiment of the present application, such as Figure 2 As shown, the display substrate 101 further includes at least one gate driving circuit 150, which is disposed in the second peripheral area 1015; Figure 3 As shown, the gate driving circuit 150 includes a plurality of shift registers 501 arranged in cascade connection, and the gate line 103 extends to the second peripheral area 1015 and is electrically connected to one stage of the shift register 501 .

[0061] For example, the shift register 501 may have a first clock signal terminal CLK and a second clock signal terminal CLKB, a signal input terminal Input, a reset signal terminal Reset, and a signal output terminal Output. Taking two clock signal lines as an example, the connection relationship of multiple cascaded shift registers 501 is as follows: Figure 3 As shown, the first clock signal line 503 and the second clock signal line 504 are electrically connected to the first clock signal terminal CLK and the second clock signal terminal CLKB of each stage of the shift register, respectively, to provide the first clock signal and the second clock signal to each stage of the shift register 501, respectively.

[0062] Optionally, the output signal end of the current pixel row is electrically connected to the pixel driving circuit of at least one pixel row through a gate line. In addition to outputting the signal to drive the corresponding pixel row, the output signal end can also provide a reset signal for the pixel driving circuit of the previous pixel row, and can also provide an input signal for the pixel driving circuit of the next pixel row. It should be noted that in the entire gate drive circuit, the input signal of the first-stage shift register is a frame start signal STV, and the first pixel row does not output a reset signal. At the same time, the shift register corresponding to the last pixel row is connected to a redundant shift register to achieve the reset of the last pixel row. In this way, under the action of an external control signal, the shift registers between the pixel rows also affect each other, generating a shift pulse signal to achieve sequential line-by-line scanning.

[0063] In some embodiments, Figure 5-1 The figure shows a partial detail diagram of a gate driving circuit, wherein at least one gate driving circuit may include a first gate driving circuit 301, a second gate driving circuit 302 and a third gate driving circuit 303; wherein the first gate driving circuit 301, the second gate driving circuit 302 and the third gate driving circuit 303 are separated by a dotted line. The first gate driving circuit 301 includes a plurality of first shift registers 3011 arranged in cascade connection, and the first shift register 3011 is electrically connected to the second scanning signal terminal of the pixel driving circuit of at least one pixel row through a gate line; the second gate driving circuit 302 includes a plurality of second shift register units 3021 arranged in cascade connection, and the second shift register unit 3021 is electrically connected to the first scanning signal terminal of the pixel driving circuit of at least one pixel row through a gate line; the third gate driving circuit 303 includes a plurality of third shift register units 3031 arranged in cascade connection, and the third shift register unit 3031 is electrically connected to the enable signal terminal EM of the pixel driving circuit of at least one pixel row through a gate line.

[0064] Specifically, the first shift register 3011 is electrically connected to the first scanning control terminal of the pixel driving circuit of one pixel row through the gate line; the second shift register unit 3021 is electrically connected to the second scanning control terminal of the pixel driving circuit of two adjacent pixel rows through the gate line; the third shift register unit 3031 is electrically connected to the light emitting control terminal of the pixel driving circuit of two adjacent pixel rows through the gate line. Different from the prior art, such as Figure 5-2 The pixel driving circuit of each pixel row shown is connected to the first gate driving circuit, the second gate driving circuit and the third gate driving circuit. The embodiment of the present application can effectively reduce the number of stages of the shift register and further reduce the power consumption of the display substrate.

[0065] A possible implementation method is provided in an embodiment of the present application. The first peripheral area is provided with a binding area, the binding area is configured to bind a display driver chip, the binding area includes a data pin, and the data line extends to the binding area and is electrically connected to a data pin.

[0066] In the embodiments of the present application, Figure 6 As shown, the first peripheral area 1014 is provided with a binding area 404, and the second fan-out area 403, the bending area 402 and the first fan-out area 401 are sequentially provided on the side of the binding area 404 close to the display area 1013. A plurality of data lines extend to the binding area 404 through the first fan-out area 401, the bending area 402 and the second fan-out area 403 and are electrically connected to the data pins. Figure 3 As shown, the first clock signal line 503 and the second clock signal line 504 are electrically connected to the binding area 160 of the first peripheral area 1014 of the substrate 101 respectively.

[0067] In an embodiment of the present application, a possible implementation method is provided, and the above-mentioned binding area may also include a clock pin. The display substrate also includes a plurality of clock signal lines, which are arranged in the second peripheral area; the clock signal lines extend along the first direction and are electrically connected to the multi-stage shift register, and the clock signal lines are configured to transmit clock signals to the shift register; the clock signal lines extend to the first peripheral area and are electrically connected to the clock pin.

[0068] In the embodiment of the present application, each shift register can be connected to a pair of clock signal lines, namely, the CLK clock signal line 503 and the CLKB clock signal line 504, and the gate line drive signals of all pixel rows are high voltages provided by the clock signal lines; since there is parasitic capacitance between each gate line and the corresponding shift register, attenuation will occur during the transmission of the clock signal line from top to bottom; since in the embodiment of the present application, the shift register is set in the short side area of ​​the display substrate, the number of pixel rows is less than the number of pixel columns, the number of scanned rows, namely, the number of shift register levels, can be effectively reduced, the transmission attenuation of the clock signal line during row-by-row scanning is improved, and insufficient charging voltage of the gate line of the pixel row scanned later is avoided, so that the display substrate can better adapt to the requirements of high refresh frequency and effectively improve the user experience.

[0069] A possible implementation method is provided in an embodiment of the present application, wherein the above-mentioned multiple data lines include a first data line and a second data line; the first peripheral area is provided with at least two binding areas, and the at least two binding areas include a first sub-binding area and a second sub-binding area. The first data line extends to the first sub-binding area and is electrically connected to the data pin in the first sub-binding area, and the second data line extends to the second sub-binding area and is electrically connected to the data pin in the second sub-binding area.

[0070] A possible implementation manner is provided in an embodiment of the present application, where the first sub-binding area and the second sub-binding area are located on the same side of the display area, or on two opposite sides of the display area.

[0071] like Figure 7 In the embodiment shown, the binding area includes a first sub-binding area 4011 and a second sub-binding area 4012; the first sub-binding area 4011 and the second sub-binding area 4012 are respectively arranged at two first peripheral areas opposite to each other on the left and right. Figure 8 In the illustrated embodiment, the first sub-binding region 4013 and the second sub-binding region 1014 are disposed in the same first peripheral region.

[0072] The embodiment of the present application sets two sub-binding areas in the first peripheral area, and each sub-binding area is bound to a display driver chip, so that two display driver chips can drive each sub-pixel in the display substrate at the same time. That is to say, in the embodiment of the present application, each sub-pixel in the display substrate can be split, one part is driven by the first display driver chip, and the other part is driven by the second display driver chip, which can effectively save the number of channels of the display driver chip and improve the pixel driving efficiency.

[0073] A possible implementation method is provided in the embodiment of the present application, such as Fig. 9 As shown, the above-mentioned multiple sub-pixels include a first pixel column 701 and a second pixel column 702 which are arranged alternately in the second direction; the sub-pixels of the first pixel column 701 are green sub-pixels, and the second pixel column 702 includes red sub-pixels and blue sub-pixels, and the red sub-pixels and the blue sub-pixels are arranged alternately along the first direction.

[0074] A possible implementation method is provided in an embodiment of the present application, where sub-pixels in the same first pixel column are electrically connected to the same first data line, and sub-pixels in the same second pixel column are electrically connected to the same second data line.

[0075] In some embodiments, Fig.10 Shown Fig. 9 In the detailed enlarged view of area A, each sub-pixel in the first pixel column, i.e., the green pixel column, is electrically connected to a first data line 901 , and each sub-pixel in the second pixel column, i.e., the red and blue pixel column, is electrically connected to a second data line 902 .

[0076] The embodiment of the present application electrically connects the first pixel column to the first data line and the second pixel column to the second data line, thereby using different display driver chips to drive the first pixel column and the second pixel column respectively, thereby saving the number of channels of each display driver chip. The two display driver chips can drive the corresponding sub-pixels at the same time, thereby improving the pixel driving efficiency.

[0077] A possible implementation method is provided in an embodiment of the present application, where the red sub-pixels in the same second pixel column are electrically connected to the same first data line, and the blue sub-pixels in the same second pixel column are electrically connected to the same second data line.

[0078] In some embodiments, Fig.11 Shown Fig. 9 Another detailed enlarged view of the middle A area, wherein each sub-pixel of the first pixel column, i.e., the green pixel column, is electrically connected to a first data line 901, each red sub-pixel in the second pixel column is electrically connected to a second data line 902, and each blue sub-pixel in the second pixel column is electrically connected to a second data line 901; that is, in the embodiment of the present application, sub-pixels of different colors are respectively connected through different data lines. Since the luminous energy of the blue sub-pixel is greater than that of the red sub-pixel, the driving data voltage of the blue sub-pixel is greater than that of the red sub-pixel. When the red and blue sub-pixels in the same second pixel column are electrically connected to the same second data line, the driving data voltage will have a large and a small voltage jump. In the embodiment of the present application, the red and blue sub-pixels in the same second pixel column are driven separately, which can avoid the above-mentioned voltage jump, and can effectively reduce the power consumption of the display driver chip, so that the power consumption of the display substrate is effectively reduced.

[0079] In some embodiments, the green sub-pixels in the same first pixel column may be electrically connected to the same first data line or the same second data line.

[0080] In some other embodiments, the green sub-pixels located in odd-numbered rows in the first pixel column may be electrically connected to the same first data line, and the green sub-pixels located in even-numbered rows in the first pixel column may be electrically connected to the same second data line.

[0081] In some further embodiments, green sub-pixels located in even-numbered rows in the first pixel column may be electrically connected to the same first data line, and green sub-pixels located in odd-numbered rows in the first pixel column may be electrically connected to the same second data line.

[0082] In some embodiments, Fig.12 Shown Fig. 9 Another detailed enlarged image of area A, in which the green sub-pixels located in odd rows and even rows in each first pixel column are electrically connected to different data lines, respectively, the red sub-pixels in each second pixel column are electrically connected to a second data line 902, and the blue sub-pixels in each second pixel column are electrically connected to a first data line 901.

[0083] In the embodiment of the present application, the green sub-pixels located in the odd rows and even rows in the same first pixel column are connected to different data lines for separate driving, and at the same time, the red sub-pixels and green sub-pixels in the second pixel column are also connected to different data lines for separate driving. That is to say, in the embodiment of the present application, the sub-pixels of each pixel row are divided into two display driver chips for separate driving. Compared with each pixel row being driven separately by a display driver chip, the single-row charging time in the embodiment of the present application is extended to twice, which can improve the driving image quality of adjacent sub-pixels. At the same time, the scanning time of each pixel row is shortened to half, which can effectively increase the pixel scanning frequency of the display substrate, further improving the user experience.

[0084] An embodiment of the present application further provides a display device, which may include the display substrate provided in the above embodiment.

[0085] The display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0086] It should be noted that the above-mentioned display device can be: any product or component with display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0087] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0088] In the above description, the technical details such as the patterning of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0089] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0090] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a first side and a second side adjacent to the first side, wherein the length of the first side is greater than the length of the second side; A plurality of sub-pixels are arranged on one side of the substrate, the plurality of sub-pixels are arranged in an array in a first direction and a second direction, the sub-pixels in the same pixel row are arranged along the second direction, and the sub-pixels in the same pixel column are arranged along the first direction, the first direction is parallel to the extension direction of the second side, and the second direction is parallel to the extension direction of the first side; A plurality of gate lines are arranged on one side of the base substrate, the gate lines extend along the second direction and are electrically connected to the sub-pixels in a pixel row, and the gate lines are configured to transmit gate drive signals to the sub-pixels; A plurality of data lines are arranged on one side of the base substrate, the data lines extend along the first direction, one of the data lines is electrically connected to at least part of the sub-pixels in a pixel column, and the data line is configured to transmit a data voltage signal to the sub-pixel.

2. The display substrate according to claim 1, characterized in that: The base substrate comprises a display area, a first peripheral area and a second peripheral area, the first peripheral area is located on a side of the display area facing the first side, the second peripheral area is located on a side of the display area facing the second side, and the plurality of sub-pixels are arranged in the display area; the display substrate further comprises: At least one gate driving circuit is arranged in the second peripheral area, and the gate driving circuit includes a plurality of cascaded shift registers. The gate line extends to the second peripheral area and is electrically connected to one level of the shift register.

3. The display substrate according to claim 2, characterized in that: The first peripheral area is provided with a binding area, the binding area is configured to bind a display driver chip, the binding area includes a data pin, the data line extends to the binding area, and is electrically connected to one of the data pins.

4. The display substrate according to claim 3, characterized in that: The multiple data lines include a first data line and a second data line; the first peripheral area is provided with at least two binding areas, and the at least two binding areas include a first sub-binding area and a second sub-binding area. The first data line extends to the first sub-binding area and is electrically connected to the data pin in the first sub-binding area, and the second data line extends to the second sub-binding area and is electrically connected to the data pin in the second sub-binding area.

5. The display substrate according to claim 4, characterized in that: The first sub-binding area and the second sub-binding area are located at the same side of the display area, or at two opposite sides of the display area.

6. The display substrate according to claim 4, characterized in that: The multiple sub-pixels include a first pixel column and a second pixel column arranged alternately in the second direction; the sub-pixels of the first pixel column are green sub-pixels, and the second pixel column includes red sub-pixels and blue sub-pixels, and the red sub-pixels and the blue sub-pixels are arranged alternately along the first direction.

7. The display substrate according to claim 6, characterized in that: The sub-pixels in the same first pixel column are electrically connected to the same first data line, and the sub-pixels in the same second pixel column are electrically connected to the same second data line.

8. The display substrate according to claim 6, characterized in that: The red sub-pixels in the same second pixel column are electrically connected to the same first data line, and the blue sub-pixels in the same second pixel column are electrically connected to the same second data line.

9. The display substrate according to claim 6, characterized in that: The green sub-pixels in the same first pixel column are electrically connected to the same first data line or the same second data line; or, The green sub-pixels in odd-numbered rows in the first pixel column are electrically connected to the same first data line, and the green sub-pixels in even-numbered rows in the first pixel column are electrically connected to the same second data line; or, The green sub-pixels in even-numbered rows in the first pixel column are electrically connected to the same first data line, and the green sub-pixels in odd-numbered rows in the first pixel column are electrically connected to the same second data line.

10. The display substrate according to claim 3, characterized in that: The binding area includes a clock pin; The display substrate further comprises a plurality of clock signal lines, which are arranged in the second peripheral area; the clock signal lines extend along the first direction and are electrically connected to the multiple stages of the shift registers, and the clock signal lines are configured to transmit clock signals to the shift registers; The clock signal line extends to the first peripheral area and is electrically connected to the clock pin.

11. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 10.

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