Package with component carrier and embedded optical chip and electrical chip with horizontal signal path therebetween

Abstract

A package (100) wherein the package (100) comprises: a component carrier (102) comprising at least one electrically conductive layer structure (104) and / or at least one electrically insulating layer structure (106); and an optical chip (108) and an electrical chip (110) functionally coupled to each other and embedded side-by-side in the component carrier (102) such that a signal path (112) between the optical chip (108) and the electrical chip (110) lies in a horizontal plane.

Description

Technical Field

[0001] The present invention relates to a package and a method for manufacturing the package. Background Art

[0002] Against the background of the ever-increasing product functionality of component carriers equipped with one or more components and the increasing miniaturization of such components as well as the ever-increasing number of components connected to component carriers such as printed circuit boards, increasingly powerful array-like components or packages with a plurality of components having a plurality of contacts or connections with increasingly smaller spacings between these contacts are being used. In particular, component carriers should be mechanically robust and electrically reliable in order to be able to operate even under harsh conditions.

[0003] US2021 / 0066269 discloses a semiconductor package comprising a first redistribution layer structure, a photonic integrated circuit, an electronic integrated circuit, a waveguide and a memory. The photonic integrated circuit is arranged above the first redistribution layer structure and electrically connected to the first redistribution layer structure, and the photonic integrated circuit comprises an optical transceiver and an optical coupler. The electronic integrated circuit is arranged above the first redistribution layer structure and electrically connected to the first redistribution layer structure. The waveguide is optically coupled to the optical coupler. The memory is electrically connected to the electronic integrated circuit.

[0004] Conventional methods of forming a package including an optical chip and an electrical chip have high complexity and may suffer from signal distortion. Summary of the invention

[0005] It may be desirable to form a compact electro-optical package with high signal integrity.

[0006] According to an exemplary embodiment of the present invention, a package is provided, which includes: a component carrier, which includes at least one electrically conductive layer structure and / or at least one electrically insulating layer structure; and an optical chip and an electrical chip, which are functionally coupled to each other and embedded side by side in the component carrier (preferably embedded side by side in the surface area of ​​the component carrier), so that a signal path between the optical chip and the electrical chip is located in a horizontal plane.

[0007] According to another exemplary embodiment of the present invention, a method for manufacturing a package is provided, wherein the method comprises: providing a component carrier comprising at least one electrically conductive layer structure and / or at least one electrically insulating layer structure; functionally coupling an optical chip and an electrical chip; and embedding the optical chip and the electrical chip side by side in the component carrier (preferably embedding the optical chip and the electrical chip side by side in a surface area of ​​the component carrier), such that a signal path between the optical chip and the electrical chip is located in a horizontal plane.

[0008] In the context of the present application, the term "package" may particularly denote a device having one or more components, such as a semiconductor die, mounted on a supporting structure and electrically connected in the package.

[0009] In the context of the present application, the term "component carrier" may particularly denote any support structure on which and / or in which one or more components can be directly or indirectly accommodated to provide mechanical support and / or electrical connection. In other words, the component carrier may be configured as a mechanical and / or electronic carrier for the components. In particular, the component carrier may be one of a printed circuit board, an organic interposer and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different types of component carriers of the above-mentioned types of component carriers.

[0010] In the context of the present application, the term "layer structure" may particularly denote a continuous layer, a patterned layer or a plurality of discontinuous islands in a common plane.

[0011] In the context of the present application, the term "chip" may particularly denote, for example, a component that performs electronic and / or optical tasks. For example, a chip may be an active component, such as a semiconductor chip comprising a semiconductor material, in particular as a main material or basic material. The semiconductor material may, for example, be a type IV semiconductor, such as silicon or germanium, or may be a type III-V semiconductor material, such as gallium arsenide. In particular, a chip may be a bare wafer or a molded wafer. At least one integrated circuit element may be monolithically integrated in such a chip.

[0012] In the context of the present application, the term "optical chip" may particularly refer to a chip having optical functions. In particular, such an optical chip may be a chip configured to receive an optical signal, and more particularly, such an optical chip may be a chip configured to convert a received optical signal into an electrical signal by an electro-optical converter (e.g., a photodiode). The optical chip may also have processing capabilities for processing optical signals and / or electrical signals, from which the optical chip may obtain an optical signal. The optical chip may be an electro-optical chip, in particular providing an optical function of an electro-optical system. In particular, the optical chip may also have an integrated semiconductor laser diode and / or an amplifier. Therefore, examples of integrated circuit elements of an optical chip may be photodiodes and / or laser diodes. For example, an integrated III-V type device, such as at least one laser, at least one amplifier and / or at least one photodiode, may be implemented in an optical chip.

[0013] In the context of the present application, the term "electrical chip" may particularly refer to a chip having an electrical function. For example, the electrical chip may be configured to process electrical signals, in particular to process electrical signals received from an optical chip. The electrical chip may also include a driving function, in particular for driving the optical chip. The electrical chip may be an electro-optical chip, in particular providing an electrical function of an electro-optical system. In particular, the electrical chip may have an amplification function, which is provided, for example, by one or more transimpedance amplifiers (TIA). The electrical chip may be used as an interface between a modulator and its driver when implemented as a transmitter. The electrical chip may be used as an interface between a photodiode and an assigned TIA when implemented as a receiver.

[0014] In the context of the present application, the term "functionally coupled chips" may particularly mean that the optical chip and the electrical chip may be interconnected to functionally cooperate with each other. For example, signal transmission (particularly electrical signal transmission and / or optical signal transmission) may be implemented between the optical chip and the electrical chip. For example, one of the chips may drive another chip. One of the chips may also process a signal provided by another chip.

[0015] In the context of the present application, the term "embedded chip" may particularly mean fully embedded or only partially embedded. In a fully embedded embodiment, the entire vertical spatial range between the upper end and the lower end of the corresponding chip is located inside the component carrier. In a partially embedded embodiment, the vertical spatial range between the upper end and the lower end of the corresponding chip is only partially located inside the component carrier, for example, the chip can protrude upward and / or downward beyond the component carrier. In one embodiment, the upper end of the at least partially embedded corresponding chip can be aligned with the upper main surface of the component carrier, and / or the lower end of the corresponding chip can be aligned with the lower main surface of the component carrier. In another embodiment, the upper end of the corresponding chip can be located below the upper main surface of the component carrier, and / or the lower end of the at least partially embedded corresponding chip can be located above the lower main surface of the component carrier. However, it is also possible that the upper end portion of the corresponding chip protrudes vertically beyond the upper main surface of the component carrier, and / or the lower end portion of the corresponding chip protrudes vertically below the upper main surface of the component carrier.

[0016] In the context of the present application, the term "chips arranged side by side" may particularly mean that the electrical chip and the optical chip are arranged laterally relative to each other. Specifically, the electrical chip and the optical chip may share at least one common horizontal plane extending through both the electrical chip and the optical chip. In an embodiment, the entire vertical extension range of the optical chip coincides with the entire vertical extension range of the electrical chip. In such an embodiment, both the electrical chip and the optical chip may have the same thickness and may have lower main surfaces aligned with each other and upper main surfaces aligned with each other. In another embodiment, only a portion of the vertical extension range of the optical chip coincides with the vertical extension range of the electrical chip. In such an embodiment, for example, the thickness of the electrical chip and the thickness of the optical chip may be different, and only the upper main surface or the lower main surface of the electrical chip and the optical chip are aligned with each other.

[0017] Each chip and component carrier can include two opposite main surfaces. The main surfaces can form the two largest surface areas of the chip or component carrier. The main surfaces are connected by circumferential sidewalls. The thickness of the chip or component carrier is defined by the distance between the two opposite main surfaces. The main surfaces can include functional parts, such as conductive traces or conductive interconnects connected to other components.

[0018] In the context of the present application, the term "the signal path between the optical chip and the electrical chip is located in a horizontal plane" may particularly mean that the signal propagation between the optical chip and the electrical chip may occur horizontally rather than vertically. Therefore, substantially the entire signal propagation between the optical chip and the electrical chip may be located in the horizontal plane of the package. In particular, no electrically conductive through-connections (such as stacked vias or metal pillars) and / or vertical optical through-connections (such as vertical optical fibers or optical fiber portions) will contribute to the signal transmission between the optical chip and the electrical chip. For example, at least a portion of an electrical redistribution layer connects the optical chip to the electrical chip, and the electrical redistribution layer may extend horizontally on one or only some thin horizontal films. Optionally, the signal path between the optical chip and the electrical chip located in the horizontal plane may also extend laterally along another path portion that leaves the optical chip from the electrical chip and / or leaves the electrical chip from the optical chip.

[0019] According to an exemplary embodiment, the package has a component carrier (such as a printed circuit board or an integrated circuit substrate) and an optical chip and a cooperating electrical chip embedded in the component carrier relative to each other in the lateral direction. Advantageously, the signal path (the signal path can be an electrical signal path and / or an optical signal path) for transmitting signals between the optical chip and the electrical chip can be horizontally defined, in particular, only horizontally defined. By taking this measure, a package with an electro-optical function can be manufactured, the package has a compact design and the signal path is very short. This can in turn promote signal integrity by strongly suppressing signal loss and signal distortion. Therefore, high signal quality can be ensured. At the same time, small signal loss can also lead to small heat dissipation of the chip into the component carrier, thereby promoting high thermal performance and suppressing thermal stress. Thermal stress reduction can keep undesirable phenomena such as warping and delamination less. In short, according to an exemplary embodiment, the transmission line of the package with embedded optical chip and electrical chip can be significantly shortened. Therefore, a highly compact package can be obtained, which has electro-optical function and high electrical reliability, mechanical reliability and thermal performance.

[0020] Detailed Description of Exemplary Embodiments

[0021] In the following, further exemplary embodiments of the package and the method will be described.

[0022] In an embodiment, the optical chip and the electrical chip are embedded side by side in the surface area of ​​the component carrier. Thus, the optical chip and the electrical chip can extend almost to the upper main surface of the package, and the optical chip and the electrical chip can be coupled by a planar redistribution layer or structure on the top side of the package to exchange signals between the optical chip and the electrical chip. Such a package is easy to manufacture and also allows very short signal paths between the electrical chip and the optical chip and also has at least one optional surface mounted chip (such as the control chip described below).

[0023] In an embodiment, the optical chip and the electrical chip are integrated in a package body, which is embedded in a component carrier. This embodiment will be described below. However, the optical chip and the electrical chip can also be embedded directly in the component carrier separately. For example, the optical chip and the electrical chip can be inserted into one or two cavities or recesses of the component carrier and can then be glued in place, for example by lamination.

[0024] In an embodiment, the optical chip and the electrical chip are integrated in a package body, which is embedded in a component carrier.The package body may include at least one dielectric layer.

[0025] In an embodiment, the optical chip and the electrical chip are encapsulated in a packaging material, which is embedded in a component carrier. This integrated body of packaging material, optical chip and electrical chip can be implemented as a whole in the component carrier, for example, in a cavity located in the component carrier. The packaging material can include a laminate material.

[0026] An advantage of the laminate material of the package body is that the material of the component carrier (including in particular the resin) can have the same or similar physical properties (e.g. coefficient of thermal expansion, CTE), which can keep the CTE mismatch and thus the warpage small. However, it can also be a wafer-level package, which can have the following advantages: It can allow for a higher density of layers of redistribution structures.

[0027] The described method of embedding an encapsulation body in a cavity of a component carrier allows for an efficient manufacturing process.

[0028] In an embodiment, the optical chip and the electrical chip are integrated in a panel-level packaging body, which is embedded in a component carrier. Panel-level packaging can refer to the following process: before separating the panel - the integrated circuit or chip is embedded in the panel - into individual independent boards, a laminate is attached to the integrated circuit or chip. In panel-level packaging, a large number of chips are embedded in a laminate in a panel format. According to the described embodiments, the optical chip and the electrical chip can be embedded in the laminate, and a portion of a single laminate with embedded chips can be embedded in a component carrier as a single panel-level packaging body.

[0029] In an embodiment, the optical chip and the electrical chip are encapsulated in a laminate (e.g., an organic laminate), which is embedded in a component carrier. This integrated body of the laminate, the optical chip, and the electrical chip can be implemented as a whole in the component carrier, for example, in a cavity located in the component carrier. This integrated body can be a panel-level packaging body.

[0030] Furthermore, the described method of embedding a panel-level package body into a cavity of a component carrier may enable an efficient manufacturing process.

[0031] In an embodiment, the optical chip and the electrical chip are embedded at the same vertical upper height and / or vertical lower height, for example, embedded at the same vertical upper height and / or vertical lower height in the surface area of ​​the component carrier. By aligning the upper main surface and / or the lower main surface of the optical chip at the electrical chip, the horizontal signal transmission between the optical chip and the electrical chip can be further simplified. A person skilled in the art will be aware of the fact that unavoidable device tolerances and / or machine tolerances may lead to very small mutual displacements between the aligned main surfaces of the chips.

[0032] In an embodiment, the upper main surface of the optical chip and the upper main surface of the electrical chip are recessed relative to the upper main surface of the component carrier. The vertical gap corresponding to the vertical recess between the upper main surface of the component carrier and the upper main surface of the chip can be partially or fully filled by at least one redistribution layer or structure, which is used to interconnect the electrical chip and the optical chip for signal transmission between the electrical chip and the optical chip. In particular, the thickness of such a redistribution layer or structure above the chip (and therefore the vertical offset between the upper surface of the optical chip and the upper surface of the electrical chip relative to the upper main surface of the component carrier) can be in the range of 10nm to 500μm, preferably in the range of 50nm to 50μm.

[0033] In an embodiment, the package includes an optical waveguide, which is particularly a polymer fiber (wherein any material with adjustable reflectivity, glass waveguides, etc. may also be options), which is configured to supply an optical signal to a semiconductor waveguide, which is particularly a silicon waveguide, an indium phosphide (InP) waveguide or a waveguide comprising a photopolymer material, and the semiconductor waveguide is located at the upper main surface of the optical chip or at the side surface of the optical chip (especially for chips where light is coupled from the edge). More generally, a material with adjustable refractive index can be used as a waveguide material. In particular, an optical waveguide can represent a physical structure that guides electromagnetic waves (such as light) in the spectrum. Examples of optical waveguides include optical fiber waveguides, transparent dielectric waveguides made of plastic and glass, liquid light guides, and liquid waveguides. However, the semiconductor waveguide can be a waveguide manufactured with semiconductor technology (especially with silicon technology or InP-based technology), and the semiconductor waveguide can form an integral part of the optical chip. Alternatively, the semiconductor waveguide can be attached to the optical chip. Highly advantageously, electromagnetic radiation propagating through an optical waveguide can be coupled into a semiconductor waveguide, thereby providing efficient optical signal transmission for optical chips.

[0034] In an embodiment, the optical waveguide is physically connected to the semiconductor waveguide (particularly overlapped in the case of evanescent field coupling). By overlapping portions of the optical waveguide (particularly horizontal portions) with portions of the semiconductor waveguide (particularly horizontal portions), evanescent field coupling can be established between the optical waveguide and the semiconductor waveguide, thereby efficiently optically coupling the optical waveguide to the optical chip. Descriptively, evanescent wave coupling can describe the coupling of electromagnetic waves from one waveguide to another waveguide by attenuating the electromagnetic field.

[0035] However, there are other possibilities for coupling light to semiconductor waveguides (e.g., silicon waveguides). For example, the waveguide connector can be edge coupled (particularly end-fire coupled), grating coupled, or evanescent field coupled. These optical coupling architectures are described, for example, in Hosam Mekawey, Mohamed Elsayed, Yehea Ismail, Mohamed A Swillam, “Optical Interconnects Finally Seeing the Light in Silicon Photonics: Past the Hype,” Nanomaterials, January 29, 2022, 12(3):485. In addition, all three coupling mechanisms mentioned can use adiabatic tapered waveguides as disclosed, for example, in Gyeongho Son, Seungjun Han, Jongwoo Park, Kyungmok Kwon, and Kyoungsik Yu, “High-efficiency broadband light coupling between optical fibers and pho-tonic integrated circuits,” Nanophotonics 7(12), October 2018. In summary, according to exemplary embodiments of the present invention, many different optical coupling mechanisms can be implemented. These optical coupling mechanisms include, but are not limited to, edge coupling, grating coupling, evanescent field coupling, and adiabatic optical coupling by tapering the waveguide (particularly with a gradual geometric change).

[0036] In an embodiment, the horizontal extension of the semiconductor waveguide does not extend beyond the horizontal extension of the optical chip.For example, the semiconductor waveguide may be flush with the edge, or may be located in the middle of the optical chip.

[0037] In an embodiment, at least a portion of the optical waveguide extends along the upper main surface of the component carrier and / or along the upper main surface of an inlay, in particular a glass inlay, which is embedded in a surface area of ​​the component carrier. For example, the optical waveguide can supply an optical signal provided at a side wall of the package, in particular at the upper end of such a side wall, to a more central part of the package where the optical chip can be arranged. This can be achieved in an easy manner by simply attaching the optical waveguide to the upper main surface of the component carrier or to an inlay, which can be specially configured to facilitate low-loss optical signal transmission. In particular, glass inlays have proven to be an excellent solution for this purpose.

[0038] In an embodiment, the package comprises a waveguide connector, which is optically coupled to the optical waveguide and, in particular, extends along the upper main surface of the component carrier and / or along the upper main surface of an inlay embedded in the surface area of ​​the component carrier, the inlay being, in particular, a glass inlay. The waveguide connector may be a fiber optic connector. Such a fiber optic connector may be an optical component coupled to an optical fiber and such a fiber optic connector enables rapid connection and disconnection. The fiber optic connector may be mechanically coupled and aligned with the optical fiber core so that light can pass through.

[0039] In an embodiment, the package comprises a waveguide connector, which is directly optically coupled to a semiconductor waveguide, in particular a silicon waveguide or a waveguide comprising a photopolymerizable material, which is located at the upper main surface of the optical chip. The waveguide connector may extend at least partially along the upper main surface of the component carrier and / or along the upper main surface of an inlay embedded in the surface area of ​​the component carrier, in particular a glass inlay. Such a waveguide connector may be surface mounted on the component carrier and / or surface mounted on the above-mentioned inlay, preferably a glass inlay. By bringing the waveguide connector into direct contact with the semiconductor waveguide, the provision of an optical waveguide may be omitted, so that the package may be made more compact.

[0040] In an embodiment, the optical chip is configured to convert the supplied optical signal into an electrical signal, and optionally configured to pre-process the electrical signal. Thus, the optical chip can directly convert the optical signal into an electrical signal, for example, by converting the optical signal directly into an electrical signal via a photodiode of the optical chip. The optical chip can also provide signal processing, such as modulation. The optical chip can include active and / or passive components, in particular monolithically integrated active and / or passive components.

[0041] Additionally or alternatively, the optical chip may be configured to convert the supplied electrical signal into an optical signal, and optionally to pre-process the optical signal.

[0042] In an embodiment, the electrical chip is configured to drive the optical chip and / or to amplify a signal from the optical chip. When the electrical chip is implemented as a driver and / or amplifier of the optical chip, the electrical chip may include a circuit and / or at least one component that can be used to control the optical chip. The electrical chip may be configured to amplify a signal, in particular an optical signal, received from the optical chip, in particular after converting the signal, in particular the optical signal, received from the optical chip into an electrical signal, and amplify the signal received from the optical chip. For example, the electrical chip may include at least one transimpedance amplifier (TIA) for this purpose.

[0043] In an embodiment, the package also includes a control chip that receives an electrical signal from the electrical chip and is configured to further process the electrical signal, in particular to forward the electrical signal to an electronic periphery. For example, the control chip can forward the electrical signal to one or more other nodes, such as forwarding the electrical signal to a central processing unit (CPU). Such additional nodes may form part of the package, or such additional nodes may be arranged elsewhere (e.g., arranged on a motherboard, on which the package may also be mounted).

[0044] In an embodiment, the package further includes a control chip configured as an additional optical chip for performing optical processing.

[0045] In an embodiment, the control chip is an application specific integrated circuit (ASIC). Such an ASIC may be an integrated circuit chip customized or customizable for a specific dedicated purpose, rather than for general use.

[0046] In an embodiment, the control chip is surface mounted on the component carrier. The control chip may be the primary heat source for the entire package (e.g., may have a power of 100W to 2kW, such as 1kW). Therefore, surface mounting the control chip rather than embedding the control chip may simplify heat removal from such a control chip.

[0047] In an embodiment, the package includes a heat sink mounted on the exposed surface of the control chip. For example, such a heat sink can be a body made of a high thermal conductivity material (such as copper or aluminum) to facilitate heat transfer from the control chip to the heat sink. In addition, the heat sink can be shaped (for example, including a plurality of cooling fins) to facilitate heat removal to the environment, such as ambient air. By attaching the heat sink to the exposed main surface of the control chip, the thermal performance of the package can be further improved. In combination with possible additional heat removal paths extending downward from the mounting surface of the control chip through the component carrier (compare with the description below), double-sided cooling can be achieved for the control chip. This can enable the package to have excellent thermal performance.

[0048] In an embodiment, the control chip is arranged directly above the electrical chip (see, for example, Figure 4 ). In this configuration, the signal path from the electronics chip to the control chip is extremely short, further promoting high signal quality and low heat loss.

[0049] In another embodiment, the control chip is arranged above the electrical chip and is laterally offset relative to the electrical chip. Figure 1Such an embodiment is shown in . A corresponding arrangement can clearly separate the heat removal path from the control chip on the one hand and the electrical chip on the other hand. In particular, undesired heating of the electrical chip by the control chip or undesired heating of the control chip by the electrical chip can then be reliably prevented.

[0050] In another embodiment, the control chip is arranged directly above the package body, and the optical chip and the electrical chip are integrated in the package body (for example, Figure 6 ). This design allows an extremely compact configuration in the horizontal plane. In addition, in this configuration, the signal paths between the electrical chip and / or optical chip on the one hand and the control chip on the other hand can be kept extremely short.

[0051] In an embodiment, the control chip is arranged directly above the packaging material of the packaging body, and the optical chip and the electrical chip are integrated in the packaging body. For this embodiment, refer to, for example Figure 4 In this configuration, the encapsulation material may form part of the mounting base for the control chip.

[0052] In an embodiment, the package includes an electrical redistribution structure (e.g., an electrical redistribution layer) that extends horizontally above the electrical chip and / or the optical chip. In the context of the present application, the term "redistribution structure" may particularly refer to an arrangement of interconnected patterned electrically conductive structures, the arrangement having a portion having a smaller pitch compared to another portion having a larger pitch. Pitch may refer to a characteristic distance between adjacent electrically conductive elements, such as trace elements and / or connecting elements. By providing spatially separated portions of the redistribution structure with different pitches, the redistribution structure may form an electrical joint between electrically connecting elements of larger size and electrically connecting elements of smaller size. In particular, in a portion having a larger pitch (e.g., greater than 50 μm), the number of electrically conductive elements per unit area is smaller than in another portion having a smaller pitch (e.g., less than 50 μm).

[0053] The electrical redistribution structure may be a NIL (Nano Imprint Lithography) or PID (Photosensitive Dielectric) patterned structure. In yet another embodiment, the redistribution structure may be made based on silicon, for example implemented as a silicon interposer.

[0054] For NIL type electrical redistribution structure, more generally, an electrical redistribution structure formed as the following design layer can be provided: the design layer has a stamped surface contour portion and a metal located in a recess of the stamped surface contour portion. In the context of the present application, the term "design layer" can mean the following layer: the layer can be flexibly processed to be used to design substantially any desired surface contour portion extending in the layer and / or extending through the layer. Therefore, any desired wiring design can be converted into a corresponding surface contour portion of the design layer, so that filling the recess formed in the design layer with an electrically conductive material can lead to a predetermined wiring design. Preferably, the design layer can be a dielectric that is initially at least partially uncured, and the dielectric can be cured during and / or after the predetermined surface contour portion is formed in the design layer. The surface contour portion can then be made permanent. Therefore, the design layer can be deformable before curing and can be non-deformable after curing. Preferably, one or more recesses in the design layer structure can have different horizontal extensions and / or vertical extensions. Alternatively, the horizontal extension and / or vertical extension of one or more recesses in the design layer structure may be the same. In the context of the present application, the term "imprinting a surface profile in a design layer" may refer to a process of imprinting or molding a predetermined surface pattern in a design layer. For example, this may be achieved by pressing a working mold (or working embossing piece) in a (particularly stationary) deformable design layer or by guiding the working mold along a (particularly stationary) deformable design layer. Such a working mold may have an opposite surface profile compared to the surface profile of the design layer being processed. During the development and manufacturing process, a master mold may first be manufactured, such as by gray scale lithography. The master mold may then be replicated by imprinting the master mold into a transparent silicone material, etc., multiple times, and a master working mold may be generated. Finally, a working mold may be made by replicating the master working mold. The working mold may be used during mass production and imprinted on the panel surface. In the context of this application, the term "embossed surface profile" may refer to a surface profile having a feature structure resulting from an embossing process performed by pressing a working mold onto a design layer. Due to this manufacturing process, the embossed surface profile has lower roughness, steeper sidewalls, and other pattern features than surface profiles that can be obtained by etching-based or laser-based patterning processes.

[0055] For a PID type electrical redistribution structure, the photoimageable dielectric may refer to a dielectric film or a dielectric layer that may be directly patterned by irradiating an electromagnetic radiation beam (particularly a laser beam) along a predetermined trajectory of the dielectric film or the dielectric layer, thereby patterning the dielectric film or layer. After this patterning process, the recesses formed in the dielectric film or the dielectric layer may be filled with an electrically conductive material, thereby obtaining an electrical redistribution structure.

[0056] In an embodiment, at least a portion of the electrical redistribution structure may extend to be connected to the electrical chip, in particular, at least a portion of the electrical redistribution structure may extend horizontally to be connected to the electrical chip, more particularly, at least a portion of the electrical redistribution structure may extend to be connected to the electrical chip at a level corresponding to the upper main surface of the component carrier. For example, the electrical redistribution structure may be formed as a surface portion of the package, which surface portion is at least partially located on the optical chip, at least partially located on the electrical chip, at least partially located between the electrical chip and the optical chip, and / or at least partially located between the electrical chip and the control chip.

[0057] In an embodiment, at least a portion of the electrical redistribution structure extends below the control chip. Thus, different spacings below the control chip on the one hand and below the electrical chip on the other hand can be bridged by the electrical redistribution structure.

[0058] In an embodiment, at least a portion of the electrical redistribution structure is disposed in a package body, in particular in a panel-level package body. Such a package body may include an electrical chip, an optical chip, and a packaging part as a single integrated body (in the case of a panel-level package body, the packaging part may be a laminate, in particular an organic laminate). Advantageously, the electrical redistribution structure (or a portion of the electrical redistribution structure) may also be integrated in the package body. This may further simplify the entire manufacturing process of the package.

[0059] In an embodiment, a further electrical redistribution structure is arranged above the electrical redistribution structure and electrically connects the electrical chip and / or the optical chip to the component carrier. Thus, a plurality of interconnected electrical redistribution structures may also be provided, which may be arranged laterally relative to each other and / or arranged one above the other. This may allow even complex electrical interconnections to be obtained without deviating from a substantially horizontal signal transmission.

[0060] In an embodiment, the electrical redistribution structure, in particular a layer, extends over at least two vertically stacked electrically conductive layer structures. For example, the electrical redistribution structure may extend over 1, 2 or 3 thin layers.

[0061] In particular, the package may include an optical redistribution structure (e.g., an optical redistribution layer) that extends to connect to the optical chip, more particularly, the optical redistribution structure extends horizontally to connect to the optical chip, and more particularly, the optical redistribution structure extends to connect to the optical chip at a level corresponding to the upper main surface of the component carrier. The optical redistribution structure may redistribute the optical signal through different structure sizes. For example, the optical redistribution structure may manage the optical junction between a larger size optical waveguide and a smaller size semiconductor waveguide that forms part of the optical chip or is connected to the optical chip.

[0062] In an embodiment, the optical redistribution structure and the electrical redistribution structure share the same horizontal plane. Preferably, both the optical redistribution structure and the electrical redistribution layer may extend along the upper major surface of the package. This may focus the optical signal propagation and the electrical signal propagation in a common horizontal plane.

[0063] In an embodiment, the package includes a heat removal structure, which is configured to remove heat from the package and extends vertically through the component carrier. More specifically, the corresponding heat removal structure can remove heat generated by the optical chip from the package, can remove heat generated by the electrical chip from the package, and / or can remove heat generated by the control chip from the package. In particular, an assigned heat removal structure can be set for each chip in the chip. The heat removal structure can be made of a high thermal conductivity material, which preferably has a thermal conductivity of at least 50W / mK. Preferably, the heat removal structure includes copper or is composed of copper.

[0064] In an embodiment, at least a portion of the heat removal structure extends between the bottom of the optical chip and / or the bottom of the electrical chip and / or the bottom of the control chip on the one hand and the lower main surface of the component carrier on the other hand. Thus, the respective heat removal structure may extend over the entire vertical thickness from the bottom side of the respective chip to the bottom main surface of the package.

[0065] In an embodiment, the heat removal structure includes at least one metal block (such as a copper block) and / or at least one metal paste structure (especially copper paste) and / or at least one metal pillar (such as a copper pillar or an array of parallel copper pillars). In particular, at least one metal block, at least one metal paste structure and / or at least one metal pillar can be vertically stacked in the corresponding heat removal structure.

[0066] In an embodiment, the package is configured so that the signal flow is horizontal and the heat flow is vertical. In other words, the signal flow and the heat flow can be perpendicular to each other. Vertical heat removal in an upward direction and / or a downward direction can be triggered by extending one or more of the above-mentioned heat removal structures through the package in a vertical direction, and / or by the above-mentioned heat sink mounted on the top of the control chip (and when the electrical chip and / or the optical chip can approach or be close to the upper main surface of the package at the upper main surface of the package, the above-mentioned heat sink is optionally mounted on the top of the electrical chip and / or the top of the optical chip). In contrast, electrical coupling structures and / or optical coupling structures (such as the above-mentioned electrical redistribution structures and / or optical redistribution structures) can promote the horizontal signal flow of electrical signals, and optionally can also promote the horizontal signal flow of optical signals. This can reliably disconnect the signal flow from the heat flow.

[0067] In an embodiment, the signal path extends in a horizontal plane corresponding to the upper main surface of the component carrier. Propagating electrical and / or optical signals along the upper main surface of the component carrier and / or the upper main surface of the package can result in a simple structure of the package and a short signal path relative to a surface-mounted control chip.

[0068] In an embodiment, the optical signal path portion and the electrical signal path portion of the signal path share the same horizontal plane. In particular, the electrical redistribution structure and the optical redistribution structure may be at least partially coplanar. This also helps to shorten the signal path.

[0069] In an embodiment, the electrical signal path portion of the signal path for transmitting electrical signals between the optical chip and the electrical chip has no vertical through-connection. In particular, for the electrical transmission, stacked vias may not be required, and for the optical transmission, vertical optical fiber portions may not be required.

[0070] In an embodiment, the component carrier is an integrated circuit substrate. In the context of the present application, the term "integrated circuit substrate" (IC substrate) can particularly refer to a component carrier having a size and spacing adjusted according to the requirements of the integrated circuit components (especially control chips) mounted thereon. The IC substrate can be a relatively small component carrier relative to the PCB, one or more integrated circuit components can be mounted on the relatively small component carrier, and the relatively small component carrier can be used as a connector between one or more chips and the PCB. For example, the IC substrate can have a size roughly the same as the electronic component to be mounted thereon (for example, in the case of a chip-scale package (CSP)). In another embodiment, the IC substrate can be larger than the allocated components (for example, in a flip chip ball grid array-FCBGA configuration). More specifically, the IC substrate can be understood as the following carrier: a carrier for an electrical connector or an electrical network, and a component carrier for a connector that is comparable to a printed circuit board (PCB) but has a relatively high density of lateral and / or vertical arrangements. The lateral connector is, for example, a conductive path, and the vertical connector can be, for example, a drill hole. These lateral connectors and / or vertical connectors can be arranged in the IC substrate and can be used to provide electrical, thermal and / or mechanical connections between accommodated components or unaccommodated components (such as bare chips), in particular IC chips, and printed circuit boards or interposers. The dielectric part of the IC substrate may include a resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres). The spacing of the IC substrate, that is, the distance between the corresponding edges of two adjacent metal structures, may not exceed 150 μm, in particular not more than 100 μm. In contrast, the spacing of the PCB may be at least 200 μm, in particular at least 300 μm.

[0071] In an embodiment, the component carrier is formed as a plate-like element. This contributes to a compact design, wherein the component carrier still provides a large base for mounting components thereon. Furthermore, in particular bare wafers as an example of embedded electronic components can be conveniently embedded in thin plates such as printed circuit boards due to their small thickness.

[0072] In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (particularly an IC substrate) and an interposer.

[0073] In the context of the present application, the term "printed circuit board" (PCB) may particularly denote a plate-like component carrier formed by laminating a plurality of electrically conductive layer structures with a plurality of electrically insulating layer structures, for example by means of applying pressure and / or providing thermal energy. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures may comprise resin and / or glass fibers, so-called prepregs or FR4 materials. The individual electrically conductive layer structures may be connected to each other in the desired manner by forming holes through the laminate, for example by laser drilling or mechanical drilling, and partially or completely filling the holes with an electrically conductive material, in particular copper, to form vias or any other through-hole connections. The filled holes connect the entire stack (through-hole connections extending through a plurality of layers or the entire stack), or the filled holes connect at least two electrically conductive layers, so-called vias. Similarly, optical interconnects may be formed through the layers of the stack to accommodate an electro-optical circuit board (EOCB). In addition to one or more components that can be embedded in the printed circuit board, the printed circuit board is generally configured to accommodate one or more components on one surface or two opposite surfaces of the plate-shaped printed circuit board. The one or more components can be connected to the corresponding main surface by welding. The dielectric portion of the PCB may include a resin with reinforcing fibers (such as glass fibers).

[0074] The substrate or interposer may include or be composed of a layer of at least one of the following: glass; silicon (Si); and / or a photosensitive or dry-etchable organic material, such as an epoxy-based laminate material (e.g., an epoxy-based laminate film); or a polymer compound (which may or may not include photosensitive and / or heat-sensitive molecules), such as polyimide or polybenzoxazole.

[0075] In an embodiment, the at least one electrically insulating layer structure comprises at least one of the following: a resin or polymer, such as an epoxy resin, a cyanate resin, a benzocyclobutene resin; a bismaleimide triazine resin; a polyphenylene derivative (e.g. based on polyphenylene ether, PPE), a polyimide (PI), a polyamide (PA), a liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE) and / or a combination thereof. A reinforcing structure, such as a mesh, a fiber, a sphere or other kinds of filler particles, made of glass (multilayer glass), for example, may also be used to form a composite material. A semi-cured resin combined with a reinforcing agent, such as a fiber impregnated with the above resin, is called a prepreg. These prepregs are usually named after their properties, such as FR4 or FR5, which describe their flame retardant properties. Although prepregs, especially FR4, are usually preferred for rigid PCBs, other materials, especially epoxy-based laminates (such as epoxy-based laminate films) or photosensitive dielectric materials may also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers and / or cyanate resins may be preferred. In addition to these polymers, low temperature co-fired ceramics (LTCC) or other low, very low or ultra-low DK materials can be used as electrically insulating structures in the component carrier.

[0076] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, magnesium, carbon, (particularly doped) silicon, titanium and platinum. Although copper is generally preferred, other materials or coatings thereof are also possible, in particular coatings with superconducting materials or conductive polymers, such as graphene or poly (3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0077] At least one further component may be embedded in the stack and / or surface mounted on the stack. The component and / or the at least one further component may be selected from the following: a non-electrically conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (such as a heat pipe), an optical element (such as an optical waveguide or optical conductor connector), an electronic component or a combination of the above. The inlay may be, for example, a metal block with or without a coating of insulating material (IMS inlay), which may be embedded or surface mounted for the purpose of promoting heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W / mK. Such materials are typically based on, but not limited to, metals, metal oxides and / or ceramics, such as copper, aluminum oxide (Al2O3) or aluminum nitride (AlN). In order to increase the heat exchange capacity, other geometries with increased surface area are also often used. Furthermore, the component may be an active electronic component (having at least one realized pn junction), a passive electronic component (such as a resistor, an inductor, or a capacitor), an electronic chip, a memory device (e.g., a DRAM or other data storage), a filter, an integrated circuit (such as a field programmable gate array (FPGA), a programmable array logic (PAL), a general purpose array logic (GAL), and a complex programmable logic device (CPLD)), a signal processing component, a power management component (such as a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), a junction field effect transistor (JFET), or an insulated gate field effect transistor (IGFET). Transistors (IGFETs), all of which are based on semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), indium phosphide (InP) and / or any other suitable inorganic compound), optoelectronic interface elements, light emitting diodes, optical couplers, voltage converters (such as DC / DC converters or AC / DC converters), cryptographic components, transmitters and / or receivers, electromechanical transducers, sensors, actuators, microelectromechanical systems (MEMS), microprocessors, capacitors, resistors, inductors, batteries, switches, cameras, antennas, logic chips and energy harvesting units. However, other components can be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element can be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, such as a ferrite core) or can be a paramagnetic element. However, the component can also be an IC substrate, an interposer or another component carrier, such as in a board-in-board configuration. The component can be surface mounted on the component carrier and / or can be embedded in the interior of the component carrier.In addition, other components, in particular components which generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, can also be used as components.

[0078] In an embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a composite of multiple layers that are stacked and connected together by applying pressure and / or heat.

[0079] After the internal layer structure of the component carrier has been processed, one or both main surfaces of the processed layer structure can be covered symmetrically or asymmetrically with one or more further electrically insulating layer structures and / or electrically conductive layer structures, in particular by lamination. In other words, the layering can be continued until the desired number of layers is obtained.

[0080] After the formation of the stack comprising the electrically insulating layer structure and the electrically conductive layer structure has been completed, the obtained layer structure or component carrier may be subjected to a surface treatment.

[0081] In particular, with regard to surface treatment, an electrically insulating solder resist may be applied to one or both of the opposite main surfaces of a layer stack or component carrier. For example, such a solder resist may be formed over the entire main surface and the solder resist layer may be subsequently patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to an electronic peripheral. Surface portions of the component carrier that are still covered with the solder resist, in particular those containing copper, may be effectively protected from oxidation or corrosion.

[0082] As far as surface treatment is concerned, a surface modification may also be selectively applied to the exposed electrically conductive surface portions of the component carrier. Such a surface modification may be an electrically conductive covering material on an exposed electrically conductive layer structure (such as a pad, conductive trace, etc., in particular a pad, conductive trace, etc. comprising or consisting of copper) on the surface of the component carrier. If such an exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (in particular copper) may be oxidized, thereby making the reliability of the component carrier low. The surface modification may then be formed as a joint between, for example, a surface mounted component and a component carrier. The surface modification has the function of protecting the exposed electrically conductive layer structure (in particular a copper circuit) and enables a connection process with one or more components, for example by welding. Examples of suitable materials for the surface modification are organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), electroless nickel immersion palladium immersion gold (ENEPIG), gold (in particular hard gold)), chemical tin (chemical and electroplating), nickel gold, nickel palladium, etc. Nickel-free materials for the surface modification may also be used, especially for high-speed applications. Examples are ISIG (immersion silver immersion gold) and EPAG (electroless palladium autocatalytic gold). BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

[0084] Figure 1 A cross-sectional view of a package according to an exemplary embodiment of the present invention is shown.

[0085] Figure 2A A cross-sectional view of a package according to another exemplary embodiment of the present invention is shown.

[0086] Figure 2B shows the method for embedding according to Figure 2A A cross-sectional view of a package body in a component carrier of a package.

[0087] Figure 3 A cross-sectional view of a package according to another exemplary embodiment of the present invention is shown.

[0088] Figure 4 A cross-sectional view of a package according to another exemplary embodiment of the present invention is shown.

[0089] Figure 5 A cross-sectional view of a package according to another exemplary embodiment of the present invention is shown.

[0090] Figure 6 A cross-sectional view of a package according to another exemplary embodiment of the present invention is shown.

[0091] Figure 7 A cross-sectional view of a package according to another exemplary embodiment of the present invention is shown.

[0092] Figures 8 to 13 Cross-sectional views of various portions of packages having different light coupling structures according to exemplary embodiments of the present invention are shown.

[0093] Fig.14 A cross-sectional view of a portion of a package according to another exemplary embodiment of the present invention is shown, the package having different couplings between an electrical chip and a corresponding electrical redistribution structure.

[0094] Fig.15 A cross-sectional view of a package according to another exemplary embodiment of the present invention is shown.

[0095] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference numerals. DETAILED DESCRIPTION

[0096] Before the exemplary embodiments will be described in more detail with reference to the accompanying drawings, some basic considerations based on which the exemplary embodiments of the present invention were developed will be summarized.

[0097] Traditionally, optical transceivers may be front panel pluggable modules. As signal speeds increase, the length of electrical transmission lines in such modules or packages may need to be reduced.

[0098] According to an exemplary embodiment of the present invention, the package includes a component carrier (e.g., an integrated circuit substrate), and an optical chip (e.g., a photonic integrated circuit) and an assigned electrical chip (in particular, an electric driver integrated circuit and / or a transimpedance amplifier circuit) can be embedded in the component carrier in a juxtaposed manner in a lateral direction. Advantageously, the signal path (in particular, an electrical signal path, optionally also an optical signal path) between the optical chip and the electrical chip can extend in a horizontal plane. This can shorten the transmission line length, in particular, shorten the electrical transmission line length. Therefore, small signal losses can achieve high signal quality and limited heat removal complexity.

[0099] In particular, the package according to the exemplary embodiment can provide an embedded fan-out package, which can be integrated by a fan-out panel level packaging (FOPLP) method for photonic integrated circuit applications. Further advantageously, a (e.g. sputtered) redistribution structure (in particular one or more redistribution layers) can be formed for connecting the package body with a (in particular ASIC-type) control chip.

[0100] The above-described embodiments have the following advantages: Specifically, the manufacturing architecture described can allow the signal path (in the horizontal plane) to be separated from the thermal path (in the vertical direction). The above-mentioned package can include an electrical chip and an optical chip (also referred to as a photonic IC), which can ensure the highest performance and the smallest form factor. In addition, a very short electrical signal path can be achieved without creating vertical interconnect elements or through-silicon vias (TSVs). Through the described package architecture, a favorable (especially optimized) wafer operating temperature can also be obtained. In particular, double-sided cooling of ASIC-type control chips can be achieved. The described package design also allows a customized heat removal architecture (especially between the electrical chip and the optical chip). In addition, the alignment of the optical joint can also be separated from the alignment of the electrical joint. In addition, an improved optical alignment tolerance can be achieved by evanescent field coupling, thereby avoiding the need to actively align the package. Advantageously, the optical joint can be optically inspected (this is because the optical waveguide can be aligned on top of the semiconductor waveguide and the optical chip). It is also possible to integrate shielding elements (particularly for shielding against electromagnetic radiation, more particularly for shielding against radio frequency radiation) and / or magnetic elements (for shielding purposes or for providing magnetic applications) in the package.

[0101] Exemplary applications of exemplary embodiments of the present invention are co-packaged optics and silicon photonics in data communications and telecommunications applications. For example, this can allow switches and transceivers to be packaged for integration into data centers and 5G wireless access networks. In addition, packages according to exemplary embodiments of the present invention can be used in automotive applications, such as lidar and / or radar. More generally, packages according to exemplary embodiments of the present invention can be used in high-speed and / or high data rate applications, such as in data centers. In addition, for example in data communications and telecommunications, a packaging technology can be configured for multiple applications. For example, packages according to exemplary embodiments can be used to manufacture transceivers, switches, network interface cards in data centers and 5G wireless access networks.

[0102] More specifically, the package according to an exemplary embodiment of the present invention can be used to form a switch (e.g., an Ethernet switch or a fiber optic network switch) or a transceiver (e.g., for converting one or more times between optical signals and electrical signals). An Ethernet switch can connect multiple optical fibers and can control routing. A photonic switch can be implemented by selectively switching optical signals supplied by optical fibers or optical ICs. A photonic switch can route optical signals between optical inputs and optical outputs without conversion or signal manipulation. An optical transceiver or optical module can have an electrical interface on one side connected to the inside of the system and an optical interface on the side connected to the outside world through an optical fiber cable or an optical fiber connector.

[0103] In particular, the following applications may be met by the package according to an exemplary embodiment of the present invention: photonic IC applications; electro-optical conversion at the IC substrate level; electro-optical IC substrates; co-packaged optics and silicon photonics in data communications and telecommunications (particularly packaging switches and transceivers for integration into data centers and 5G wireless access networks); optical communications applications (data communications, telecommunications, 5G wireless access networks, in-tower radar networks); computing applications such as high performance computing (HPC), photonic computing, quantum computing; automotive applications such as lidar.

[0104] According to an exemplary embodiment of the present invention, an integrated circuit substrate packaging technology for photonic integrated circuit applications is provided, wherein a fan-out package body is integrated into an IC substrate by a fan-out panel-level package body (FOPLP) method. The embodiment relates to an IC substrate package with an integrated optical joint and an electrical joint. For example, an optical redistribution layer for optical interconnection can be implemented based on a waveguide. The electrical redistribution structure can be used for electrical interconnection. In addition, the package according to the exemplary embodiment of the present invention can be designed to package a package body including heterogeneous component integration (i.e., the integration of optical chips and electrical chips). In particular, an exemplary embodiment provides an integrated circuit substrate with an embedded package body, wherein the optical chip and the electrical chip can be packaged together in a single package. A thermal path between the package body, the substrate and the environment can be realized at the IC substrate level. The integration of the package body can allow a short signal path (in the form of an electrical redistribution structure) to be manufactured between the package body and a dedicated integrated circuit or a control chip. Thus, exemplary embodiments provide a highly efficient optical junction (particularly in the form of an optical redistribution layer based on a refractive index tunable material, such as implemented as a polymer waveguide) and thermal management solution integrated in an IC substrate package.

[0105] In an embodiment, the package body can be embedded in the IC substrate in the following manner: a cavity is formed in the core, and the package body is inserted into the cavity after the bottom of the cavity is closed with a temporary carrier. After the package body is glued and / or laminated in place, the temporary carrier can be moved, and subsequent layers can be formed on the bottom and / or top side. In particular, this can lead to a design in which the surface of the package and the surface of the substrate can be at the same height level (the design can be represented as a quick-mount package). After embedding the package body, an electrical redistribution structure can be partially realized on the surface of the package body and partially on the surface of the substrate. This electrical redistribution structure can be formed by thin film technology, such as sputtering or thick film technology, such as electroplating. The electrical redistribution structure can thus be connected to the package body by an ASIC-type control chip, which can be surface-mounted on the substrate. It is highly advantageous that a very short signal path (preferably showing no cross-sectional changes) can be achieved by this design. The optical redistribution layer can be realized by embedding one or more glass inlays. This optical joint can allow optical signal coupling between an optical fiber connector and a semiconductor waveguide (particularly a silicon waveguide). The polymer waveguide may be located on top of the glass inlay, while the semiconductor waveguide may be implemented on the surface of the optical chip.The optical signal may be transmitted from the optical fiber connector through the polymer waveguide to the semiconductor waveguide by using evanescent field coupling.

[0106] This manufacturing architecture can make it possible to obtain high optical alignment accuracy, thereby facilitating mass production. In addition, a thermal path from the control chip through the substrate toward the package environment can also be established. The heat removal structure can be integrated in the integrated circuit substrate. Therefore, a heat conductive material (such as a copper coin, or any other heat conductive block and paste) can be embedded in the body of the integrated circuit substrate. Since the control chip is surface mounted, this design can allow double-sided cooling of the control chip, which may be the main heat source of the entire package. In addition, this design can provide a preferred thermal path for manufacturing, to reduce the thermal resistance between the optical chip and the electrical chip or even minimize the thermal resistance between the optical chip and the electrical chip. Therefore, exemplary embodiments can provide the possibility of separating the thermal path from the electrical path, thereby ensuring appropriate operating temperature.

[0107] Of course, other manufacturing processes may also be used to embed the package body.

[0108] Figure 1 A cross-sectional view of a package 100 according to an exemplary embodiment of the present invention is shown.

[0109] Figure 1A package 100 is shown that includes a component carrier 102. The component carrier 102 can be an integrated circuit (IC) substrate. The component carrier 102 can include a laminated stack of layers, which includes an electrically conductive layer structure 104 and an electrically insulating layer structure 106. As shown in detail 150, the electrically conductive layer structure 104 can include a patterned metal layer (such as a patterned copper foil or a patterned deposited copper layer) and a vertical through-connection portion, which is, for example, a copper-filled via, which can be formed by drilling and electroplating. The electrically insulating layer structure 106 can include a corresponding resin (such as a corresponding epoxy resin), which preferably includes reinforcing particles (such as glass fibers or glass balls). For example, the electrically insulating layer structure 106 can be made of FR4. The electrically insulating layer structure 106 can also include a resin layer that does not contain glass (fiber).

[0110] also, Figure 1 An optical chip 108 is shown, which may be a photonic IC. The optical chip 108 may convert an optical signal into an electrical signal, and may process or pre-process the converted electrical signal. In addition, an electrical chip 110 is provided, which is functionally coupled to the optical chip 108. More specifically, the electrical chip 110 may drive or amplify the optical chip 108. Both the electrical chip 110 and the optical chip 108 may be manufactured using semiconductor technology, in particular InP technology or silicon technology, for example as a silicon wafer. As shown, the electrical chip 110 and the optical chip 108 are embedded side by side in the surface area of ​​the component carrier 102. Therefore, a signal path 112 between the optical chip 108 and the electrical chip 110 extends in a horizontal plane. As shown in FIG. Figure 1 As shown in FIG, both the optical chip 108 and the electrical chip 110 are embedded in the component carrier 102. For example, both the optical chip 108 and the electrical chip 110 may be inserted into a common cavity located in the upper main surface of the component carrier 102. Alternatively, the optical chip 108 may be inserted into a first cavity located in the upper main surface of the component carrier 102, while the electrical chip 110 may be inserted into a second cavity located in the upper main surface of the component carrier 102.

[0111] The optical chip 108 and the electrical chip 110 are embedded in the surface area of ​​the component carrier 102 at the same vertical upper height. Furthermore, the optical chip 108 and the electrical chip 110 are embedded in the surface area of ​​the component carrier 102 at the same vertical lower level. The optical chip 108 and the electrical chip 110 are laterally spaced apart from each other by a portion of the component carrier 102. As shown, the electrical redistribution structure 130 also extends partially below the control chip 124. Also as shown, the electrical redistribution structure 130 extends from the optical chip 108 above the electrical chip 110 to the control chip 124. This ensures that the electrical signals in the horizontal plane are directly fanned out.

[0112] Referring now to the supply and processing (e.g., modulation) of optical signals at the package 100, the package 100 includes an optical waveguide 116, which may be a material (e.g., a polymer fiber) with a tunable refractive index. The optical waveguide 116 may be configured to supply the optical signal to a semiconductor waveguide 118 disposed at the upper major surface of the optical chip 108. As shown, the optical waveguide 116 extends horizontally along a portion of the optical chip 108, a portion of the upper major surface of the component carrier 102, and a portion of the upper major surface of the inlay 120. The inlay 120 is preferably a glass inlay and is embedded in a surface region of the component carrier 102.

[0113] On the right side of the optical waveguide 116, a waveguide connector 122 is provided to optically couple with the optical waveguide 116. The waveguide connector 122 also extends horizontally and is arranged on the upper main surface of the inlay 120. The waveguide connector 122 can be connected with the optical peripheral of the package 100 to receive an optical signal. The optical signal is coupled into the optical waveguide 116 by the waveguide connector 122, and is coupled from the optical waveguide 116 into the semiconductor waveguide 118. Therefore, the optical waveguide 116 and the semiconductor waveguide 118 together form an optical redistribution structure 128, which extends horizontally to optically connect the waveguide connector 122 to the optical chip 108.

[0114] like Figure 1As shown in , the optical redistribution structure 128 and the electrical redistribution structure 130 share a common horizontal plane. The height (in the vertical direction) of the optical redistribution structure 128 may be different from the height of the electrical redistribution structure 130 (in this case, the optical redistribution structure 128 may be thicker than the electrical redistribution structure 130). Alternatively, the height of the optical redistribution structure 128 and the height of the electrical redistribution structure 130 may be the same. In the embodiment shown, the common horizontal plane corresponds to the height level of the electrical redistribution structure 130, and a portion of the optical redistribution structure 128 is also formed at this height level. Therefore, the optical signal and the electrical signal are processed within the common horizontal plane. This has a positive impact on signal integrity and can result in low optical signal loss and electrical signal loss.

[0115] The optical signal may be processed by the optical chip 108 when coupled to the semiconductor waveguide 118. The processing may include converting the optical signal into an electrical signal or converting the electrical signal into an optical signal through an optical-to-electrical converter of the optical chip 108, such as a photodiode. Although a receiver function is described herein (i.e., the optical signal is converted into an electrical signal by a photodiode), a laser diode (in a transmitter configuration) may also be used to convert the electrical signal into an optical signal. Thereafter, if necessary or required, the optical chip 108 may further process the electrical signal. The optical chip 108 may then forward the electrical signal to the electrical chip 110 and / or the control chip 124. Preferably, the electrical chip 110 is coupled to the optical chip 108 to drive or amplify the optical chip 108, and the control chip 124 may further process the electrical signal and / or may forward the electrical signal to another electronic entity (such as a CPU, not shown).

[0116] The control chip 124, which may be an ASIC, may be surface mounted on the component carrier 102. Figure 1 As shown in , the control chip 124 is arranged above the electrical chip 110, and the control chip 124 is laterally displaced relative to the electrical chip 110. The control chip 124 can be electrically coupled to the electrical redistribution structure 130 through a metal connection structure 154 (e.g., a solder ball) located on the bottom side of the control chip 124, and can be thermally coupled to the heat removal structure 132 described below. Since the control chip 124 may be the main heat source of the entire package 100, the heat sink 126 can be mounted on the exposed upper main surface of the control chip 124. The metal plate 156 of the heat sink 126 can be attached to the control chip 124, and the cooling fins 158 can dissipate the heat flowing from the control chip 124 to the metal plate 156 toward the environment.

[0117] Now refer to Figure 1The heat removal structures 132 are vertically extended, and each of the heat removal structures 132 is configured to remove heat from a corresponding one of the chips 108, 110, 124 of the package 100 toward the bottom side. The first heat removal structure 132 extends from the bottom of the optical chip 108 to the bottom main surface of the package 100. The second heat removal structure 132 extends from the bottom of the electrical chip 110 to the bottom main surface of the package 100. The third heat removal structure 132 extends from the bottom of the control chip 124 to the bottom main surface of the package 100. Each of the first removal structure 132 and the second heat removal structure 132 includes a metal paste structure 136 (e.g., copper paste) attached to the corresponding chip 108, 110, and includes a metal block 134 (e.g., copper block) attached to the corresponding metal paste structure 136. The third heat removal structure 132 includes a metal paste structure 136 (e.g., copper paste) located between two metal blocks 134 (e.g., copper blocks).

[0118] Due to the configuration, the electrical and optical signal flows 142 are horizontal, while the heat flow 144 is vertical. The signal feed path extends in a horizontal plane. Heat removal from the chips 108, 110 is performed downward, while heat removal from the main heat source, i.e., the control chip 124, is performed upward and downward in a double-sided cooling manner. This architecture ensures short signal paths and highly favorable thermal management at the same time.

[0119] Although not shown, electromagnetic shielding structures and / or one or more barrier layers may also be implemented in all embodiments of the package 100. Although not shown, various portions of the surface area may be provided with a surface finish such as solder resist, ENIPIG, or the like.

[0120] The advantage of the package 100 shown is that the signal path (in the horizontal plane) is separated from the thermal path (in the vertical direction). Very short electrical signal paths can be obtained without vertical interconnects. In addition, appropriate wafer operating temperatures can be obtained, for which double-sided cooling of the ASIC is a highly advantageous measure. More generally, customized heat removal can be achieved, especially between the electrical chip 110 and the optical chip 108. In addition, the separation of the alignment of the optical joint and the alignment of the electrical joint is also advantageous. Improved optical alignment tolerances can be achieved, especially by the evanescent field coupling between the optical waveguide 116 and the semiconductor waveguide 118 (which can avoid the need for active alignment with the package body). In addition, the optical joint can be optically inspected because the optical waveguide 116 is aligned on top of the semiconductor waveguide 118 of the optical chip 108.

[0121] therefore, Figure 1An IC substrate type package 100 is shown, which includes an IC substrate 102 having an embedded optical chip 108 and an electrical chip 110. In addition, a surface mounted ASIC type control chip 124 is provided. An electrical redistribution structure 130 interconnects the optical chip 108 with the electrical chip 110 in a direct fan-out architecture. A copper structure for heat dissipation is provided in the heat removal structure 132. The glass inlay 120 advantageously carries the light supply component and can provide a mechanical joint for the waveguide connector 122.

[0122] Figure 2A A cross-sectional view of a package 100 according to an exemplary embodiment of the present invention is shown. Figure 2B shows the method for embedding according to Figure 2A FIG. 1 is a cross-sectional view of a package body 114 in a component carrier 102 of a package 100 .

[0123] In particular, Figure 2A and Figure 2B The implementation method and Figure 1 The implementation method of Figure 2A and Figure 2B , the optical chip 108 and the electrical chip 110 are integrated in a package body 114. The package body 114 is integrally embedded in the component carrier 102. As shown, the optical chip 108 and the electrical chip 110 are encapsulated in an encapsulation material 140 of the package body 114. Figure 2B It is also shown that at least a portion of the electrical redistribution structure 130 (which may be implemented as a planar redistribution layer) is also integrated in the package body 114, more specifically, at least a portion of the electrical redistribution structure 130 is integrated at the upper main surface of the package body 114. In addition, at least a portion of the optical redistribution structure 128 may also be integrated in the package body 114, more specifically, at least a portion of the optical redistribution structure 128 may also be integrated at the same main surface of the package body 114. In the illustrated embodiment, the portion of the optical redistribution structure 128 integrated in the package body 114 includes a semiconductor waveguide 118. The semiconductor waveguide 118 may be formed in a manner integral with the optical chip 108, or the semiconductor waveguide 118 may be formed on the optical chip 108. The entire package body 114 may be embedded in a cavity or hole formed in the integrated circuit substrate 102, or the entire package body 114 may be embedded in a preform of the integrated circuit substrate 102. Therefore, embedding the package body 114 in the integrated circuit substrate 102 can provide the package 100 with electrical functions, optical functions, and electrical and optical redistribution functions.

[0124] Although the lower portion of the layered electrical redistribution structure 130 is formed as a part of the package body 114 (see Figure 2B ), but the upper portion of the layered electrical redistribution structure 130 is partially formed on the lower portion of the electrical redistribution structure 130 and partially formed on the component carrier 102, see Figure 2A .

[0125] like Figure 2A As shown in , the electrical redistribution structure 130 extends horizontally over the electrical chip 110 and the optical chip 108. Considering two portions of the electrical redistribution structure 130, one portion being formed as a portion of the package body 114 and the other portion being formed on the portion formed as a portion of the package body 114, the electrical redistribution structure 130 extends over more than one vertically stacked electrically conductive layer structure.

[0126] As shown, the optical waveguide 116 extends horizontally along a portion of the package body 114 , a portion of the upper major surface of the component carrier 102 , and a portion of the upper major surface of the inlay 120 .

[0127] The fan-out type package body 114 including both the electrical chip 110 and the optical chip 108 may ensure high performance and a small form factor.

[0128] Figure 3 A cross-sectional view of a package 100 according to another exemplary embodiment of the present invention is shown.

[0129] In particular, Figure 3 The implementation method and Figure 2A and Figure 2B The implementation method of Figure 3 The heat removal structure 132 located below the control chip 124 includes a metal block 134 located below an array of parallel metal pillars 138 (eg, copper pillars).

[0130] Figure 4 A cross-sectional view of a package 100 according to another exemplary embodiment of the present invention is shown.

[0131] In particular, Figure 4 The implementation method and Figure 2A and Figure 2B The implementation method of Figure 4 , the control chip 124 is arranged directly above the electrical chip 110. More specifically, according to Figure 4 ,and Figure 1In contrast, the package body 114 can be shifted toward the left side so that a portion of the encapsulation material 140 is also directly below the control chip 124. This design allows the manufacture of an even more compact package 100 in the horizontal direction. In addition, this design makes it possible to form the entire electrical redistribution structure 130 as part of the package body 114.

[0132] Figure 5 A cross-sectional view of a package 100 according to another exemplary embodiment of the present invention is shown.

[0133] In particular, Figure 5 The implementation method and Figure 2A and Figure 2B The implementation method of Figure 5 , there is no need to set the optical waveguide 116. On the contrary, according to Figure 5 , the waveguide connector 122 is directly connected to the semiconductor waveguide 118. More specifically, according to Figure 5 The package 100 includes a waveguide connector 122, which is directly optically coupled to a semiconductor waveguide 118, such as a silicon waveguide, at the upper main surface of the optical chip 108. As shown, the waveguide connector 122 extends partially along the package body 114, partially along the upper main surface of the component carrier 102, and partially along the upper main surface of the inlay 120 (which can be a glass inlay). However, the waveguide connector 122 can also be placed directly on the optical chip 108, and the optical chip 108 can provide the mechanical joint instead of the glass inlay 120. The inlay 120 is embedded in the surface area of ​​the component carrier 102. In short, a direct optical joint is established from the optical fiber or waveguide connector 122 to the optical chip 108.

[0134] Figure 6 A cross-sectional view of a package 100 according to another exemplary embodiment of the present invention is shown.

[0135] In particular, Figure 6 The implementation method and Figure 2A and Figure 2B The implementation method of Figure 6 , the control chip 124 is arranged directly above a portion of the electrical chip 110, and the control chip 124 is arranged directly above a portion of the optical chip 108. Therefore, according to Figure 6 , the entire control chip 124 is arranged directly above the package body 114, wherein the optical chip 108 and the electrical chip 110 are integrated in the package body 114. More specifically, according to Figure 6 ,and Figure 1In contrast, the package body 114 can be moved towards the left side so that a portion of the encapsulation material 140 is also directly below the control chip 124. This design allows the manufacture of an even more compact package 100 in a horizontal plane. In addition, this design makes it possible to form the entire electrical redistribution structure 130 as part of the package body 114.

[0136] according to Figure 6 , the horizontal extension or planar extension of the control chip 124 is smaller than the horizontal extension or planar extension of the packaging material 140 of the package body 114. In this context, the term "horizontal extension or planar extension" may refer to the corresponding extension in the horizontal plane, i.e., according to Figure 6 , the corresponding extension in a plane perpendicular to the vertical direction. Another difference is that in Figure 2A and Figure 2B In the embodiment, the metal connection structure 154 has different vertical extensions. For example, a larger extension is used for better heat dissipation, while a smaller extension is used for more reliable signal transmission from the control chip 124 to the electrical redistribution structure 130 .

[0137] Figure 7 A cross-sectional view of a package 100 according to another exemplary embodiment of the present invention is shown.

[0138] In particular, Figure 7 The implementation method and Figure 6 The implementation method of Figure 7 , the package body 114 is a panel-level package body. Therefore, according to Figure 7 , the optical chip 108 and the electrical chip 110 are encapsulated in an organic laminate (e.g., a PCB laminate or an IC substrate laminate) embedded in the component carrier 102. The optical chip 108, the electrical chip 110, and the electrical redistribution structure 130 (or a portion of the electrical redistribution structure 130) can be integrated in a panel-level package body. The panel-level package body uses an organic laminate type encapsulation part.

[0139] In addition, according to Figure 7 , the outer contour of the control chip 124 is partially flush with the outer contour of the panel-level package body (ie, according to Figure 7 on the left side of the ).

[0140] Figures 8 to 13 Cross-sectional views of various portions of a package 100 having different light coupling structures according to an exemplary embodiment of the present invention are shown.

[0141] according to Figures 8 to 10, shows an optical coupling architecture with an optical junction. An optical waveguide 116 (which may in particular be based on polymer or glass) or a waveguide connector 122 may be provided.

[0142] Reference Figure 8 , the optical waveguide 116 is optically connected to the semiconductor waveguide 118 via a connection region located in a horizontal plane.

[0143] Reference Fig. 9 , the waveguide connector 122 is optically connected to the semiconductor waveguide 118 via a connection area located in a horizontal plane.

[0144] Reference Fig.10 The waveguide connector 122 is optically connected to the semiconductor waveguide 118 via a connection region located in a vertical plane. In addition, the optical fiber 199 is optically connected to the waveguide connector 122.

[0145] according to Figures 11 to 13 , shows an optical coupling architecture with two optical junctions. An optical waveguide 116 (which may in particular be based on polymer or glass) and a waveguide connector 122 may be provided.

[0146] Reference Fig.11 The waveguide connector 122 is optically connected to the optical waveguide 116 via a connection region located in a horizontal plane, and the optical waveguide 116 is optically connected to the semiconductor waveguide 118 via a connection region located in a horizontal plane. In addition, the optical fiber 199 is optically connected to the waveguide connector 122.

[0147] Reference Fig.12 The waveguide connector 122 is optically connected to the optical waveguide 116 via a connection region located in a vertical plane. The optical waveguide 116 is optically connected to the semiconductor waveguide 118 via a connection region located in a horizontal plane. In addition, the optical fiber 199 is optically connected to the waveguide connector 122.

[0148] Reference Fig.13 The waveguide connector 122 is optically connected to the optical waveguide 116 via a connection region located in a vertical plane, and the optical waveguide 116 is optically connected to the semiconductor waveguide 118 via a connection region located in a vertical plane. In addition, the optical fiber 199 is optically connected to the waveguide connector 122.

[0149] Fig.14 A cross-sectional view of a portion of a package 100 according to another exemplary embodiment of the present invention is shown, wherein the electrical chip 110 and the corresponding electrical redistribution structure 130 have different coupling architectures.

[0150] according to Fig.14, one or more pads 193 on the main surface of the electrical chip 110 (wherein corresponding couplings may also be established with the optical chip 108 and / or the control chip 124) are provided with protruding bumps 197 or are formed in an integral manner with the protruding bumps 197. The protruding bumps 197 may be metal piles or metal columns. The protruding bumps 197 may be embedded in a dielectric material, for example, in a dielectric laminate, which may form part of the component carrier 102. By exposing the protruding bumps 197, the protruding bumps 197 can be directly connected to the electrical redistribution structure 130 without difficulty.

[0151] Fig.15 A cross-sectional view of a package 100 according to another exemplary embodiment of the present invention is shown.

[0152] according to Fig.15 The optical redistribution structure 128 includes a semiconductor waveguide 118 and an optical waveguide 116, which are attached laterally to the optical chip 108. This lateral optical coupling can be achieved over the entire height of the optical chip 108 or only over a portion of the height. Fig.15 Also shown are two optical junctions.

[0153] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plural form. Furthermore, elements described in association with different embodiments may be combined.

[0154] It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.

[0155] The implementation of the invention is not limited to the preferred embodiments shown in the drawings and described above. On the contrary, multiple variations using the solutions shown and according to the principle of the invention are possible, even in the case of fundamentally different embodiments.

Claims

1. A package (100), wherein: The package (100) comprises: A component carrier (102), the component carrier (102) comprising at least one electrically conductive layer structure (104) and / or at least one electrically insulating layer structure (106); and An optical chip (108) and an electrical chip (110) are functionally coupled to each other and are embedded side by side in the component carrier (102) so that a signal path (112) between the optical chip (108) and the electrical chip (110) is located in a horizontal plane.

2. The package (100) according to claim 1, comprising at least one of the following features: in, The optical chip (108) and the electrical chip (110) are integrated in a package body (114), and the package body (114) is embedded in the component carrier (102). wherein, in particular, the package body (114) is a panel-level package body, and the optical chip (108) and the electrical chip (110) are encapsulated in a laminate embedded in the component carrier (102); The optical chip (108) and the electrical chip (110) are embedded at the same vertical upper height and / or at the same vertical lower height, in particular, the optical chip (108) and the electrical chip (110) are embedded at the same vertical upper height and / or at the same vertical lower height in the surface area of ​​the component carrier (102); The upper main surface of the optical chip (108) and the upper main surface of the electrical chip (110) are recessed relative to the upper main surface of the component carrier (102).

3. The package (100) according to any one of claims 1 to 2, wherein the package (100) comprises an optical waveguide (116), in particular, the optical waveguide (116) is a polymer fiber, and the optical waveguide (116) is configured to supply an optical signal to a semiconductor waveguide (118) located at an upper main surface or a side surface of the optical chip (108), in particular, the semiconductor waveguide (118) is a silicon waveguide, an indium phosphide waveguide or a waveguide comprising a photopolymerizable material.

4. The package (100) according to claim 3, comprising at least one of the following features: in, The optical waveguide (116) is physically connected to the semiconductor waveguide (118); wherein at least a portion of the optical waveguide (116) extends along an upper main surface of the component carrier (102) and / or along an upper main surface of an inlay (120) embedded in a surface region of the component carrier (102), in particular, the inlay (120) is a glass inlay; The package (100) comprises a waveguide connector (122) which is optically coupled to the optical waveguide (116) and, in particular, the waveguide connector (122) extends along an upper main surface of the component carrier (102) and / or along an upper main surface of an inlay (120) embedded in a surface area of ​​the component carrier (102), in particular, the inlay (120) being a glass inlay.

5. The package (100) according to any one of claims 1 to 2, comprising a waveguide connector (122), the waveguide connector (122) being directly optically coupled to a semiconductor waveguide (118) located at an upper main surface of the optical chip (108), in particular, the semiconductor waveguide (118) being a silicon waveguide or a waveguide comprising a photopolymerizable material, wherein: In particular, the waveguide connector (122) extends at least partially along an upper main surface of the component carrier (102) and / or along an upper main surface of an inlay (120) embedded in a surface area of ​​the component carrier (102), in particular, the inlay (120) is a glass inlay.

6. The package (100) according to any one of claims 1 to 5, comprising at least one of the following features: in, The optical chip (108) is configured to convert the supplied optical signal into an electrical signal and / or to convert the supplied electrical signal into an optical signal, and optionally, the optical chip (108) is configured to pre-process the electrical signal and / or the optical signal; The electrical chip (110) is configured to drive the optical chip (108), and / or the electrical chip (110) is configured to amplify the signal received from the optical chip (108). In particular, the electrical chip (110) is configured to amplify the signal received from the optical chip (108) after converting the signal received from the optical chip (108) into an electrical signal.

7. The package (100) according to any one of claims 1 to 6, comprising one of the following features: The package (100) further comprises a control chip (124), wherein the control chip (124) receives the electrical signal from the electrical chip (110), and the control chip (124) is configured to further process the electrical signal, and in particular, the control chip (124) is configured to forward the electrical signal to an electronic peripheral; The package (100) further includes a control chip (124) configured as an additional optical chip.

8. The package (100) according to claim 7, comprising at least one of the following features: in, The control chip (124) is surface mounted on the component carrier (102); The package (100) includes a heat sink (126), and the heat sink (126) is mounted on an exposed surface of the control chip (124); The control chip (124) is arranged directly above the electrical chip (110); The control chip (124) is arranged above the electrical chip (110) and is laterally displaced relative to the electrical chip (110); The control chip (124) is arranged directly above the package body (114), and the optical chip (108) and the electrical chip (110) are integrated in the package body (114); The control chip (124) is arranged directly above the packaging material (140) of the packaging body (114), and the optical chip (108) and the electrical chip (110) are integrated in the packaging body (114).

9. The package (100) according to any one of claims 1 to 8, wherein the package (100) comprises an optical redistribution structure (128), wherein the optical redistribution structure (128) extends to be connected to the optical chip (108), in particular, the optical redistribution structure (128) extends horizontally to be connected to the optical chip (108), and more particularly, the optical redistribution structure (128) extends to be connected to the optical chip (108) at a horizontal height corresponding to the upper main surface of the component carrier (102).

10. The package (100) according to any one of claims 1 to 9, comprising an electrical redistribution structure (130), wherein the electrical redistribution structure (130) extends horizontally above the electrical chip (110) and / or the optical chip (108).

11. The package (100) according to claim 10, comprising at least one of the following features: in, At least a portion of the electrical redistribution structure (130) extends over at least two vertically stacked electrical conductive layer structures; Wherein, at least a portion of the electrical redistribution structure (130) extends below the control chip (124); Wherein, at least a portion of the electrical redistribution structure (130) is disposed in a package body (114), and in particular, at least a portion of the electrical redistribution structure (130) is disposed in a panel-level package body; wherein another electrical redistribution structure is arranged above the electrical redistribution structure (130), and the other electrical redistribution structure electrically connects the electrical chip (110) and / or the optical chip (108) to the component carrier (102); Wherein, the optical redistribution structure (128) and the electrical redistribution structure (130) share the same horizontal plane.

12. The package (100) according to any one of claims 1 to 11, comprising a heat removal structure (132) configured to remove heat from the package (100) and extending vertically through the component carrier (102).

13. The package (100) according to claim 12, comprising at least one of the following features: in, At least a portion of the heat removal structure (132) extends between: a bottom of the optical chip (108) and / or a bottom of the electrical chip (110) and / or a bottom of the control chip (124); and a lower major surface of the component carrier (102); The heat removal structure (132) includes at least one metal block (134) and / or at least one metal paste structure (136) and / or at least one metal column (138).

14. The package (100) according to any one of claims 1 to 13, comprising at least one of the following features: The package (100) is configured such that the signal flow (142) is horizontal and the heat flow (144) is vertical; in, The signal path (112) extends in a horizontal plane corresponding to an upper main surface of the component carrier (102) or an upper main surface of the package (100); wherein the optical signal path portion and the electrical signal path portion of the signal path (112) share the same horizontal plane; Wherein, the electrical signal path portion of the signal path (112) for transmitting electrical signals between the optical chip (108) and the electrical chip (110) has no vertical through-connection portion; Wherein, the component carrier (102) is an integrated circuit substrate.

15. A method of manufacturing a package (100), wherein: The method comprises: Providing a component carrier (102), the component carrier (102) comprising at least one electrically conductive layer structure (104) and / or at least one electrically insulating layer structure (106); functionally coupling the optical chip (108) to the electrical chip (110); and The optical chip (108) and the electrical chip (110) are embedded side by side in the component carrier (102) so that a signal path (112) between the optical chip (108) and the electrical chip (110) is located in a horizontal plane.

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