Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system, and the method comprises the steps: forming a plurality of capacitor holes which penetrate through a first stacking layer in a stacking direction, the first stacking layer comprises a first region and a second region, and the capacitor holes are located in the first region and the second region; forming a first electrode layer on the inner wall of the capacitor hole; forming a dielectric layer in the first region and the second region; forming a second electrode layer on one side, deviating from the first stacking layer, of the dielectric layer; removing the second electrode layer on the first stack layer in the second region; and forming a contact structure penetrating through the first stacking layer in the second region along the stacking direction. According to the method, a serious etching load effect can be greatly prevented from occurring in the first region when the capacitor hole is formed, a capacitor structure with a uniform size can be formed in the first region, and the reliability of the capacitor structure is improved.

Description

Semiconductor structure and manufacturing method thereof, memory and memory system

Technical field

[0001] [Corrected 21.07.2023 according to Rule 91] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same, a memory and a memory system. [Background Technology]

[0002] [Corrected on 21.07.2023 according to Rule 91] Dynamic Random Access Memory (DRAM) is a semiconductor memory device. DRAM is composed of a number of repeated memory cells, each of which includes a capacitor structure configured to store charge. The capacitor structure affects the storage capacity of the DRAM.

[0003] [Corrected 21.07.2023 according to Rule 91] The capacitor structure in existing DRAM is usually located in the core area. However, when making the capacitor holes in the core area, severe etching loading effect is prone to occur, which affects the reliability of the final capacitor structure.

[0004] [Corrected 21.07.2023 in accordance with Rule 91] [Summary of the invention]

[0005] [Corrected 21.07.2023 according to Rule 91] The present application aims to provide a semiconductor structure and its manufacturing method, a memory and a memory system, which can effectively improve the etching load effect of the core area when manufacturing capacitor holes and improve the reliability of the capacitor structure.

[0006] [Corrected 21.07.2023 according to Rule 91] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0007] [Corrected 21.07.2023 according to Rule 91] forming a plurality of capacitor holes penetrating a first stacked layer along a stacking direction, the first stacked layer comprising a first region and a second region, the capacitor holes being located in the first region and the second region;

[0008] [Corrected 21.07.2023 in accordance with Rule 91] forming a first electrode layer on an inner wall of the capacitor hole;

[0009] [Corrected 21.07.2023 in accordance with Rule 91] forming a dielectric layer in the first region and the second region;

[0010] [Corrected 21.07.2023 in accordance with Rule 91] forming a second electrode layer on a side of the dielectric layer facing away from the first stack of layers;

[0011] [Corrected 21.07.2023 in accordance with Rule 91] removing the second electrode layer on the first stack in the second region;

[0012] [Corrected 21.07.2023 according to Rule 91] A contact structure is formed that penetrates the first stack layer in the second region along the stacking direction.

[0013] [Corrected 21.07.2023 according to Rule 91] On the other hand, an embodiment of the present application further provides another method for manufacturing a semiconductor structure, comprising:

[0014] [Corrected 21.07.2023 according to Rule 91] forming a plurality of capacitor holes penetrating a first stacked layer along a stacking direction, the first stacked layer comprising a first region and a second region, the capacitor holes being located in the first region and the second region;

[0015] [Corrected 21.07.2023 in accordance with Rule 91] forming a first electrode layer on an inner wall of the capacitor hole in the first region;

[0016] [Corrected 21.07.2023 in accordance with Rule 91] removing part of the first stacked layer in the first region and the second region;

[0017] [Corrected 21.07.2023 in accordance with Rule 91] forming a dielectric layer and a second electrode layer in the first region, the second electrode layer being located on a side of the dielectric layer facing away from the first electrode layer;

[0018] [Corrected 21.07.2023 in accordance with Rule 91] forming a flat layer in the second region;

[0019] [Corrected 21.07.2023 according to Rule 91] A contact structure is formed that penetrates the planar layer along the stacking direction.

[0020] [Corrected 21.07.2023 according to Rule 91] On the other hand, an embodiment of the present application further provides another method for manufacturing a semiconductor structure, comprising:

[0021] [Corrected 21.07.2023 according to Rule 91] forming a plurality of capacitor holes penetrating a first stacked layer along a stacking direction, the first stacked layer comprising a first region and a second region, the capacitor holes being located in the first region and the second region;

[0022] [Corrected 21.07.2023 in accordance with Rule 91] forming a first electrode layer on inner walls of the capacitor holes in the first region and the second region;

[0023] [Corrected 21.07.2023 according to Rule 91] A dielectric layer is formed on one side of the first stacked layer in the first region and the second region, and the dielectric layer covers a side of the first electrode layer facing away from the inner wall of the capacitor hole;

[0024] [Corrected 21.07.2023 according to Rule 91] forming a second electrode layer on a side of the dielectric layer in the first region facing away from the first electrode layer;

[0025] [Corrected 21.07.2023 in accordance with Rule 91] removing the first stacked layer, the dielectric layer and the first electrode layer in the second region;

[0026] [Corrected 21.07.2023 in accordance with Rule 91] forming a flat layer in the second region;

[0027] [Corrected 21.07.2023 according to Rule 91] A contact structure is formed that penetrates the planar layer along the stacking direction.

[0028] [Corrected 21.07.2023 according to Rule 91] In another aspect, an embodiment of the present application further provides a semiconductor structure, comprising:

[0029] [Corrected 21.07.2023 in accordance with Rule 91] a first stacking structure comprising a first region and a second region;

[0030] [Corrected 21.07.2023 according to Rule 91] a first electrode layer located in the first region and the second region, the first electrode layer penetrating the first stacked structure along the stacking direction, and the first electrode layer in the first region and the first electrode layer in the second region being spaced apart;

[0031] [Corrected 21.07.2023 in accordance with Rule 91] a dielectric layer located in the first region and the second region;

[0032] [Corrected 21.07.2023 according to Rule 91] a second electrode layer located in the first region and the second region, with the dielectric layer provided between the first electrode layer and the second electrode layer, and the second electrode layer in the first region and the second electrode layer in the second region being spaced apart;

[0033] [Corrected 21.07.2023 according to Rule 91] A contact structure, which extends through the first stacking structure in the second region along the stacking direction.

[0034] [Corrected on 21.07.2023 according to Rule 91] On the other hand, an embodiment of the present application further provides a memory comprising the semiconductor structure and the peripheral circuit structure described in any one of the above items, wherein the peripheral circuit structure and the semiconductor structure are electrically connected.

[0035] [Corrected on 21.07.2023 according to Rule 91] On the other hand, an embodiment of the present application also provides a memory system, comprising at least one of the above-mentioned memories, and a controller coupled to the memory, wherein the controller is used to control the memory to store data.

[0036] [Corrected on 21.07.2023 according to Rule 91] The semiconductor structure and its manufacturing method, memory and memory system provided by the embodiments of the present application form a plurality of capacitor holes penetrating the first stacking layer along the stacking direction, the first stacking layer includes a first region and a second region, and the capacitor holes are located in the first region and the second region, thereby greatly avoiding a serious etching load effect in the first region when forming the capacitor holes, ensuring the size consistency of the capacitor holes in the first region as much as possible, and preventing insufficient etching. Subsequently, a first electrode layer is formed on the inner wall of the capacitor hole; a dielectric layer is formed in the first region and the second region; a second electrode layer is formed on the side of the dielectric layer away from the first stacking layer; the second electrode layer on the first stacking layer in the second region is removed; and a contact structure of the first stacking layer penetrating the second region along the stacking direction is formed, thereby forming a capacitor structure with uniform size in the first region, thereby improving the reliability of the capacitor structure.

Brief Description of the Drawings

[0037] [Corrected on 21.07.2023 according to Rule 91] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0038] [Corrected 21.07.2023 according to Rule 91] FIG1 is a schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0039] [Corrected 21.07.2023 according to Rule 91] FIG. 2A to FIG. 2F are schematic cross-sectional views of a semiconductor structure at different process steps provided in an embodiment of the present application;

[0040] [Corrected 21.07.2023 in accordance with Rule 91] Figure 3A is a schematic cross-sectional view of the structure along line C1-C1 in Figure 2A;

[0041] [Corrected 21.07.2023 in accordance with Rule 91] Figure 3B is a schematic cross-sectional view of the structure along line C2-C2 in Figure 2B;

[0042] [Corrected 21.07.2023 in accordance with Rule 91] Figure 3C is a schematic cross-sectional view of the structure along line C3-C3 in Figure 2C;

[0043] [Corrected 21.07.2023 in accordance with Rule 91] Figure 3D is a schematic cross-sectional view of the structure along line C4-C4 in Figure 2D;

[0044] [Corrected 21.07.2023 in accordance with Rule 91] FIG3E is a schematic cross-sectional view of the structure along line C5-C5 in FIG2F ;

[0045] [Corrected 21.07.2023 according to Rule 91] FIG4A is a schematic cross-sectional view of another semiconductor structure provided in an embodiment of the present application;

[0046] [Corrected 21.07.2023 according to Rule 91] Figure 4B is a schematic cross-sectional view of the structure along line dd in Figure 4A;

[0047] [Corrected 21.07.2023 according to Rule 91] FIG. 5A to FIG. 5F are schematic cross-sectional views of another embodiment of the semiconductor structure according to different process steps;

[0048] [Corrected 21.07.2023 according to Rule 91] Figure 6A is a schematic cross-sectional view of the structure along line D1-D1 in Figure 5A;

[0049] [Corrected 21.07.2023 according to Rule 91] Figure 6B is a schematic cross-sectional view of the structure along line D2-D2 in Figure 5B;

[0050] [Corrected 21.07.2023 in accordance with Rule 91] FIG6C is a schematic cross-sectional view of the structure along line D3-D3 in FIG5C;

[0051] [Corrected 21.07.2023 according to Rule 91] Figure 6D is a schematic cross-sectional view of the structure along line D4-D4 in Figure 5D;

[0052] [Corrected 21.07.2023 according to Rule 91] FIG6E is a schematic cross-sectional view of the structure along line D5-D5 in FIG5F;

[0053] [Corrected 21.07.2023 according to Rule 91] FIG. 7A to FIG. 7E are schematic cross-sectional views of a semiconductor structure according to an embodiment of the present application at different process steps;

[0054] [Corrected 21.07.2023 according to Rule 91] FIG7F is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0055] [Corrected 21.07.2023 according to Rule 91] Figure 8A is a schematic cross-sectional view of the structure along line E1-E1 in Figure 7A;

[0056] [Corrected 21.07.2023 according to Rule 91] Figure 8B is a schematic cross-sectional view of the structure along line E2-E2 in Figure 7B;

[0057] [Corrected 21.07.2023 according to Rule 91] Figure 8C is a schematic cross-sectional view of the structure along line E3-E3 in Figure 7C;

[0058] [Corrected 21.07.2023 according to Rule 91] Figure 8D is a schematic cross-sectional view of the structure along line E4-E4 in Figure 7E;

[0059] [Corrected 21.07.2023 according to Rule 91] FIG. 9A to FIG. 9J are schematic cross-sectional views of another semiconductor structure at different process steps provided by an embodiment of the present application;

[0060] [Corrected 21.07.2023 according to Rule 91] FIG10A is a schematic cross-sectional view of the structure along line F1-F1 in FIG9A;

[0061] [Corrected 21.07.2023 according to Rule 91] Figure 10B is a schematic cross-sectional view of the structure along line F2-F2 in Figure 9B;

[0062] [Corrected 21.07.2023 according to Rule 91] Figure 10C is a schematic cross-sectional view of the structure along line F3-F3 in Figure 9C;

[0063] [Corrected 21.07.2023 according to Rule 91] Figure 10D is a schematic cross-sectional view of the structure along line F4-F4 in Figure 9D;

[0064] [Corrected 21.07.2023 according to Rule 91] Figure 10E is a schematic cross-sectional view of the structure along line F5-F5 in Figure 9E;

[0065] [Corrected 21.07.2023 according to Rule 91] Figure 10F is a schematic cross-sectional view of the structure along line F6-F6 in Figure 9F;

[0066] [Corrected 21.07.2023 according to Rule 91] Figure 10G is a schematic cross-sectional view of the structure along line F7-F7 in Figure 9G;

[0067] [Corrected 21.07.2023 according to Rule 91] Figure 10H is a schematic cross-sectional view of the structure along line F8-F8 in Figure 9H;

[0068] [Corrected 21.07.2023 according to Rule 91] Figure 10I is a schematic cross-sectional view of the structure along line F9-F9 in Figure 9I;

[0069] [Corrected 21.07.2023 according to Rule 91] Figure 10J is a schematic cross-sectional view of the structure along line F10-F10 in Figure 9J;

[0070] [Corrected 21.07.2023 according to Rule 91] FIG. 11A to FIG. 11E are schematic cross-sectional views of another semiconductor structure at different process steps provided by an embodiment of the present application;

[0071] [Corrected 21.07.2023 according to Rule 91] FIG11F is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0072] [Corrected 21.07.2023 according to Rule 91] Figure 12A is a schematic cross-sectional view of the structure along line G1-G1 in Figure 11A;

[0073] [Corrected 21.07.2023 according to Rule 91] Figure 12B is a schematic cross-sectional view of the structure along line G2-G2 in Figure 11B;

[0074] [Corrected 21.07.2023 according to Rule 91] Figure 12C is a schematic cross-sectional view of the structure along line G3-G3 in Figure 11C;

[0075] [Corrected 21.07.2023 according to Rule 91] Figure 12D is a schematic cross-sectional view of the structure along line G4-G4 in Figure 11D;

[0076] [Corrected 21.07.2023 according to Rule 91] Figure 12E is a schematic cross-sectional view of the structure along line G5-G5 in Figure 11E;

[0077] [Corrected 21.07.2023 according to Rule 91] FIG13 is a schematic flow chart of a method for manufacturing another semiconductor structure provided in an embodiment of the present application;

[0078] [Corrected 21.07.2023 according to Rule 91] FIG. 14A to FIG. 14H are schematic cross-sectional views of another semiconductor structure at different process steps provided in an embodiment of the present application;

[0079] [Corrected 21.07.2023 according to Rule 91] FIG14I is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0080] [Corrected 21.07.2023 according to Rule 91] Figure 15A is a schematic cross-sectional view of the structure along line H1-H1 in Figure 14A;

[0081] [Corrected 21.07.2023 according to Rule 91] Figure 15B is a schematic cross-sectional view of the structure along line H2-H2 in Figure 14B;

[0082] [Corrected 21.07.2023 according to Rule 91] FIG15C is a schematic cross-sectional view of the structure along line H3-H3 in FIG14C;

[0083] [Corrected 21.07.2023 according to Rule 91] Figure 15D is a schematic cross-sectional view of the structure along line H4-H4 in Figure 14D;

[0084] [Corrected 21.07.2023 according to Rule 91] Figure 15E is a schematic cross-sectional view of the structure along line H5-H5 in Figure 14E;

[0085] [Corrected 21.07.2023 according to Rule 91] Figure 15F is a schematic cross-sectional view of the structure along line H6-H6 in Figure 14F;

[0086] [Corrected 21.07.2023 according to Rule 91] Figure 15G is a schematic cross-sectional view of the structure along line H7-H7 in Figure 14G;

[0087] [Corrected 21.07.2023 according to Rule 91] Figure 15H is a schematic cross-sectional view of the structure along line H8-H8 in Figure 14H;

[0088] [Corrected 21.07.2023 according to Rule 91] Figure 16 is a structural diagram of the system provided in an embodiment of the present application. [Specific implementation method]

[0089] [Corrected 21.07.2023 according to Rule 91] The present application is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application and do not limit the scope of the present application. Similarly, the following examples are only some examples of the present application and not all examples. All other examples obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0090] [Corrected on 21.07.2023 according to Rule 91] In the description herein, it should be understood that the terms “center”, “lateral”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms “first” and “second” are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the said features.

[0091] [Corrected 21.07.2023 in accordance with Rule 91] It should be noted that, in the description herein, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0092] [Corrected 21.07.2023 as per Rule 91] It is to be understood that the meanings of “on”, “over” and “over” in the description herein are to be interpreted in the broadest manner so that “on” not only means “on” something with no intervening features or layers (i.e. directly on something), but also includes “on” something with intervening features or layers.

[0093] [Corrected 21.07.2023 in accordance with Rule 91] The terms used herein are intended only to describe specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item", and "a" used herein are intended to include the plural form. "Multiple" means two or more. It should also be understood that the terms "include" and / or "comprising" used herein specify the presence of stated features, integers, steps, operations, units, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0094] [Corrected 21.07.2023 according to Rule 91] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, a memory, and a memory system.

[0095] [Corrected 21.07.2023 according to Rule 91] Please refer to FIG1 , which is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. The method for manufacturing a semiconductor structure may include the following steps S101-S106, wherein:

[0096] [Corrected 21.07.2023 according to Rule 91] Step S101. Forming a plurality of capacitor holes penetrating a first stacked layer along a stacking direction, the first stacked layer comprising a first region and a second region, the capacitor holes being located in the first region and the second region;

[0097] [Corrected 21.07.2023 according to Rule 91] Step S102. Forming a first electrode layer on the inner wall of the capacitor hole;

[0098] [Corrected 21.07.2023 according to Rule 91] Step S103. Forming a dielectric layer in the first region and the second region;

[0099] [Corrected 21.07.2023 according to Rule 91] Step S104. Forming a second electrode layer on a side of the dielectric layer facing away from the first stacked layer;

[0100] [Corrected 21.07.2023 according to Rule 91] Step S105. Removing the second electrode layer on the first stacked layer in the second region;

[0101] [Corrected 21.07.2023 according to Rule 91] Step S106. Form a contact structure that penetrates the first stack layer in the second region along the stacking direction.

[0102] [Corrected 21.07.2023 in accordance with Rule 91] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0103] [Corrected 21.07.2023 according to Rule 91] Please refer to Figures 2A to 2F, 5A to 5F, and 7A to 7E. Figures 2A to 2F are schematic cross-sectional views of the semiconductor structure 10 provided in different process steps according to an embodiment of the present application. Figures 5A to 5F are another schematic cross-sectional view of the semiconductor structure 10 provided in different process steps according to an embodiment of the present application. Figures 7A to 7E are another schematic cross-sectional view of the semiconductor structure 10 provided in different process steps according to an embodiment of the present application. The semiconductor structure 10 may include a cup-type capacitor structure, a pillar-type capacitor structure, or a cylindrical capacitor structure. The above steps S101-S106 will be further described below in conjunction with Figures 2A to 2F, 5A to 5F, and 7A to 7E, wherein:

[0104] [Corrected 21.07.2023 according to Rule 91] Step S101. A plurality of capacitor holes Q1 are formed through the first stacking layer 11 along the stacking direction z, wherein the first stacking layer 11 includes a first area AA and a second area BB, and the capacitor holes Q1 are located in the first area AA and the second area BB.

[0105] [Corrected 21.07.2023 according to Rule 91] Wherein, if the semiconductor structure 10 is a cup-type capacitor structure, a pillar-type capacitor structure or a cylindrical capacitor structure, please refer to Figures 2A and 3A above. Figure 3A is a schematic diagram of the cross-sectional structure along the C1-C1 line in Figure 2A. The first area AA is the area corresponding to the storage array, and the second area BB is other areas. The first area AA and the second area BB can be adjacent to each other, for example, the second area BB is arranged around the first area AA. The capacitor holes Q1 can be distributed in the entire area of ​​the first stacked layer 11 and are arranged at intervals inside. Preferably, these capacitor holes Q1 can be set to the same size and the same spacing.

[0106] [Corrected 21.07.2023 according to Rule 91] Specifically, the first stacked layer 11 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first stacked layer 11 can be formed by alternating layers of different insulating materials, such as alternating layers of silicon dioxide and silicon nitride.

[0107] [Corrected 21.07.2023 in accordance with Rule 91] Capacitor holes Q1 can be formed in both the first region AA and the second region BB of the first stacked layer 11 through two orthogonal or angled patterning processes. In this case, since the pattern of the capacitor holes Q1 is relatively uniformly distributed across the entire surface of the first stacked layer 11, that is, the density difference between the etching patterns corresponding to the first region AA and the second region BB is relatively small, the difference in etching depth and size of the capacitor holes Q1 formed in the first region AA and the second region BB is relatively small, thereby minimizing the occurrence of a severe etching loading effect. Furthermore, even if a certain etching loading effect exists, affecting the etching depth and hole size of the capacitor holes Q1 at the edge, since the second region BB is generally disposed around the first region AA, the etching loading effect generally only affects the outermost capacitor holes Q1 in the second region BB and is unlikely to affect the capacitor holes Q1 in the first region AA. Therefore, by forming the capacitor holes Q1 in both the first area AA and the second area BB, the serious etching load effect in the first area AA can be greatly avoided, and the etching depth and size of the capacitor holes Q1 in the first area AA can be kept consistent as much as possible, avoiding the phenomenon that some capacitor holes Q1 have insufficient etching depth or are too small in size.

[0108] [Corrected 21.07.2023 according to Rule 91] In other embodiments, please refer to Figures 4A and 4B, Figure 4A shows a schematic cross-sectional structure diagram of another semiconductor structure 20 provided in an embodiment of the present application, and Figure 4B is a schematic cross-sectional structure diagram along line dd in Figure 4A. Among them, the semiconductor structure 20 includes a first stacking structure 21, and a second stacking layer 22 located on the first stacking structure 21, the first stacking structure 21 includes a channel structure 211, the second stacking layer 22 includes a core area aa and a non-core area bb, and a capacitor hole q is formed in the core area aa. Specifically, the capacitor hole q can be directly formed in the core area aa, and then the first electrode layer, the dielectric layer and the second electrode layer are made to obtain a capacitor structure located in the core area aa. However, since capacitor hole q does not need to be made in non-core area bb when making capacitor hole q, that is, the density difference of the etching patterns of core area aa and non-core area bb is large, the capacitor hole q at the junction of core area aa and non-core area bb will have a serious etching load effect, so that the capacitor hole q at the edge of core area aa and the capacitor hole q in the middle of core area aa have obvious differences in etching depth and hole size. For example, the etching depth of capacitor hole q at the edge of core area aa is shallow and cannot penetrate the second stacking layer 22 along the stacking direction z, thereby causing the capacitor structure finally formed at the edge of core area aa to be unable to be electrically connected to the channel structure 211, or the size of capacitor hole q is too small, which affects the formation of subsequent capacitor structure and affects the reliability of the capacitor structure. The semiconductor structure 10 provided in the embodiment of the present application at least partially solves the above technical problems.

[0109] [Corrected as of July 21, 2023, in accordance with Rule 91] It should be noted that, in the semiconductor structure 10 provided in the embodiment of the present application, the capacitor structure may be formed after the channel structure is formed. That is, referring to FIG. 2A and FIG. 3A , before the above-mentioned step S101, the manufacturing method may further include:

[0110] [Corrected 21.07.2023 according to Rule 91] forming a second stacked structure 12, the second stacked structure 12 comprising a plurality of channel structures 121 spaced apart along a first direction x and a second direction y, and a gate structure 122 extending along the second direction y and connecting the plurality of channel structures 121, the gate structure 122 being located between two adjacent channel structures 121, the first direction x, the second direction y, and the stacking direction z being perpendicular to each other;

[0111] [Corrected 21.07.2023 according to Rule 91] The first stack layer 11 is formed on the second stack structure 12.

[0112] [Corrected 21.07.2023 according to Rule 91] The position of the channel structure 121 corresponds to at least the position of the capacitor hole Q1 in the first area AA. The first direction x and the second direction y may be extension directions of the first stacked layer 11, which are perpendicular to the stacking direction z of the first stacked layer 11. The gate structure 122 may include a gate spacer layer 1221 and a gate layer 1222. The material of the gate spacer layer 1221 may include an insulating material such as an oxide, and the material of the gate layer 1222 may be any one or a combination of tungsten, cobalt, copper, aluminum, polysilicon, and doped crystalline silicon.

[0113] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the channel structure 121 is formed on a substrate, which may include at least one of single crystal silicon (Si), single crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. Specifically, the substrate can be etched to form a plurality of active portions extending along a first direction x and spaced apart along a second direction y. Next, a gate structure 122 is formed extending along the second direction y and connecting at least the active portions corresponding to the first region AA. The gate structure 122 extends through the active portions along the stacking direction z to form the channel structure 121.

[0114] [Corrected 21.07.2023 according to Rule 91] In some embodiments, adjacent gate structures 122 along the first direction x can be further filled with an insulating material for isolation, thereby achieving electrical insulation between adjacent gate structures 122. After filling with the insulating material, the substrate outside the channel structure 121 (i.e., the bottom substrate) can be removed, and bit lines 123 can be formed, connected to the channel structure 121.

[0115] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the position of the channel structure 121 may correspond only to the position of the capacitor hole Q1 in the first area AA, and at the same time, the position of the gate structure 122 corresponds only to the first area AA, that is, the second stacked structure 12 may include a core area corresponding to the first area AA, and a non-core area corresponding to the second area BB, and the channel structure 121 and the gate structure 122 may be located only in the core area. In other embodiments, the position of the channel structure 121 may also correspond to the position of the capacitor hole Q1 in the second area BB, and at the same time, the position of the gate structure 122 may correspond to at least the first area AA, that is, the channel structure 121 may be located in the core area and the non-core area (for example, please continue to refer to Figure 2A), and the gate structure 122 may be located in the core area and the non-core area, or only in the core area, without limitation here.

[0116] [Corrected 21.07.2023 according to Rule 91] Step S102. Form a first electrode layer 13 on the inner wall of the capacitor hole Q1.

[0117] [Corrected 21.07.2023 according to Rule 91] Wherein, if the semiconductor structure 10 is a cup-type capacitor structure, a pillar-type capacitor structure or a cylinder1-type capacitor structure, please continue to refer to Figures 2A, 2B and 3B, and Figure 3B is a schematic diagram of the cross-sectional structure along the C2-C2 line in Figure 2B. The material of the first electrode layer 13 includes conductive materials such as metals or metal compounds, such as tungsten, copper, titanium nitride (TiN), etc. A layer of conductive material can be first formed on one side of the first stacked layer 11, and then the conductive material outside the capacitor hole Q1 is removed to obtain the first electrode layer 13 located in the capacitor hole Q1.

[0118] [Corrected on 21.07.2023 according to Rule 91] It should be pointed out that since the capacitor hole Q1 is arranged at intervals in the first area AA and the second area BB, the inside of the first electrode layer 13 in the first area AA and the inside of the first electrode layer 13 in the second area BB are also arranged at intervals, that is, the first electrode layer 13 in the first area AA and the first electrode layer 13 in the second area BB both include multiple isolated parts, and these parts are not connected to each other.

[0119] [Corrected 21.07.2023 according to Rule 91] Step S103. Form a dielectric layer 14 in the first area AA and the second area BB.

[0120] [Corrected 21.07.2023 according to Rule 91] The dielectric layer 14 is made of a material having a high dielectric constant and can be formed by a thin film deposition process. The formation position of the dielectric layer 14 varies for different types of capacitor structures.

[0121] [Corrected 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2B, 2C and 3C. Figure 3C is a schematic cross-sectional structure diagram along the C3-C3 line in Figure 2C. Specifically, for a cup-type capacitor structure, after forming the first electrode layer 13, a dielectric layer 14 can be formed directly. At this time, the above step S103 includes: forming a dielectric layer 14 on one side of the first stacked layer 11 in the first area AA and the second area BB, and the dielectric layer 14 covers the side of the first electrode layer 13 away from the inner wall of the capacitor hole Q1. The dielectric layer 14 not only covers the first electrode layer 13 in the capacitor hole Q1, but also covers the top surface of the first stacked layer 11.

[0122] [Corrected 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a pillar-type capacitor structure, please refer to Figures 5A to 5F, which are another cross-sectional structural schematic diagram of the semiconductor structure 10 provided in the embodiment of the present application under different process steps. Among them, please continue to refer to Figure 2B, Figures 5A to 5C, and Figures 6A to 6C, Figure 6A is a cross-sectional structural schematic diagram along the D1-D1 line in Figure 5A, Figure 6B is a cross-sectional structural schematic diagram along the D2-D2 line in Figure 5B, and Figure 6C is a cross-sectional structural schematic diagram along the D3-D3 line in Figure 5C. Specifically, for the pillar-type capacitor structure, after forming the first electrode layer 13, it is necessary to first remove a portion of the first stacked layer 11 and then form the dielectric layer 14. That is, the first stacked layer 11 may include a sacrificial layer 111. Before the above-mentioned step S103, the manufacturing method further includes:

[0123] [Corrected 21.07.2023 according to Rule 91] A filling layer 15 is formed on a side of the first electrode layer 13 facing away from the inner wall of the capacitor hole Q1, and the filling layer 15 fills the capacitor hole Q1;

[0124] [Corrected 21.07.2023 according to Rule 91] A plurality of spacing holes Q2 are formed along the stacking direction z through a portion of the first stacking layer 11, and the sacrificial layer 111 is removed to form a first empty groove Q3, wherein the spacing holes Q2 are located in the first area AA and the second area BB.

[0125] [Corrected 21 July 2023 in accordance with Rule 91] The first stacked layer 11 may include alternating sacrificial layers 111 and spacer layers 112. The sacrificial layers 111 may be made of silicon dioxide, and the spacer layers 112 may be made of silicon nitride. The filling layer 15 is generally made of a different material than the first stacked layer 11. For example, the filling layer 15 may be made of carbon. When a portion of the first stacked layer 11 is removed and then the dielectric layer 14 is formed, the dielectric layer 14 may be located on the first stacked layer 11 and fill the first trench Q3 and the spacer hole Q2.

[0126] [Corrected 21.07.2023 according to Rule 91] Specifically, the spacer hole Q2 can be formed by multiple etchings. For example, a hole pattern corresponding to the spacer hole Q2 is first formed on the spacer layer 112 through a mask. Then, the sacrificial layer 111 is removed by wet etching or dry etching through the hole pattern to expose the adjacent spacer layer 112 below. Then, the exposed spacer layer 112 is further etched downward to further expose the adjacent sacrificial layer 111 below. Then, the sacrificial layer 111 is removed through the exposed position of the sacrificial layer 111. Through this multiple etching method, all sacrificial layers 111 in the first stacked layer 11 are removed, thereby obtaining a spacer hole Q2 that penetrates a portion of the first stacked layer 11 along the stacking direction z.

[0127] [Corrected 21.07.2023 in accordance with Rule 91] It should be noted that the figure only illustrates one cross-sectional shape (circular in the figure) and arrangement of the spacing holes Q2. In other embodiments, the spacing holes Q2 may also have other cross-sectional shapes (such as trapezoidal) and arrangements, without limitation. In other embodiments, the spacing holes Q2 may be formed by other methods, such as a single etching, in addition to the multiple etching method mentioned above, without limitation.

[0128] [Corrected 21.07.2023 according to Rule 91] At the same time, in the process of forming the spacing hole Q2, the sacrificial layer 111 is removed together to obtain the first empty groove Q3. After the spacing hole Q2 and the first empty groove Q3 are formed, the dielectric layer 14 is formed (that is, the above-mentioned step S103 is performed again). At this time, the dielectric layer 14 not only covers the top surface of the first stacked layer 11, but also covers the inner wall of the first empty groove Q3 and the inner wall of the spacing hole Q2. In the process of removing the sacrificial layer 111 in the first stacked layer 11, since the capacitor hole Q1 is filled with the filling layer 15, the first stacked layer 11 will not collapse under the support of the filling layer 15.

[0129] [Corrected 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a cylindrical capacitor structure, please refer to Figures 7A to 7E. Figures 7A to 7E are another schematic cross-sectional structure diagram of the semiconductor structure 10 provided in different process steps according to an embodiment of the present application. Among them, please continue to refer to Figures 5B, 7A and 7B, and 8A and 8B. Figure 8A is a schematic cross-sectional structure diagram along the E1-E1 line in Figure 7A, and Figure 8B is a schematic cross-sectional structure diagram along the E2-E2 line in Figure 7B. Specifically, for a cylindrical capacitor structure, similar to a pillar capacitor structure, before forming the dielectric layer 14, it is also necessary to remove a portion of the first stacking layer 11, and for a cylindrical capacitor structure, it is necessary to further remove the filling layer 15, that is, the above step of "forming a plurality of spacing holes Q2 that penetrate a portion of the first stacking layer 11 along the stacking direction z, and removing the sacrificial layer 111 to form a first empty groove Q3" also includes:

[0130] [Corrected 21.07.2023 according to Rule 91] The filling layer 15 is removed to form a second empty groove Q4;

[0131] [Corrected on 21.07.2023 according to Rule 91] The filling layer 15 can be removed by dry or wet etching. When the dielectric layer 14 is subsequently formed, the difference from the above-mentioned pillar-type capacitor structure is that the dielectric layer 14 is located not only in the first empty groove Q3 and the spacing hole Q2, but also in the second empty groove Q4.

[0132] [Corrected 21.07.2023 according to Rule 91] Step S104. Form a second electrode layer 16 on the side of the dielectric layer 14 facing away from the first stacked layer 11.

[0133] [Corrected 21.07.2023 in accordance with Rule 91] The second electrode layer 16 is primarily made of a conductive material, such as tungsten, cobalt, copper, aluminum, or any one or a combination of polycrystalline silicon and doped crystalline silicon. The second electrode layer 16 is located in the first region AA and the second region BB, and the location of the second electrode layer 16 varies for different types of capacitor structures.

[0134] [Corrected 21.07.2023 in accordance with Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2C and 2D, as well as Figure 3D, which is a schematic cross-sectional view of the structure along line C4-C4 in Figure 2D. Specifically, for the cup-type capacitor structure, the second electrode layer 16 is not only located on the top of the first stacked layer 11 (on the dielectric layer 14 on the top surface), but also located in the capacitor hole Q1 (on the dielectric layer 14 in the capacitor hole Q1).

[0135] [Corrected 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to Figures 5C and 5D, as well as Figure 6D, which is a schematic cross-sectional structural diagram along line D4-D4 in Figure 5D. Specifically, for the pillar-type capacitor structure, the second electrode layer 16 is not only located on the top of the first stacked layer 11 (on the dielectric layer 14 on the top surface), but also located in the spacing hole Q2 and the first empty trench Q3 (on the dielectric layer 14 in the spacing hole Q2 and the first empty trench Q3).

[0136] [Corrected 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a cylindrical capacitor structure, please continue to refer to Figures 7B and 7C, as well as Figure 8C, which is a schematic cross-sectional view of the structure along line E3-E3 in Figure 7C. Specifically, for the cylindrical capacitor structure, the second electrode layer 16 is not only located on the top of the first stacked layer 11 (on the dielectric layer 14 on the top surface), but also located in the spacing hole Q2, the first empty trench Q3, and the second empty trench Q4 (on the dielectric layer 14 in the spacing hole Q2, the first empty trench Q3, and the second empty trench Q4).

[0137] [Corrected 21.07.2023 according to Rule 91] Step S105. Remove the second electrode layer 16 on the first stacked layer 11 in the second region BB.

[0138] [Corrected on 21.07.2023 according to Rule 91] The second electrode layer 16 on the top surface of the first stacked layer 11 in the second region BB can be removed by a process such as back etching.

[0139] [Corrected on 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a cup-type capacitor structure, please continue to refer to Figures 2C and 2D. After the second electrode layer 16 is formed, there may still be gaps in the capacitor hole Q1, which need to be filled. That is, the manufacturing method may also include: forming a semiconductor layer 17 on the side of the second electrode layer 16 in the first area AA and the second area BB away from the dielectric layer 14, and the semiconductor layer 17 fills the capacitor hole Q1.

[0140] [Corrected 21.07.2023 according to Rule 91] The material of semiconductor layer 17 includes a semiconductor material such as polysilicon and / or silicide (e.g., SiGe). Semiconductor layer 17 is located on top of first stacked layer 11 (on top second electrode layer 16) and in capacitor hole Q1 (on second electrode layer 16 in capacitor hole Q1).

[0141] [Corrected on 21.07.2023 according to Rule 91] Specifically, for the cup-type capacitor structure, after the semiconductor layer 17 is formed, it is necessary to isolate the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB. To this end, please continue to refer to Figures 2D and 2E. The second electrode layer 16 on the first stacked layer 11 in the second area BB can be directly removed. At the same time, since the semiconductor layer 17 is made of a conductive material, it is necessary to further remove the semiconductor layer 17 on the first stacked layer 11 in the second area BB, so as to achieve isolation of the second electrode layer 16 in the first area AA and the second area BB, and subsequently power is turned on to achieve electrical insulation between the two.

[0142] [Corrected 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a pillar-type capacitor structure, please continue to refer to Figures 5D and 5E. The second electrode layer 16 in the first area AA and the second area BB can be directly separated by removing the second electrode layer 16 on the first stacked layer 11 in the second area BB.

[0143] [Corrected on 21.07.2023 according to Rule 91] In some embodiments, for example, if the semiconductor structure 10 is a cylindrical capacitor structure, please continue to refer to Figures 7C and 7D. Similar to the above-mentioned pillar-type capacitor structure, in the cylindrical capacitor structure, the second electrode layer 16 in the first area AA and the second area BB can also be directly removed by removing the second electrode layer 16 on the first stacked layer 11 in the second area BB to achieve the isolation.

[0144] [Corrected 21.07.2023 in accordance with Rule 91] It should be noted that after the second electrode layer 16 in the first area AA and the second area BB are separated, the first electrode layer 13, dielectric layer 14, and second electrode layer 16 in the first area AA will together function as a capacitor structure, which has charge storage capabilities. Furthermore, because the second electrode layer 16 in the cylindrical capacitor structure is located not only in the spacing hole Q2 and the first slot Q3 but also in the second slot Q4, the cylindrical capacitor structure significantly increases the effective area of ​​the second electrode layer 16 compared to a pillar-type capacitor structure that does not form the second slot Q4, thereby improving the charge storage capacity of the capacitor structure.

[0145] [Corrected 21.07.2023 according to Rule 91] Step S106. Form a contact structure 18 that penetrates the first stack layer 11 in the second region BB along the stacking direction z.

[0146] [Corrected 21.07.2023 according to Rule 91] Please continue to refer to Figures 2F and 3E, Figures 5F and 6E, and Figures 7E and 8D respectively. Figure 3E is a schematic diagram of the cross-sectional structure along the C5-C5 line in Figure 2F, Figure 6E is a schematic diagram of the cross-sectional structure along the D5-D5 line in Figure 5F, and Figure 8D is a schematic diagram of the cross-sectional structure along the E4-E4 line in Figure 7E. The specific number of contact structures 18 and their formation positions in the second area BB can be determined according to actual needs and are not limited here. The contact structure 18 may include an insulating layer 181 and a conductive layer 182 located on the side of the insulating layer 181 facing away from the first stacked layer 11. The material of the insulating layer 181 includes an insulating material such as silicon oxide, and the material of the conductive layer 182 includes a metal material such as tungsten. In addition to penetrating the first stacked layer 11, the contact structure 18 will further penetrate the second stacked structure 12 along the stacking direction z and be electrically connected to the peripheral circuit.

[0147] [Corrected on 21.07.2023 according to Rule 91] It is easy to understand that after the contact structure 18 is formed, the final first stacked layer 11, such as the first stacked layer 11 after removing the sacrificial layer 111 in the pillar-type capacitor structure, or the first stacked layer 11 after not removing the sacrificial layer 111 in the cup capacitor structure, can be used as the first stacked structure 11a.

[0148] [Corrected on 21.07.2023 according to Rule 91] An embodiment of the present application also provides a semiconductor structure 10. Please continue to refer to the above-mentioned Figures 2F and 3E, Figures 5F and 6E, and Figures 7E and 8D. The semiconductor structure 10 may include a cup-type capacitor structure, a pillar-type capacitor structure, or a cylindrical capacitor structure.

[0149] [Corrected on 21.07.2023 according to Rule 91] The semiconductor structure 10 includes: a first stacking structure 11a, the stacking structure 11a includes a first area AA and a second area BB; a first electrode layer 13 located in the first area AA and the second area BB, the first electrode layer 13 passes through the first stacking structure 11a along the stacking direction z, and the first electrode layer 13 in the first area AA and the first electrode layer 13 in the second area BB are spaced apart; a dielectric layer 14 located in the first area AA and the second area BB; a second electrode layer 16 located in the first area AA and the second area BB, the dielectric layer 14 is provided between the first electrode layer 13 and the second electrode layer 16, and the second electrode layer 16 in the first area AA and the second area BB are spaced apart; a contact structure 18, the contact structure 18 passes through the first stacking structure 11a in the second area BB along the stacking direction z.

[0150] [Corrected 21 July 2023 in accordance with Rule 91] The first area AA is the area corresponding to the memory array, and the second area BB is another area. The first area AA and the second area BB may be adjacent to each other, for example, the second area BB is disposed around the first area AA. The material of the first electrode layer 13 includes a metal or other conductive material, such as tungsten or copper. The material of the dielectric layer 14 is a material with a high dielectric constant. The material of the second electrode layer 16 is primarily a conductive material, and may be any one or a combination of tungsten, cobalt, copper, aluminum, polysilicon, or doped crystalline silicon.

[0151] [Corrected 21.07.2023 in accordance with Rule 91] The specific number of contact structures 18 and their locations within the second region BB can be determined based on practical needs and are not limited herein. Contact structure 18 may include an insulating layer 181 and a conductive layer 182 located on a side of the insulating layer 181 facing away from the first stacked structure 11a. The insulating layer 181 may be made of an insulating material such as silicon oxide, and the conductive layer 182 may be made of a metal such as tungsten.

[0152] [Corrected 21 July 2023 in accordance with Rule 91] Specifically, the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are spaced apart from each other, primarily meaning that the second electrode layer 16 in the first area AA and the second electrode layer 16 in the second area BB are separated from each other, with no direct contact between them. Furthermore, the interior of the first electrode layer 13 in the first area AA and the interior of the first electrode layer 13 in the second area BB are spaced apart along a first direction x and a second direction y, with the first direction x, the second direction y, and the stacking direction z being mutually perpendicular. In other words, the first electrode layer 13 in the first area AA and the first electrode layer 13 in the second area BB each include multiple separated portions that are not connected to each other. The first direction x and the second direction y may be the extension directions of the stacked layer 11.

[0153] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the dielectric layer 14 is located on one side of the first stacked structure 11a and penetrates portions of the first stacked structure 11a in the first area AA and the second area BB along the stacking direction z; the second electrode layer 16 is located on the first stacked structure 11a in the first area AA and covers a side of the dielectric layer 14 in the first stacked structure 11a that faces away from the first electrode layer 13. That is, the dielectric layer 14 is located on the top surface of the first stacked structure 11a in the first area AA and the second area BB, and within the first stacked structure 11a, and the second electrode layer 16 is located on the top surface of the first stacked structure 11a in the first area AA and the second area BB, and within the first stacked structure 11a. Furthermore, for different types of capacitor structures, the dielectric layer 14 and the second electrode layer 16 are located in different locations within the first stacked structure 11a.

[0154] [Corrected on 21.07.2023 according to Rule 91] For example, in some embodiments, please continue to refer to Figures 2F and 3E. If the semiconductor structure 10 is a cup-type capacitor structure, the dielectric layer 14 in the first stacking structure 11a covers the side of the first electrode layer 13 in the first area AA and the second area BB facing away from the first stacking structure 11a.

[0155] [Corrected on 21.07.2023 according to Rule 91] In some embodiments, please continue to refer to Figures 2F and 3E. If the semiconductor structure 10 is a cup-type capacitor structure, the semiconductor structure 10 also includes a semiconductor layer 17, and the semiconductor layer 17 is located on the first stacking structure 11a in the first area AA, and covers the side of the second electrode layer 16 in the first stacking structure 11a in the first area AA and the second area BB away from the dielectric layer 14.

[0156] [Corrected 21.07.2023 according to Rule 91] In which, the first electrode layer 13, the dielectric layer 14, the second electrode layer 16 and the semiconductor layer 17 in the first area AA can be used together as a capacitor structure, and since the first electrode layer 13 is arranged at intervals, a plurality of capacitor structures with uniform sizes are formed in the first area AA. The material of the semiconductor layer 17 includes semiconductor materials such as polysilicon and / or silicide (such as SiGe silicon germanium). The first electrode layer 13 in the first stacked structure 11a is arranged around the dielectric layer 14 in the first stacked structure 11a. The dielectric layer 14 in the first stacked structure 11a is arranged around the second electrode layer 16 in the first stacked structure 11a. The second electrode layer 16 in the first stacked structure 11a is arranged around the semiconductor layer 17 in the first stacked structure 11a.

[0157] [Corrected on 21.07.2023 according to Rule 91] For example, in some embodiments, please continue to refer to Figures 5F and 6E, and Figures 7E and 8D. If the semiconductor structure 10 is a pillar-type capacitor structure or a cylindrical capacitor structure, the dielectric layer in the first stacked structure 11a is located at least between two adjacent first electrode layers that are spaced apart.

[0158] [Corrected on 21.07.2023 according to Rule 91] In particular, the first electrode layer 13, the dielectric layer 14 and the second electrode layer 16 in the first area AA can together serve as a capacitor structure, and since the first electrode layer 13 is arranged at intervals, a plurality of capacitor structures arranged at intervals and having uniform sizes are formed in the first area AA.

[0159] [Corrected 21.07.2023 according to Rule 91] Specifically, referring to Figures 5F and 6E , if the semiconductor structure 10 is a pillar-type capacitor structure, the semiconductor structure 10 further includes a filling layer 15 located within the first stacked structure 11a in the first region AA and the second region BB. The filling layer 15 is spaced apart, and the first electrode layer 13 is disposed around the filling layer 15. The material of the filling layer 15 may include carbon.

[0160] [Corrected on 21.07.2023 according to Rule 91] Please continue to refer to Figure 7E and Figure 8D. If the semiconductor structure 10 is a cylindrical capacitor structure, the dielectric layer 14 in the first stacked structure 11a also covers the side of the first electrode layer 13 facing away from the first stacked structure 11a.

[0161] [Corrected 21.07.2023 according to Rule 91] In some embodiments, referring to Figures 5F and 6E, and Figures 7E and 8D, if the semiconductor structure 10 is a pillar-type capacitor structure or a cylindrical-type capacitor structure, the first stacked structure 11a includes a plurality of stacked spacer layers 112, and the dielectric layer 14 and the second electrode layer 16 are further located between two adjacent spacer layers 112 in the first region AA and the second region BB along the stacking direction z. The material of the spacer layer 112 may include silicon nitride.

[0162] [Corrected 21.07.2023 according to Rule 91] In some embodiments, please continue to refer to Figures 2F and 3E, Figures 5F and 6E, and Figures 7E and 8D. If the semiconductor structure 10 is a cup-type capacitor structure, a pillar-type capacitor structure, or a cylindrical capacitor structure, the semiconductor structure 10 may further include a second stacked structure 12. The second stacked structure 12 is located on a side of the first stacked structure 11a away from the second electrode layer 16, and includes a plurality of channel structures 121 spaced apart along the first direction x and the second direction y, and a gate structure 122 extending along the second direction y and connecting the plurality of channel structures 121, wherein the gate structure 122 is located between two adjacent channel structures 121.

[0163] [Corrected 21.07.2023 according to Rule 91] The position of the channel structure 121 corresponds at least to the position of the first electrode layer 13 in the first area AA, and the contact structure 18 penetrates the first stacking structure 11a and the second stacking structure 12 along the stacking direction z.

[0164] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the position of the channel structure 121 also corresponds to the position of the first electrode layer 13 in the second region BB, and the position of the gate structure 122 corresponds to at least the first region AA. That is, the gate structure 122 may be formed at corresponding positions in both the first region AA and the second region BB, or only at the position corresponding to the first region AA, without limitation.

[0165] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the gate structure 122 may include a gate spacer layer 1221 and a gate layer 1222. The gate spacer layer 1221 may be made of an insulating material such as an oxide, and the gate layer 1222 may be made of any one or a combination of tungsten, cobalt, copper, aluminum, polycrystalline silicon, and doped crystalline silicon. Adjacent gate structures 122 along the first direction x may be further separated by insulating material to achieve electrical isolation between adjacent gate structures 122.

[0166] [Corrected on 21.07.2023 according to Rule 91] In some embodiments, the semiconductor structure 10 may further include a bit line 123 . The bit line 123 may be located on a side of the channel structure 121 away from the first stacked structure 11 a and connected to the channel structure 121 .

[0167] [Corrected on 21.07.2023 according to Rule 91] It should be understood that the structures and manufacturing processes of the various components of the semiconductor structure 10 in the embodiment of the present application can refer to the above-mentioned embodiment of the manufacturing method of the semiconductor structure 10, and will not be repeated here.

[0168] [Corrected on 21.07.2023 according to Rule 91] As can be seen from the above, the semiconductor structure 10 and the manufacturing method thereof provided in the embodiment of the present application form a plurality of capacitor holes Q1 passing through the first stacking layer 11 along the stacking direction z, and the first stacking layer 11 includes a first area AA and a second area BB. The capacitor holes Q1 are located in the first area AA and the second area BB, thereby greatly avoiding a serious etching load effect in the first area AA when forming the capacitor holes Q1, and ensuring the size consistency of the capacitor holes Q1 in the first area AA as much as possible, and preventing insufficient etching. Subsequently, a first electrode layer 13 is formed on the inner wall of the capacitor hole Q1; a dielectric layer 14 is formed in the first area AA and the second area BB; a second electrode layer 16 is formed on the side of the dielectric layer 14 away from the first stacking layer 11; the second electrode layer 16 on the first stacking layer 11 in the second area BB is removed; and a contact structure 18 is formed passing through the first stacking layer 11 in the second area BB along the stacking direction z, so that a capacitor structure with uniform size can be formed in the first area AA, thereby improving the reliability of the capacitor structure.

[0169] [Corrected 21.07.2023 according to Rule 91] The present application also provides another method for manufacturing a semiconductor structure 30 . The method for manufacturing the semiconductor structure 30 may include the following steps S201 - S206 , wherein:

[0170] [Corrected 21.07.2023 according to Rule 91] Step S201. Forming a plurality of capacitor holes penetrating a first stacked layer along a stacking direction, the first stacked layer comprising a first region and a second region, the capacitor holes being located in the first region and the second region;

[0171] [Corrected 21.07.2023 according to Rule 91] Step S202. Forming a first electrode layer on the inner wall of the capacitor hole in the first region;

[0172] [Corrected 21.07.2023 according to Rule 91] Step S203. Removing part of the first stacked layer in the first region and the second region;

[0173] [Corrected 21.07.2023 according to Rule 91] Step S204. Forming a dielectric layer and a second electrode layer in the first region, the second electrode layer being located on a side of the dielectric layer facing away from the first electrode layer;

[0174] [Corrected 21.07.2023 according to Rule 91] Step S205. Forming a flat layer in the second region;

[0175] [Corrected 21.07.2023 according to Rule 91] Step S206. Form a contact structure penetrating the planar layer along the stacking direction.

[0176] [Corrected 21.07.2023 in accordance with Rule 91] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0177] [Corrected 21.07.2023 according to Rule 91] Please refer to Figures 9A to 9J and 11A to 11E. Figures 9A to 9J are schematic cross-sectional views of another semiconductor structure 30 provided in an embodiment of the present application at different process steps. Figures 11A to 11E are schematic cross-sectional views of another semiconductor structure 30 provided in an embodiment of the present application at different process steps. The semiconductor structure 30 may include a pillar-type capacitor structure or a cylindrical-type capacitor structure. The above steps S201-S206 will be further described below in conjunction with Figures 9A to 9J and 11A to 11E, wherein:

[0178] [Corrected 21.07.2023 according to Rule 91] Step S201. A plurality of capacitor holes Q1 are formed through the first stacking layer 31 along the stacking direction z, wherein the first stacking layer 31 includes a first area AA and a second area BB, and the capacitor holes Q1 are located in the first area AA and the second area BB.

[0179] [Corrected 21.07.2023 according to Rule 91] Wherein, if the semiconductor structure 30 is a pillar-type capacitor structure or a cylindrical-type capacitor structure, please refer to Figures 9A and 10A above. Figure 10A is a schematic diagram of the cross-sectional structure along the F1-F1 line in Figure 9A. The first area AA is the area corresponding to the storage array, and the second area BB is other areas. The first area AA and the second area BB can be adjacent to each other, for example, the second area BB is arranged around the first area AA. The capacitor holes Q1 can be distributed in the entire area of ​​the first stacked layer 31 and are arranged at intervals inside. Preferably, these capacitor holes Q1 can be set to the same size and the same spacing.

[0180] [Corrected 21.07.2023 according to Rule 91] Specifically, the first stacked layer 31 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first stacked layer 31 can be formed by alternating layers of different insulating materials, such as alternating layers of silicon dioxide and silicon nitride.

[0181] [Corrected 21.07.2023 in accordance with Rule 91] Capacitor holes Q1 can be formed in both the first region AA and the second region BB of the first stacked layer 31 through two orthogonal or angled patterning processes. In this case, since the pattern of the capacitor holes Q1 is relatively uniformly distributed across the entire surface of the first stacked layer 31, that is, the density difference between the etched patterns corresponding to the first region AA and the second region BB is relatively small, the difference in the etch depth and size of the capacitor holes Q1 formed in the first region AA and the second region BB is relatively small, thereby minimizing the occurrence of a severe etch loading effect. Furthermore, even if a certain etch loading effect exists, affecting the etch depth and hole size of the capacitor holes Q1 at the edge, since the second region BB is generally disposed around the first region AA, the etch loading effect generally only affects the capacitor holes Q1 on the outermost edge of the second region BB and is unlikely to affect the capacitor holes Q1 in the first region AA. Therefore, by forming the capacitor holes Q1 in both the first area AA and the second area BB, the serious etching load effect in the first area AA can be greatly avoided, and the etching depth and size of the capacitor holes Q1 in the first area AA can be kept consistent as much as possible, avoiding the phenomenon that some capacitor holes Q1 have insufficient etching depth or are too small in size.

[0182] [Corrected 21.07.2023 according to Rule 91] In some embodiments, before step S201, the production method may further include:

[0183] [Corrected 21.07.2023 according to Rule 91] forming a second stacked structure 32, the second stacked structure 32 comprising a plurality of channel structures 321 spaced apart along a first direction x and a second direction y, and a gate structure 322 extending along the second direction y and connecting the plurality of channel structures 321, the gate structure 322 being located between two adjacent channel structures 321, the first direction x, the second direction y, and the stacking direction z being perpendicular to each other;

[0184] [Corrected 21.07.2023 according to Rule 91] The first stack layer 31 is formed on the second stack structure 32.

[0185] [Corrected 21.07.2023 according to Rule 91] The position of the channel structure 321 corresponds to at least the position of the capacitor hole Q1 in the first area AA. The first direction x and the second direction y may be extension directions of the first stacked layer 31, which are perpendicular to the stacking direction z of the first stacked layer 31. The gate structure 322 may include a gate spacer 3221 and a gate layer 3222. The material of the gate spacer 3221 may include an insulating material such as an oxide, and the material of the gate layer 3222 may be any one or a combination of tungsten, cobalt, copper, aluminum, polysilicon, and doped crystalline silicon.

[0186] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the channel structure 321 is formed on a substrate, which may include at least one of single crystal silicon (Si), single crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. Specifically, the substrate can be etched to form a plurality of active portions extending along a first direction x and spaced apart along a second direction y. Next, a gate structure 322 is formed extending along the second direction y and connecting at least the active portions corresponding to the first region AA. The gate structure 322 extends through the active portions along the stacking direction z to form the channel structure 321.

[0187] [Corrected 21.07.2023 according to Rule 91] In some embodiments, adjacent gate structures 322 along the first direction x can be further filled with an insulating material for isolation, thereby achieving electrical insulation between adjacent gate structures 322. After filling with the insulating material, the substrate outside the channel structure 321 (i.e., the bottom substrate) can be removed, and a bit line 323 can be formed, which is connected to the channel structure 321.

[0188] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the position of the channel structure 321 may correspond only to the position of the capacitor hole Q1 in the first area AA, and at the same time, the position of the gate structure 322 corresponds only to the first area AA, that is, the second stacked structure 32 may include a core area corresponding to the first area AA, and a non-core area corresponding to the second area BB, and the channel structure 321 and the gate structure 322 may be located only in the core area. In other embodiments, the position of the channel structure 321 may also correspond to the position of the capacitor hole Q1 in the second area BB, and at the same time, the position of the gate structure 322 may correspond to at least the first area AA, that is, the channel structure 321 may be located in the core area and the non-core area (for example, please continue to refer to Figure 9A), and the gate structure 322 may be located in the core area and the non-core area, or only in the core area, without limitation here.

[0189] [Corrected 21.07.2023 according to Rule 91] Step S202. Form a first electrode layer 33 on the inner wall of the capacitor hole Q1 in the first area AA.

[0190] [Corrected 21.07.2023 according to Rule 91] In some embodiments, if the semiconductor structure 30 is a pillar-type capacitor structure or a cylindrical-type capacitor structure, please continue to refer to Figures 9A to 9D, and Figures 10B to 10D. Figure 10B is a schematic cross-sectional structural diagram along line F2-F2 in Figure 9B, Figure 10C is a schematic cross-sectional structural diagram along line F3-F3 in Figure 9C, and Figure 10D is a schematic cross-sectional structural diagram along line F4-F4 in Figure 9D. Before the above step S202, the manufacturing method further includes:

[0191] [Corrected 21.07.2023 according to Rule 91] forming a sacrificial structure 34 in the capacitor hole Q1 in the first area AA and the second area BB;

[0192] [Corrected 21.07.2023 according to Rule 91] removing the sacrificial structure 34 in the first area AA and exposing the capacitor hole Q1 in the first area AA;

[0193] [Corrected on 21.07.2023 according to Rule 91] At this time, the above-mentioned step S202 specifically includes: forming a first electrode layer 33 on the exposed inner wall of the capacitor hole Q1.

[0194] [Corrected 21.07.2023 according to Rule 91] The material of the first electrode layer 33 includes a conductive material such as a metal or a metal compound, such as tungsten, copper, or titanium nitride (TiN). The material of the sacrificial structure 34 includes carbon. By forming the sacrificial structure 34 and removing the sacrificial structure 34 in the first area AA to expose the capacitor hole Q1 in the first area AA, and retaining only the sacrificial structure 34 in the second area BB, a capacitor structure can be subsequently formed only in the first area AA.

[0195] [Corrected 21.07.2023 according to Rule 91] Specifically, a layer of conductive material can be formed on one side of the first stacked layer 31, and the conductive material will cover the inner wall of the capacitor hole Q1 exposed in the first area AA. Thereafter, the conductive material outside the inner wall of the capacitor hole Q1 is removed to obtain the first electrode layer 33 located in the first area AA.

[0196] [Corrected on 21.07.2023 according to Rule 91] It should be noted that since the capacitor hole Q1 is arranged at intervals in the first area AA and the second area BB, the first electrode layer 33 in the first area AA is also arranged at intervals, that is, the first electrode layer 33 in the first area AA includes multiple isolated parts, and these parts are not connected to each other.

[0197] [Corrected 21.07.2023 according to Rule 91] Step S203. Remove part of the first stacked layer 31 in the first area AA and the second area BB.

[0198] [Corrected on 21.07.2023 according to Rule 91] If the semiconductor structure 30 is a pillar-type capacitor structure or a cylindrical-type capacitor structure, in order to prevent the first stacked layer 31 from collapsing when a portion of the first stacked layer 31 is removed, the capacitor hole Q1 in the first area AA needs to be filled first.

[0199] [Corrected 21.07.2023 according to Rule 91] In some embodiments, please continue to refer to FIG. 9D and FIG. 9E , as well as FIG. 10E , FIG. 10E is a schematic cross-sectional view of the structure along line F5-F5 in FIG. 9E . Before the above step S203 , the manufacturing method may further include:

[0200] [Corrected 21.07.2023 according to Rule 91] A filling layer 35 is formed on one side of the first stacked layer 31 in the first area AA and the second area BB, and the filling layer 35 covers the side of the first electrode layer 33 in the first area AA away from the inner wall of the capacitor hole Q1, and fills the capacitor hole Q1 in the first area AA.

[0201] [Corrected 21.07.2023 according to Rule 91] The filling layer 35 may be made of a material with good hardness, such as polysilicon. The filling layer 35 is located on the top surface of the first stacked layer 31 in the first and second regions AA and BB, and in the capacitor hole Q1 in the first region AA.

[0202] [Corrected on 21.07.2023 according to Rule 91] Specifically, after the capacitor hole Q1 in the first area AA is filled, if the semiconductor structure 30 is a pillar-type capacitor structure, please continue to refer to Figures 9E and 9F, as well as Figure 10F. Figure 10F is a schematic cross-sectional structure diagram along line F6-F6 in Figure 9F.

[0203] [Corrected 21.07.2023 according to Rule 91] The first stacked layer 31 may include sacrificial layers 311 and spacer layers 312 arranged alternately. Step S203 may specifically include:

[0204] [Corrected 21.07.2023 according to Rule 91] forming a plurality of spaced holes Q2 penetrating a portion of the first stacked layer 31 in the first area AA along the stacking direction z, and removing the sacrificial layer 311 to form a first empty groove Q3;

[0205] [Corrected 21.07.2023 according to Rule 91] The sacrificial structure 34 in the second region BB is removed.

[0206] [Corrected 21.07.2023 according to Rule 91] The sacrificial layer 311 may be made of silicon dioxide, and the spacer layer 312 may be made of silicon nitride. The spacer hole Q2 also penetrates the filling layer 35 along the stacking direction z and extends into the first stacked layer 31 . The spacer hole Q2 is located only in the first region AA.

[0207] [Corrected 21.07.2023 according to Rule 91] Specifically, the spacer hole Q2 can be formed by multiple etching processes. For example, a hole pattern corresponding to the spacer hole Q2 is first formed on the filling layer 35 at the top of the first stack layer 31 in the first region AA through a mask, and the filling layer at the top of the first stack layer 31 in the second region BB is removed. Then, the top spacer layer 312 is etched downward through the pattern of the filling layer 35 to expose a portion of the adjacent sacrificial layer 311 below. Then, the sacrificial layer 311 is removed through the exposed portion by wet or dry etching to expose the adjacent spacer layer 312 below. Then, the exposed spacer layer 312 is further etched downward to further expose the adjacent sacrificial layer 311 below. Finally, the sacrificial layer 311 is removed through the exposed portion of the sacrificial layer 311. This multiple etching process removes all of the sacrificial layer 311 within the first stack layer 31, leaving only the bottom spacer layer 312, thereby forming the spacer hole Q2 that penetrates a portion of the first stack layer 31 along the stacking direction z.

[0208] [Corrected 21.07.2023 in accordance with Rule 91] It should be noted that the figure only illustrates one cross-sectional shape (square in the figure) and arrangement of the spacing holes Q2. In other embodiments, the spacing holes Q2 may also have other cross-sectional shapes (such as trapezoidal or circular) and arrangements, without limitation. In other embodiments, the spacing holes Q2 may be formed by other methods besides the multiple etching method mentioned above, without limitation.

[0209] [Corrected 21.07.2023 in accordance with Rule 91] Simultaneously, during the formation of spacer hole Q2, sacrificial layer 311 is removed, resulting in first vacant trench Q3. During this process, the sacrificial structure 34 in second area BB and the filler layer in first area AA provide effective support. Subsequently, the sacrificial structure 34 in second area BB (i.e., the remaining sacrificial structure 34) is also removed, leaving only the spacer layer 312 at the bottom of second area BB.

[0210] [Corrected 21.07.2023 according to Rule 91] In some embodiments, if the semiconductor structure 30 is a cylindrical capacitor structure, please refer to Figures 11A to 11E, which are another cross-sectional structural diagram of the semiconductor structure 30 at different process steps provided in an embodiment of the present application. Please continue to refer to Figures 9E and 11A, and Figure 12A, which is a cross-sectional structural diagram along line G1-G1 in Figure 11A. The above step S203 may further include:

[0211] [Corrected 21.07.2023 according to Rule 91] The filling layer 35 in the capacitor hole Q1 in the first area AA is removed to form a second empty groove Q4.

[0212] [Corrected on 21.07.2023 according to Rule 91] Similar to the pillar-type capacitor structure, the cylindrical capacitor structure also needs to form the spacing hole Q2 and the first slot Q3, and the only difference is that the cylindrical capacitor structure also needs to form the second slot Q4.

[0213] [Corrected 21.07.2023 according to Rule 91] Step S204. A dielectric layer 36 and a second electrode layer 37 are formed in the first area AA, wherein the second electrode layer 37 is located on a side of the dielectric layer 36 facing away from the first electrode layer 33.

[0214] [Corrected on 21.07.2023 according to Rule 91] In which, if the semiconductor structure 30 is a pillar-type capacitor structure, please continue to refer to Figures 9F to 9H, as well as Figures 10G and 10H. Figure 10G is a schematic diagram of the cross-sectional structure along the F7-F7 line in Figure 9G, and Figure 10H is a schematic diagram of the cross-sectional structure along the F8-F8 line in Figure 9H. The dielectric layer 36 and the second electrode layer 37 are not only located on top of the first stacked layer 31, but also fill the spacing hole Q2 and the first empty groove Q3. If the semiconductor structure 30 is a cylindrical capacitor structure, please continue to refer to Figures 11A to 11C, as well as Figures 12B and 12C. Figure 12B is a schematic diagram of the cross-sectional structure along the G2-G2 line in Figure 11B, and Figure 12C is a schematic diagram of the cross-sectional structure along the G3-G3 line in Figure 11C. The dielectric layer 36 and the second electrode layer 37 are not only located on the top of the first stacking layer 31, but also fill the spacing hole Q2, the first empty groove Q3 and the second empty groove Q4.

[0215] [Corrected 21.07.2023 in accordance with Rule 91] Specifically, dielectric layer 36 is made of a material having a high dielectric constant and can be formed using a thin film deposition process. Second electrode layer 37 is primarily made of a conductive material, such as tungsten, cobalt, copper, aluminum, titanium nitride, silicon germanium, polysilicon, or doped crystalline silicon, or any combination thereof.

[0216] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the above step S204 may specifically include:

[0217] [Corrected 21.07.2023 according to Rule 91] forming a dielectric layer 36 on one side of the first stacked layer 31 in the first area AA and the second area BB;

[0218] [Corrected 21.07.2023 according to Rule 91] forming a second electrode layer on a side of the dielectric layer 36 facing away from the first stacked layer 31;

[0219] [Corrected 21.07.2023 according to Rule 91] The dielectric layer 36 and the second electrode layer 37 in the second region BB are removed.

[0220] [Corrected on 21.07.2023 according to Rule 91] In which, the dielectric layer 36 and the second electrode layer 37 can be formed by a thin film deposition process, and the dielectric layer 36 and the second electrode layer 37 in the second area BB are removed by dry etching, leaving only the dielectric layer 36 and the second electrode layer 37 in the first area AA. At this time, only a portion of the bottom spacer layer 312 is retained in the second area BB.

[0221] [Corrected 21.07.2023 according to Rule 91] Step S205. Form a flat layer 38 in the second area BB.

[0222] [Corrected 21.07.2023 in accordance with Rule 91] If the semiconductor structure 30 is a pillar-type capacitor structure or a cylindrical capacitor structure, please continue to refer to FIG. 9I and FIG. 10I , and FIG. 11D and FIG. 12D , respectively. FIG. 10I is a schematic cross-sectional view taken along line F9-F9 in FIG. 9I , and FIG. 12D is a schematic cross-sectional view taken along line G4-G4 in FIG. 11D . The material of the planarization layer 38 may include an oxide, such as silicon dioxide. The planarization layer 38 may be processed by CMP (Chemical Mechanical Polishing) so that the top surface of the planarization layer 38 is substantially flush with the top surface of the second electrode layer 37 in the first area AA.

[0223] [Corrected 21.07.2023 according to Rule 91] Step S206. Form a contact structure 39 penetrating the planar layer 38 along the stacking direction z.

[0224] [Corrected 21.07.2023 according to Rule 91] Wherein, if the semiconductor structure 30 is a pillar-type capacitor structure or a cylindrical capacitor structure, please continue to refer to Figures 9J and 10J, and Figures 11E and 12E respectively. Figure 10J is a schematic cross-sectional structural diagram along line F10-10 in Figure 9J, and Figure 12E is a schematic cross-sectional structural diagram along line G5-G5 in Figure 11E. The contact structure 39 can be located at any position in the second region BB. The specific number of contact structures 39 and their formation positions in the second region BB can be determined according to actual needs and are not limited here. The contact structure 39 may include an insulating layer 391 and a conductive layer 392 located on the side of the insulating layer 391 facing away from the first stacked layer 31. The material of the insulating layer 391 includes an insulating material such as silicon oxide, and the material of the conductive layer 392 includes a metal material such as tungsten. In addition to penetrating the planar layer 38, the contact structure 39 will further penetrate the second stacked structure 32 along the stacking direction z and be electrically connected to the peripheral circuit.

[0225] [Corrected 21.07.2023 according to Rule 91] The embodiment of the present application also provides a semiconductor structure 30, please continue to refer to the above-mentioned Figures 9J, 10J, 11E, 12E and 11F.

[0226] [Corrected 21.07.2023 according to Rule 91] The semiconductor structure 30 includes a second stacked structure 32, a first stacked layer 31, and a capacitor structure. The capacitor structure is located within the first stacked layer 31. The first stacked layer 31 is located on the second stacked structure 32 and includes a first area AA and a second area BB. The second stacked structure 32 includes a plurality of channel structures 321 spaced apart along a first direction x and a second direction y, and a gate structure 322 extending along the second direction y and connecting the plurality of channel structures 321. The gate structure 322 is located between two adjacent channel structures 321. The first area AA of the first stacked layer 31 has capacitor holes Q1 spaced apart, and the positions of the channel structures 321 correspond at least to the positions of the capacitor holes Q1 in the first area AA. The gate structure 322 may include a gate spacer 3221 and a gate layer 3222. The gate spacer 3221 is located between the gate layer 3222 and the channel structure 321. Adjacent gate structures 322 are isolated and electrically insulated by insulating material. The second stack structure 32 further includes a bit line 323 . The bit line 323 is located on a side of the second stack structure 32 away from the first stack layer 31 and is connected to the channel structure 321 .

[0227] [Corrected 21.07.2023 according to Rule 91] The first stacked layer 31 includes spacer layers 312 spaced apart in the stacking direction z. One spacer layer 312 is located at an end of the second stacked structure 32 away from the bit line 323. A first empty trench Q3 is defined between two adjacent spacer layers 312. The capacitor hole Q1 extends through the spacer layer 412. The spacer layer 412 may be made of silicon nitride.

[0228] [Corrected 21.07.2023 according to Rule 91] Referring to Figure 9J, in some embodiments, the capacitor structure further comprises a first electrode layer 33, a dielectric layer 36, and a second electrode layer 37. The first electrode layer 33 is located on the inner wall of the capacitor hole Q1 in the first area AA, that is, the first electrode layer 33 is connected to the spacer layer 312 and the channel structure 321. Due to the presence of the capacitor hole Q1, the first electrode layer 33 and the spacer layer 312 each include multiple isolated portions that are not connected to each other. The dielectric layer 36 is located on one side of the first stacked layer 31 in the first area AA and covers the side of the first electrode layer 33 facing away from the second stacked structure 32. The second electrode layer 37 is located on the side of the dielectric layer 36 facing away from the first electrode layer 33 in the first area AA. The first stacked layer 31 further comprises a filling layer 35, which is located on the side of the first electrode layer 33 facing away from the spacer layer 312 and the second stacked structure 32 and fills the capacitor hole Q1. That is, the first electrode layer 33 is disposed around the filling layer 35. The dielectric layer 36 also covers the filling layer 35. The dielectric layer 36 and the second electrode layer 37 also fill the first trench Q3. The dielectric layer 36 filling the first trench Q3 is connected to the spacer layer 312 and the first electrode layer 33, and surrounds the second electrode layer 37 filling the first trench Q3. The first stacked layer 31 also has a spacing hole Q2 that penetrates at least a portion of the spacer layer 312 along the stacking direction z. The spacing hole Q2 has two adjacent first electrode layers 33 extending along the stacking direction z as its inner wall. The dielectric layer 36 and the second electrode layer 37 also fill the spacing hole Q2. That is, the dielectric layer 36 located in the spacing hole Q2 is connected to the spacer layer 312 located on the second stacked structure 32, and the dielectric layer 36 located in the spacing hole Q2 surrounds the second electrode layer 37 located in the spacing hole Q2.

[0229] [Corrected 21.07.2023 according to Rule 91] Since the first electrode layers 33 are arranged at intervals, a plurality of capacitor structures arranged at intervals and having uniform sizes are formed in the first area AA.

[0230] [Corrected on 21.07.2023 according to Rule 91] Please refer to Figure 11E. In some embodiments, the filling layer 35 located in the capacitor hole Q1 can also be replaced by a dielectric layer 36 and a second electrode layer 37. That is, between two adjacent partitions of the spacer layer 312, there are multiple first electrode layers 33 that are opposite to and connected to the channel structure 321. The two adjacent first electrode layers 33 are separated by the dielectric layer 36, and part of the second electrode layer 37 is filled in the gap formed by the dielectric layer 36, and is arranged opposite to the first electrode layer 33 in the stacking direction z.

[0231] [Corrected 21.07.2023 according to Rule 91] The semiconductor structure 30 further includes a planarization layer 38 located in the second region BB. The planarization layer 38 is disposed adjacent to the first stacked layer 31 in the first region AA and is located on a side of the second stacked structure 32 away from the bit line 323. A portion of the spacer layer 312 located on the second stacked structure 32 is located within the second region BB. The planarization layer 38 covers the spacer layer 312 and the second stacked structure 32 located within the second region BB.

[0232] [Corrected 21.07.2023 in accordance with Rule 91] The semiconductor structure 30 also includes a contact structure 39 extending through the planar layer 38 along the stacking direction z. The contact structure 39 may include an insulating layer 391 and a conductive layer 392 located on a side of the insulating layer 391 facing away from the first stacked layer 31. The insulating layer 391 may be made of an insulating material such as silicon oxide, and the conductive layer 392 may be made of a metal such as tungsten. In addition to extending through the planar layer 38, the contact structure 39 further extends through the second stacked structure 32 along the stacking direction z and is electrically connected to peripheral circuitry.

[0233] [Corrected on 21.07.2023 according to Rule 91] Please refer to Figure 11F. The semiconductor structure 30 further includes an interconnection dielectric layer 1101 and an interconnection circuit layer 1102 located in the interconnection dielectric layer 1101. The interconnection circuit layer 1102 is connected to the second electrode layer 37.

[0234] [Corrected on 21.07.2023 according to Rule 91] As can be seen from the above, the manufacturing method of the semiconductor structure 30 provided in the embodiment of the present application forms a plurality of capacitor holes Q1 penetrating the first stacking layer 31 along the stacking direction z, the first stacking layer 31 includes a first area AA and a second area BB, and the capacitor holes Q1 are located in the first area AA and the second area BB, thereby greatly avoiding a serious etching load effect in the first area AA when forming the capacitor holes Q1, and ensuring the size consistency of the capacitor holes Q1 in the first area AA as much as possible, and preventing insufficient etching. Subsequently, a first electrode layer 33 is formed on the inner wall of the capacitor hole Q1; a portion of the first stacking layer 31 in the first area AA and the second area BB is removed; a dielectric layer 36 and a second electrode layer 37 are formed in the first area AA, the second electrode layer 37 being located on the side of the dielectric layer 36 away from the first electrode layer 33; a flat layer 38 is formed in the second area BB; and a contact structure 39 is formed penetrating the flat layer 38 along the stacking direction z, so that a capacitor structure with uniform size can be formed in the first area AA, thereby improving the reliability of the capacitor structure.

[0235] [Corrected 21.07.2023 according to Rule 91] The present application also provides a flow chart of another method for manufacturing a semiconductor structure. Please refer to FIG13 . The method for manufacturing the semiconductor structure may include the following steps S301-S307, wherein:

[0236] [Corrected 21.07.2023 according to Rule 91] Step S301. Forming a plurality of capacitor holes penetrating a first stacked layer along a stacking direction, the first stacked layer comprising a first region and a second region, the capacitor holes being located in the first region and the second region;

[0237] [Corrected 21.07.2023 according to Rule 91] Step S302. Forming a first electrode layer on the inner walls of the capacitor holes in the first region and the second region;

[0238] [Corrected 21.07.2023 according to Rule 91] Step S303. Forming a dielectric layer on one side of the first stacked layer in the first region and the second region, wherein the dielectric layer covers a side of the first electrode layer facing away from the inner wall of the capacitor hole;

[0239] [Corrected 21.07.2023 according to Rule 91] Step S304. Forming a second electrode layer on a side of the dielectric layer in the first region facing away from the first electrode layer;

[0240] [Corrected 21.07.2023 according to Rule 91] Step S305. Removing the first stacked layer, the dielectric layer and the first electrode layer in the second region;

[0241] [Corrected 21.07.2023 according to Rule 91] Step S306. Forming a flat layer in the second region;

[0242] [Corrected 21.07.2023 according to Rule 91] Step S307. Form a contact structure penetrating the planar layer along the stacking direction.

[0243] [Corrected 21.07.2023 in accordance with Rule 91] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after or between any of the steps shown.

[0244] [Corrected 21.07.2023 in accordance with Rule 91] Referring to Figures 14A to 14H , which are schematic cross-sectional views of another semiconductor structure 40 according to an embodiment of the present application at different process steps, the semiconductor structure 10 may be a cup-type capacitor structure. Steps S301-S307 will be further described below in conjunction with Figures 14A to 14H , wherein:

[0245] [Corrected 21.07.2023 according to Rule 91] Step S301. A plurality of capacitor holes Q1 are formed through the first stacking layer 41 along the stacking direction z, wherein the first stacking layer 41 includes a first area AA and a second area BB, and the capacitor holes Q1 are located in the first area AA and the second area BB.

[0246] [Corrected 21.07.2023 according to Rule 91] Please continue to refer to Figures 14A and 15A. Figure 15A is a schematic cross-sectional structural diagram along line H1-H1 in Figure 14A. The first area AA is the area corresponding to the memory array, and the second area BB is other areas. The first area AA and the second area BB can be adjacent to each other, for example, the second area BB is arranged around the first area AA. The capacitor holes Q1 can be distributed throughout the entire area of ​​the first stacked layer 41 and spaced apart internally. Preferably, these capacitor holes Q1 can be set to the same size and the same spacing.

[0247] [Corrected 21.07.2023 according to Rule 91] Specifically, the first stacked layer 41 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first stacked layer 41 may include alternating sacrificial layers 411 and spacer layers 412. The material of the sacrificial layers 411 may include silicon dioxide, and the material of the spacer layers 412 may include silicon nitride.

[0248] [Corrected 21.07.2023 in accordance with Rule 91] Capacitor holes Q1 can be formed in both the first region AA and the second region BB of the first stacked layer 41 through two orthogonal or angled patterning processes. In this case, since the pattern of the capacitor holes Q1 is relatively uniformly distributed across the entire surface of the first stacked layer 41, that is, the density difference between the etched patterns corresponding to the first region AA and the second region BB is relatively small, the difference in the etch depth and size of the capacitor holes Q1 formed in the first region AA and the second region BB is relatively small, thereby minimizing the occurrence of a severe etch loading effect. Furthermore, even if a certain etch loading effect exists, affecting the etch depth and hole size of the capacitor holes Q1 at the edges, since the second region BB is typically disposed around the first region AA, the etch loading effect generally only affects the outermost capacitor holes Q1 in the second region BB and is unlikely to affect the capacitor holes Q1 in the first region AA. Therefore, by forming the capacitor holes Q1 in both the first area AA and the second area BB, the serious etching load effect in the first area AA can be greatly avoided, and the etching depth and size of the capacitor holes Q1 in the first area AA can be kept consistent as much as possible, avoiding the phenomenon that some capacitor holes Q1 have insufficient etching depth or are too small in size.

[0249] [Corrected 21.07.2023 according to Rule 91] In some embodiments, before step S101, the production method may further include:

[0250] [Corrected 21.07.2023 according to Rule 91] forming a second stacked structure 42, the second stacked structure 42 comprising a plurality of channel structures 421 spaced apart along a first direction x and a second direction y, and a gate structure 422 extending along the second direction y and connecting the plurality of channel structures 421, the gate structure 422 being located between two adjacent channel structures 421, the first direction x, the second direction y, and the stacking direction z being perpendicular to each other;

[0251] [Corrected 21.07.2023 according to Rule 91] The first stack layer 41 is formed on the second stack structure 42.

[0252] [Corrected 21.07.2023 according to Rule 91] The position of the channel structure 421 corresponds to at least the position of the capacitor hole Q1 in the first area AA. The first direction x and the second direction y may be the extension direction of the first stacked layer 11, which are perpendicular to the stacking direction z of the first stacked layer 41. The gate structure 422 may include a gate spacer 4221 and a gate layer 4222. The material of the gate spacer 4221 may include an insulating material such as an oxide, and the material of the gate layer 4222 may be any one or a combination of tungsten, cobalt, copper, aluminum, polysilicon, and doped crystalline silicon.

[0253] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the channel structure 421 is formed on a substrate, which may include at least one of single crystal silicon (Si), single crystal germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art. Specifically, the substrate can be etched to form a plurality of active portions extending along a first direction x and spaced apart along a second direction y. Next, a gate structure 422 is formed extending along the second direction y and connecting at least the active portions corresponding to the first region AA. The gate structure 422 extends through the active portions along the stacking direction z to form the channel structure 421.

[0254] [Corrected 21.07.2023 according to Rule 91] In some embodiments, adjacent gate structures 422 along the first direction x can be further filled with an insulating material for isolation, thereby achieving electrical insulation between adjacent gate structures 422. After filling with the insulating material, the substrate outside the channel structure 421 (i.e., the bottom substrate) can be removed, and a bit line 423 can be formed, which is connected to the channel structure 421.

[0255] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the position of the channel structure 421 may correspond only to the position of the capacitor hole Q1 in the first area AA, and at the same time, the position of the gate structure 422 may correspond only to the first area AA, that is, the second stacked structure 42 may include a core area corresponding to the first area AA, and a non-core area corresponding to the second area BB, and the channel structure 421 and the gate structure 422 may be located only in the core area. In other embodiments, the position of the channel structure 421 may also correspond to the position of the capacitor hole Q1 in the second area BB, and at the same time, the position of the gate structure 422 may correspond to at least the first area AA, that is, the channel structure 421 may be located in the core area and the non-core area (for example, please continue to refer to Figure 14A), and the gate structure 422 may be located in the core area and the non-core area, or only in the core area, without limitation here.

[0256] [Corrected 21.07.2023 according to Rule 91] Step S302. Form a first electrode layer 43 on the inner wall of the capacitor hole Q1 in the first area AA and the second area BB.

[0257] [Corrected 21.07.2023 in accordance with Rule 91] With reference to Figures 14A and 14B, as well as Figure 15B, Figure 15B is a schematic cross-sectional view of the structure along line H2-H2 in Figure 14B. The material of the first electrode layer 43 includes a conductive material such as a metal or a metal compound, such as tungsten, copper, or titanium nitride (TiN). A layer of conductive material can be first formed on one side of the first stacked layer 41, and then the conductive material outside the capacitor hole Q1 can be etched away to obtain the first electrode layer 43 located within the capacitor hole Q1.

[0258] [Corrected on 21.07.2023 according to Rule 91] It should be pointed out that since the capacitor hole Q1 is arranged at intervals in the first area AA and the second area BB, the inside of the first electrode layer 43 in the first area AA and the inside of the first electrode layer 43 in the second area BB are also arranged at intervals, that is, the first electrode layer 43 in the first area AA and the first electrode layer 43 in the second area BB both include multiple isolated parts, and these parts are not connected to each other.

[0259] [Corrected 21.07.2023 according to Rule 91] Step S303. A dielectric layer 44 is formed on one side of the first stacked layer 41 in the first area AA and the second area BB, and the dielectric layer 44 covers the side of the first electrode layer 43 away from the inner wall of the capacitor hole Q1.

[0260] [Corrected 21.07.2023 in accordance with Rule 91] Please continue to refer to Figures 14B and 14C, as well as Figure 15C. Figure 15C is a schematic cross-sectional view of the structure along line H3-H3 in Figure 14C. Dielectric layer 44 is made of a material with a high dielectric constant and can be formed using a thin film deposition process. This dielectric layer 44 not only covers the first electrode layer 43 in capacitor hole Q1, but also covers the top surface of the first stacked layer 41.

[0261] [Corrected 21.07.2023 according to Rule 91] Step S304. Form a second electrode layer 45 on the side of the dielectric layer 44 facing away from the first electrode layer 43 in the first area AA.

[0262] [Corrected 21.07.2023 according to Rule 91] The second electrode layer 45 is primarily made of a conductive material, such as tungsten, cobalt, copper, aluminum, or any one or a combination of polysilicon and doped crystalline silicon. The second electrode layer 45 is located only in the first area AA.

[0263] [Corrected 21.07.2023 according to Rule 91] In some embodiments, to ensure that the second electrode layer 45 is formed only in the first area AA, the capacitor hole Q1 in the second area BB needs to be filled before forming the second electrode layer 45. Please continue to refer to Figures 14C to 14F and Figures 15D to 15F. Figure 15D is a schematic cross-sectional view of the structure along line H4-H4 in Figure 14D, Figure 15E is a schematic cross-sectional view of the structure along line H5-H5 in Figure 14E, and Figure 15F is a schematic cross-sectional view of the structure along line H6-H6 in Figure 14F. Before the above step S304, the manufacturing method further includes:

[0264] [Corrected 21.07.2023 according to Rule 91] A filling layer 46 is formed in the capacitor hole Q1 in the first area AA and the second area BB, and the filling layer 46 covers a side of the dielectric layer 44 facing away from the first electrode layer 43;

[0265] [Corrected 21.07.2023 according to Rule 91] The filling layer 46 in the first area AA is removed, and the dielectric layer 44 in the first area AA is exposed.

[0266] [Corrected 21.07.2023 according to Rule 91] The material of the filling layer 46 may include an oxide, such as silicon dioxide. A filling layer 46 may be first formed on one side of the first stacked layer 41 by a thin film deposition process. At this time, the filling layer 46 will fill the capacitor hole Q1. Then, the filling layer 46 outside the capacitor hole Q1 in the first area AA and the second area BB is removed, and only the filling layer 46 inside the capacitor hole Q1 is retained. Then, the second area BB is covered by a mask, and the filling layer 46 in the first area AA is removed. At this time, the dielectric layer 44 in the capacitor hole Q1 in the first area AA will be exposed again. At this time, the above-mentioned step S304 specifically includes: forming a second electrode layer 45 on the side of the dielectric layer 44 exposed in the first area away from the first electrode layer 43.

[0267] [Corrected 21.07.2023 according to Rule 91] In some embodiments, after forming the second electrode layer 45, gaps may still exist in the capacitor hole Q1 and need to be filled. That is, referring to FIG. 14E and FIG. 14F, the manufacturing method further includes:

[0268] [Corrected 21.07.2023 according to Rule 91] A semiconductor layer 47 is formed on a side of the second electrode layer 45 in the first area AA facing away from the dielectric layer 44, and the semiconductor layer 47 fills the capacitor hole Q1 in the first area AA.

[0269] [Corrected 21.07.2023 according to Rule 91] The material of semiconductor layer 47 includes a semiconductor material such as polysilicon and / or silicide (e.g., SiGe). Semiconductor layer 47 is located on top of the first stacked layer 41 in the first area AA (on the second electrode layer 45 on top) and within capacitor hole Q1 in the first area AA (on the second electrode layer 45 in capacitor hole Q1).

[0270] [Corrected 21.07.2023 according to Rule 91] Step S305. Remove the first stacked layer 41, the dielectric layer 44 and the first electrode layer 43 in the second region BB.

[0271] [Corrected on 21.07.2023 according to Rule 91] Please continue to refer to Figures 14F and 14G, as well as Figure 15G. Figure 15G is a schematic diagram of the cross-sectional structure along the H7-H7 line in Figure 14G. The various film layers in the second area BB can be removed by dry etching. In addition to removing the above-mentioned first stacking layer 41, the dielectric layer 44 and the first electrode layer 43, the manufacturing method also includes: removing the filling layer 46 in the second area BB.

[0272] [Corrected 21.07.2023 according to Rule 91] Step S306. Form a flat layer 48 in the second area BB.

[0273] [Corrected 21 July 2023 in accordance with Rule 91] Please continue to refer to Figures 14G and 14H, as well as Figure 15H. Figure 15H is a schematic cross-sectional view of the structure along line H8-H8 in Figure 14H. The material of planarization layer 48 may include an oxide, such as silicon dioxide. Planarization layer 48 may be processed by CMP (Chemical Mechanical Polishing) to make the top surface of planarization layer 48 substantially flush with the top surface of second electrode layer 45 in first area AA.

[0274] [Corrected 21.07.2023 according to Rule 91] Step S307. Form a contact structure 49 penetrating the planar layer 48 along the stacking direction z.

[0275] [Corrected 21.07.2023 according to Rule 91] In which, please continue to refer to Figures 14H and 15H. The contact structure 49 can be located at any position in the second area BB. The specific number of contact structures 49 and their formation positions in the second area BB can be determined according to actual needs and are not limited here. The contact structure 49 may include an insulating layer 491 and a conductive layer 492 located on the side of the insulating layer 491 away from the first stacked layer 41. The material of the insulating layer 491 includes an insulating material such as silicon oxide, and the material of the conductive layer 492 includes a metal material such as tungsten. In addition to penetrating the flat layer 48, the contact structure 49 will further penetrate the second stacked structure 42 along the stacking direction z and be electrically connected to the peripheral circuit.

[0276] [Corrected 21.07.2023 according to Rule 91] The embodiment of the present application also provides a semiconductor structure 40, please continue to refer to the above-mentioned Figures 14H, 15H and 15I.

[0277] [Corrected 21.07.2023 according to Rule 91] The semiconductor structure 40 includes a second stacked structure 42, a first stacked layer 41, and a capacitor structure. The capacitor structure is located within the first stacked layer 41. The first stacked layer 41 is located on the second stacked structure 42 and includes a first area AA and a second area BB. The second stacked structure 42 includes a plurality of channel structures 421 spaced apart along a first direction x and a second direction y, and a gate structure 422 extending along the second direction y and connecting the plurality of channel structures 421. The gate structure 422 is located between two adjacent channel structures 421. The first area AA of the first stacked layer 41 has capacitor holes Q1 spaced apart, and the position of the channel structure 421 corresponds to at least the position of the capacitor hole Q1 in the first area AA. The gate structure 422 may include a gate spacer 4221 and a gate layer 4222. The gate spacer 4221 is located between the gate layer 4222 and the channel structure 421. Adjacent gate structures 422 are isolated and electrically insulated by insulating material. The second stack structure 42 further includes a bit line 423 . The bit line 423 is located on a side of the second stack structure 42 away from the first stack layer 41 and is connected to the channel structure 421 .

[0278] [Corrected 21.07.2023 according to Rule 91] The first stacked layer 41 includes alternating sacrificial layers 411 and spacer layers 412. One spacer layer 412 is located at an end of the second stacked structure 42 away from the bit line 423. The capacitor hole Q1 extends through the sacrificial layers 411 and the spacer layers 412. The sacrificial layers 411 may be made of silicon dioxide, and the spacer layers 412 may be made of silicon nitride.

[0279] [Corrected 21.07.2023 in accordance with Rule 91] The capacitor structure also includes a first electrode layer 43, a dielectric layer 44, a second electrode layer 45, and a semiconductor layer 47. The first electrode layer 43 is located on the inner wall of the capacitor hole Q1 in the first area AA. The first electrode layer 43, sacrificial layer 411, and spacer layer 412 in the first area AA each include multiple isolated portions that are not connected to each other. The dielectric layer 44 is located on one side of the first stacked layer 41 in the first area AA and covers the side of the first electrode layer 43 facing away from the inner wall of the capacitor hole Q1. The second electrode layer 45 is located on the side of the dielectric layer 44 in the first area AA facing away from the first electrode layer 43. The semiconductor layer 47 is located on the side of the second electrode layer 45 in the first area AA facing away from the dielectric layer 44 and fills the capacitor hole Q1 in the first area AA. In other words, the first electrode layer 43 is disposed around the dielectric layer 44, the dielectric layer 14 is disposed around the second electrode layer 16, and the second electrode layer 16 is disposed around the semiconductor layer 17. The semiconductor layer 17 is connected to the second electrode 45, and is used to fill the capacitor hole Q1 and serve as an output electrode of the capacitor structure. Since the first electrode layer 43 is arranged at intervals, a plurality of capacitor structures with uniform size and arranged at intervals are formed in the first area AA.

[0280] [Corrected 21.07.2023 according to Rule 91] The semiconductor structure 40 further includes a planar layer 48 located in the second region BB. The planar layer 48 is arranged adjacent to the first stacked layer 41 in the first region AA and is located on a side of the second stacked structure 42 away from the bit line 423.

[0281] [Corrected 21.07.2023 in accordance with Rule 91] The semiconductor structure 40 further includes a contact structure 49 extending through the planar layer 48 along the stacking direction z. The contact structure 49 may include an insulating layer 491 and a conductive layer 492 located on a side of the insulating layer 491 facing away from the first stacked layer 41. The insulating layer 491 may be made of an insulating material such as silicon oxide, and the conductive layer 492 may be made of a metal such as tungsten. In addition to extending through the planar layer 48, the contact structure 49 further extends through the second stacked structure 42 along the stacking direction z and is electrically connected to peripheral circuitry.

[0282] [Corrected on 21.07.2023 according to Rule 91] The semiconductor structure 40 further includes an interconnection dielectric layer 1101 and an interconnection circuit layer 1102 located within the interconnection dielectric layer 1101 , wherein the interconnection circuit layer 1102 is connected to the semiconductor layer 47 .

[0283] [Corrected 21.07.2023 according to Rule 91] As can be seen from the above, the method for manufacturing the semiconductor structure 40 provided in the embodiment of the present application forms a plurality of capacitor holes Q1 penetrating the first stacking layer 41 along the stacking direction z, the first stacking layer 41 includes a first area AA and a second area BB, and the capacitor holes Q1 are located in the first area AA and the second area BB, thereby greatly avoiding a serious etching load effect in the first area AA when forming the capacitor holes Q1, ensuring the size consistency of the capacitor holes Q1 in the first area AA as much as possible, and preventing insufficient etching. Subsequently, by forming the first capacitor hole Q1 on the inner wall of the capacitor hole Q1, the capacitor hole Q1 is formed. a dielectric layer 44 is formed on one side of the first stacked layer 41 in the first area AA and the second area BB, and the dielectric layer 44 covers the side of the first electrode layer 43 away from the inner wall of the capacitor hole Q1; a second electrode layer 45 is formed on the side of the dielectric layer 44 in the first area AA away from the first electrode layer 43; the first stacked layer 41, the dielectric layer 44 and the first electrode layer 43 in the second area BB are removed; a flat layer 48 is formed in the second area BB; a contact structure 49 is formed that passes through the flat layer 48 along the stacking direction z, so that a capacitor structure with uniform size can be formed in the first area AA, thereby improving the reliability of the capacitor structure.

[0284] [Corrected 21.07.2023 according to Rule 91] Please refer to Figures 7F, 11F, and 14I. Figure 7F is a schematic diagram of the structure of an exemplary memory 110 provided in an embodiment of the present application. Figure 11F is a schematic diagram of the structure of an exemplary memory 110 provided in an embodiment of the present application. Figure 14I is a schematic diagram of the structure of an exemplary memory 130 provided in an embodiment of the present application.

[0285] [Corrected 21.07.2023 in accordance with Rule 91] Memory 110 / 120 / 130 includes the semiconductor structure 10 / 30 / 40 described above and a peripheral circuit structure 113. Peripheral circuit structure 113 is located on a side of the interconnect dielectric layer 1101 of the semiconductor structure 10 / 30 / 40 facing away from the first stacked layer 11 and is bonded to the semiconductor structure 10 / 30 / 40. Specifically, the semiconductor structure 10 / 30 / 40 is connected to the interconnect circuit layer 1102 of the semiconductor structure 10 / 30 / 40.

[0286] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the peripheral circuit structure 113 may further include a word line driver, a bit line driver, a column decoder, a sensing circuit, a data buffer, a program verification logic and an erase verification circuit, etc., which may perform the above operations according to the obtained computer program instructions.

[0287] [Corrected 21.07.2023 according to Rule 91] It should be pointed out that the peripheral circuit structure 113 and the semiconductor structure 201 can be stacked or tiled, and there is no restriction here.

[0288] [Corrected 21.07.2023 according to Rule 91] In addition, see Figure 16, which is a structural diagram of an exemplary system 100 provided in an embodiment of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein. As shown in Figure 16, system 100 may include a host 101 and a memory system 102, and memory system 102 includes one or more memories 110 / 120 / 130 and a controller 1022. Host 101 can be a processor (e.g., a central processing unit (CPU)) or an on-chip memory system (System on Chip, SOC) (e.g., an application processor (AP)) of an electronic device. The host 101 may be configured to transmit data to or receive data from the memory 110 / 120 / 130 .

[0289] [Corrected on 21.07.2023 according to Rule 91] In the examples of the present application, the memory 110 / 120 / 130 is not limited to three-dimensional DRAM memory. Without violating the disclosure or teachings of the present application, the memory 110 / 120 / 130 may also be other types of volatile memories such as a dependent data memory that serves as a temporary storage medium for an operating system or other running programs (which may be referred to as system memory).

[0290] [Corrected 21.07.2023 according to Rule 91] In some embodiments, the controller 1022 is coupled to the memory 110 / 120 / 130 and the host 101 and is configured to control the memory 110 / 120 / 130, such as controlling the memory 110 / 120 / 130 to perform data write and read operations. The controller 1022 can manage data stored in the memory 110 / 120 / 130 and communicate with the host 101.

[0291] [Corrected 21.07.2023 according to Rule 91] The controller 1022 may be configured to control operations of the memory 110 / 120 / 130, such as read, erase, and program operations. The controller 1022 may also be configured to manage various functions regarding data stored or to be stored in the memory 110 / 120 / 130, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.

[0292] [Corrected 21.07.2023 according to Rule 91] The controller 1022 and one or more memories 110 / 120 / 130 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of electronic products.

[0293] [Corrected on 21.07.2023 according to Rule 91] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of capacitor holes penetrating through a first stacking layer along a stacking direction, wherein the first stacking layer includes a first region and a second region, and the capacitor holes are located in the first region and the second region; forming a first electrode layer on the inner wall of the capacitor hole; forming a dielectric layer in the first region and the second region; forming a second electrode layer on a side of the dielectric layer facing away from the first stacked layer; removing the second electrode layer on the first stacked layer in the second region; A contact structure is formed that penetrates the first stacking layer in the second region along the stacking direction.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The first stacked layer includes a sacrificial layer, and the manufacturing method further includes: Forming a filling layer on a side of the first electrode layer away from the inner wall of the capacitor hole, and the filling layer fills the capacitor hole; A plurality of spacing holes penetrating a portion of the first stacking layer are formed along the stacking direction, and the sacrificial layer is removed to form a first empty groove, wherein the spacing holes are located in the first region and the second region.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The forming of a dielectric layer in the first region and the second region comprises: Forming a dielectric layer on one side of the first stacked layer in the first region and the second region, wherein the dielectric layer covers the inner wall of the first empty groove and the inner wall of the spacing hole; Wherein, the second electrode layer is located in the first empty groove and the spacing hole.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The forming of a plurality of spacing holes penetrating a portion of the first stacking layer along the stacking direction and removing the sacrificial layer to form a first empty groove further includes: Removing the filling layer to form a second empty slot; Wherein, the dielectric layer and the second electrode layer are also located in the second empty groove.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of a dielectric layer in the first region and the second region comprises: Forming a dielectric layer on one side of the first stacked layer in the first region and the second region, and the dielectric layer covers a side of the first electrode layer away from the inner wall of the capacitor hole; Wherein, the second electrode layer is located in the capacitor hole.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The production method further comprises: forming a semiconductor layer on a side of the second electrode layer in the first region and the second region facing away from the dielectric layer, and the semiconductor layer fills the capacitor hole; The removing of the second electrode layer on the first stacked layer in the second region further includes: removing the semiconductor layer on the first stacked layer in the second region.

7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that: Also includes: forming a second stacking structure, wherein the second stacking structure comprises a plurality of channel structures spaced apart along a first direction and a second direction, and a gate structure extending along the second direction and connecting the plurality of channel structures, wherein the gate structure is located between two adjacent channel structures, and the first direction, the second direction and the stacking direction are perpendicular to each other; forming the first stacking layer on the second stacking structure; The position of the channel structure at least corresponds to the position of the capacitor hole in the first region.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The position of the channel structure also corresponds to the position of the capacitor hole in the second region, and the position of the gate structure at least corresponds to the first region.

9. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of capacitor holes penetrating through a first stacking layer along a stacking direction, wherein the first stacking layer includes a first region and a second region, and the capacitor holes are located in the first region and the second region; forming a first electrode layer on the inner wall of the capacitor hole in the first region; removing a portion of the first stacked layer in the first region and the second region; forming a dielectric layer and a second electrode layer in the first region, wherein the second electrode layer is located on a side of the dielectric layer away from the first electrode layer; forming a planar layer in the second region; A contact structure is formed that penetrates the planar layer along the stacking direction.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: The forming of a dielectric layer and a second electrode layer in the first region comprises: forming a dielectric layer on one side of the first stacked layer in the first region and the second region; forming a second electrode layer on a side of the dielectric layer facing away from the first stacked layer; The dielectric layer and the second electrode layer in the second region are removed.

11. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: Before forming a first electrode layer on the inner wall of the capacitor hole in the first region, the method further includes: forming a sacrificial structure in the capacitor holes in the first region and the second region; removing the sacrificial structure in the first region and exposing the capacitor hole in the first region; The forming of the first electrode layer on the inner wall of the capacitor hole in the first region includes: forming the first electrode layer on the exposed inner wall of the capacitor hole.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The first stacked layer includes a sacrificial layer, and removing a portion of the first stacked layer in the first region and the second region includes: forming a plurality of spacing holes penetrating a portion of the first stacked layer in the first region along the stacking direction, and removing the sacrificial layer to form a first empty groove; removing the sacrificial structure in the second region; The dielectric layer and the second electrode layer fill the spacing holes and the first empty grooves.

13. The method for manufacturing a semiconductor structure according to claim 9, characterized in that: Also includes: A filling layer is formed on one side of the first stacked layer in the first region and the second region, and the filling layer covers a side of the first electrode layer in the first region away from the inner wall of the capacitor hole and fills the capacitor hole in the first region.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that: The removing of part of the first stacked layer in the first region and the second region further includes: Removing the filling layer in the capacitor hole in the first region to form a second empty slot; The dielectric layer and the second electrode layer also fill the second empty groove.

15. The method for manufacturing a semiconductor structure according to any one of claims 9 to 14, characterized in that: Also includes: A second stacking structure is formed, wherein the second stacking structure includes a plurality of channel structures spaced apart along a first direction and a second direction, and a gate structure extending along the second direction and connecting the plurality of channel structures, wherein the gate structure is located between two adjacent channel structures. Between the channel structures, the first direction, the second direction and the stacking direction are perpendicular to each other; forming the first stacking layer on the second stacking structure; The position of the channel structure at least corresponds to the position of the capacitor hole in the first region.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The position of the channel structure also corresponds to the position of the capacitor hole in the second region, and the position of the gate structure at least corresponds to the first region.

17. A method for manufacturing a semiconductor structure, characterized in that: include: forming a plurality of capacitor holes penetrating through a first stacking layer along a stacking direction, wherein the first stacking layer includes a first region and a second region, and the capacitor holes are located in the first region and the second region; forming a first electrode layer on the inner wall of the capacitor hole in the first area and the second area; Forming a dielectric layer on one side of the first stacked layer in the first region and the second region, and the dielectric layer covers a side of the first electrode layer away from the inner wall of the capacitor hole; forming a second electrode layer on a side of the dielectric layer in the first region facing away from the first electrode layer; removing the first stacked layer, the dielectric layer and the first electrode layer in the second region; forming a planar layer in the second region; A contact structure is formed that penetrates the planar layer along the stacking direction.

18. The method for manufacturing a semiconductor structure according to claim 17, characterized in that: Also includes: forming a filling layer in the capacitor holes in the first region and the second region, wherein the filling layer covers a side of the dielectric layer away from the first electrode layer; removing the filling layer in the first region and exposing the dielectric layer in the first region; The forming of the second electrode layer on a side of the dielectric layer in the first region facing away from the first electrode layer comprises: forming the second electrode layer on a side of the dielectric layer exposed in the first region facing away from the first electrode layer.

19. The method for manufacturing a semiconductor structure according to claim 18, characterized in that: The removing of the first stacked layer, the dielectric layer and the first electrode layer in the second region further includes: The filling layer in the second region is removed.

20. The method for manufacturing a semiconductor structure according to claim 18, characterized in that: Also includes: A semiconductor layer is formed on a side of the second electrode layer in the first region facing away from the dielectric layer, and the semiconductor layer fills the capacitor hole in the first region.

21. The method for manufacturing a semiconductor structure according to any one of claims 17 to 20, characterized in that: Also includes: forming a second stacking structure, wherein the second stacking structure comprises a plurality of channel structures spaced apart along a first direction and a second direction, and a gate structure extending along the second direction and connecting the plurality of channel structures, wherein the gate structure is located between two adjacent channel structures, and the first direction, the second direction and the stacking direction are perpendicular to each other; forming the first stacking layer on the second stacking structure; The position of the channel structure at least corresponds to the position of the capacitor hole in the first region.

22. The method for manufacturing a semiconductor structure according to claim 21, characterized in that: The position of the channel structure also corresponds to the position of the capacitor hole in the second region, and the position of the gate structure at least corresponds to the first region.

23. A semiconductor structure, characterized in that: include: a first stacking structure, the first stacking structure comprising a first region and a second region; a first electrode layer located in the first region and the second region, wherein the first electrode layer penetrates the first stacking structure along a stacking direction, and the first electrode layer in the first region and the first electrode layer in the second region are arranged at intervals; a dielectric layer located in the first region and the second region; a second electrode layer located in the first region and the second region, wherein the dielectric layer is disposed between the first electrode layer and the second electrode layer, and the second electrode layer in the first region and the second electrode layer in the second region are spaced apart; A contact structure is provided, wherein the contact structure penetrates the first stacking structure in the second region along the stacking direction.

24. The semiconductor structure according to claim 23, characterized in that The first electrode layers in the first region and the second region are spaced apart along a first direction and a second direction, and the first direction, the second direction and the stacking direction are perpendicular to each other.

25. The semiconductor structure according to claim 23, characterized in that The dielectric layer is located on one side of the first stacked structure and penetrates a portion of the first stacked structure in the first region and the second region along the stacking direction; The second electrode layer is located on the first stacked structure in the first region, and covers a side of the dielectric layer in the first stacked structure that is away from the first electrode layer.

26. The semiconductor structure according to claim 25, characterized in that The dielectric layer in the first stacked structure covers a side of the first electrode layer in the first region and the second region facing away from the first stacked structure.

27. The semiconductor structure according to claim 26, characterized in that The semiconductor structure further includes a semiconductor layer, which is located on the first stacked structure in the first region and covers a side of the second electrode layer in the first stacked structure in the first region and the second region that is away from the dielectric layer.

28. The semiconductor structure according to claim 25, characterized in that The dielectric layer in the first stacked structure is at least located between two adjacent first electrode layers that are spaced apart from each other.

29. The semiconductor structure according to claim 28, characterized in that The semiconductor structure further includes a filling layer located in the first stacked structure in the first region and the second region. The filling layer is arranged at intervals inside, and the first electrode layer is arranged around the filling layer.

30. The semiconductor structure according to claim 28, characterized in that The dielectric layer in the first stacked structure also covers a side of the first electrode layer facing away from the first stacked structure.

31. The semiconductor structure according to claim 25, characterized in that The first stacking structure includes a plurality of stacked spacer layers, and the dielectric layer and the second electrode layer are also located between two adjacent spacer layers in the first region and the second region along the stacking direction.

32. The semiconductor structure according to any one of claims 24 to 31, characterized in that: The semiconductor structure further includes a second stacked structure, which is located on a side of the first stacked structure away from the second electrode layer and includes a plurality of channel structures spaced apart along the first direction and the second direction, and a gate structure extending along the second direction and connecting the plurality of channel structures, wherein the gate structure is located between two adjacent channel structures; The position of the channel structure at least corresponds to the position of the first electrode layer in the first region, and the contact structure penetrates the first stacking structure and the second stacking structure along the stacking direction.

33. The semiconductor structure according to claim 32, characterized in that The position of the channel structure also corresponds to the position of the first electrode layer in the second region, and the position of the gate structure at least corresponds to the first region.

34. A memory, characterized in that: It comprises a semiconductor structure and a peripheral circuit structure as described in any one of claims 23 to 33, wherein the peripheral circuit structure and the semiconductor structure are electrically connected.

35. A memory system, characterized in that: The device comprises at least one memory as claimed in claim 34, and a controller coupled to the memory, wherein the controller is used to control the memory to store data.

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