Method for manufacturing an electrically conductive structure, electrically conductive structure and microelectromechanical system

Abstract

The application provides a conductive structure preparation method, a conductive structure and a micro-electro-mechanical system, and relates to the technical field of semiconductors. Different pre-configured sputtering powers are used to sputter at least two crystalline metal layers on the side of an amorphous adhesive layer away from a base layer, so that the grain size of the crystalline metal layer closest to the amorphous adhesive layer is less than a set first size threshold, and the grain size of the crystalline metal layer farthest from the amorphous adhesive layer is greater than a set second size threshold; on the side of the crystalline metal layer farthest from the amorphous adhesive layer away from the base layer, an array of arranged metal wires is formed, the grain size of the metal wires from the side close to the crystalline metal layer to the side away from the crystalline metal layer is increasingly greater, and the grain size of the side of the metal wires close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesive layer, so that the metal wires are not prone to falling off from the base layer, and the reliability is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a conductive structure preparation method, a conductive structure and a micro-electro-mechanical system. BACKGROUND

[0002] Micro-electro-mechanical system (MEMS) is a kind of micro device combining electrical performance and mechanical performance, which has the advantages of small size, low power consumption, good performance and good compatibility with IC manufacturing process. Metal can be used to prepare conductive structure in micro-electro-mechanical system due to its good electrical conductivity and chemical stability.

[0003] Generally, the conductive structure includes a substrate layer, a crystalline metal layer arranged on one side of an amorphous adhesion layer, and an array of metal wires arranged on one side of the crystalline metal layer. The metal wires of the current conductive structure are prone to fall off from the substrate layer and the amorphous adhesion layer, causing damage to the micro-electro-mechanical system and affecting the use of the micro-electro-mechanical system. SUMMARY

[0004] The present application provides a conductive structure preparation method, a conductive structure and a micro-electro-mechanical system, which are used to solve the problem that the metal wires are prone to fall off from the substrate layer and the amorphous adhesion layer in the prior art, causing damage to the micro-electro-mechanical system.

[0005] In a first aspect, the present application provides a conductive structure preparation method, comprising:

[0006] Sputtering an amorphous adhesion layer on one side of a substrate layer;

[0007] Sputtering at least two layers of crystalline metal layers in sequence on the side of the amorphous adhesion layer away from the substrate layer with different pre-configured sputtering powers, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is less than a set first size threshold, the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is greater than a set second size threshold, and the second size threshold is greater than the first size threshold, wherein each sputtering power is used to sputter one layer of crystalline metal layer;

[0008] Forming an array of metal wires on the side of the crystalline metal layer farthest from the amorphous adhesion layer away from the substrate layer, wherein the grain size of the metal wires from the side close to the crystalline metal layer to the side away from the crystalline metal layer becomes larger and larger, and the grain size of the side of the metal wires close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer;

[0009] Removing the part of the amorphous adhesion layer and the at least two layers of crystalline metal layers on the substrate layer whose orthographic projection does not overlap with the orthographic projection of the metal wires on the substrate layer.

[0010] In a possible implementation, the sputtering power of the amorphous adhesion layer ranges from 500 W to 40 kW, and the sputtering power of each of the sputtering of the crystalline metal layer ranges from 100 W to 10 kW.

[0011] In a possible implementation, the crystalline metal layer includes two layers,

[0012] The sputtering power of the amorphous adhesion layer is 25 kW, the power of the first sputtering of the crystalline metal layer is 2 kW, and the power of the second sputtering of the crystalline metal layer is 1 kW;

[0013] Alternatively, the sputtering power of the amorphous adhesion layer is 1 kW, the power of the first sputtering of the crystalline metal layer is 10 kW, and the power of the second sputtering of the crystalline metal layer is 100 W;

[0014] Alternatively, the sputtering power of the amorphous adhesion layer is 40 kW, the power of the first sputtering of the crystalline metal layer is 100 W, and the power of the second sputtering of the crystalline metal layer is 10 kW;

[0015] Alternatively, the sputtering power of the amorphous adhesion layer is 20 kW, the power of the first sputtering of the crystalline metal layer is 5 kW, and the power of the second sputtering of the crystalline metal layer is 500 W.

[0016] In a possible implementation, the second size threshold is set to range from 25 nm to 50 nm.

[0017] In a possible implementation, when sputtering the amorphous adhesion layer and the at least two layers of the crystalline metal layer, the pressure of the sputtering reactor ranges from 5x10 -9 mTorr to 5x10 -5 mTorr.

[0018] In a possible implementation, the thickness of the amorphous adhesion layer ranges from 2 nm to 50 nm, and the total thickness of the at least two layers of the crystalline metal layer ranges from 50 nm to 500 nm.

[0019] In a possible implementation, the part of the amorphous adhesion layer and the at least two layers of the crystalline metal layer, whose orthographic projection on the substrate layer does not overlap with the orthographic projection of the metal wire on the substrate layer, is removed, including:

[0020] The part of the amorphous adhesion layer and the at least two layers of the crystalline metal layer, whose orthographic projection on the substrate layer does not overlap with the orthographic projection of the metal wire on the substrate layer, is removed by ion beam etching.

[0021] In a possible implementation, the arrayed metal wires are formed on the side of the crystalline metal layer farthest from the substrate layer, including:

[0022] forming an array of spaced photoresist on the side of the farthest crystalline metal layer from the amorphous adhesion layer to form a plating pattern;

[0023] electroplating a metal wire in the exposed area between each adjacent two photoresists;

[0024] removing the array of spaced photoresists by a brushing machine to form an array of spaced metal wires.

[0025] In a second aspect, the present application provides a conductive structure prepared by the method for preparing a conductive structure.

[0026] In a third aspect, the present application further provides a micro-electro-mechanical system comprising a plurality of conductive elements, each of the conductive elements being electrically connected by the conductive structure provided in the second aspect.

[0027] The present application provides a method for preparing a conductive structure, a conductive structure and a micro-electro-mechanical system. Different sputtering powers are pre-configured to sputter at least two crystalline metal layers on the side of the amorphous adhesion layer away from the substrate layer, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is less than a first size threshold. In this way, the crystalline metal layer closest to the amorphous adhesion layer has better adhesion with the amorphous adhesion layer, and the metal wire subsequently grown on the at least two crystalline metal layers is less likely to fall off the amorphous adhesion layer.

[0028] In addition, an array of spaced metal wires is formed on the side of the crystalline metal layer farthest from the amorphous adhesion layer away from the substrate layer. Since the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is greater than a second size threshold, the grain size of the side of the metal wire close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer, and the grain size of the metal wire from the side close to the crystalline metal layer to the side away from the crystalline metal layer becomes larger and larger. In this way, the grain size of the at least two crystalline metal layers is large overall. According to the Hall-Petch law, the greater the grain size, the lower the hardness. According to the principle that the greater the grain size, the lower the hardness, the metal wire has low hardness overall. When the metal wire is formed, the impact force on the at least two crystalline metal layers, the amorphous adhesion layer and the substrate layer is small, so the adhesion between the substrate layer and the amorphous adhesion layer is not easily damaged, and the metal wire is less likely to fall off the substrate layer, thereby improving the product quality and service life of the micro-electro-mechanical system. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0030] Figure 1 The step flow chart of the conductive structure preparation method provided by the embodiments of the present application is shown in the figure.

[0031] Figure 2 The process flow chart of the conductive structure preparation method provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0032] In the following, the embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, the description of the known structures and technologies is omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0033] In the drawings, various structural schematic diagrams according to the embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which some details are enlarged for the purpose of clear expression, and some details can be omitted. The shapes of various regions, layers shown in the figures and their relative size, positional relationship are only exemplary, and in actuality, there can be deviations due to manufacturing tolerances or technical limitations, and the skilled in the art can additionally design regions / layers with different shapes, sizes, relative positions according to actual needs.

[0034] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or there can be an intermediate layer / element between them. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0035] In the following, the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail with specific embodiments. The following specific embodiments can be combined with each other, and for the same or similar concepts or processes, some embodiments can not be described again. In the following, the embodiments of the present application will be described with reference to the drawings.

[0036] Please refer to Figure 1 and Figure 2 The embodiments of the present application provide a conductive structure preparation method, comprising:

[0037] S101: sputtering an amorphous adhesion layer 202 on one side of a substrate layer 201.

[0038] The process of S101 is shown in (a)-(b) of FIG. 1. Figure 2 The sputtering method can be, but is not limited to, magnetron sputtering. The material of the substrate layer 201 can be, but is not limited to, a single crystal Si wafer or a SiO2 wafer. The material of the amorphous adhesion layer 202 can include Ti or Cr.

[0039] S102: sequentially sputtering at least two crystalline metal layers 203 on the side of the amorphous adhesion layer 202 away from the substrate layer 201 with different pre-configured sputtering powers, so that the grain size of the crystalline metal layer 203 closest to the amorphous adhesion layer 202 is less than a set first size threshold, and the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 is greater than a set second size threshold.

[0040] The second size threshold is greater than the first size threshold, and each sputtering power is used to sputter a crystalline metal layer 203.

[0041] The process of S101 is shown in (b)-(c) of FIG. 1. Figure 2 The material of the crystalline metal layer 203 can be, but is not limited to, metal Au. The crystalline metal layer 203 can be 2, 3, or 4 layers (2 layers in this embodiment). Figure 2

[0042] Further, the sputtering power of the amorphous adhesion layer 202 ranges from 500 W to 40 kW. For example, the sputtering power of the amorphous adhesion layer 202 can be, but is not limited to, 25 kW, 1 kW, 20 kW, or 40 kW. The sputtering power for sputtering the crystalline metal layer 203 ranges from 100 W to 10 kW, and the sputtering power for sputtering the crystalline metal layer 203 can be, but is not limited to, 100 W, 500 W, 1 kW, 2 kW, 5 kW, or 10 kW. When the sputtering power for sputtering the crystalline metal layer 203 ranges from 100 W to 10 kW, different sputtering powers can be selected between 100 W and 10 kW, so that the grain size of the crystalline metal layer 203 closest to the amorphous adhesion layer 202 is less than the set first size threshold, and the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 is greater than the set second size threshold. The set second size threshold can range from 25 nm to 50 nm, for example, the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 can be, but is not limited to, 25 nm, 37.9 nm, 41.8 nm, 45.9 nm, and 39.3 nm.

[0043] ​It should be noted that the sputtering method for sputtering the at least two crystalline metal layers 203 can also be a magnetron sputtering method; the combination of the amorphous adhesion layer 202 and the at least two crystalline metal layers 203 can be referred to as a metal seed layer.

[0044] In addition, when sputtering the amorphous adhesion layer 202 and the at least two crystalline metal layers 203, the pressure range of the sputtering reactor is 5x10 -9 mTorr~5x10 -5 mTorr, for example, the pressure of the sputtering reactor can be 2x10 6 mTorr, 5x10 - 5 mTorr, or 5x10 -9 mTorr.

[0045] In addition, the thickness of the amorphous adhesion layer 202 ranges from 2nm to 50nm, for example, the thickness of the amorphous adhesion layer 202 is 2nm, 10nm or 50nm; the total thickness of the at least two crystalline metal layers 203 ranges from 50nm to 500nm. For example, the total thickness of the at least two crystalline metal layers 203 ranges from 50nm, 200nm or 500nm, which is not limited herein. It can be understood that the thickness of the amorphous adhesion layer 202 and the thickness of the at least two crystalline metal layers 203 can be controlled by respectively controlling the sputtering time of the amorphous adhesion layer 202 and the at least two crystalline metal layers 203, the longer the sputtering time, the greater the thickness of the amorphous adhesion layer 202 and the thickness of the at least two crystalline metal layers 203.

[0046] S103: Forming an array of metal wires 205 on the side of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 and away from the substrate layer 201.

[0047] Wherein, the grain size of the metal wire 205 from the side close to the crystalline metal layer 203 to the side away from the crystalline metal layer 203 becomes larger and larger, and the grain size of the side of the metal wire 205 close to the crystalline metal layer 203 is equal to the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202.

[0048] It can be understood that, since the grain size of the metal wire 205 from the side close to the crystalline metal layer 203 to the side away from the crystalline metal layer 203 becomes larger and larger, the grain size of the side of the metal wire 205 away from the crystalline metal layer 203 is larger. For example, the grain size of the side of the metal wire 205 away from the crystalline metal layer 203 can be, but is not limited to, 56.9nm, 63.1nm, 67.1nm, or 75.7nm, etc.

[0049] Exemplarily, S103 can be specifically implemented as:

[0050] Step 1: Forming an array of spaced photoresist 204 on the side of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 and away from the substrate layer 201 to form a plating pattern.

[0051] In step 1, the process is as shown in (c)-(d) of FIG. 1. Figure 2

[0052] Step 2: Electroplating a metal wire 205 in the exposed area between each adjacent two photoresist 204.

[0053] In step 2, the process is as shown in (d)-(e) of FIG. 1. Figure 2

[0054] Specifically, direct current plating can be used to electroplate a metal wire 205 in the exposed area between each adjacent two photoresist 204.

[0055] S104: Removing the part of the amorphous adhesion layer 202 and the at least two layers of crystalline metal layer 203 whose orthographic projection on the substrate layer 201 does not overlap with the orthographic projection of the metal wire 205 on the substrate layer 201.

[0056] Specifically, ion beam etching can be used to remove the part of the amorphous adhesion layer 202 and the at least two layers of crystalline metal layer 203 whose orthographic projection on the substrate layer 201 does not overlap with the orthographic projection of the metal wire 205 on the substrate layer 201.

[0057] In step 3-S104, the process is as shown in (e)-(f) of FIG. 1. Figure 2

[0058] According to the inventor's experiments, the grain size of the second layer of crystalline metal layer 203 of the conductive structure obtained by the process flow of the prior art is 24.1 nm; the grain size of the metal wire 205 is 46.6 nm, and the scratch depth of the metal wire 205 is 4793 nm.

[0059] The following four specific examples are used to illustrate the conductive structure preparation method of the embodiments of the present application.

[0060] Embodiment 1:

[0061] ​​​A 6-inch <110> silicon wafer with a thickness of 655±10 μm (i.e. the substrate layer 201) is used. An amorphous Cr layer (i.e. the amorphous adhesion layer 202) with a thickness of 10 nm is first deposited on the silicon wafer by magnetron sputtering at a power of 20 kW, and then an Au layer (i.e. the first layer of crystalline metal layer 203) with a thickness of 150 nm is deposited at a power of 5 kW, and then a Au layer (i.e. the second layer of crystalline metal layer 203) with a thickness of 50 nm is deposited at a power of 500 W. During the deposition, the pressure in the reactor chamber is 5×10 -9 A photoresist layer 204 is formed on the second layer of crystalline metal layer 203 by using a photolithography process. A gold layer is plated on the exposed area by using a direct current plating method. The residual photoresist 204 is removed by using a brush washing machine. The excess metal seed layer is removed by using an ion beam etching method to obtain the conductive structure 1. It is tested that the grain size of the second layer of crystalline metal layer 203 of the conductive structure 1 is 39.3 nm, and the grain size of the metal wire 205 is 63.1 nm. The scratch depth of the metal wire 205 is 6560 nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. The hardness of the metal wire 205 is low in the whole. When the metal wire 205 with low hardness is formed, the impact force on the amorphous adhesion layer 202, the two side crystalline metal layers 203 and the substrate layer 201 is small. Thus, the adhesion between the substrate layer 201 and the amorphous adhesion layer 202 is not easily damaged, so that the substrate layer 201 is not easily separated from the amorphous adhesion layer 202, and the product quality and service life of the micro-electro-mechanical system are improved.

[0062] Example 2

[0063] An 8-inch <110> silicon wafer with a thickness of 655±10 μm is used. A SiO2 film with a thickness of 1 μm is grown on the silicon wafer by chemical vapor deposition (CVD) to obtain the substrate layer 201. An amorphous Cr layer (i.e. the amorphous adhesion layer 202) with a thickness of 2 nm is first deposited on the SiO2 film by magnetron sputtering at a power of 1 kW, and then an Au layer (i.e. the first layer of crystalline metal layer 203) with a thickness of 150 nm is deposited at a power of 10 kW, and then a Au layer (i.e. the second layer of crystalline metal layer 203) with a thickness of 30 nm is deposited at a power of 100 W. During the deposition, the pressure in the reactor chamber is 5×10 -5mTorr, a photoresist 204 layer arranged in an array is made on the second layer of crystalline metal layer 203 using a photolithography process, a gold layer is plated in the exposed area using direct current electroplating method, residual photoresist 204 is removed using a brush washing machine, and the excess metal seed layer is removed by ion beam etching to obtain the conductive structure 2. After testing, the grain size of the second layer of crystalline metal layer 203 of the conductive structure 2 is 45.9 nm; the grain size of the metal wire 205 is 75.17 nm, and the scratch depth of the metal wire 205 is 7546 nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. The overall hardness of the metal wire 205 is low. When the metal wire 205 with low hardness is formed, the impact force on the amorphous adhesion layer 202, the two side crystalline metal layers 203 and the substrate layer 201 is small. Therefore, it is not easy to damage the connection between the substrate layer 201 and the amorphous adhesion layer 202, so that the substrate layer 201 is not easy to fall off from the amorphous adhesion layer 202, and the product quality and service life of the micro-electromechanical system are improved.

[0064] Example 3:

[0065] An 8-inch <110> type silicon wafer with a thickness of 655±10 μm is used. A 1 μm thick SiO2 film is grown on the silicon wafer by chemical vapor deposition (CVD) to obtain the substrate layer 201. A 250 nm amorphous Ti layer (i.e. amorphous adhesion layer 202) is first deposited on the SiO2 film by magnetron sputtering at a power of 40 kW, then a 200 nm crystalline Au layer (i.e. first layer of crystalline metal layer 203) is deposited at a power of 100 W, and then a 300 nm crystalline Au layer (i.e. second layer of crystalline metal layer 203) is continuously deposited at a power of 10 kW. The reactor chamber pressure during deposition is 5×10 -9mTorr, a photoresist layer 204 arranged in an array is made on the second crystalline metal layer 203 using a photolithography process, a gold layer is plated in the exposed area using a direct current electroplating method, residual photoresist 204 is removed using a brush washing machine, and the excess metal seed layer is removed by ion beam etching to obtain the conductive structure 3. Tests show that the grain size of the second crystalline metal layer 203 of the conductive structure 3 is 37.9 nm; the grain size of the metal wire 205 is 56.9 nm, and the scratch depth of the metal wire 205 is 6267 nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. When the metal wire 205 with low hardness is formed, the impact force on the amorphous adhesion layer 202, the two side crystalline metal layers 203 and the substrate layer 201 is small. Therefore, it is not easy to damage the continuity between the substrate layer 201 and the amorphous adhesion layer 202, so that the substrate layer 201 is not easy to fall off from the amorphous adhesion layer 202, and the product quality and service life of the micro-electro-mechanical system are improved.

[0066] Example 4:

[0067] An 8-inch <110> type silicon wafer with a thickness of 655±10 μm (i.e. the substrate layer 201) is used. An amorphous Cr layer (i.e. the amorphous adhesion layer 202) with a thickness of 10 nm is deposited on the silicon wafer by a magnetron sputtering method at a power of 20 kW, followed by deposition of a crystalline Au layer (i.e. the first crystalline metal layer 203) with a thickness of 150 nm at a power of 5 kW, and then deposition of a crystalline Au layer (i.e. the second crystalline metal layer 203) with a thickness of 50 nm at a power of 500 W. The reactor chamber pressure during deposition is 5×10 -9 mTorr, a photoresist layer 204 arranged in an array is made on the second crystalline metal layer 203 using a photolithography process, a gold layer is plated in the exposed area using a direct current electroplating method, residual photoresist 204 is removed using a brush washing machine, and the excess metal seed layer is removed by ion beam etching to obtain the conductive structure 3. Tests show that the grain size of the second crystalline metal layer 203 of the conductive structure 3 is 37.9 nm; the grain size of the metal wire 205 is 56.9 nm, and the scratch depth of the metal wire 205 is 6267 nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. When the metal wire 205 with low hardness is formed, the impact force on the amorphous adhesion layer 202, the two side crystalline metal layers 203 and the substrate layer 201 is small. Therefore, it is not easy to damage the continuity between the substrate layer 201 and the amorphous adhesion layer 202, so that the substrate layer 201 is not easy to fall off from the amorphous adhesion layer 202, and the product quality and service life of the micro-electro-mechanical system are improved.

[0068] In addition, the application further provides a micro-electro-mechanical system comprising a plurality of conductive elements, each of the conductive elements being electrically connected by using the conductive structure provided in the above-mentioned embodiments.

[0069] In addition, the application further provides a micro-electro-mechanical system comprising a plurality of conductive elements, each of the conductive elements being electrically connected by using the conductive structure provided in the above-mentioned embodiments.

[0070] In summary, the application provides a conductive structure preparation method, a conductive structure and a micro-electro-mechanical system. Different sputtering powers are pre-configured to sputter at least two crystalline metal layers in sequence on a side of an amorphous adhesion layer away from a substrate layer, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is less than a first size threshold. In this way, the crystalline metal layer closest to the amorphous adhesion layer has better adhesion with the amorphous adhesion layer, and the metal wires subsequently grown on the at least two crystalline metal layers are less likely to fall off the amorphous adhesion layer.

[0071] In addition, on a side of the crystalline metal layer farthest from the substrate layer, the metal wires are arranged in an array. Since the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is greater than a second size threshold, the grain size of the side of the metal wire close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer, and the grain size of the metal wire increases from the side close to the crystalline metal layer to the side away from the crystalline metal layer. In this way, the grain size of the at least two crystalline metal layers is large overall. According to the Hall-Petch law, the greater the grain size, the lower the hardness. Therefore, the hardness of the at least two crystalline metal layers is low overall. When the at least two crystalline metal layers with low hardness are formed, the impact force on the amorphous adhesion layer and the substrate layer is small. In this way, the adhesion between the substrate layer and the amorphous adhesion layer is not easily damaged, the metal wires are less likely to fall off the substrate layer, and the product quality and service life of the micro-electro-mechanical system are improved.

[0072] In the above description, the technical details such as the configuration of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions and the like with the required shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0073] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure without departing from the spirit and scope of the application. Accordingly, it is intended that such additions and modifications be included within the scope of the application. It is the following claims, including any amendments thereto, which define the scope of the application.

[0074] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A method for preparing a conductive structure, characterized in that, The method comprises: sputtering an amorphous adhesion layer on one side of a substrate layer; sputtering at least two crystalline metal layers in sequence on the side of the amorphous adhesion layer away from the substrate layer with different pre-configured sputtering powers, so that the crystalline grain size of the crystalline metal layer closest to the amorphous adhesion layer is less than a set first size threshold, the crystalline grain size of the crystalline metal layer farthest from the amorphous adhesion layer is greater than a set second size threshold, and the second size threshold is greater than the first size threshold, wherein each sputtering power is used to sputter one of the crystalline metal layers; forming an array of metal wires on the side of the crystalline metal layer farthest from the amorphous adhesion layer away from the substrate layer, wherein the crystalline grain size of the metal wires increases from the side close to the crystalline metal layer to the side away from the crystalline metal layer, and the crystalline grain size of the side of the metal wires close to the crystalline metal layer is equal to the crystalline grain size of the crystalline metal layer farthest from the amorphous adhesion layer; removing the parts of the amorphous adhesion layer and the at least two crystalline metal layers on the substrate layer whose orthographic projections do not overlap with the orthographic projection of the metal wires on the substrate layer; The sputtering power of the amorphous adhesion layer ranges from 500W to 40kW, and the sputtering power of each sputtering of the crystalline metal layer ranges from 100W to 10kW; the crystalline metal layer includes two layers, the sputtering power of the amorphous adhesion layer is 25kW, the power of the first sputtering of the crystalline metal layer is 2KW, and the power of the second sputtering of the crystalline metal layer is 1KW; or, the sputtering power of the amorphous adhesion layer is 1kW, the power of the first sputtering of the crystalline metal layer is 10KW, and the power of the second sputtering of the crystalline metal layer is 100W; or, the sputtering power of the amorphous adhesion layer is 40kW, the power of the first sputtering of the crystalline metal layer is 100W, and the power of the second sputtering of the crystalline metal layer is 10KW; or, the sputtering power of the amorphous adhesion layer is 20kW, the power of the first sputtering of the crystalline metal layer is 5KW, and the power of the second sputtering of the crystalline metal layer is 500W; the set second size threshold ranges from 25nm to 50nm.

2. The method of claim 1, wherein, The pressure in the sputter reactor during sputtering of the amorphous adhesion layer and the at least two crystalline metal layers is in the range of 5 x 10 -9 mTorr ~ 5 x 10 -5 mTorr.

3. The method of claim 1, wherein, The thickness of the amorphous adhesion layer ranges from 2nm to 50nm, and the total thickness of the at least two crystalline metal layers ranges from 50nm to 500nm.

4. The method of claim 1, wherein, The removing the parts of the amorphous adhesion layer and the at least two crystalline metal layers on the substrate layer whose orthographic projections do not overlap with the orthographic projection of the metal wires on the substrate layer comprises: using ion beam etching to remove the parts of the amorphous adhesion layer and the at least two crystalline metal layers on the substrate layer whose orthographic projections do not overlap with the orthographic projection of the metal wires on the substrate layer.

5. The method of claim 1, wherein, The forming an array of metal wires on the side of the crystalline metal layer farthest from the amorphous adhesion layer away from the substrate layer comprises: forming an array of spaced photoresist on the side of the crystalline metal layer farthest from the amorphous adhesion layer to form a plating pattern; plating a metal wire in the exposed area between each adjacent pair of photoresist; removing the array of spaced photoresist using a brush machine to form an array of spaced metal wires.

6. An electrically conductive structure, characterized by The conductive structure is prepared by the method of any one of claims 1-5.

7. A microelectromechanical system, characterized by The conductive structure comprises a plurality of conductive elements, and each of the conductive elements is electrically connected by the conductive structure of claim 6.

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