Method for preparing auxiliary dielectric layer based on volatile sacrificial layer

Abstract

The invention discloses a method for preparing an auxiliary dielectric layer based on a volatile sacrificial layer, and belongs to the technical field of construction processes of transistors. The method for preparing the auxiliary dielectric layer based on the volatile sacrificial layer comprises the following steps: depositing a volatile material on a substrate to obtain the volatile sacrificial layer; and depositing a dielectric layer material on the surface of the volatile sacrificial layer, then performing post-processing, and obtaining a Van der Waals contact dielectric layer on the surface of the substrate. According to the method, a volatile material is used as a seed crystal layer for growing a dielectric layer material and a sacrificial layer for forming a Van der Waals gap, so that the problems of damage to a two-dimensional semiconductor material caused by in-situ deposition and insufficient density and non-uniform film thickness of a directly deposited dielectric layer material are avoided, and the construction process of a transistor device is optimized. According to the method, Van der Waals contact of the in-situ deposited dielectric layer can be realized without transfer, and the method is compatible with a silicon-based transistor construction process and is expected to be applied to a silicon-based manufacturing process.

Description

Technical Field

[0001] The invention relates to the technical field of transistor construction technology, and in particular to a method for preparing a dielectric layer based on a volatile sacrificial layer. Background Art

[0002] As one of the important parts of transistor construction, the dielectric layer plays an irreplaceable role in both silicon-based transistors and two-dimensional transistors with two-dimensional semiconductor materials as channels. The two-dimensional semiconductor material has excellent gate-controlled properties due to its atomically thin thickness, which can effectively avoid the short channel effect. Since the surface of two-dimensional semiconductor materials is smooth and has no dangling bonds, transistors constructed using extremely thin two-dimensional semiconductor materials can make up for the serious scattering problem after the silicon-based transistor is thinned, which causes a serious decrease in carrier mobility. However, the characteristic of no dangling bonds also makes it difficult to directly deposit a gate dielectric layer on the surface of a two-dimensional semiconductor material. Even using methods such as atomic layer deposition, problems such as uneven deposition and pinholes will inevitably occur, which seriously limits the application of two-dimensional semiconductor materials.

[0003] At present, the main solutions involve two directions. One is in-situ pretreatment, which includes depositing a seed layer, a metal seed layer or in-situ ozone treatment in advance in the target deposition area of ​​the two-dimensional semiconductor material. On the one hand, this treatment method introduces heterogeneous materials other than dielectric layer materials. The dielectric constant of these heterogeneous materials is usually low, which will lead to a decrease in the dielectric constant of the prepared gate dielectric layer structure as a whole, a decrease in gate capacitance, and a weakened gate control capability. On the other hand, ozone treatment will cause a certain degree of damage to the channel area, resulting in a decrease in electrical performance and is not suitable for single-layer materials; the second is a non-in-situ transfer process. This method is to deposit the required dielectric layer material on a non-target substrate and then transfer it to the corresponding position of the target substrate through an organic support layer to achieve van der Waals contact between the dielectric layer material and the two-dimensional semiconductor material. Although this method can achieve a good van der Waals contact interface, it is easy to introduce residual organic matter, causing n-type doping of the two-dimensional semiconductor material. At the same time, it is easy to introduce additional artificial stress during the transfer process, which may cause cracks in the dielectric layer film and affect the intrinsic dielectric properties of the dielectric layer material. Therefore, there is an urgent need to develop a large-scale dielectric layer thin film preparation process for a single dielectric layer material with a van der Waals contact interface that does not damage the intrinsic properties of the two-dimensional semiconductor channel material and the dielectric layer material. Summary of the invention

[0004] The purpose of the present invention is to provide a method for preparing a volatile sacrificial layer-assisted dielectric layer material to solve the above problems in the prior art.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] One of the technical solutions of the present invention: a method for preparing a dielectric layer based on a volatile sacrificial layer, comprising the following steps: depositing a volatile material on a substrate to obtain a volatile sacrificial layer; depositing a dielectric layer material on the surface of the volatile sacrificial layer, and then performing post-processing (to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate) to obtain a patterned dielectric layer with van der Waals contact on the surface of the substrate.

[0007] The van der Waals contact specifically refers to the formation of a van der Waals gap of a certain size between the in-situ deposited dielectric layer and the substrate (two-dimensional semiconductor material) after the volatile sacrificial layer sandwiched between the dielectric layer and the substrate evaporates and dissipates. At this time, the dielectric layer material and the substrate material are in van der Waals contact without chemical bonds, that is, non-direct contact, thereby avoiding the influence of the in-situ deposited dielectric layer on the intrinsic properties of the substrate (two-dimensional semiconductor material).

[0008] The method of the present invention utilizes the low-temperature volatile diffusion property of the volatile sacrificial layer. After the deposition of the dielectric layer material is completed, the volatile sacrificial layer is evaporated and dissipated by post-processing to remove the sacrificial layer, thereby obtaining a good contact interface and realizing the van der Waals contact between the dielectric layer and the substrate (two-dimensional semiconductor material). At the same time, the volatile sacrificial layer pre-deposited during the deposition of the dielectric layer can be used as a seed layer for the growth of the dielectric layer, thereby improving the density of the dielectric layer material deposited on the surface of the substrate (two-dimensional semiconductor material). In addition, due to the blocking of the sacrificial layer, damage and doping of the channel material during the deposition of the dielectric layer material can be avoided.

[0009] Furthermore, the volatile material includes one or more of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO and Sb2O3; the deposition thickness of the volatile material is 1 to 100 nm, and the surface roughness (Ra) of the deposited volatile sacrificial layer is ≤ 3 nm. If the roughness of the sacrificial layer is too large, it will affect the interface state of the dielectric layer material deposited thereon, resulting in limited gate control performance of the device.

[0010] Furthermore, when the volatile material is a plurality of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO and Sb2O3, the plurality of volatile materials can be combined in any proportion.

[0011] Furthermore, the dielectric layer material includes HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5 and Ba x Sr 1-xOne or more of TiO3 (0 < x < 1); the deposition thickness of the dielectric layer material is 1 to 30 nm, and the surface roughness (Ra) of the deposited dielectric layer ≤ 1 nm. A flat dielectric layer surface is conducive to forming a good contact interface with the subsequently deposited gate electrode, obtaining a more uniform gate control effect.

[0012] Further, when the dielectric layer material is HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5 and Ba x Sr 1-x TiO3 (0 < x < 1) in multiple types, the multiple dielectric layer materials can be combined in any proportion.

[0013] Further, after depositing the volatile material on the substrate and before depositing the dielectric layer material on the surface of the volatile sacrificial layer, there is also a step of patterning;

[0014] Or, before depositing the volatile material on the substrate, there is also a step of patterning (that is, the finally obtained dielectric layer is a patterned dielectric layer).

[0015] Further, the step of patterning includes: first spin-coating a photoresist (including an electron beam photoresist or a photolithography resist) on the surface of the volatile sacrificial layer, drying at 100 - 200 °C for 1 - 3 min; then, exposing the pre-designed graphic area by electron beam, ultraviolet light or laser; finally, putting the exposed sample into a developer for development and a fixer for fixing, so that the area where the dielectric layer is to be deposited as designed is exposed, and the patterning process is completed;

[0016] Or, first spin-coating a photoresist (including an electron beam photoresist or a photolithography resist) on the surface of the substrate, drying at 100 - 200 °C for 1 - 3 min; then, exposing the pre-designed graphic area by electron beam, ultraviolet light or laser; finally, putting the exposed sample into a developer for development and a fixer for fixing, so that the area where the dielectric layer is to be deposited as designed is exposed, and the patterning process is completed.

[0017] Further, the exposure method in the patterning includes electron beam exposure, ultraviolet lithography or laser direct writing.

[0018] Further, when exposing by electron beam, the corresponding spin-coated photoresist is an electron beam photoresist; when exposing by ultraviolet light or laser, the corresponding spin-coated photoresist is a photolithography resist.

[0019] Furthermore, the post-treatment also includes a degumming step; the degumming step includes: soaking the sample in hot acetone at 85 to 150° C. for 15 to 30 minutes and ultrasonicating for 5 to 10 seconds, then taking out the sample, washing away residual acetone with isopropanol and drying with nitrogen.

[0020] The purpose of soaking in hot acetone is to dissolve and remove the exposure glue used in the patterning process. When the exposure glue is dissolved and removed, the non-patterned excess dielectric layer or the non-patterned excess dielectric layer and the excess volatile sacrificial layer covering the surface of the exposure glue are also removed, leaving only the dielectric layer and the volatile sacrificial layer in the patterned area to obtain a patterned dielectric layer / sacrificial layer structure.

[0021] Furthermore, the post-treatment method includes annealing treatment. The purpose of the post-treatment is to evaporate the volatile sacrificial layer covered by the patterned dielectric layer.

[0022] Further, the annealing treatment includes vacuum annealing treatment, annealing treatment in normal pressure atmosphere, annealing treatment in Se vapor atmosphere, annealing treatment in Te vapor atmosphere or annealing treatment in S vapor atmosphere;

[0023] The vacuum annealing treatment conditions include: annealing temperature of 80-300°C, annealing vacuum of 5×10 -1 ~1×10 -9 mbar, annealing time is 0.5~3h, annealing atmosphere is Ar, N2, H2, Cl2, SF6, N2O, CO2, O2 or CH 4-y F y (0≤y≤4), gas flow rate is 0~100sccm.

[0024] Further, the method of depositing the volatile material includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition;

[0025] And / or, the method of depositing the dielectric layer material includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition.

[0026] Furthermore, the substrate includes a two-dimensional semiconductor material; the two-dimensional semiconductor material includes but is not limited to: MoS2, WSe2, WS2, MoTe2 or NbSe2.

[0027] Furthermore, metal electrodes (source and drain) are deposited on the surface of the two-dimensional semiconductor material; the metal electrodes include but are not limited to: Au, Ag, Cu, Pt, Cr, Pb, Ni or Al.

[0028] The second technical solution of the present invention: a transistor device prepared according to the above method for preparing a dielectric layer assisted by a volatile sacrificial layer.

[0029] The present invention discloses the following technical effects:

[0030] The present invention realizes the van der Waals contact between the in-situ grown patterned dielectric layer and the substrate (two-dimensional semiconductor material), and optimizes the electrical properties of the transistor device including the on-off ratio, hysteresis window, off-state current, etc. The present invention obtains a good dielectric layer / two-dimensional semiconductor material contact interface, which is conducive to promoting the development of two-dimensional transistors in the field of electronic devices. Compared with the existing dielectric layer preparation methods in the field, the method of the present invention has the following advantages:

[0031] (1) Compared with directly depositing a dielectric layer in situ on the surface of a two-dimensional semiconductor material, the volatile sacrificial layer pre-deposited in the present invention can effectively prevent the damage and doping of the extremely thin two-dimensional semiconductor material caused by the in-situ deposition.

[0032] (2) The volatile sacrificial layer pre-deposited in advance in the present invention can be used as a seed layer for the deposition of dielectric layer materials, thereby improving the density of the in-situ deposited dielectric layer.

[0033] (3) The present invention can achieve van der Waals contact between the in-situ deposited dielectric layer and the two-dimensional semiconductor material by post-processing to remove the volatile sacrificial layer, thereby optimizing the serious carrier scattering problem caused by the poor contact interface.

[0034] (4) Compared with the method of transferring the dielectric layer, the present invention does not introduce additional artificial stress, thus avoiding possible damage to the dielectric layer during the transfer process.

[0035] (5) The volatile sacrificial layer of the present invention is compatible with the patterning process and can meet any pattern design requirements.

[0036] (6) The technical solution of the present invention is compatible with silicon-based processes, does not require complex transfer processes, and has the potential to be applied to the construction process of silicon-based transistor gate dielectric layers. At the same time, through continuous optimization of the process parameters of the present invention, large-scale wafer-level preparation can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 Schematic diagram of the process flow of the method for preparing a dielectric layer assisted by a volatile sacrificial layer in Example 1;

[0039] Figure 2 This is an AFM morphology characterization photograph of the hafnium oxide dielectric layer deposited with Se as a sacrificial layer in Example 1;

[0040] Figure 3 AFM height characterization data of the hafnium oxide dielectric layer with Se as a sacrificial layer deposited in Example 1 (i.e., the total thickness curve of the dielectric layer + the sacrificial layer);

[0041] Figure 4 It is a schematic structural diagram of a top-gate field effect transistor device constructed based on the process of in-situ deposition of a hafnium oxide dielectric layer using Se as a sacrificial layer in Example 1;

[0042] Figure 5 This is a 500-fold magnified optical microscope image of a top-gate field effect transistor device constructed based on the process of in-situ deposition of a hafnium oxide dielectric layer using Se as a sacrificial layer in Example 1;

[0043] Figure 6 The electrical performance test curve of the top-gate field effect transistor device constructed based on the process of in-situ deposition of hafnium oxide dielectric layer using Se as sacrificial layer in Example 1;

[0044] Figure 7 This is a test curve of the electrical performance of a top-gate field effect transistor device constructed based on the process of transferring the hafnium oxide dielectric layer from the organic support layer in the comparative example. DETAILED DESCRIPTION

[0045] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as limiting the present invention, but should be understood as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0046] It should be understood that the terms described in the present invention are only for describing a particular embodiment and are not intended to limit the present invention. In addition, for the numerical range in the present invention, it should be understood that each intermediate value between the upper and lower limits of the scope is also specifically disclosed. The intermediate value in any stated value or stated range, and each smaller range between any other stated value or intermediate value in the described range is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded in the scope.

[0047] Unless otherwise indicated, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art. Although the present invention describes only preferred methods and materials, any methods and materials similar or equivalent to those described herein may also be used in the implementation or testing of the present invention. All documents mentioned in this specification are incorporated by reference to disclose and describe the methods and / or materials associated with the documents. In the event of a conflict with any incorporated document, the content of this specification shall prevail.

[0048] It will be apparent to those skilled in the art that various modifications and variations may be made to the specific embodiments of the present invention description without departing from the scope or spirit of the present invention. Other embodiments derived from the present invention description will be apparent to the skilled artisan. The present invention description and examples are exemplary only.

[0049] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0050] As a first aspect of the present invention, the present invention provides a method for preparing a dielectric layer based on a volatile sacrificial layer, comprising the following steps: depositing a volatile material on a substrate to obtain a volatile sacrificial layer; depositing a dielectric layer material on the surface of the volatile sacrificial layer, and then performing post-processing (to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate) to obtain a dielectric layer with van der Waals contact on the surface of the substrate.

[0051] The method is characterized in that a volatile material is used as a sacrificial layer and a seed layer for the growth of a dielectric layer material, and after the densification deposition of the dielectric layer is completed on the surface of the volatile sacrificial layer, it is removed by post-processing, so that a certain size of van der Waals gap is formed between the in-situ deposited dielectric layer and the underlying substrate (two-dimensional semiconductor material), and van der Waals contact between the in-situ deposited dielectric layer and the substrate (two-dimensional semiconductor material) is achieved. At the same time, the preparation scale can be expanded to the wafer level by optimizing the process parameters of the present invention.

[0052] As a preferred embodiment of the present invention, the volatile material includes one or more of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO, and Sb2O3.

[0053] As a preferred embodiment of the present invention, when the volatile material is a plurality of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO, and Sb2O3, the multiple volatile materials can be combined in any proportion.

[0054] As a preferred embodiment of the present invention, the deposition thickness of the volatile sacrificial layer is 1 to 100 nm, and the surface roughness of the deposited volatile sacrificial layer is ≤ 3 nm.

[0055] As a preferred embodiment of the present invention, the dielectric layer material includes one or more of HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5, and Ba x Sr 1-x TiO3 (0 < x < 1).

[0056] As a preferred embodiment of the present invention, when the dielectric layer material is a plurality of HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5, and Ba x Sr 1-x TiO3 (0 < x < 1), the multiple dielectric layer materials can be combined in any proportion.

[0057] As a preferred embodiment of the present invention, the deposition thickness of the dielectric layer material is 1 to 30 nm, and the surface roughness of the deposited dielectric layer is ≤ 1 nm.

[0058] As a preferred embodiment of the present invention, after depositing the volatile material on the substrate and before depositing the dielectric layer material on the surface of the volatile sacrificial layer, it further includes a patterning treatment step;

[0059] Or, before depositing the volatile material on the substrate, it further includes a patterning treatment step.

[0060] As a preferred embodiment of the present invention, before the post-treatment, it further includes a degumming treatment step.

[0061] As a preferred embodiment of the present invention, the method for preparing a dielectric layer based on a volatile sacrificial layer comprises the following more specific steps: depositing a volatile material on a substrate to obtain a volatile sacrificial layer; performing a patterning process on the surface of the volatile sacrificial layer; depositing a dielectric layer material on the surface of the patterned volatile sacrificial layer, and then sequentially performing a stripping process and a post-processing process (to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate) to obtain a patterned dielectric layer with van der Waals contact on the substrate;

[0062] Alternatively, the substrate is patterned; a volatile material is deposited on the surface of the patterned substrate to obtain a volatile sacrificial layer; a dielectric layer material is deposited on the surface of the volatile sacrificial layer, and then a stripping treatment and a post-treatment are performed in sequence (to remove the volatile sacrificial layer sandwiched between the dielectric layer and the substrate) to obtain a patterned dielectric layer with van der Waals contact on the substrate surface.

[0063] As a preferred embodiment of the present invention, the patterning process includes electron beam exposure, ultraviolet lithography or laser direct writing.

[0064] As a preferred embodiment of the present invention, the patterning process comprises: firstly, spin coating an exposure glue (including an electron beam exposure glue or a photoresist) on the surface of the volatile sacrificial layer, and drying at 100-200° C. for 1-3 minutes; then, exposing the pre-designed graphic area by electron beam, ultraviolet light or laser; finally, placing the exposed sample in a developer for development, and fixing it in a fixer, so that the designed area where the dielectric layer is to be deposited is exposed, that is, the patterning process is completed;

[0065] Alternatively, first, an exposure glue (including electron beam exposure glue or photoresist) is spin-coated on the surface of the substrate and dried at 100-200° C. for 1-3 minutes; then, a pre-designed graphic area is exposed by electron beam, ultraviolet light or laser; finally, the exposed sample is placed in a developer for development and fixed in a fixer to expose the designed area where the dielectric layer is to be deposited, thereby completing the patterning process.

[0066] As a preferred embodiment of the present invention, when exposure is performed by electron beam, the corresponding exposure glue to be spin-coated is electron beam exposure glue; when exposure is performed by ultraviolet light or laser, the corresponding exposure glue to be spin-coated is photoresist.

[0067] As a preferred embodiment of the present invention, the degumming treatment includes: first soaking the sample in hot acetone at 85-150° C. for 15-30 minutes and ultrasonicating for 5-10 seconds, then taking out the sample, washing away residual acetone with isopropanol and drying with nitrogen.

[0068] As a preferred embodiment of the present invention, the post-treatment method includes annealing treatment.

[0069] As a preferred embodiment of the present invention, the annealing treatment includes vacuum annealing treatment, annealing treatment in normal pressure atmosphere, annealing treatment in Se vapor atmosphere, annealing treatment in Te vapor atmosphere or annealing treatment in S vapor atmosphere;

[0070] The vacuum annealing treatment conditions include: annealing temperature of 80-300°C, annealing vacuum of 5×10 -1 ~1×10 -9 mbar, annealing time is 0.5~3h, annealing atmosphere is Ar, N2, H2, Cl2, SF6, N2O, CO2, O2 or CH 4-y F y (0≤y≤4), gas flow rate is 0~100sccm.

[0071] As a preferred embodiment of the present invention, the method of depositing the volatile material includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition;

[0072] And / or, the method of depositing the dielectric layer material includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition. The deposition method described in the present invention is not limited to the above methods. As long as it can achieve the deposition of thin films in the art and can ensure the stability of the interface properties of the volatile sacrificial layer during the deposition process, and the deposition method without evaporation and diffusion can be used as the optional deposition method in the present invention.

[0073] As a preferred embodiment of the present invention, the substrate includes a two-dimensional semiconductor material and a source (S) and a drain (D) deposited in advance on the two-dimensional semiconductor material.

[0074] As a preferred embodiment of the present invention, the two-dimensional semiconductor material includes but is not limited to: MoS2, WSe2, WS2, MoTe2 or NbSe2.

[0075] As a preferred embodiment of the present invention, the source (S) and the drain (D) include but are not limited to: Au, Ag, Cu, Pt, Cr, Pb, Ni or Al.

[0076] As a second aspect of the present invention, the present invention provides a transistor device prepared according to the above method for preparing a dielectric layer assisted by a volatile sacrificial layer.

[0077] The technical solution of the present invention is further described below in conjunction with specific embodiments.

[0078] The normal temperature involved in the specific embodiment of the present invention specifically refers to 20-30°C.

[0079] Example 1

[0080] A method for preparing a dielectric layer based on a volatile sacrificial layer (process flow diagram as shown in FIG. Figure 1 The steps are as follows:

[0081] (1) A single layer of MoS2 two-dimensional semiconductor material was prepared on the surface of a silicon substrate, and then a 30 nm thick Au electrode (source and drain) was evaporated on the surface of the MoS2 two-dimensional semiconductor material as a substrate, and a 6 nm thick Se volatile sacrificial layer thin film was deposited on the surface of the substrate by thermal evaporation. The specific parameters of thermal evaporation are: power ratio of 10.8%, power change rate of 0.5u / s, evaporation rate of The vacuum degree of the cavity is 2.1×10 -8 torr, the rotation motor speed is 10 rpm. The surface roughness Ra of the Se volatile sacrificial layer film after deposition is about 1.2 nm, and the deposition thickness is 6 nm.

[0082] (2) Spin-coating an electron beam exposure glue (polymethyl methacrylate) on the surface of the Se volatile sacrificial layer and drying it at 100°C for 1 min; then, patterning the exposure glue using an electron beam; finally, developing the exposed sample in a developer, fixing it in isopropyl alcohol, and drying it with nitrogen, thereby completing the patterning process on the surface of the Se volatile sacrificial layer film.

[0083] (3) The dielectric layer material is deposited on the patterned sample. A hafnium oxide (HfO2) film is deposited on the surface of the patterned Se volatile sacrificial layer film by atomic layer deposition for 180 cycles. The deposition procedure for each cycle is to first inject the hafnium (Hf) source into the chamber, purge it evenly, then inject the water source into the chamber, purge it evenly and react, then inject the water source again, purge it evenly and react. The continuous cycle of water source injection and reaction is to make the hafnium source of the previous layer react more completely. The deposition temperature is 90°C. The low temperature deposition is to ensure that the volatile Se sacrificial layer film does not change and maintain a stable interface state during the hafnium oxide deposition process. The surface roughness Ra of the hafnium oxide film after deposition is about 0.8nm (such as Figure 2 The AFM morphology characterization photograph in FIG. 2 shows that the deposition thickness is 26 nm (as shown in FIG. Figure 3 (as shown in the AFM height characterization data figure).

[0084] (4) The deposited sample is placed in 120°C hot acetone for degumming. After soaking for 30 minutes, it is ultrasonicated for 10 seconds. Then the sample is taken out, and the residual acetone on the sample is cleaned with isopropyl alcohol at room temperature, and then blown dry with nitrogen. The purpose of soaking in hot acetone is to dissolve and remove the exposure glue used in the patterning process. When the exposure glue is dissolved and removed, the non-patterned redundant dielectric layer covering the surface of the exposure glue is also removed, leaving only the dielectric layer in the patterned area; in addition, due to the low evaporation temperature of Se, the bonding force with the target substrate is weak during the thermal evaporation process, so that in the acetone degumming process, when the exposure glue is removed, the Se film directly exposed to the acetone will be removed together, and the Se film covered with hafnium oxide will not be removed, thereby obtaining a patterned hafnium oxide dielectric layer (HfO2 / Se structure) with Se as a sacrificial layer.

[0085] (5) Since the Se volatile sacrificial layer film can evaporate at a relatively low temperature, the sample after debonding is subjected to vacuum annealing treatment in order to remove the volatile Se sacrificial layer by annealing and retain the hafnium oxide deposited on the Se to achieve van der Waals contact between the hafnium oxide dielectric layer and the two-dimensional semiconductor channel material. The annealing parameters are: vacuum degree 2.1×10 -5 mbar, annealing temperature 150℃, annealing time 2h. On the one hand, the Se volatile sacrificial layer film serves as an auxiliary layer for the growth of hafnium oxide, assisting the densification growth of the dielectric layer and avoiding the damage to the channel material during the in-situ growth of hafnium oxide. On the other hand, after the growth of hafnium oxide, the Se volatile sacrificial layer film can be volatilized and removed by simple annealing, so that a certain size of van der Waals gap (vdW gap) is generated between hafnium oxide and the channel material, realizing the van der Waals stacking of the hafnium oxide dielectric layer and the two-dimensional semiconductor material, optimizing the contact interface between the two, and avoiding serious carrier interface scattering. In addition, under the action of annealing, the surface flatness of the hafnium oxide dielectric layer is further optimized.

[0086] (6) Finally, a 30 nm thick Au electrode is deposited on the annealed hafnium oxide dielectric layer by thermal evaporation as the gate of the transistor device. The schematic diagram and optical microscope image of the transistor device (top gate field effect transistor) constructed in the embodiment are shown in FIG. Figure 4 and Figure 5 shown.

[0087] The electrical performance of the van der Waals stacked field effect transistor constructed in this embodiment was tested. The applied drain bias voltage V ds =1V, source grounded V s =0, substrate grounded, top gate voltage swept from -2V to 2V, test results are shown in Figure 6 .like Figure 6 I ds -V tgAs shown in the curve, the off-state current of the device is as low as 10fA, the switching ratio is about 7 orders of magnitude, and the hysteresis window is only about 130mV. The smaller hysteresis window proves that there are fewer defects in the contact interface between hafnium oxide and the two-dimensional semiconductor material, and less electron capture during the first test curve scanning process, so that the corresponding required voltage under the same current during the retracement process is not much different, and the switching ratio of 7 orders of magnitude meets the requirements of transistors specified in the International Roadmap for Devices and Systems (IRDS), proving that the application of the present invention in the construction of transistors is feasible.

[0088] Example 2

[0089] A method for preparing a dielectric layer based on a volatile sacrificial layer, the steps are as follows:

[0090] (1) A single layer of MoS2 two-dimensional semiconductor material is prepared on the surface of a silicon substrate, and then a 25 nm thick Au electrode (source and drain) is evaporated on the surface of the MoS2 two-dimensional semiconductor material as a substrate, and an electron beam exposure glue (polymethyl methacrylate) is spin-coated on the surface of the substrate and dried at 150°C for 2 min; then, the exposure glue is patterned by electron beam exposure; finally, the exposed sample is placed in a developer for development, fixed in isopropyl alcohol, and blown dry with nitrogen, and patterned in advance to expose the target deposition area.

[0091] (2) A 10 nm thick Te volatile sacrificial layer film is deposited on the surface of the patterned sample by thermal evaporation. The specific parameters of thermal evaporation are: power ratio of 13.5%, power change rate of 0.5u / s, evaporation rate of The vacuum degree of the cavity is 2.2×10 -8 torr, the rotation motor speed is 10 rpm. The surface roughness Ra of the Se volatile sacrificial layer film after deposition is about 1 nm, and the deposition thickness is 6 nm.

[0092] (3) A hafnium oxide film was deposited on the surface of the Te volatile sacrificial layer film by atomic layer deposition for 180 cycles. The deposition procedure for each cycle was to first inject the hafnium source into the chamber, purge it evenly, then inject the water source into the chamber, purge it evenly and react, then inject the water source again, purge it evenly and react. The purpose of the two consecutive cycles of water source injection and reaction was to make the hafnium source of the previous layer react more completely. The deposition temperature was 90°C. The low temperature deposition was to ensure that the volatile Te sacrificial layer film did not change and maintain a stable interface state during the hafnium oxide deposition process. The surface roughness Ra of the hafnium oxide film after deposition was about 0.8nm, and the deposition thickness was 26nm.

[0093] (4) The deposited sample is placed in 120°C hot acetone for degumming, soaked for 30 minutes and then subjected to ultrasound for 10 seconds. The sample is taken out, and the residual acetone on the sample is cleaned with isopropanol at room temperature and dried with nitrogen to obtain a patterned hafnium oxide dielectric layer (HfO2 / Te structure) with Te as the sacrificial layer.

[0094] (5) Since the volatile Te sacrificial layer film can evaporate at a relatively low temperature, the sample after debonding is subjected to vacuum annealing treatment in order to remove the volatile Te sacrificial layer by annealing and retain the hafnium oxide deposited on Te to achieve van der Waals contact between the hafnium oxide dielectric layer and the two-dimensional semiconductor channel material. The annealing parameters are: vacuum degree 2.1×10 -5 mbar, annealing temperature 200℃, annealing time 2h. On the one hand, the Te volatile sacrificial layer film serves as an auxiliary layer for the growth of hafnium oxide, assisting the densification growth of the dielectric layer and avoiding the damage to the channel material during the in-situ growth of hafnium oxide. On the other hand, after the growth of hafnium oxide, the Te volatile sacrificial layer film can be volatilized and removed by simple annealing, so that a certain size of van der Waals gap (vdW gap) is generated between hafnium oxide and the channel material, realizing the van der Waals stacking of the hafnium oxide dielectric layer and the two-dimensional semiconductor material, optimizing the contact interface between the two and avoiding serious carrier interface scattering. In addition, under the action of annealing, the surface flatness of the hafnium oxide dielectric layer is further optimized.

[0095] (6) Finally, a 25 nm thick Au electrode is deposited by thermal evaporation on the annealed hafnium oxide dielectric layer as the gate of the transistor device.

[0096] The electrical performance of the van der Waals stacked field effect transistor constructed in this embodiment was tested. The applied drain bias voltage V ds =1V, source grounded V s = 0, the substrate is grounded, and the top gate voltage is swept from -2 V to 2 V. The test shows that the off-state current of the device is as low as 10 fA, the switching ratio is about 7 orders of magnitude, and the hysteresis window is about 200 mV.

[0097] Comparative Example 1

[0098] A top-gate field effect transistor constructed by an organic support layer-assisted transfer of a hafnium oxide dielectric layer, the steps are as follows:

[0099] (1) A layer of PMMA exposure glue was spin-coated on a 300 nm thick silicon oxide and baked for 1 min, followed by electron beam exposure and development to obtain a patterned PMMA glue layer.

[0100] (2) A thin film of hafnium oxide dielectric layer material was deposited on the patterned PMMA glue layer by atomic layer deposition for 180 cycles. The surface roughness Ra of the hafnium oxide film after deposition was about 0.5 nm, and the deposition thickness was 26 nm. The deposited sample was then placed in 120°C hot acetone and soaked for 25 min and ultrasonicated for 10 s before being taken out. The residual acetone was cleaned with room temperature isopropanol, and the debonding process was completed after drying with nitrogen gas, and the excess hafnium oxide dielectric layer material was removed to obtain a patterned dielectric layer material.

[0101] (3) Spin-coat two layers of PMMA on the sample surface as an organic support layer for transfer. After each spin coating, dry the sample on a hot plate at 90°C for 1 min.

[0102] (4) The sample is placed in deionized water. Since the adhesion between the organic support layer and the patterned dielectric layer material is greater than the adhesion between the hafnium oxide dielectric layer material and the silicon oxide substrate, the hafnium oxide dielectric layer adheres to the organic support layer and is peeled off together during the process of slowly peeling off the organic support layer.

[0103] (5) The peeled organic support layer carrying the patterned hafnium oxide dielectric layer material is transferred to the target area of ​​the MoS2 two-dimensional semiconductor material and the source (S) and drain (D) combination structure prepared in advance, and then immersed in 85°C hot acetone for degumming. After soaking for 30 minutes, it is ultrasonicated for 10 seconds, and then the sample is taken out, and the residual acetone is cleaned with room temperature isopropanol and blown dry to complete the transfer of the hafnium oxide dielectric layer.

[0104] (6) Thermally evaporate an Au electrode on the transferred hafnium oxide dielectric layer as a top gate electrode to complete the construction of the field effect transistor.

[0105] In this comparative example, except for the different preparation process of the hafnium oxide dielectric layer, the construction process of other structures of the transistor device remains consistent with that of Example 1.

[0106] The electrical performance of the transistor constructed by the patterned hafnium oxide dielectric layer transferred from the organic support layer in this comparative example was tested. The bias voltage V ds =1V, V s Grounded, top gate voltage is -3~3V, the obtained I ds -V tg Curve like Figure 7As shown, it can be seen from the test curve that the hysteresis window of the transistor constructed by the method of transferring the dielectric layer is as high as 1.15V, which is much larger than the hysteresis window of the transistor constructed by the process of the present invention. This is because a large artificial stress is introduced during the transfer process, which inevitably produces a certain degree of microcracks or hole damage in the hafnium oxide dielectric layer during the transfer process, resulting in an increase in defects in the hafnium oxide dielectric layer after the transfer and a decrease in performance. At the same time, the off-state current is on the order of 10pA, which is much larger than the off-state current of the order of 10fA obtained in Example 1 of the present invention, which will cause the power consumption of the device to increase significantly, which is inconsistent with the low power consumption requirements of the international device and system roadmap. The large off-state current also causes the switching ratio of the transistor constructed by the transfer hafnium oxide process to decrease, which is not suitable for subsequent logic cascades.

[0107] The embodiments described above are only descriptions of the preferred modes of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A method for preparing a dielectric layer based on a volatile sacrificial layer, characterized in that: The following steps are involved: Depositing a volatile material on a substrate to obtain a volatile sacrificial layer; A dielectric layer material is deposited on the surface of the volatile sacrificial layer, and then post-processed to obtain a dielectric layer with van der Waals contact on the surface of the substrate.

2. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 1, characterized in that: The volatile material includes one or more of Te, S, Zn, Bi, BP, Se, Cd, Cr, Ge, Mg, ZnO and Sb2O3; the deposition thickness of the volatile material is 1 to 100 nm, and the surface roughness of the deposited volatile sacrificial layer is ≤3 nm.

3. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 1, characterized in that: The dielectric layer material includes one or more of HfO2, Al2O3, SrTiO3, h-BN, SiO2, Sb2O3, ZrO2, TiO2, BaTiO3, PZT, PbTiO3, LaSrTiO3, BaTaO3, LiNbO3, ZrAlSiO4, PVDF, Bi2SeO5, and Ba x Sr 1-x TiO3, where 0 < x < 1; the deposition thickness of the dielectric layer material is 1 - 30 nm, and the surface roughness of the deposited dielectric layer ≤ 1 nm.

4. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 1, characterized in that: The method further includes a patterning step after depositing the volatile material on the substrate and before depositing the dielectric layer material on the surface of the volatile sacrificial layer; Alternatively, the step of depositing the volatile material on the substrate further includes a patterning step.

5. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 4, characterized in that: The patterning process includes electron beam exposure, ultraviolet lithography or laser direct writing.

6. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 5, characterized in that: The post-treatment also includes a degumming step; the degumming step includes: soaking the sample in hot acetone at 85-150°C for 15-30 minutes and ultrasonicating for 5-10 seconds, then taking out the sample, washing away residual acetone with isopropanol and drying with nitrogen.

7. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 1, characterized in that: The post-processing method includes annealing.

8. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 7, characterized in that: The annealing treatment includes vacuum annealing treatment, annealing treatment in normal pressure atmosphere, annealing treatment in Se vapor atmosphere, annealing treatment in Te vapor atmosphere or annealing treatment in S vapor atmosphere; The vacuum annealing treatment conditions include: annealing temperature of 80-300°C, annealing vacuum of 5×10 -1 ~1×10 - 9 mbar, annealing time is 0.5~3h, annealing atmosphere is Ar, N2, H2, Cl2, SF6, N2O, CO2, O2 or CH 4-y F y , 0≤y≤4, gas flow rate is 0~100sccm.

9. The method for preparing a dielectric layer based on a volatile sacrificial layer as claimed in claim 1, characterized in that: The method of depositing the volatile material includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition; And / or, the method of depositing the dielectric layer material includes one of magnetron sputtering, thermal evaporation, electron beam evaporation, atomic layer deposition, pulsed laser deposition, molecular beam epitaxy, sol-gel method, chemical vapor deposition, plasma enhanced chemical vapor deposition and metal organic chemical vapor deposition.

10. A transistor device prepared according to the method for preparing a dielectric layer using a volatile sacrificial layer as an auxiliary material according to any one of claims 1 to 9.

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