SNR test method and system based on ATE test platform, medium and equipment

Abstract

The invention discloses an SNR test method and system based on an ATE test platform, a medium and equipment, and the method comprises the steps: adjusting the original signal frequency of an analog signal or the original sampling frequency of a to-be-tested chip according to a preset undersampling algorithm, controlling a preset signal generator, outputting the analog signal to the to-be-tested chip, and outputting the analog signal to the to-be-tested chip; sending the analog signal to the to-be-tested chip to enable the to-be-tested chip to carry out undersampling on the analog signal to obtain sampling data, and converting the sampling data into a digital signal; and processing the digital signal according to a signal-to-noise ratio calculation algorithm preset by the ATE test platform to obtain a signal-to-noise ratio test result, and completing the signal-to-noise ratio test of the to-be-tested chip. By using the improved undersampling algorithm, when the analog signal frequency and the sampling frequency do not meet the Nyquist sampling law, the frequency of the analog signal or the sampling frequency is adjusted, spectrum leakage can be effectively reduced, signal-to-noise ratio testing can still be carried out on the premise that a window function does not need to be used, and therefore the testing process is simplified, and the testing efficiency is improved. The test efficiency is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic testing and measurement, and relates to an SNR testing method, system, medium and equipment based on an ATE testing platform. Background Art

[0002] When using the ATE (automatic test equipment) platform to test the SNR (signal-to-noise ratio) parameters of ADC (analog-to-digital converter) chips, there are specific technical challenges. In particular, when the analog signal input is a 70MHz sine wave and the ADC sampling frequency is set to 80MHz, this setting does not meet the requirements of the Nyquist sampling theorem, that is, the sampling frequency should be at least twice the highest frequency of the sampled signal; due to this mismatch, serious spectrum leakage problems occur, affecting the accuracy of the SNR test results.

[0003] In the prior art, the solution to this problem mainly relies on coherent sampling algorithms and windowing function technology. These methods can reduce spectrum leakage, but also increase the complexity and time cost of data processing. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present application provides an SNR test method, system, medium and device based on an ATE test platform, which solves the technical problem of directly obtaining accurate SNR test results without using a window function to process spectrum leakage.

[0005] To achieve the above object, in a first aspect, the present invention provides an SNR test method based on an ATE test platform, comprising:

[0006] According to a preset undersampling algorithm, the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested is adjusted, and a preset signal generator is controlled to output the analog signal to the chip to be tested, so that the chip to be tested performs undersampling on the analog signal to obtain sampling data, and converts the sampling data into a digital signal; wherein the signal frequency of the analog signal and the sampling frequency of the chip to be tested do not satisfy the Nyquist sampling theorem;

[0007] According to the signal-to-noise ratio calculation algorithm preset in the ATE test platform, the digital signal is processed to obtain a signal-to-noise ratio test result, thereby completing the signal-to-noise ratio test of the chip to be tested.

[0008] Compared with the prior art, the embodiments of the present application have the following beneficial effects: by using a preset undersampling algorithm, when the analog signal frequency and the sampling frequency do not satisfy the Nyquist sampling theorem, the frequency or the sampling frequency of the analog signal is adjusted, which can effectively avoid the occurrence of signal aliasing and reduce spectrum leakage. Without the need to use a window function to process spectrum leakage, the signal-to-noise ratio test can still be effectively performed, thereby simplifying the test process and improving test efficiency.

[0009] In some embodiments of the first aspect of the present application, adjusting the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested according to a preset undersampling algorithm, and controlling a preset signal generator to output the analog signal to the chip to be tested, so that the chip to be tested undersamples the analog signal to obtain sampling data, includes:

[0010] Outputting an analog signal to the chip under test according to the preset original signal frequency of the analog signal;

[0011] According to a preset under-sampling algorithm, the original sampling frequency of the chip under test is adjusted to obtain a sampling frequency, so that the chip under test under-samples the analog signal according to the sampling frequency to obtain sampling data.

[0012] Compared with the prior art, the above embodiment has the following beneficial effects: when the original frequency of the analog signal is fixed, undersampling can be performed by adjusting the sampling frequency of the chip to be tested. This feature ensures that different test requirements can be flexibly responded to during the test process.

[0013] In some embodiments of the first aspect of the present application, adjusting the original sampling frequency of the chip to be tested according to a preset undersampling algorithm to obtain the sampling frequency includes:

[0014] Keeping the original signal frequency of the analog signal unchanged, adjusting the original sampling frequency of the chip to be tested according to the undersampling algorithm to obtain the sampling frequency;

[0015] The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

[0016] Compared with the prior art, the above embodiment has the following beneficial effects: when using the undersampling algorithm, a constant K is introduced, where K is the Kth period of the collected waveform. By selecting the values ​​of K and Mx and adjusting the sampling frequency, the occurrence of signal aliasing can be effectively avoided, spectrum leakage can be reduced, and the accuracy of the SNR test results can be improved.

[0017] In some embodiments of the first aspect of the present application, the method further includes adjusting the original signal frequency of the analog signal or the original sampling frequency of the chip under test according to a preset undersampling algorithm, and controlling a preset signal generator to output the analog signal to the chip under test, so that the chip under test undersamples the analog signal to obtain sampling data, and further includes:

[0018] According to a preset undersampling algorithm, the original signal frequency of the analog signal is adjusted to obtain a signal frequency;

[0019] According to the signal frequency, an analog signal is output to the chip under test, so that the chip under test undersamples the analog signal according to the original sampling frequency to obtain sampling data.

[0020] Compared with the prior art, the above embodiment has the following beneficial effects: by flexibly adjusting the frequency of the analog signal, undersampling is achieved while keeping the sampling frequency of the chip to be tested unchanged, thereby enhancing the flexibility and applicability of the test system, while improving the quality of the SNR test results and the test efficiency, and is particularly suitable for application scenarios that need to maintain a fixed sampling frequency.

[0021] In some embodiments of the first aspect of the present application, adjusting the original signal frequency of the analog signal according to a preset undersampling algorithm to obtain the signal frequency includes:

[0022] Keeping the original sampling frequency of the chip under test unchanged, adjusting the original signal frequency of the analog signal according to the undersampling algorithm to obtain the signal frequency;

[0023] The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

[0024] Compared with the prior art, the above embodiment has the following beneficial effects: when using the undersampling algorithm, a constant K is introduced, where K is the Kth period of the collected waveform. By selecting the values ​​of K and Mx, the original signal frequency of the analog signal is adjusted, which can effectively avoid the occurrence of signal aliasing and reduce spectrum leakage, thereby improving the accuracy of the SNR test results.

[0025] In some embodiments of the first aspect of the present application, the controlling a preset signal generator to output an analog signal to the chip to be tested includes:

[0026] According to the preset signal generator, the original analog signal is output;

[0027] The original analog signal is processed according to a preset bandpass filter to obtain an analog signal and send it to the chip to be tested.

[0028] Compared with the prior art, the above embodiment has the following beneficial effects: a signal generator and a bandpass filter are used to generate high-quality analog signal input, thereby reducing noise interference and ensuring the purity and reliability of data during the SNR test.

[0029] In some embodiments of the first aspect of the present application, outputting the original analog signal according to a preset signal generator includes:

[0030] The output power of the original analog signal is:

[0031] Output power = 10 + 20Log10 (0.5 * Vpp) * 0.8913 + insertion loss; wherein, the insertion loss includes: filter insertion loss, power divider insertion loss and balun insertion loss, and Vpp represents the input voltage range of the test chip.

[0032] Compared with the prior art, the above embodiment has the following beneficial effects: by accurately calculating the output power of the original analog signal, various insertion loss factors are taken into account, ensuring that the input voltage near the chip end meets the full-scale state as much as possible, thereby maximizing the performance of the ADC test chip.

[0033] In a second aspect, the present invention further provides an SNR test system based on an ATE test platform, comprising: a signal conversion module and a signal calculation module;

[0034] The signal conversion module is used to adjust the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested according to a preset undersampling algorithm, and control a preset signal generator to output an analog signal to the chip to be tested, so that the chip to be tested performs undersampling on the analog signal to obtain sampling data, and convert the sampling data into a digital signal; wherein the signal frequency of the analog signal and the sampling frequency of the chip to be tested do not satisfy the Nyquist sampling theorem;

[0035] The signal calculation module is used to process the digital signal according to the signal-to-noise ratio calculation algorithm preset in the ATE test platform, obtain the signal-to-noise ratio test result, and complete the signal-to-noise ratio test of the chip to be tested.

[0036] Compared with the prior art, the above embodiments of the present application have the following beneficial effects: by using a preset undersampling algorithm, when the analog signal frequency and the sampling frequency do not satisfy the Nyquist sampling theorem, the frequency or the sampling frequency of the analog signal is adjusted, which can effectively avoid the occurrence of signal aliasing and reduce spectrum leakage. Without the need to use a window function to process spectrum leakage, the signal-to-noise ratio test can still be effectively performed, thereby simplifying the test process and improving test efficiency.

[0037] In a third aspect, the present invention also provides an SNR testing device based on an ATE testing platform, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when loaded into the processor, implements the steps of the SNR testing method based on the ATE testing platform.

[0038] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the SNR test method based on an ATE test platform are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 : A flow chart of an SNR testing method based on an ATE testing platform provided in some embodiments of the present invention.

[0040] Figure 2 : is a structural schematic diagram of an SNR test system based on an ATE test platform provided in some embodiments of the present invention.

[0041] Figure 3 : A structural diagram of an SNR test device based on an ATE test platform provided in some embodiments of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Embodiment 1:

[0044] Please refer to Figure 1 , an SNR test method based on an ATE test platform provided by an embodiment of the present invention, comprising steps S1 to S2:

[0045] Step S1: According to a preset undersampling algorithm, adjust the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested, and control the preset signal generator to output the analog signal to the chip to be tested, so that the chip to be tested undersamples the analog signal to obtain sampling data, and convert the sampling data into a digital signal.

[0046] Among them, the signal frequency of the analog signal and the sampling frequency of the chip to be tested do not satisfy the Nyquist sampling theorem. Under normal circumstances, after sampling using a conventional undersampling algorithm, it is often necessary to use a window function for processing to reduce spectrum leakage. In this application, by improving the undersampling algorithm, effective testing can be achieved even when the window function is not used.

[0047] In some embodiments of the present application, step S1 includes steps S11 to S12, and the specific steps are as follows:

[0048] S11: outputting an analog signal to the chip to be tested according to a preset original signal frequency of the analog signal;

[0049] S12: According to a preset under-sampling algorithm, the original sampling frequency of the chip under test is adjusted to obtain a sampling frequency, so that the chip under test under-samples the analog signal according to the sampling frequency to obtain sampling data.

[0050] Furthermore, when adjusting the original sampling frequency of the chip to be tested, it can be achieved through the following preferred implementations:

[0051] Keeping the original signal frequency of the analog signal unchanged, adjusting the original sampling frequency of the chip to be tested according to the undersampling algorithm to obtain the sampling frequency;

[0052] The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

[0053] In some embodiments of the present application, step S1 can also be implemented through steps S13 to S14 as another implementation method. The specific steps are as follows:

[0054] S13: adjusting the original signal frequency of the analog signal according to a preset undersampling algorithm to obtain a signal frequency;

[0055] S14: outputting an analog signal to the chip under test according to the signal frequency, so that the chip under test undersamples the analog signal according to the original sampling frequency to obtain sampling data.

[0056] Furthermore, when adjusting the original signal frequency of the analog signal, it can be achieved through the following preferred implementations:

[0057] Keeping the original sampling frequency of the chip under test unchanged, adjusting the original signal frequency of the analog signal according to the undersampling algorithm to obtain the signal frequency;

[0058] The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

[0059] In this embodiment, by using a preset undersampling algorithm, when the analog signal frequency and the sampling frequency do not satisfy the Nyquist sampling theorem, the frequency or the sampling frequency of the analog signal is adjusted, so that the occurrence of signal aliasing can be effectively avoided and spectrum leakage can be reduced. Without the need to use a window function to process spectrum leakage, the signal-to-noise ratio test can still be effectively performed, thereby simplifying the test process and improving test efficiency.

[0060] For example, the original sampling frequency Fs = 80MHz, the number of sampling points N = 2 14 =16384, the original signal frequency of the analog signal Ft = 70MHz, in order to facilitate the fast Fourier transform change and meet the Mx According to the requirements, under the above test conditions, K=1 and Mx=-2048 need to be selected to meet the algorithm requirements and obtain the best test results; if the Ft frequency is higher than 120MHz, the value of K can be selected as a non-1 value, because the selection of the K value needs to be determined based on the ratio of the frequency of the analog signal and the sampling clock, as well as the value of Mx, in addition to meeting the requirement of being an integer. And because Mx must be an odd or prime number and Mx and N are mutually prime, Mx is -2047. In order to meet the undersampling algorithm, Mx=-2047 is brought back. According to the undersampling algorithm, if the original signal frequency Ft of the analog signal is guaranteed to remain unchanged, Fs=79.9944200MHz can be obtained; if Fs is guaranteed to remain unchanged, Ft=70.0048828125MHz can be obtained.

[0061] Furthermore, when controlling the preset signal generator to output the analog signal to the chip to be tested, steps S15 to S16 can be used as a preferred implementation to achieve:

[0062] S15: outputting the original analog signal according to the preset signal generator;

[0063] S16: Processing the original analog signal according to a preset bandpass filter to obtain an analog signal and sending it to the chip to be tested.

[0064] As a preferred implementation, a low-noise signal generator such as the SMB100B low-noise signal generator can be used as an analog signal generator to control the noise below -120db, which is helpful for SNR testing. In addition, when the signal generator provides an analog signal such as a 70HMz sine wave, it will also be mixed with waveforms of other frequencies. These noises are unnecessary parts in the test and will affect the test results. Introducing a 69-71MHz bandpass filter in the circuit can effectively filter out high and low frequency noises other than 70MHz, reducing the impact of noise on the test results.

[0065] In this preferred embodiment, a signal generator and a bandpass filter are used to generate high-quality analog signal input, which reduces noise interference and ensures the purity and reliability of data during the SNR test.

[0066] Furthermore, when the original analog signal is output according to the preset signal generator, it can be achieved by the following preferred implementations:

[0067] The output power of the original analog signal is:

[0068] Output power = 10 + 20Log10 (0.5 * Vpp) * 0.8913 + insertion loss; wherein, the insertion loss includes: filter insertion loss, power divider insertion loss and balun insertion loss, and Vpp represents the input voltage range of the test chip.

[0069] As an implementation method, the input voltage near the chip can be visually checked by using the auxiliary tools built into the ATE test platform, and the output voltage of the signal generator can be fine-tuned to make the input voltage near the chip meet the full scale as much as possible.

[0070] In this preferred embodiment, by accurately calculating the output power of the original analog signal and taking various insertion loss factors into consideration, it is ensured that the input voltage near the chip end meets the full-scale state as much as possible, thereby maximizing the performance of the ADC test chip.

[0071] Furthermore, when outputting analog signals to the chip under test, a power divider can be used according to actual test needs to convert the analog signals from one channel into multiple identical signals, and simultaneously input them into multiple test channels of the chip under test for testing. By designing the circuits to be of equal length in the Layout, the signals input to the chip can be in the same phase, thereby reducing the difficulty of the test process.

[0072] Step S2: According to the signal-to-noise ratio calculation algorithm preset by the ATE test platform, the digital signal is processed to obtain a signal-to-noise ratio test result, thereby completing the signal-to-noise ratio test of the chip to be tested.

[0073] In this embodiment, after the chip under test converts the analog signal into a digital signal, the PS1600 board of the ATE test platform can be used to collect the digital signal. After collecting the digital signal, the built-in signal-to-noise ratio calculation algorithm of the ATE test platform is used, which belongs to the prior art and will not be described in detail here. In addition, of course, other similar schemes that have been disclosed can also be used to replace the acquisition scheme or the signal-to-noise ratio calculation method.

[0074] In summary, compared with the prior art, the above embodiments of the present application have the following beneficial effects: by using a preset undersampling algorithm, when the analog signal frequency and the sampling frequency do not satisfy the Nyquist sampling theorem, the frequency or the sampling frequency of the analog signal is adjusted, which can effectively avoid the occurrence of signal aliasing and reduce spectrum leakage. Without the need to use a window function to process spectrum leakage, the signal-to-noise ratio test can still be effectively performed, thereby simplifying the test process and improving test efficiency.

[0075] Embodiment 2:

[0076] Please refer to Figure 2 , based on the same inventive concept, an SNR test system based on an ATE test platform disclosed in an embodiment of the present invention includes: a signal conversion module M1 and a signal calculation module M2;

[0077] The signal conversion module M1 is used to adjust the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested according to a preset undersampling algorithm, and control a preset signal generator to output an analog signal to the chip to be tested, so that the chip to be tested performs undersampling on the analog signal to obtain sampling data, and convert the sampling data into a digital signal; wherein the signal frequency of the analog signal and the sampling frequency of the chip to be tested do not satisfy the Nyquist sampling theorem;

[0078] The signal conversion module M1 includes: an original signal output unit and a sampling adjustment unit; the original signal output unit is used to output an analog signal to the chip to be tested according to a preset original signal frequency of the analog signal;

[0079] The sampling adjustment unit is used to adjust the original sampling frequency of the chip under test according to a preset undersampling algorithm to obtain a sampling frequency, so that the chip under test undersamples the analog signal according to the sampling frequency to obtain sampling data.

[0080] Furthermore, the sampling adjustment unit can be implemented by the following preferred implementations:

[0081] Keeping the original signal frequency of the analog signal unchanged, adjusting the original sampling frequency of the chip to be tested according to the undersampling algorithm to obtain the sampling frequency;

[0082] The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

[0083] Preferably, the signal conversion module M1 may further include: a signal adjustment unit and an original sampling unit; the signal adjustment unit is used to adjust the original signal frequency of the analog signal according to a preset undersampling algorithm to obtain a signal frequency;

[0084] The original sampling unit is used to output an analog signal to the chip under test according to the signal frequency, so that the chip under test undersamples the analog signal according to the original sampling frequency to obtain sampling data.

[0085] Furthermore, the signal adjustment unit can be implemented by the following preferred implementations:

[0086] Keeping the original sampling frequency of the chip under test unchanged, adjusting the original signal frequency of the analog signal according to the undersampling algorithm to obtain the signal frequency;

[0087] The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

[0088] Preferably, the outputting of the analog signal to the chip under test can be achieved by the following preferred implementations:

[0089] According to the preset signal generator, the original analog signal is output;

[0090] The original analog signal is processed according to a preset bandpass filter to obtain an analog signal and send it to the chip to be tested.

[0091] Furthermore, the outputting of the original analog signal can be realized by the following preferred implementations:

[0092] The output power of the original analog signal is:

[0093] Output power = 10 + 20Log10 (0.5 * Vpp) * 0.8913 + insertion loss; wherein, the insertion loss includes: filter insertion loss, power divider insertion loss and balun insertion loss, and Vpp represents the input voltage range of the test chip.

[0094] In this embodiment, the signal conversion module M1 uses a preset undersampling algorithm to adjust the frequency or sampling frequency of the analog signal when the analog signal frequency and the sampling frequency do not satisfy the Nyquist sampling theorem, thereby effectively avoiding the occurrence of signal aliasing and reducing spectrum leakage. Without the need to use a window function to process spectrum leakage, the signal-to-noise ratio test can still be effectively performed, thereby simplifying the test process and improving test efficiency.

[0095] The signal calculation module M2 is used to process the digital signal according to the signal-to-noise ratio calculation algorithm preset in the ATE test platform, obtain the signal-to-noise ratio test result, and complete the signal-to-noise ratio test of the chip to be tested.

[0096] In this embodiment, the indicator output module M2 is processed by the signal-to-noise ratio calculation algorithm preset by the ATE test platform, which ensures the automation and standardization of the test process and improves the test efficiency.

[0097] In summary, compared with the prior art, the embodiments of the present application have the following beneficial effects: by using a preset undersampling algorithm, when the analog signal frequency and the sampling frequency do not satisfy the Nyquist sampling theorem, the frequency or the sampling frequency of the analog signal is adjusted, which can effectively avoid the occurrence of signal aliasing and reduce spectrum leakage. Without the need to use a window function to process spectrum leakage, the signal-to-noise ratio test can still be effectively performed, thereby simplifying the test process and improving test efficiency.

[0098] The division of the modules described above is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules may be combined or integrated into another system.

[0099] Embodiment three:

[0100] Figure 3 The structure diagram of an SNR test device based on an ATE test platform of the present application is shown. Figure 3 As shown, the SNR test device may include: a processor N1, a memory N2, a data interface N3 and a communication bus N4.

[0101] Among them: the processor N1, the memory N2, and the data interface N3 communicate with each other through the communication bus N4; the data interface N3 is used for data communication with other devices such as an input device or an output device; the processor N1 is used to execute the program N5, which can specifically execute the relevant steps in the above-mentioned SNR test method embodiment based on the ATE test platform.

[0102] Specifically, the program N5 may include program codes, and the program codes include computer executable instructions.

[0103] The processor N1 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application. The one or more processors included in the SNR test equipment based on the ATE test platform may be processors of the same type, such as one or more CPUs, or may be processors of different types, such as one or more CPUs and one or more ASICs.

[0104] The memory N2 is used to store the program N5. The memory N2 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk storage.

[0105] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system or other device. In addition, the embodiments of the present application are not directed to any particular programming language.

[0106] Embodiment 4:

[0107] An embodiment of the present invention also provides a computer-readable storage medium, which stores at least one executable instruction. When the executable instruction is executed on an SNR test device / system based on an ATE test platform, the SNR test device / system based on the ATE test platform executes the SNR test method based on the ATE test platform in any of the above method embodiments.

[0108] In the specification provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. Similarly, in order to simplify the application and help understand one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present application, the various features of the embodiments of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. Wherein, the claims that follow the specific embodiment are thus clearly incorporated into the specific embodiment, wherein each claim itself is used as a separate embodiment of the application.

[0109] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive.

Claims

1. A SNR test method based on an ATE test platform, characterized in that: include: According to a preset undersampling algorithm, the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested is adjusted, and a preset signal generator is controlled to output the analog signal to the chip to be tested, so that the chip to be tested performs undersampling on the analog signal to obtain sampling data, and converts the sampling data into a digital signal; wherein the signal frequency of the analog signal and the sampling frequency of the chip to be tested do not satisfy the Nyquist sampling theorem; According to the signal-to-noise ratio calculation algorithm preset in the ATE test platform, the digital signal is processed to obtain the signal-to-noise ratio test result, thereby completing the signal-to-noise ratio test of the chip to be tested.

2. The SNR test method based on the ATE test platform as claimed in claim 1, characterized in that: The method of adjusting the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested according to a preset undersampling algorithm, and controlling a preset signal generator to output the analog signal to the chip to be tested, so that the chip to be tested undersamples the analog signal to obtain sampling data, includes: Outputting an analog signal to the chip under test according to the preset original signal frequency of the analog signal; According to a preset under-sampling algorithm, the original sampling frequency of the chip under test is adjusted to obtain a sampling frequency, so that the chip under test under-samples the analog signal according to the sampling frequency to obtain sampling data.

3. The SNR test method based on the ATE test platform as claimed in claim 2, characterized in that: The step of adjusting the original sampling frequency of the chip to be tested according to a preset undersampling algorithm to obtain the sampling frequency includes: Keeping the original signal frequency of the analog signal unchanged, adjusting the original sampling frequency of the chip to be tested according to the undersampling algorithm to obtain the sampling frequency; The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

4. The SNR test method based on an ATE test platform as claimed in claim 1, characterized in that: The method further comprises: adjusting the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested according to a preset undersampling algorithm, and controlling a preset signal generator to output the analog signal to the chip to be tested, so that the chip to be tested undersamples the analog signal to obtain sampling data; According to a preset undersampling algorithm, the original signal frequency of the analog signal is adjusted to obtain a signal frequency; According to the signal frequency, an analog signal is output to the chip under test, so that the chip under test undersamples the analog signal according to the original sampling frequency to obtain sampling data.

5. The SNR test method based on ATE test platform as claimed in claim 4, characterized in that: The method of adjusting the original signal frequency of the analog signal according to a preset undersampling algorithm to obtain the signal frequency includes: Keeping the original sampling frequency of the chip under test unchanged, adjusting the original signal frequency of the analog signal according to the undersampling algorithm to obtain the signal frequency; The undersampling algorithm is as follows: Among them, Ft is the original signal frequency of the analog signal; Fs is the original sampling frequency; Mx is the number of cycles collected in the analog signal, which is an odd or prime number. Select between; N is the number of sampling points, which must be a power of 2; K represents the Kth cycle of the acquired waveform, which is an integer.

6. The SNR test method based on an ATE test platform according to any one of claims 1 to 5, characterized in that: The control of the preset signal generator to output an analog signal to the chip to be tested includes: According to the preset signal generator, the original analog signal is output; The original analog signal is processed according to a preset bandpass filter to obtain an analog signal and send it to the chip to be tested.

7. The SNR test method based on ATE test platform as claimed in claim 6, characterized in that: The method of outputting the original analog signal according to the preset signal generator comprises: The output power of the original analog signal is: Output power = 10 + 20Log10 (0.5 * Vpp) * 0.8913 + insertion loss; wherein, the insertion loss includes: filter insertion loss, power divider insertion loss and balun insertion loss, and Vpp represents the input voltage range of the test chip.

8. An SNR test system based on an ATE test platform, characterized in that: include: Signal conversion module and signal calculation module; The signal conversion module is used to adjust the original signal frequency of the analog signal or the original sampling frequency of the chip to be tested according to a preset undersampling algorithm, and control a preset signal generator to output an analog signal to the chip to be tested, so that the chip to be tested performs undersampling on the analog signal to obtain sampling data, and convert the sampling data into a digital signal; wherein the signal frequency of the analog signal and the sampling frequency of the chip to be tested do not satisfy the Nyquist sampling theorem; The signal calculation module is used to process the digital signal according to the signal-to-noise ratio calculation algorithm preset in the ATE test platform, obtain the signal-to-noise ratio test result, and complete the signal-to-noise ratio test of the chip to be tested.

9. An SNR test device based on an ATE test platform, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into the processor, the steps of the SNR test method based on the ATE test platform according to claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the SNR test method based on an ATE test platform according to claims 1 to 7 are implemented.

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