Heterogeneous TSV chip reliability test device based on lead bonding

Abstract

The invention relates to a heterogeneous TSV chip reliability test device based on lead bonding. The heterogeneous TSV chip reliability test device comprises a heterogeneous TSV chip, a chip clamp, a test PCB and a test unit. The heterogeneous TSV chip is mounted on the chip clamp; the chip clamp is installed on the test PCB. The test PCB is mounted on the test unit; the heterogeneous TSV chip comprises a silicon substrate and a plurality of TSV test link groups, the silicon substrate is provided with a plurality of test blocks, and each test block is provided with at least one TSV test link group; the TSV test link group is provided with a plurality of TSV test links, and the link types of the plurality of TSV test links are different; among different test blocks, the TSV test links belonging to the same type contain different numbers of TSV structures; each TSV test link is provided with three lead bonding portions, and the TSV test link is bonded with a bonding pad lead of the test PCB based on the lead bonding portions.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a heterogeneous TSV chip reliability test device based on wire bonding. Background Art

[0002] As advanced chip manufacturing processes move toward 3 nm, the density of transistors on the two-dimensional plane of the wafer is gradually approaching the physical limit, accompanied by a substantial increase in chip R&D costs and an extension of the R&D cycle. As a result, "Moore's Law" has failed. Three-dimensional integrated packaging based on through-silicon-vias (TSV) structures has therefore come into being. Three-dimensional integrated packaging integrates wafers vertically through TSV and stacking to obtain packaged chips with smaller size, higher bandwidth, lower latency, and higher performance. It can also achieve heterogeneous integration with micro-electromechanical systems (MEMS) to obtain functionally integrated, high-performance, and low-cost chip products. This significant advantage has made three-dimensional packaged chips gain attention from academia and engineering, and related products have gradually moved from laboratories to market applications.

[0003] As "Moore's Law" gradually fails, the traditional technical route of improving chip performance by increasing the two-dimensional density of transistors has encountered a bottleneck. Therefore, three-dimensional integrated packaging based on through-silicon-vias (TSV) structure came into being. Three-dimensional integrated packaging integrates wafers in the vertical direction through TSV, thereby achieving packaged chips with smaller size, higher bandwidth, lower latency and higher performance. With the diversification of chip functions, heterogeneous integration is also the main route for the development of semiconductor technology in the post-Moore era. Therefore, the integration of three-dimensional integrated packaging and heterogeneous integration will be an important development direction for high-performance chips in the future. As one of the typical and key structures of three-dimensional integrated packaging, TSV undertakes energy, signal path and mechanical support functions in the chip. Its reliability directly affects the performance and service life of the chip, so it needs to be scientifically, comprehensively and accurately tested and evaluated for reliability.

[0004] However, for heterogeneous chips, the distribution of TSVs will show different distributions according to their functional requirements, which means that the degradation stresses on TSVs in different positions are also different, which directly leads to huge differences in the performance and service life of different TSVs. This shows that the layout of TSVs in heterogeneous chips and the presence or absence of redundant structures have an important impact on the reliability of the chip. The current research on the reliability of TSV structures is mainly based on finite element thermal simulation, supplemented by experimental research. The few experimental studies designed dedicated TSV test chips, but did not pay attention to the heterogeneity of the TSV interconnection structure in the chip, which has great limitations in evaluating the reliability of heterogeneous three-dimensional integrated chips. Summary of the invention

[0005] The object of the present invention is to provide a heterogeneous TSV chip reliability test device based on wire bonding.

[0006] To achieve the above-mentioned invention object, the present invention provides a heterogeneous TSV chip reliability test device based on wire bonding, comprising: a heterogeneous TSV chip, a chip fixture, a test PCB board and a test unit; The heterogeneous TSV chip is detachably mounted on the chip fixture; The chip fixture is detachably mounted on the test PCB board; The test PCB is detachably mounted on the test unit, and the test PCB is electrically connected to the test unit; The heterogeneous TSV chip is connected to the test PCB board by wire bonding; The heterogeneous TSV chip includes: a silicon substrate and a plurality of TSV test link groups arranged on the silicon substrate; The silicon substrate is provided with a plurality of test blocks, and each of the test blocks is provided with at least one TSV test link group; The TSV test link group includes a plurality of TSV test links, and the link types of the plurality of TSV test links are different; The number of TSV structures included in the TSV test links of the same type is different between different test blocks; Three wire bonding parts are arranged in each of the TSV test links, and the TSV test links are selectively wire-bonded with pads of the test PCB board based on the wire bonding parts and using a Kelvin chain four-wire test method.

[0007] According to one aspect of the present invention, the TSV test link comprises: a central TSV structure and a surrounding TSV structure; There are a plurality of peripheral TSV structures, and the plurality of peripheral TSV structures are regularly distributed on a circle with the central TSV structure as the center.

[0008] According to one aspect of the present invention, a plurality of first TSV test link groups are provided in a first test block of the silicon substrate; The first TSV structure pitches adopted by the first TSV test links in different first TSV test link groups are different; A plurality of second TSV test link groups are arranged in a second test block of the silicon substrate; The second TSV structure pitches adopted by the second TSV test links in different second TSV test link groups are the same or different; The second central TSV structure of the second TSV test link in the second TSV test link group is an interconnection redundant structure formed by multiple TSV structures; The number of TSV structures included in the second central TSV structures of different second TSV test link groups is different; A plurality of third TSV test link groups are arranged in a third test block of the silicon substrate; The third TSV structure pitches adopted by the third TSV test links in different third TSV test link groups are the same or different; A third surrounding TSV structure in the third TSV test link of the third TSV test link group is an interconnection redundant structure formed by multiple TSV structures; In different third TSV test link groups, the number of TSV structures included in the third surrounding TSV structures using the interconnection redundant structure is different; A plurality of fourth TSV test link groups are arranged in a fourth test block of the silicon substrate; The fourth TSV structure pitches adopted by the fourth TSV test links in different fourth TSV test link groups are the same or different; The fourth central TSV structure and the fourth peripheral TSV structure of the fourth TSV test link of the fourth TSV test link group are interconnected redundant structures formed by multiple TSV structures; In different fourth TSV test link groups, the number of TSV structures included in the fourth central TSV structure and the fourth peripheral TSV structure using the interconnection redundant structure is different.

[0009] According to one aspect of the present invention, the second TSV structure pitches used by the second TSV test links of the plurality of second TSV test link groups are the same, the third TSV structure pitches used by the third TSV test links of the plurality of third TSV test link groups are the same, the fourth TSV structure pitches used by the fourth TSV test links of the plurality of fourth TSV test link groups are the same, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitch of the same first TSV test link; or, The second TSV structural pitches adopted by the second TSV test links of the plurality of second TSV test link groups are different, the third TSV structural pitches adopted by the third TSV test links of the plurality of third TSV test link groups are different, the fourth TSV structural pitches adopted by the fourth TSV test links of the plurality of fourth TSV test link groups are different, and the second TSV structural pitch, the third TSV structural pitch and the fourth TSV structural pitch are set based on the first TSV structural pitches of different first TSV test links.

[0010] According to one aspect of the present invention, the TSV test link further comprises: a top electrode and a bottom electrode; The top electrode and the bottom electrode are electrically connected to the central TSV structure and the surrounding TSV structure contained in each TSV test link based on the link type of the TSV test link; The three wire bonding parts are arranged in one-to-one correspondence with the test points of the TSV test link, and the wire bonding parts are arranged on the upper side of the corresponding top electrodes; One of the three wire bonding portions corresponds to the central TSV structure of the TSV test link, and the other wire bonding portions selectively correspond to the peripheral TSV structures.

[0011] According to one aspect of the present invention, the silicon substrate comprises: a silicon substrate, an oxide layer disposed on the upper side of the silicon substrate, an upper dielectric layer disposed on the upper side of the oxide layer, a lower first dielectric layer disposed on the lower side of the silicon substrate, and a lower second dielectric layer disposed on the lower side of the lower first dielectric layer; The top electrode is arranged between the upper dielectric layer and the oxide layer; The bottom electrode is disposed between the lower first dielectric layer and the lower second dielectric layer.

[0012] According to one aspect of the present invention, the chip fixture is in the form of a regular plate as a whole, and is provided with a chip mounting hole penetrating the body thereof; The chip mounting hole is a stepped hole; The heterogeneous TSV chip is detachably mounted in the chip mounting hole, wherein a transition fit is adopted between the heterogeneous TSV chip and the chip mounting hole.

[0013] According to one aspect of the present invention, the test PCB board is a regular board as a whole; The test PCB board is provided with a fixture installation area, a test area and a fixed installation area; The pads are regularly arranged around the fixture mounting area; At least one test area is provided on the test PCB board, and the test area is electrically connected to the pad; The test area is provided with a plurality of test points corresponding one to one with the pads; Along the circumference of the test PCB board, a plurality of fixed installation areas are provided, and each of the fixed installation areas is provided with a fixed installation structure for fixing the test PCB board body; The chip fixture is detachably connected to the fixture mounting area.

[0014] According to one aspect of the present invention, the fixture installation area is configured as a through hole penetrating the test PCB board or as a groove opening at one side of the test PCB board, wherein the chip fixture (2) transitionally matches the through hole or groove of the fixture installation area (3b); The fixed installation structure is a through hole.

[0015] According to one aspect of the present invention, the test unit comprises: A temperature and humidity test chamber, used for applying temperature stress and humidity stress to the heterogeneous TSV chip; A vibration table, used for applying vibration stress to the heterogeneous TSV chip; A power supply and signal generator, used to apply electrical stress to the heterogeneous TSV chip; A signal acquisition device, electrically connected to the test PCB board, for collecting electrical signals; The vibration table is installed in the temperature and humidity test box; The test PCB board is installed on the vibration table based on the fixed installation area.

[0016] According to a solution of the present invention, this solution can not only realize single stress loading test, but also conveniently and comprehensively realize multi-stress (temperature, current / voltage, humidity, vibration) loading on actual heterogeneous TSV chips, thereby realizing scientific, comprehensive and accurate evaluation of the reliability of TSV structure through experimental means.

[0017] According to a solution of the present invention, the heterogeneous TSV chip of this solution can realize the individual or combined lead-out of any TSV structure through the wire bonding part on one side, has a flexible and changeable test sample volume, and has the characteristics of low cost, high flexibility and modularity, and can provide a hardware basis for the reliability test and evaluation of the TSV structure.

[0018] According to a solution of the present invention, by setting electrodes on TSV, not only can diversified connections of multiple TSV structures be achieved, but also the lead-out of TSV structures can be conveniently achieved by wire bonding, which provides effective guarantee for the flexible testing of the present invention.

[0019] According to a solution of the present invention, the problem of difficulty in chip reliability testing based on wire bonding is effectively solved, and the test is stable, reliable, flexible and diverse, with low cost and high test efficiency.

[0020] According to a solution of the present invention, the heterogeneous TSV chip of the present invention can selectively implement multi-stress testing on a single TSV and multiple TSV links.

[0021] According to one solution of the present invention, during the implementation of the test, the natural frequency of the test device can be adjusted and corrected to meet the vibration test needs and improve the test flexibility and applicability of the solution.

[0022] According to one solution of the present invention, during the testing process, the present invention implements online testing of the electrical performance of different test loops based on the Kelvin chain four-wire test method, thereby clarifying the impact of factors such as TSV quantity, layout, and redundant structure on TSV reliability, and providing necessary calibration data and reference basis for the optimized design of heterogeneous TSV chips.

[0023] According to a solution of the present invention, the present invention provides more test ports to realize online testing of different TSV links, which can greatly improve the test efficiency while ensuring the consistency of the service environment; at the same time, the present invention provides TSV test links under a variety of distribution parameter combinations, which can directly clarify the direct impact of different distribution parameters on TSV reliability based on reliability testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a perspective view schematically showing a heterogeneous TSV chip according to an embodiment of the present invention; Figure 2 Schematically represents the distribution of heterogeneous TSV chips on a wafer, wherein (a) represents the link layout of the heterogeneous TSV chip, and (b) represents the TSV structure distribution diagram in the heterogeneous TSV chip; Figure 3 is a three-dimensional structural diagram schematically showing a TSV test link according to an embodiment of the present invention; Figure 4 is a diagram schematically showing a test block distribution diagram of a heterogeneous TSV chip according to an embodiment of the present invention; Figure 5 is a cross-sectional view schematically showing a heterogeneous TSV chip according to an embodiment of the present invention; Figure 6 is a structural diagram schematically showing a chip clamp according to an embodiment of the present invention; Figure 7is a schematic diagram showing a combined installation structure of a heterogeneous TSV chip and a chip fixture according to an embodiment of the present invention; Figure 8 is a structural diagram schematically showing a test PCB board according to an embodiment of the present invention; Fig. 9 Schematically shows a combined installation structure diagram of a heterogeneous TSV chip, a chip fixture and a test PCB board according to an embodiment of the present invention; Fig.10 FIG. 1 is a diagram schematically showing a connection structure between a wire bonding portion and a pad according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] When describing the embodiments of the present invention, the orientation or positional relationship expressed by the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or positional relationship shown in the relevant drawings and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0027] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments cannot be described one by one here, but the embodiments of the present invention are not therefore limited to the following embodiments.

[0028] Combination Figure 1 , Figure 2 , Figure 3 and Figure 4As shown, according to an embodiment of the present invention, a heterogeneous TSV chip reliability test device based on wire bonding of the present invention comprises: a heterogeneous TSV chip 1, a chip fixture 2, a test PCB board 3 and a test unit; in this embodiment, the heterogeneous TSV chip 1 is detachably mounted on the chip fixture 2; the chip fixture 2 is detachably mounted on the test PCB board 3; the test PCB board 3 is detachably mounted on the test unit, and the test PCB board 3 is electrically connected to the test unit; wherein, the heterogeneous TSV chip 1 is wire-bonded to the test PCB board 3. In this embodiment, the heterogeneous TSV chip 1 includes: a silicon substrate 11 and a plurality of TSV test link groups 12 arranged on the silicon substrate 11; wherein, a plurality of test blocks are arranged on the silicon substrate 11, and each test block is provided with at least one TSV test link group 12; further, the TSV test link group 12 has a plurality of TSV test links 12a, and the link types of the plurality of TSV test links 12a are different; wherein, the TSV test links 12a in a TSV test link group 12 can be set to four, so as to correspond to four link types respectively, which is specifically: 2, 4, 6, and 8 surrounding TSV structures are evenly arranged on the circumference of a circle with a central TSV structure as the center; of course, the TSV test links 12a in each TSV test link group 12 can also be set to other numbers, such as five, six, etc., so as to correspond to the increase or decrease of corresponding link types respectively.

[0029] In this embodiment, the area of ​​each test block can be allocated according to the number of arranged TSV test link groups 12, the number and distribution of TSV test links 12a. For example, four test blocks are arranged on the silicon substrate 11, which are: a first test block A, a second test block B, a third test block C and a fourth test block D; accordingly, according to the specific number and distribution of TSV test links 12a, the area of ​​the first test block A can be divided into the largest, while the areas of the second test block B and the third test block C can be divided into the same, and the area of ​​the fourth test block D is the smallest, wherein the TSV test link 12a in the first test block A, the second test block B, the third test block C and the fourth test block D has the smallest area. The number of 2a is set in a ratio of 4:2:2:1, so that a sufficient number of TSV test links 12a are provided in the first test block A, which can be used to fully clarify the influence of the TSV structure pitch and the number of surrounding TSV structures on the reliability of the central TSV structure; the second test block B is used to clarify the influence of the number of surrounding TSV structures on the reliability of the central TSV structure under different redundancy forms; the third test block C is used to clarify the influence of the number of surrounding TSV structures and the surrounding TSV structures under different redundancy forms on the reliability of the central TSV structure; the fourth test block D is used to clarify the influence of the number of different surrounding TSV structures and the redundancy forms on the reliability of the central TSV structure with different redundancy forms.

[0030] Therefore, through the above-mentioned chip structure, each test block can have different effects. Therefore, for each test block, there is no need to repeatedly set the other three types of pitches in the first test block A, so as to realize the analysis of all the above-mentioned influencing factors, which effectively reduces the complexity of the chip structure of the present invention.

[0031] In this embodiment, the number of TSV structures included in the TSV test link 12a of the same type is different between different test blocks. For example, the number of TSV structures included in the TSV test link 12a of the same type between the first test block A and the second test block B is different, the number of TSV structures included in the TSV test link 12a of the same type between the second test block B and the third test block C is different, and the number of TSV structures included in the TSV test link 12a of the same type between the third test block C and the fourth test block D is different.

[0032] In this embodiment, three wire bonding parts 12aI are provided in each TSV test link 12a, and the TSV test link 12a is selectively wire-bonded with the pad 3a of the test PCB board 3 based on the wire bonding part 12aI and using the Kelvin chain four-wire test method.

[0033] Combination Figure 2 , Figure 3 and Figure 4 As shown, according to an embodiment of the present invention, the TSV test link 12a includes: a central TSV structure 12a1 and a surrounding TSV structure 12a2; wherein, there are multiple surrounding TSV structures 12a2, and the multiple surrounding TSV structures 12a2 are regularly distributed on the circumference of a circle with the central TSV structure 12a1 as the center; specifically, the multiple surrounding TSV structures 12a2 are distributed at equal intervals on the circumference of a circle with the central TSV structure 12a1 as the center.

[0034] To further facilitate the description of the present solution, the TSV test link groups 12 on each test block may be named respectively, wherein the TSV test link group 12 on the first test block A is named the first TSV test link group 12A, the TSV test link 12a in the first TSV test link group 12A is named the first TSV test link 12aA, the central TSV structure 12a1 in the first TSV test link 12aA is named the first central TSV structure 12a1A, and the surrounding TSV structure 12a2 in the first TSV test link 12aA is named the first surrounding TSV structure 12a2A; The TSV test link group 12 on the second test block B is named as the second TSV test link group 12B, the TSV test link 12a in the second TSV test link group 12B is named as the second TSV test link 12aB, the central TSV structure 12a1 in the second TSV test link 12aB is named as the second central TSV structure 12a1B, and the surrounding TSV structure 12a2 in the second TSV test link 12aB is named as the second surrounding TSV structure 12a2B; The TSV test link group 12 on the third test block C is named as a third TSV test link group 12C, the TSV test link 12a in the third TSV test link group 12C is named as a third TSV test link 12aC, the central TSV structure 12a1 in the third TSV test link 12aC is named as a third central TSV structure 12a1C, and the surrounding TSV structure 12a2 in the third TSV test link 12aC is named as a third surrounding TSV structure 12a2C; The TSV test link group 12 on the fourth test block D is named a fourth TSV test link group 12D, the TSV test link 12a in the fourth TSV test link group 12D is named a fourth TSV test link 12aD, the central TSV structure 12a1 in the fourth TSV test link 12aD is named a fourth central TSV structure 12a1D, and the surrounding TSV structure 12a2 in the fourth TSV test link 12aD is named a fourth surrounding TSV structure 12a2D.

[0035] Combination Figure 2 and Figure 4 As shown, according to one embodiment of the present invention, a plurality of first TSV test link groups 12A are arranged in the first test block A of the silicon substrate 11; wherein, four first TSV test link groups 12A are arranged in the first test block A, and each first TSV test link group 12A contains four first TSV test links 12aA of different types. In this embodiment, the first TSV structure pitches used by the first TSV test links 12aA in different first TSV test link groups 12A are different; specifically, between different first TSV test link groups 12A, the same type of first TSV test links 12aA can achieve flexible control of their first TSV structure pitches by controlling the radius of the circle of the first surrounding TSV structure 12a2A around the first central TSV structure 12a1A, wherein the first TSV structure pitches between adjacent first TSV test link groups 12A are arranged in a sequentially increasing manner, and the first TSV structure pitches selected in each first TSV test link group 12A are set according to actual measurement needs, as long as no interference occurs, and will not be repeated here.

[0036] Combination Figure 2 and Figure 4 As shown, according to an embodiment of the present invention, a plurality of second TSV test link groups 12B are provided in the second test block B of the silicon substrate 11; wherein, two second TSV test link groups 12B are provided in the second test block B, and each second TSV test link group 12B contains four different types of second TSV test links 12aB, and the four types of the second TSV test links 12aB are consistent with the four types of the first TSV test links 12aA. Accordingly, the second TSV structure pitches used by the second TSV test links 12aB in different second TSV test link groups 12B are the same or different.

[0037] In this embodiment, the second central TSV structure 12a1B of the second TSV test link 12aB in the second TSV test link group 12B is an interconnected redundant structure composed of multiple TSV structures; wherein the number of TSV structures included in the second central TSV structure 12a1B of different second TSV test link groups 12B is different; specifically, the second central TSV structure 12a1B in one second TSV test link group 12B adopts an interconnected redundant structure composed of two TSV structures, and the second central TSV structure 12a1B in another second TSV test link group 12B adopts an interconnected redundant structure composed of four TSV structures. In this embodiment, in order to facilitate the reliable connection of multiple TSV structures, regular metal plates can be correspondingly set at the ends of multiple TSV structures to achieve mutual interconnection redundancy. If the metal electrode needs to be connected at the end of the TSV structure, the regular metal plate can be set together with the metal electrode. If the metal electrode does not need to be connected at the end of the TSV structure, the regular metal plate is set independently. When an interconnection redundant structure consisting of two TSV structures is adopted, the regular metal plate used is an oblong metal plate. If an interconnection redundant structure consisting of four TSV structures is adopted, the regular metal plate used is a circular metal plate. This can facilitate the unification of the layout positions between adjacent TSV structures in each interconnection redundant structure.

[0038] Combination Figure 2 and Figure 4 As shown, according to an embodiment of the present invention, a plurality of third TSV test link groups 12C are provided in the third test block C of the silicon substrate 11; wherein, two third TSV test link groups 12C are provided in the third test block C, and each third TSV test link group 12C contains four third TSV test links 12aC of different types, and the four types of the third TSV test links 12aC are consistent with the four types of the first TSV test links 12aA. Accordingly, the third TSV structure pitches adopted by the third TSV test links 12aC in different third TSV test link groups 12C are the same or different.

[0039] In this embodiment, a third surrounding TSV structure 12a2C in the third TSV test link 12aC of the third TSV test link group 12C is an interconnected redundant structure composed of multiple TSV structures; for example, the second third surrounding TSV structure 12a2C in the clockwise direction along the port of the third TSV test link 12aC is set as a redundant structure. Of course, other third surrounding TSV structures 12a2C can also be set as redundant structures, but the control of a single variable (redundant form, redundant number, and redundant position) must be guaranteed. Among them, in different third TSV test link groups 12C, the number of TSV structures contained in the third surrounding TSV structure 12a2C using an interconnected redundant structure is different. Specifically, the third surrounding TSV structure 12a2C in one third TSV test link group 12C adopts an interconnected redundant structure composed of two TSV structures, and the third surrounding TSV structure 12a2C in another third TSV test link group 12C adopts an interconnected redundant structure composed of four TSV structures. In this embodiment, in order to facilitate the reliable connection of multiple TSV structures, regular metal plates can be correspondingly set at the ends of multiple TSV structures to achieve mutual interconnection redundancy. If the metal electrode needs to be connected at the end of the TSV structure, the regular metal plate can be set together with the metal electrode. If the metal electrode does not need to be connected at the end of the TSV structure, the regular metal plate is set independently. When an interconnection redundant structure consisting of two TSV structures is adopted, the regular metal plate used is an oblong metal plate. If an interconnection redundant structure consisting of four TSV structures is adopted, the regular metal plate used is a circular metal plate. This can facilitate the unification of the layout positions between adjacent TSV structures in each interconnection redundant structure.

[0040] Combination Figure 2 and Figure 4 As shown, according to an embodiment of the present invention, a plurality of fourth TSV test link groups 12D are provided in the fourth test block D of the silicon substrate 11; wherein, two fourth TSV test link groups 12D are provided in the fourth test block D, and each fourth TSV test link group 12D contains two fourth TSV test links 12aD of different types, and the two types of the fourth TSV test links 12aD are selected based on the four types of the first TSV test links 12aA. Accordingly, the fourth TSV structure pitches adopted by the fourth TSV test links 12aD in different fourth TSV test link groups 12D are the same or different.

[0041] In this embodiment, the fourth central TSV structure 12a1D and a fourth peripheral TSV structure 12a2D of the fourth TSV test link 12aD of the fourth TSV test link group 12D are respectively interconnected redundant structures composed of multiple TSV structures; for example, the second fourth peripheral TSV structure 12a2D clockwise along the port of the fourth TSV test link 12aD is set as a redundant structure. Of course, other fourth peripheral TSV structures 12a2D can also be set as redundant structures, but the control of a single variable (redundant form, redundant quantity, and redundant position) must be guaranteed. Among them, in different fourth TSV test link groups 12D, the number of TSV structures contained in the fourth central TSV structure 12a1D and the fourth peripheral TSV structure 12a2D using the interconnected redundant structure is different. Specifically, the fourth central TSV structure 12a1D and the fourth surrounding TSV structure 12a2D in a fourth TSV test link group 12D both adopt an interconnection redundant structure composed of two TSV structures, and the fourth central TSV structure 12a1D and the fourth surrounding TSV structure 12a2D in another fourth TSV test link group 12D both adopt an interconnection redundant structure composed of four TSV structures. In this embodiment, in order to facilitate the reliable connection of multiple TSV structures, regular metal plates can be correspondingly arranged at the ends of multiple TSV structures to achieve mutual interconnection redundancy, wherein, if the metal electrode needs to be connected at the end of the TSV structure, the regular metal plate can be arranged integrally with the metal electrode, and if the metal electrode does not need to be connected at the end of the TSV structure, the regular metal plate is independently arranged, wherein, when the interconnection redundant structure composed of two TSV structures is adopted, the regular metal plate adopted is an oblong metal plate, and if the interconnection redundant structure composed of four TSV structures is adopted, the regular metal plate adopted is a circular metal plate, thereby facilitating the unification of the arrangement positions between adjacent TSV structures in each interconnection redundant structure.

[0042] Combination Figure 2 and Figure 4 As shown, according to an embodiment of the present invention, the second TSV structure pitches used by the second TSV test links 12aB of the plurality of second TSV test link groups 12B are the same, the third TSV structure pitches used by the third TSV test links 12aC of the plurality of third TSV test link groups 12C are the same, the fourth TSV structure pitches used by the fourth TSV test links 12aD of the plurality of fourth TSV test link groups 12D are the same, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitch of the same first TSV test link 12aA; In another embodiment, the second TSV structure pitch adopted by the second TSV test link 12aB of multiple second TSV test link groups 12B is different, the third TSV structure pitch adopted by the third TSV test link 12aC of multiple third TSV test link groups 12C is different, and the fourth TSV structure pitch adopted by the fourth TSV test link 12aD of multiple fourth TSV test link groups 12D is different, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitch of different first TSV test links 12aA, wherein the selected first TSV test link 12aA can be set according to specific actual needs, which will not be repeated here.

[0043] Combination Figure 3 and Figure 5 As shown, according to one embodiment of the present invention, the TSV test link 12a also includes: a top electrode 12a3 and a bottom electrode 12a4; wherein the top electrode 12a3 and the bottom electrode 12a4 are electrically connected to the central TSV structure 12a1 and the surrounding TSV structure 12a2 contained therein based on the link type of each TSV test link 12a; three wire bonding parts 12aI are arranged in one-to-one correspondence with the measuring points of the TSV test link 12a, and the wire bonding parts 12aI are arranged on the upper side of the corresponding top electrode 12a3; one of the three wire bonding parts 12aI corresponds to the central TSV structure 12a1 of the TSV test link 12a, and the remaining wire bonding parts 12aI selectively correspond to the surrounding TSV structures 12a2, for example, the remaining wire bonding parts 12aI are selected to be arranged at the surrounding TSV structures 12a2 at the head and tail of the corresponding TSV test link 12a.

[0044] In this embodiment, the wire bonding part 12aI is a long strip of metal, which includes: a first bonding part and a second bonding part fixed to each other; wherein the first bonding part and the second bonding part are both long strips, and the second bonding part is arranged at one end of the first bonding part perpendicular to the first bonding part; in this embodiment, the end of the first bonding part away from the second bonding part is electrically connected to the selected TSV structure. In this embodiment, if the TSV structure on which the wire bonding part 12aI is installed adopts a redundant structure, the wire bonding part 12aI is installed on the symmetry axis of the corresponding regular metal plate to achieve a balance relative to the position of each TSV structure; wherein the wire bonding part 12aI is welded to the regular metal plate. Further, in order to achieve accurate and reliable relative position during installation, a corresponding embedding groove can be set on the regular metal plate, thereby, the wire bonding part 12aI can be welded to each other in a manner of cooperating with the embedding groove to avoid slippage and deviation of the wire bonding part 12aI during welding.

[0045] like Figure 5 As shown, according to one embodiment of the present invention, the silicon substrate 11 includes: a silicon base 111, an oxide layer 112 arranged on the upper side of the silicon base 111, an upper dielectric layer 113 arranged on the upper side of the oxide layer 112, a lower first dielectric layer 114 arranged on the lower side of the silicon base 111, and a lower second dielectric layer 115 arranged on the lower side of the lower first dielectric layer 114; in this embodiment, the top electrode 12a3 is arranged between the upper dielectric layer 113 and the oxide layer 112; the bottom electrode 12a4 is arranged between the lower first dielectric layer 114 and the lower second dielectric layer 115.

[0046] like Figure 2 As shown, according to one embodiment of the present invention, the heterogeneous TSV chip 1 of the present invention is prepared based on 8-inch wafer tape-out, and is distributed on the wafer in a rectangular arrangement, wherein the heterogeneous TSV chip 1 adopts a square structure with a side length of L chip , the distance between them is L t , the diameter of the TSV structure is D TSV .

[0047] Combination Figure 6 and Figure 7 As shown, according to one embodiment of the present invention, the chip fixture 2 is in the form of a regular plate as a whole, and a chip mounting hole 2a is provided on the chip fixture 2 that passes through the body thereof. In this embodiment, the chip fixture 2 is in the form of a square as a whole, and the chip mounting hole 2a is arranged coaxially with the chip fixture 2 at the center of the chip fixture 2. Among them, the chip mounting hole 2a is a stepped hole; wherein the chip mounting hole 2a includes a first mounting hole portion and a second mounting hole portion which are coaxially arranged, the outer dimensions of the first mounting hole portion are matched with the outer dimensions of the heterogeneous TSV chip 1, and the outer dimensions of the second mounting hole portion are smaller than the outer dimensions of the heterogeneous TSV chip 1, and then a step for the heterogeneous TSV chip 1 to contact is formed at the position where the first mounting hole portion and the second mounting hole portion are connected, thereby realizing the detachable installation of the heterogeneous TSV chip 1 in the chip mounting hole 2a, wherein a transition fit is adopted between the heterogeneous TSV chip 1 and the chip mounting hole 2a, thereby achieving a gap-free fit between the structures to ensure the stability of the test structure during the test process (various load loading processes); further, the detachable connection method between the heterogeneous TSV chip 1 and the chip mounting hole 2a can be further combined with a threaded connection or a snap-on connection to achieve a stable connection.

[0048] In this embodiment, the structural dimension parameters of the chip fixture 2 can be seen in Table 1.

[0049] Table 1

[0050] Combination Figure 8 and Fig. 9 As shown, according to an embodiment of the present invention, the test PCB board 3 is a regular plate body as a whole; specifically, the test PCB board 3 is provided with a fixture installation area 3b, a test area 3c and a fixed installation area 3d; wherein the pads 3a are regularly arranged around the fixture installation area 3b. In this embodiment, at least one test area 3c is provided on the test PCB board 3, and the test area 3c is electrically connected to the pads 3a; in this embodiment, the test area 3c can be set to four, and then, it can be evenly distributed around the fixture installation area 3b, so as to facilitate the connection with the pads 3a around the fixture installation area 3b; wherein, the test area 3c is provided with a plurality of test points corresponding to the pads 3a one by one, and then, when the test PCB board 3 is electrically connected to the test unit, it can be connected to the test points on the test area 3c based on the wire, which effectively avoids the difficulty of directly connecting with the wire bonding part 12aI in the TSV test link 12a. Furthermore, multiple fixed installation areas 3d are provided along the circumference of the test PCB board 3, and the fixed installation areas 3d are respectively provided with fixed installation structures for fixing the main body of the test PCB board 3; the fixed installation structure provided can conveniently realize the fixed installation of the test PCB board 3, thereby improving the testing convenience of this solution.

[0051] In this embodiment, the chip clamp 2 is detachably connected to the clamp mounting area 3b.

[0052] Combination Figure 8 and Fig. 9 As shown, according to an embodiment of the present invention, the fixture installation area 3b is set as a through hole penetrating the test PCB board 3 or as a groove opening on one side of the test PCB board 3; wherein, the size of the fixture installation area 3b is set to match the heterogeneous TSV chip 1, thereby, the accurate installation of the chip fixture 2 can be achieved. In this embodiment, if the fixture installation area 3b is set as a through hole penetrating the test PCB board 3, the through hole can also be set as a stepped hole, and the chip fixture 2 can be accurately limited by the bearing limit of the chip fixture 2 and the stepped hole; similarly, if the fixture installation area 3b is set as a groove, the chip fixture 2 can also be accurately fixed. Among them, a transition fit is adopted between the chip fixture 2 and the fixture installation area 3b, thereby, there is no gap fit between the structures to ensure the stability of the test structure during the test process (various load loading processes), and further, the detachable connection method of the chip fixture 2 and the fixture installation area 3b can be further combined with the threaded connection and the snap connection method to achieve a stable connection.

[0053] In this embodiment, the fixed installation structure is a through hole. By setting the fixed installation structure as a through hole, it is convenient for fasteners such as threaded connectors to pass through, so as to achieve fixed installation of the test PCB board 3.

[0054] According to one embodiment of the present invention, the test unit includes: a temperature and humidity test chamber, a vibration table, a power supply and a signal generator, and a signal acquisition device; wherein the temperature and humidity test chamber is used to load temperature stress and humidity stress on the heterogeneous TSV chip 1; the vibration table is used to load vibration stress on the heterogeneous TSV chip 1; the power supply and the signal generator are used to load electrical stress on the heterogeneous TSV chip 1; the signal acquisition device is electrically connected to the test PCB board 3 for collecting electrical signals; in this embodiment, the vibration table is installed in the temperature and humidity test chamber; the test PCB board 3 is installed on the vibration table based on the fixed installation area 3d.

[0055] Through the above settings, this solution can conveniently implement single stress loading or multi-stress combination loading on the heterogeneous TSV chip 1 through the set test unit, which effectively improves the test comprehensiveness of this solution.

[0056] To further illustrate this solution, the test process of this solution is further described in conjunction with the accompanying drawings.

[0057] (1) Clarify the test objectives, i.e., determine multiple stress types (such as at least one of temperature, humidity, electrical stress, and vibration) and load parameters (such as temperature range and loading cycle, humidity range and loading cycle, electrical stress range and loading cycle, vibration evaluation rate range and vibration magnitude), and the TSV test link (test object) of the heterogeneous TSV chip 1; (2) Connect the wire bonding portion 12a1 of the determined TSV test link to the corresponding pad 3a of the test PCB 3 by wire bonding (see Fig.10 ), and connect the test points of the corresponding test area 3c on the test PCB board 3 to the corresponding modules of the test unit (such as power supply and signal generator and / or signal acquisition device) through high temperature resistant silicone wires; (3) The test PCB board 3 is mounted on a vibration table, and vibration tests, temperature stress tests, humidity stress tests, electrical stress tests, etc. are performed on the test PCB board 3, the chip fixture 2, and the heterogeneous TSV chip 1 assembly to achieve reliability testing and analysis under multiple stress states.

[0058] Through the above configuration, the overall structure composed of the heterogeneous TSV chip 1, the chip fixture 2, and the test PCB board 3 in the present invention can conveniently realize multi-stress loading, and thus can conveniently and flexibly realize multi-stress reliability testing. Among them, the heterogeneous TSV chip 1 can be mounted on the chip fixture 2 as a bare chip, and its upper and lower surfaces can be conveniently exposed in the test environment, fully enabling the reliability test of the entire heterogeneous TSV chip 1 in a multi-stress environment.

[0059] The above contents are merely examples of specific solutions of the present invention. For devices and structures not described in detail therein, it should be understood that they can be implemented by adopting general devices and general methods available in the art.

[0060] The above is only one solution of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A reliability test device for heterogeneous TSV chips based on wire bonding, characterized in that: include: Heterogeneous TSV chip (1), chip fixture (2), test PCB board (3) and test unit; The heterogeneous TSV chip (1) is detachably mounted on the chip fixture (2); The chip fixture (2) is detachably mounted on the test PCB board (3); The test PCB board (3) is detachably mounted on the test unit, and the test PCB board (3) is electrically connected to the test unit; The heterogeneous TSV chip (1) is connected to the test PCB board (3) by wire bonding; The heterogeneous TSV chip (1) comprises: a silicon substrate (11) and a plurality of TSV test link groups (12) arranged on the silicon substrate (11); The silicon substrate (11) is provided with a plurality of test blocks, and each of the test blocks is provided with at least one TSV test link group (12); The TSV test link group (12) comprises a plurality of TSV test links (12a), and the link types of the plurality of TSV test links (12a) are different; The number of TSV structures included in the TSV test link (12a) of the same type is different between different test blocks; Three wire bonding parts (12aI) are arranged in each of the TSV test links (12a), and the TSV test links (12a) are selectively wire bonded to pads (3a) of the test PCB board (3) based on the wire bonding parts (12aI) and using a Kelvin chain four-wire test method.

2. The heterogeneous TSV chip reliability test device according to claim 1, characterized in that: The TSV test link (12a) comprises: a central TSV structure (12a1) and a peripheral TSV structure (12a2); There are a plurality of peripheral TSV structures (12a2), and the plurality of peripheral TSV structures (12a2) are regularly distributed on a circle with the central TSV structure (12a1) as the center.

3. The heterogeneous TSV chip reliability test device according to claim 2, characterized in that: A plurality of first TSV test link groups (12A) are arranged in a first test block of the silicon substrate (11); The first TSV structure pitches adopted by the first TSV test links (12aA) in different first TSV test link groups (12A) are different; A plurality of second TSV test link groups (12B) are arranged in a second test block of the silicon substrate (11); The second TSV structure pitches adopted by the second TSV test links (12aB) in different second TSV test link groups (12B) are the same or different; The second central TSV structure (12a1B) of the second TSV test link (12aB) in the second TSV test link group (12B) is an interconnection redundant structure formed by a plurality of TSV structures; The number of TSV structures included in the second central TSV structures (12a1B) of different second TSV test link groups (12B) is different; A plurality of third TSV test link groups (12C) are arranged in a third test block of the silicon substrate (11); The third TSV structure pitches adopted by the third TSV test links (12aC) in different third TSV test link groups (12C) are the same or different; A third surrounding TSV structure (12a2C) in the third TSV test link (12aC) of the third TSV test link group (12C) is an interconnection redundant structure formed by a plurality of TSV structures; In different third TSV test link groups (12C), the number of TSV structures included in the third surrounding TSV structure (12a2C) with an interconnection redundant structure is different; A plurality of fourth TSV test link groups (12D) are arranged in a fourth test block of the silicon substrate (11); The fourth TSV structure pitches adopted by the fourth TSV test links (12aD) in different fourth TSV test link groups (12D) are the same or different; The fourth central TSV structure (12a1D) and a fourth peripheral TSV structure (12a2D) of the fourth TSV test link (12aD) of the fourth TSV test link group (12D) are interconnected redundant structures formed by multiple TSV structures; In different fourth TSV test link groups (12D), the number of TSV structures included in the fourth central TSV structure (12a1D) and the fourth peripheral TSV structure (12a2D) using an interconnection redundant structure is different.

4. The heterogeneous TSV chip reliability test device according to claim 3, characterized in that: The second TSV structure pitches adopted by the second TSV test links (12aB) of the plurality of second TSV test link groups (12B) are the same, the third TSV structure pitches adopted by the third TSV test links (12aC) of the plurality of third TSV test link groups (12C) are the same, the fourth TSV structure pitches adopted by the fourth TSV test links (12aD) of the plurality of fourth TSV test link groups (12D) are the same, and the second TSV structure pitch, the third TSV structure pitch and the fourth TSV structure pitch are set based on the first TSV structure pitch of the same first TSV test link (12aA); or, The second TSV structural pitches adopted by the second TSV test links (12aB) of the plurality of second TSV test link groups (12B) are different, the third TSV structural pitches adopted by the third TSV test links (12aC) of the plurality of third TSV test link groups (12C) are different, the fourth TSV structural pitches adopted by the fourth TSV test links (12aD) of the plurality of fourth TSV test link groups (12D) are different, and the second TSV structural pitch, the third TSV structural pitch and the fourth TSV structural pitch are set based on the first TSV structural pitches of different first TSV test links (12aA).

5. The heterogeneous TSV chip reliability test device according to claim 4, characterized in that: The TSV test link (12a) further comprises: a top electrode (12a3) and a bottom electrode (12a4); The top electrode (12a3) and the bottom electrode (12a4) are electrically connected to the central TSV structure (12a1) and the surrounding TSV structure (12a2) contained in each TSV test link (12a) based on the link type of the TSV test link (12a); The three wire bonding parts (12aI) are arranged in one-to-one correspondence with the test points of the TSV test link (12a), and the wire bonding part (12aI) is arranged on the upper side of the corresponding top electrode (12a3); One of the three wire bonding portions (12aI) corresponds to the central TSV structure (12a1) of the TSV test link (12a), and the remaining wire bonding portions (12aI) selectively correspond to the peripheral TSV structure (12a2).

6. The heterogeneous TSV chip reliability test device according to claim 5, characterized in that: The silicon substrate (11) comprises: a silicon substrate (111), an oxide layer (112) arranged on the upper side of the silicon substrate (111), an upper dielectric layer (113) arranged on the upper side of the oxide layer (112), a lower first dielectric layer (114) arranged on the lower side of the silicon substrate (111), and a lower second dielectric layer (115) arranged on the lower side of the lower first dielectric layer (114); The top electrode (12a3) is arranged between the upper dielectric layer (113) and the oxide layer (112); The bottom electrode (12a4) is arranged between the lower first dielectric layer (114) and the lower second dielectric layer (115).

7. The heterogeneous TSV chip reliability test device according to claim 6, characterized in that: The chip fixture (2) is in the form of a regular plate as a whole, and is provided with a chip mounting hole (2a) penetrating the body of the chip fixture (2); The chip mounting hole (2a) is a stepped hole; The heterogeneous TSV chip (1) is detachably mounted in the chip mounting hole (2a), wherein a transition fit is adopted between the heterogeneous TSV chip (1) and the chip mounting hole (2a).

8. The heterogeneous TSV chip reliability test device according to claim 7, characterized in that: The test PCB board (3) is in the form of a regular plate as a whole; The test PCB board (3) is provided with a fixture installation area (3b), a test area (3c) and a fixed installation area (3d); The solder pads (3a) are regularly arranged around the fixture installation area (3b); At least one test area (3c) is provided on the test PCB board (3), and the test area (3c) is electrically connected to the pad (3a); The test area (3c) is provided with a plurality of test points corresponding one to one with the pads (3a); A plurality of fixed installation areas (3d) are provided along the circumference of the test PCB board (3), and each of the fixed installation areas (3d) is provided with a fixed installation structure for fixing the body of the test PCB board (3); The chip clamp (2) is detachably connected to the clamp mounting area (3b).

9. The heterogeneous TSV chip reliability test device according to claim 8, characterized in that: The fixture installation area (3b) is configured as a through hole penetrating the test PCB board (3) or as a groove opening on one side of the test PCB board (3), wherein the chip fixture (2) is transitionally matched with the through hole or groove of the fixture installation area (3b); The fixed installation structure is a through hole.

10. The heterogeneous TSV chip reliability test device according to claim 9, characterized in that: The test unit comprises: A temperature and humidity test chamber, used for applying temperature stress and humidity stress to the heterogeneous TSV chip (1); A vibration table, used for applying vibration stress to the heterogeneous TSV chip (1); A power supply and signal generator, used for applying electrical stress to the heterogeneous TSV chip (1); A signal collection device, electrically connected to the test PCB board (3) and used for collecting electrical signals; The vibration table is installed in the temperature and humidity test box; The test PCB board (3) is installed on the vibration table based on the fixed installation area (3d).

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