Chip waveform de-embedding method, device, electronic device, storage medium

Abstract

The present invention discloses a chip waveform de-embedding method, device, electronic device, and storage medium, relating to the field of chip testing technology. The method comprises: soldering a first LPDDR5 chip to a first test circuit board via an adapter board; soldering a second LPDDR5 chip to a second test circuit board; acquiring the first chip waveform and the second chip waveform of the first test circuit board and the second test circuit board using an oscilloscope, and performing fast Fourier transform on the first chip waveform and the second chip waveform to obtain a first frequency domain signal and a second frequency domain signal; obtaining a first transfer function of the adapter board based on the first frequency domain signal and the second frequency domain signal; obtaining a third frequency domain signal based on the first frequency domain signal and the first transfer function; and performing an inverse Fourier transform on the third frequency domain signal to obtain the first test waveform of the LPDDR5 chip. The method according to an embodiment of the present invention can improve the accuracy of chip waveform testing.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip waveform de-embedding method, device, electronic equipment, and storage medium. Background Art

[0002] Signal testing of DDR chips requires a fixture to aid in waveform measurement. The fixture acts as an intermediary between the test circuit board and the chip under test, connecting the two. When the test circuit board is testing the chip under test, the oscilloscope probe contacts the fixture to measure the chip's waveform. However, the fixture typically contains structures such as vias and traces. This complex internal structure can cause signal loss and reflections, resulting in inaccurate measurement results due to the oscilloscope's measurement of the waveform inconsistent with the chip's actual waveform. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a chip waveform de-embedding method, device, electronic device, and storage medium, which can improve the accuracy of chip waveform measurement.

[0004] In a first aspect, a chip waveform de-embedding method according to an embodiment of the present invention includes:

[0005] Design an adapter board based on the layout of the LPDDR5 chip; the surface of the adapter board is provided with a surface pad, and the bottom surface of the adapter board is provided with a bottom pad, and the surface pad and the bottom pad are connected through a via;

[0006] Obtain a first test circuit board and a second test circuit board;

[0007] Soldering the first LPDDR5 chip to the surface pads of the adapter board, and soldering the bottom pads of the adapter board to the first test circuit board, so that the first LPDDR5 chip is connected to the first test circuit board through the adapter board;

[0008] Soldering a second LPDDR5 chip to the surface of the second test circuit board;

[0009] Acquire a first chip waveform of the first test circuit board through an oscilloscope, and perform fast Fourier transform calculation on the first chip waveform to obtain a first frequency domain signal;

[0010] Acquire a second chip waveform of the second test circuit board through an oscilloscope, and perform fast Fourier transform calculation on the second chip waveform to obtain a second frequency domain signal;

[0011] Obtaining a first transfer function of the adapter board according to the first frequency domain signal and the second frequency domain signal;

[0012] obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function;

[0013] Perform an inverse Fourier transform on the third frequency domain signal to obtain a first test waveform of the LPDDR5 chip.

[0014] According to some embodiments of the present invention, the calculation formula of the first transfer function is:

[0015] ;

[0016] in, represents the first chip waveform, represents the first frequency domain signal, represents the second chip waveform, represents the second frequency domain signal, and H represents the first transfer function.

[0017] According to some embodiments of the present invention, obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function includes:

[0018] performing an inverse operation on the first transfer function to obtain an inverse transfer function;

[0019] A convolution operation is performed on the first frequency domain signal and the inverse transfer function to obtain the third frequency domain signal.

[0020] According to some embodiments of the present invention, the method further comprises:

[0021] Import the design file of the adapter board into the simulation software and select the circuit routing to be tested;

[0022] Obtaining the S parameters of the adapter plate through the simulation software;

[0023] Inputting the S parameters into the oscilloscope, so that the oscilloscope obtains the second transfer function of the adapter board according to the S parameters;

[0024] performing a deconvolution operation on the first frequency domain signal and the second transfer function to obtain a fourth frequency domain signal;

[0025] Perform an inverse Fourier transform on the fourth frequency domain signal to obtain a second test waveform of the LPDDR5 chip.

[0026] According to some embodiments of the present invention, the method further comprises:

[0027] Calculating a first error between the first test waveform and the second chip waveform;

[0028] calculating a second error between the second test waveform and the second chip waveform;

[0029] The first test waveform or the second test waveform is determined as a final test waveform according to the first error and the second error.

[0030] According to some embodiments of the present invention, the calculation formula of the first error is:

[0031] ;

[0032] in, represents the first test waveform, represents the second chip waveform, N is the total number of samples, is the first error.

[0033] According to some embodiments of the present invention, the adapter board is a six-layer board, including a top board, four inner-layer boards, and a bottom board, the thickness of the bottom board is greater than the sum of the thicknesses of the top board and the four inner-layer boards, and a circuit is arranged in the inner-layer board; the method further includes:

[0034] Milling grooves around the bottom of the bottom plate according to a preset depth and a preset width, so that the bottom of the bottom plate serves as the lower layer, and the top of the bottom plate, the top plate, and the four inner layer plates serve as the upper layer; wherein the preset depth is less than the thickness of the bottom plate;

[0035] Four extension plates are formed on portions of the peripheral surface of the upper portion that protrude from the peripheral surface of the lower portion;

[0036] A test pad is provided on the surface of each extension plate, and a gap is formed between any two adjacent extension plates;

[0037] Lead the test points of the line routing to the surface of the adapter board and connect them to the corresponding test pads.

[0038] In the second aspect, a chip waveform de-embedding device according to an embodiment of the present invention includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the chip waveform de-embedding method as described in the embodiment of the first aspect.

[0039] In a third aspect, an electronic device according to an embodiment of the present invention includes: the chip waveform de-embedding device described in the embodiment of the second aspect.

[0040] In a fourth aspect, a storage medium according to an embodiment of the present invention stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the chip waveform de-embedding method described in the embodiment of the first aspect.

[0041] The chip waveform de-embedding method, device, electronic device, and storage medium according to the embodiments of the present invention have at least the following beneficial effects: by introducing an adapter board, it is possible to complete the test of the LPDDR5 chip and de-embed the measured waveform, thereby avoiding signal loss and reflection caused by the internal structure of the adapter board, so that the waveform measured by the oscilloscope is consistent with the actual waveform of the chip, thereby ensuring the accuracy of the measurement results.

[0042] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0044] Figure 1 A flowchart of the steps of a chip waveform de-embedding method according to an embodiment of the present invention;

[0045] Figure 2 This is a schematic structural diagram of an adapter board according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the internal wiring of the adapter board according to an embodiment of the present invention;

[0047] Figure 4 is a schematic top view of an adapter plate according to an embodiment of the present invention;

[0048] Figure 5 2 is a schematic front view of an adapter plate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. The step numbers in the following embodiments are provided only for the convenience of explanation and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0050] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0051] The terms "first," "second," "third," and "fourth," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0052] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0053] Signal testing of DDR chips requires a fixture to aid in waveform measurement. The fixture acts as an intermediary between the test circuit board and the chip under test, connecting the two. When the test circuit board is testing the chip under test, the oscilloscope probe contacts the fixture to measure the chip's waveform. However, the fixture typically contains structures such as vias and traces. This complex internal structure can cause signal loss and reflections, resulting in inaccurate measurement results due to the oscilloscope's measurement of the waveform inconsistent with the chip's actual waveform.

[0054] To this end, embodiments of the present invention provide a chip waveform de-embedding method, device, electronic device, and storage medium. These methods, when an adapter board is introduced, can not only complete the testing of the LPDDR5 chip, but also de-embed the measured waveform, thereby avoiding signal loss and reflection caused by the internal structure of the adapter board. This ensures that the waveform measured by the oscilloscope is consistent with the actual waveform of the chip, thereby ensuring the accuracy of the measurement results.

[0055] The chip waveform de-embedding method, device, electronic device, and storage medium according to the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0056] On the one hand, the embodiment of the present invention provides a chip waveform de-embedding method, such as Figure 1 As shown, the method includes the following steps:

[0057] Step S100: Designing an adapter board 100 based on the layout of the LPDDR5 chip; a surface pad 200 is provided on the surface of the adapter board 100, and a bottom pad (not shown) is provided on the bottom surface of the adapter board 100, and the surface pad 200 and the bottom pad are connected via a via;

[0058] Step S200: Acquire a first test circuit board and a second test circuit board;

[0059] Step S300: Solder the first LPDDR5 chip to the surface pads 200 of the adapter board 100, and solder the bottom pads of the adapter board 100 to the first test circuit board, so that the first LPDDR5 chip is connected to the first test circuit board through the adapter board 100;

[0060] Step S400: Soldering a second LPDDR5 chip to the surface of a second test circuit board;

[0061] Step S500: Acquire a first chip waveform of a first test circuit board through an oscilloscope, and perform fast Fourier transform calculation on the first chip waveform to obtain a first frequency domain signal;

[0062] Step S600: Acquire a second chip waveform of a second test circuit board through an oscilloscope, and perform fast Fourier transform calculation on the second chip waveform to obtain a second frequency domain signal;

[0063] Step S700: Obtaining a first transfer function of the adapter board 100 according to the first frequency domain signal and the second frequency domain signal;

[0064] Step S800: obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function;

[0065] Step S900: Perform an inverse Fourier transform on the third frequency domain signal to obtain a first test waveform of the LPDDR5 chip.

[0066] Specifically, if Figure 2 As shown, since the surface of the adapter board 100 is provided with a surface solder pad 200, the bottom surface of the adapter board 100 is provided with a bottom solder pad (not shown), and the surface solder pad 200 is connected to the bottom solder pad through a via hole, the first LPDDR5 chip is soldered to the surface solder pad 200 of the adapter board 100, and after the bottom solder pad of the adapter board 100 is soldered to the first test circuit board, the first LPDDR5 chip can be connected to the first test circuit board through the surface solder pad 200, the via hole and the bottom solder pad.

[0067] like Figure 5As shown, in some embodiments of the present application, the adapter board 100 adopts a six-layer board design, including a top board 110, four inner-layer boards 120 and a bottom board 130, wherein the thickness of the bottom board 130 is greater than the sum of the thicknesses of the top board 110 and the four inner-layer boards 120. The inner-layer board 120 of the adapter board 100 is provided with circuit traces, such as Figure 3 The adapter plate 100 is divided into an upper portion 140 and a lower portion 150. The surface area of the upper portion 140 is larger than that of the lower portion 150. The surface of the upper portion 140 protrudes from the surface of the lower portion 150 to form four extension plates 400 (such as Figure 4 As shown), a test pad 300 is provided on the surface of each extension board 400; the test points of the line routing are led out to the surface of the adapter board 100 and connected to the corresponding test pad 300.

[0068] It should be noted that the surface pads 200 and the bottom pads of the adapter board 100 are in one-to-one correspondence, and the two are connected through conductive holes to achieve the conduction of the circuits of each layer of the adapter board 100. At the same time, the design of the surface pads 200 and the bottom pads corresponds to the layout of the LPDDR5 chip. The circuit routing inside the adapter board 100 includes various circuits required by the LPDDR5 chip, such as power lines, data lines, clock lines, control lines, ground lines, etc. For the circuits that need to be tested, the test points of the corresponding circuit routings are brought out to the surface of the adapter board 100 and connected to the corresponding test pads 300, such as Figure 2 As shown. By connecting the surface pads 200 and the bottom pads with vias, electrical interconnection is achieved. The signal test line segments of the circuit routing are led out from the middle layer to the surface test pads 300, that is, a T-shaped topology is adopted. The led signal test line segments need to be as short as possible to reduce the reflection caused by the T-shaped topology. When testing the LPDDR5 chip, the first LPDDR5 chip is first soldered to the surface of the adapter board 100, and then the adapter board 100 is soldered to the first test circuit board. In this way, the first test circuit board can drive the first LPDDR5 chip to start working. During the operation of the first LPDDR5 chip, for the items to be tested, the corresponding test pads 300 are connected to an oscilloscope. The oscilloscope can then be used to display and measure various waveforms during the operation of the LPDDR5 chip, thereby implementing various parameter tests of the LPDDR5 chip, such as testing whether the eye width and eye height of the LPDDR5 chip's eye diagram meet the design standards, and testing whether the signal integrity of the LPDDR5 chip meets the requirements. At the same time, since the first test circuit board is designed with a test circuit, components such as capacitors, resistors, and MOS tubes are required. In order to avoid collision between the adapter board 100 and the components on the test circuit board when the adapter board 100 is installed on the test circuit board, such as Figure 4As shown, a controlled-depth milling process is used to mill grooves around the bottom of the adapter plate 100, dividing the adapter plate 100 into an upper portion 140 and a lower portion 150. The surface area of the upper portion 140 is larger than that of the lower portion 150, forming a T-shape as a whole. In this example, the total thickness of the adapter plate 100 is 2.4 mm, and the controlled-depth milling process is used to mill off 1.6 mm of the thickness at the bottom to prevent collisions between the adapter plate 100 and components on the test circuit board after soldering. It should be noted that the total thickness of the adapter plate 100 and the milled thickness can be adjusted according to actual needs, and are not limited to this.

[0069] Although the introduction of the adapter board 100 can make the testing of the LPDDR5 chip more convenient and comprehensive, the adapter board 100 is provided with conductive holes, line traces, etc. inside. These structures may cause signal loss and reflection, making the waveform measured by the oscilloscope inconsistent with the actual waveform of the chip, resulting in inaccurate measurement results. For this reason, in addition to obtaining the waveform of the first chip of the first test circuit board through the oscilloscope, the waveform of the second chip of the second test circuit board is also obtained through the oscilloscope. Unlike the first test circuit board, the second test circuit board does not introduce the adapter board 100. Instead, the second LPDDR5 chip is directly soldered to the surface of the second test circuit board, thereby avoiding the signal loss and reflection caused by the adapter board 100.

[0070] After obtaining the waveform of the first chip of the first test circuit board and the waveform of the second chip of the second test circuit board using an oscilloscope, fast Fourier transform (FFT) calculations are performed on the waveform of the first chip and the waveform of the second chip, respectively, to convert the waveform of the first chip and the waveform of the second chip from time domain signals to frequency domain signals, thereby obtaining first frequency domain signals and second frequency domain signals. Based on the first frequency domain signals and the second frequency domain signals, a first transfer function of the adapter board 100 is obtained, wherein the calculation formula of the first transfer function is as follows:

[0071] ;

[0072] in, represents the first chip waveform, represents the first frequency domain signal obtained by performing fast Fourier transform on the first chip waveform, represents the second chip waveform, represents a second frequency domain signal obtained by performing fast Fourier transform on the second chip waveform, and H represents the first transfer function.

[0073] After obtaining the first transfer function, a third frequency domain signal can be obtained according to the first frequency domain signal and the first transfer function, which specifically includes the following steps:

[0074] Step S810: performing an inverse operation on the first transfer function to obtain an inverse transfer function;

[0075] Step S820: performing a convolution operation on the first frequency domain signal and the inverse transfer function to obtain a third frequency domain signal.

[0076] Specifically, the transfer inverse function is: , then the third frequency domain signal is the result of convolving the first frequency domain signal with the inverse transfer function. Finally, the third frequency domain signal is subjected to an inverse Fourier transform to obtain the first test waveform of the LPDDR5 chip. It should be noted that since the second frequency domain signal is not affected by the adapter board 100, the first transfer function of the adapter board 100 can be obtained based on the first and second frequency domain signals. Then, by convolving the first frequency domain signal with the inverse transfer function of the first transfer function, the third frequency domain signal is the signal obtained by removing the interference of the adapter board 100 from the first frequency domain signal.

[0077] According to the chip waveform de-embedding method of the embodiment of the present application, it is possible to complete the test of the LPDDR5 chip and de-embed the measured waveform when the adapter board 100 is introduced, thereby avoiding signal loss and reflection caused by the internal structure of the adapter board 100, so that the waveform measured by the oscilloscope is consistent with the actual waveform of the chip, thereby ensuring the accuracy of the measurement results.

[0078] Furthermore, in some embodiments of the present application, the chip waveform de-embedding method of the embodiment of the present application further includes the following five steps:

[0079] (1) Import the design file of the adapter board 100 into the simulation software and select the circuit routing to be tested;

[0080] (2) Obtaining the S parameters of the adapter board 100 through simulation software;

[0081] (3) Inputting the S parameters into the oscilloscope, so that the oscilloscope obtains the second transfer function of the adapter board 100 according to the S parameters;

[0082] (4) performing a deconvolution operation on the first frequency domain signal and the second transfer function to obtain a fourth frequency domain signal;

[0083] (5) Perform inverse Fourier transform on the fourth frequency domain signal to obtain the second test waveform of the LPDDR5 chip.

[0084] The simulation software can be common software such as Spice, ADS, or Proteus. By importing the design file of the adapter board 100 into the simulation software and selecting the circuit routing to be tested, the corresponding S parameters can be obtained. Then, the S parameters are exported from the simulation file and saved as an S2P file. The file is imported into the oscilloscope so that the oscilloscope obtains the S parameters and obtains the second transfer function of the adapter board 100 based on the S parameters. The calculation method of the second transfer function is as follows:

[0085] ;

[0086] in, is the second transfer function, is the forward transmission coefficient of the adapter plate 100, is the transmission delay of the adapter board 100.

[0087] After obtaining the second transfer function, the first frequency domain signal is deconvolved with the second transfer function to obtain a fourth frequency domain signal. The fourth frequency domain signal is the signal obtained by removing the interference of the adapter board 100 from the first frequency domain signal. In this example, simulation software is used to obtain the S parameters of the adapter board 100, and then an oscilloscope is used to obtain the second transfer function of the adapter board 100 based on the S parameters of the adapter board 100. The first frequency domain signal is then deconvolved with the second transfer function to obtain the chip signal measured after removing the interference of the adapter board 100. Finally, an inverse Fourier transform is performed on the fourth frequency domain signal to obtain the second test waveform of the LPDDR5 chip.

[0088] Furthermore, in some embodiments of the present application, the chip waveform de-embedding method further includes the following three steps:

[0089] Calculating a first error between the first test waveform and the second chip waveform;

[0090] calculating a second error between the second test waveform and the second chip waveform;

[0091] The first test waveform or the second test waveform is determined as a final test waveform according to the first error and the second error.

[0092] The first test waveform is obtained by removing the interference of the adapter board 100 based on the second chip waveform obtained by the second test circuit board; the second test waveform is obtained by removing the interference of the adapter board 100 based on the S parameters obtained by simulation software. By comparing the errors between the two test waveforms and the second chip waveform, it is possible to determine which waveform is closer to the actual waveform of the LPDDR5 chip, thereby determining the final de-embedding method. If the first error between the first test waveform and the second chip waveform is less than the second error between the second test waveform and the second chip waveform, the first test waveform is used as the final test waveform of the LPDDR5 chip; if the first error between the first test waveform and the second chip waveform is greater than the second error between the second test waveform and the second chip waveform, the first test waveform is used as the final test waveform of the LPDDR5 chip, and the second test waveform is used as the final test waveform of the LPDDR5 chip. In this way, the most effective de-embedding method can be determined, accurately removing the interference of the adapter board 100 on the chip waveform, and improving the accuracy of the measured chip waveform.

[0093] In some embodiments of the present application, the calculation formula of the first error is:

[0094] ;

[0095] in, represents the first test waveform, represents the second chip waveform, N is the total number of samples, It should be noted that the calculation formula of the second error is similar to that of the first error.

[0096] Furthermore, if Figure 5 As shown, in some embodiments of the present application, the chip waveform de-embedding method further includes the following three steps:

[0097] Mill grooves around the bottom of the bottom plate 130 according to a predetermined depth and a predetermined width, so that the bottom of the bottom plate 130 serves as the lower layer 150, and the top of the bottom plate 130, the top plate 110, and the four inner layers 120 serve as the upper layer 140; wherein the predetermined depth is less than the thickness of the bottom plate 130;

[0098] Four extension plates 400 are formed on the portion of the upper portion 140 that protrudes from the lower portion 150.

[0099] A test pad 300 is provided on the surface of each extension plate 400 , and a gap 410 is formed between any two adjacent extension plates 400 ;

[0100] The test points of the line routing are led out of the surface of the adapter board 100 and connected to the corresponding test pads 300 .

[0101] Specifically, the adapter board 100 adopts a six-layer board design, including a top plate 110, four inner layers 120 and a bottom plate 130, wherein the thickness of the bottom plate 130 is greater than the sum of the thicknesses of the top plate 110 and the four inner layers 120; when milling grooves around the bottom of the adapter board 100, the bottom of the bottom plate 130 is milled around the bottom, and the depth of the milling grooves does not exceed the thickness of the bottom plate 130, so that the top plate 110 and the four inner layers 120 are both located in the upper layer 140 of the adapter board 100, avoiding affecting the line routing in the inner layer 120. At the same time, the stacking spacing between the top plate 110 and the four inner layers 120 is as small as possible to achieve good signal shielding and impedance reference when testing the line routing. In terms of the board material selection of the adapter board 100, it is necessary to select a high-speed board with a good low dielectric constant and low dielectric loss tangent to reduce the loss during signal transmission. In this example, the dielectric constant of the plate material of the adapter board 100 is lower than 3.71, and the dielectric loss factor is lower than 0.002 at a frequency of 1 GHz, which meets the requirements of high-speed transmission and low loss of signals. In this example, the total thickness of the adapter board 100 is 2.4 mm, and the bottom is milled off by 1.6 mm of thickness using a controlled depth milling process to avoid collisions with parts on the test circuit board after the adapter board 100 is welded. A gap 410 is formed between any two adjacent extension plates 400, leaving four corners corresponding to the four edges of the LPDDR5 chip, which is convenient for positioning the adapter board 100 when it is welded to the first test circuit board. In order to conduct a comprehensive test of the LPDDR5 chip, it is necessary to select the key signals of the LPDDR5 chip as test points. In this example, the following signals are used as test points:

[0102] For data lines: the WCK differential signal, RDQS differential signal, and two random data single-ended signals of each channel of the LPDDR5 chip are brought out as the first signal test point;

[0103] For clock and address / control lines: The clock differential signal (CK), two random CA signals, and two random CS signals of each channel of the LPDDR5 chip are brought out as the second signal test point.

[0104] Power test point: Bring out the VDDQ, VDD1, VDD2H, and VDD2L pins of the LPDDR5 chip as power test points.

[0105] After selecting the above test points, connect all the test points to the corresponding test pads 300 through routing. After selecting the first signal test point, the second signal test point and the power test point, the first signal test point, the second signal test point and the power test point also need to be connected to the ground test point as a basis, and the GND signal of the LPDDR5 chip is brought out as the ground test point. To this end, GND ground holes are evenly arranged around the WCK differential signal, RDQS differential signal, data single-ended signal, clock differential signal, CA signal, CS signal, VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal to achieve grounding; the signal of the GND ground hole is brought out as a ground test point; and the ground test point is connected to the corresponding test pad 300.

[0106] It should be noted that for the traces that need to be tested, GND grounding is used, and GND holes are evenly drilled around the signals to achieve the effect of signal shielding and reduce the crosstalk between high-speed signals.

[0107] like Figure 2As shown, in some embodiments of the present application, the signal test pads 310 corresponding to the first signal test point, the second signal test point and the power test point are designed as elliptical pads, and the ground test pads 320 corresponding to the GND test point are designed as rectangular pads, which are convenient for distinguishing and processing during later testing. It should be noted that the signal test pads 310 and the ground test pads 320 can also be designed as other shapes, as long as the shapes of the two are different. At the same time, each ground test pad 320 and the signal test pad 310 are equally spaced around the four extension plates 400 and maintain a spacing of more than 0.75mm to avoid collisions between the test leads during testing. At the same time, a gap 410 is formed between any two adjacent extension plates 400, thereby leaving four corners corresponding to the four edges of the LPDDR5 chip, which is convenient for positioning the adapter plate 100 when the adapter plate 100 is soldered to the first test circuit board. Due to the high thickness of adapter board 100, the vias connecting the surface pads 200 and the bottom pads require through-holes with the largest possible diameter to meet the required diameter-to-depth ratio during machining. The connecting vias at test pads 300 (i.e., vias for the WCK differential signal, RDQS differential signal, data single-ended signal, clock differential signal, CA signal, CS signal, VDDQ signal, VDD1 signal, VDD2H signal, and VDD2L signal) use blind vias in layers 1-3 to connect the test pads to inner-layer traces to eliminate reflections caused by via stubs. The differential signals of the adapter board 100 (such as WCK differential signals, RDQS differential signals, and clock differential signals) are controlled within 100Ω impedance, the single-ended signals (such as data single-ended signals, CA signals, CS signals, etc.) are controlled within 50Ω impedance, and the power supply lines (such as VDDQ signals, VDD1 signals, VDD2H signals, VDD2L signals, etc.) are kept at a line width of more than 12 mils.

[0108] On the other hand, an embodiment of the present application also proposes a chip waveform de-embedding device, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the above-mentioned chip waveform de-embedding method.

[0109] The processor may be implemented as a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0110] The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory and is called by the processor to execute the chip waveform de-embedding method of the embodiments of this application. The memory and the processor can be connected via a bus or the like.

[0111] On the other hand, an embodiment of the present invention further provides an electronic device, comprising the above-mentioned chip waveform de-embedding device.

[0112] On the other hand, an embodiment of the present invention further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned chip waveform de-embedding method is implemented.

[0113] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory optionally includes a memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of the above-mentioned networks include but are not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0114] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described in accordance with embodiments of the present disclosure, those skilled in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of this disclosure.

[0115] Some aspects of the present disclosure have been described above with reference to the block diagrams and flow charts of the systems, methods, systems and / or computer program products according to the exemplary embodiments. It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively. Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full. In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0116] Therefore, the blocks in the block diagrams and flow charts support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions, and program instruction means for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts, and combinations of blocks in the block diagrams and flow charts, can be implemented by a dedicated hardware computer system that performs the specific functions, elements, or steps, or a combination of dedicated hardware and computer instructions.

[0117] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0118] Software component can be encoded with any one in various programming languages.A kind of exemplary programming language can be low-level programming language, such as the assembly language associated with specific hardware architecture and / or operating system platform.Comprise that the software component of assembly language instruction may need to be converted to executable machine code by assembler before being executed by hardware architecture and / or platform.Another exemplary programming language can be a more advanced programming language, and it can be transplanted across multiple architectures.Comprise that the software component of more advanced programming language may need to be converted to intermediate representation by interpreter or compiler before execution.Other examples of programming language include but are not limited to macro language, shell or command language, job control language, script language, database query or search language or report writing language.In one or more exemplary embodiments, the software component that comprises the instruction of one in the above-mentioned programming language example can be directly executed by operating system or other software component, without first being converted into another form.

[0119] Software components can be stored as files or other data storage structures. Software components of similar types or related functions can be stored together, such as in a specific directory, folder, or library. Software components can be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0120] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the scope of the present invention.

Claims

1. A chip waveform de-embedding method, characterized in that: include: Design an adapter board based on the layout of the LPDDR5 chip; the surface of the adapter board is provided with a surface pad, and the bottom surface of the adapter board is provided with a bottom pad, and the surface pad and the bottom pad are connected through a via; Obtain a first test circuit board and a second test circuit board; Soldering the first LPDDR5 chip to the surface pads of the adapter board, and soldering the bottom pads of the adapter board to the first test circuit board, so that the first LPDDR5 chip is connected to the first test circuit board through the adapter board; Soldering a second LPDDR5 chip to the surface of the second test circuit board; Acquire a first chip waveform of the first test circuit board through an oscilloscope, and perform fast Fourier transform calculation on the first chip waveform to obtain a first frequency domain signal; Acquire a second chip waveform of the second test circuit board through an oscilloscope, and perform fast Fourier transform calculation on the second chip waveform to obtain a second frequency domain signal; Obtaining a first transfer function of the adapter board according to the first frequency domain signal and the second frequency domain signal; obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function; Performing an inverse Fourier transform on the third frequency domain signal to obtain a first test waveform of the LPDDR5 chip; The obtaining of a third frequency domain signal according to the first frequency domain signal and the first transfer function includes: performing an inverse operation on the first transfer function to obtain an inverse transfer function; performing a convolution operation on the first frequency domain signal and the inverse transfer function to obtain the third frequency domain signal; The method further comprises: Import the design file of the adapter board into the simulation software and select the circuit routing to be tested; Obtaining the S parameters of the adapter plate through the simulation software; Inputting the S parameters into the oscilloscope, so that the oscilloscope obtains the second transfer function of the adapter board according to the S parameters; performing a deconvolution operation on the first frequency domain signal and the second transfer function to obtain a fourth frequency domain signal; Perform an inverse Fourier transform on the fourth frequency domain signal to obtain a second test waveform of the LPDDR5 chip.

2. The chip waveform de-embedding method according to claim 1, characterized in that: The calculation formula of the first transfer function is: ； in, represents the first chip waveform, represents the first frequency domain signal, represents the second chip waveform, represents the second frequency domain signal, and H represents the first transfer function.

3. The chip waveform de-embedding method according to claim 1, characterized in that: The method further comprises: Calculating a first error between the first test waveform and the second chip waveform; calculating a second error between the second test waveform and the second chip waveform; The first test waveform or the second test waveform is determined as a final test waveform according to the first error and the second error.

4. The chip waveform de-embedding method according to claim 3, characterized in that: The calculation formula of the first error is: ; in, represents the first test waveform, represents the second chip waveform, N is the total number of samples, is the first error.

5. The chip waveform de-embedding method according to claim 1, characterized in that: The adapter board is a six-layer board, including a top board, four inner-layer boards, and a bottom board, wherein the thickness of the bottom board is greater than the sum of the thicknesses of the top board and the four inner-layer boards, and circuit routing is provided in the inner-layer boards; the method further comprises: Milling grooves around the bottom of the bottom plate according to a preset depth and a preset width, so that the bottom of the bottom plate serves as the lower layer, and the top of the bottom plate, the top plate, and the four inner layer plates serve as the upper layer; wherein the preset depth is less than the thickness of the bottom plate; Four extension plates are formed on portions of the peripheral surface of the upper portion that protrude from the peripheral surface of the lower portion; A test pad is provided on the surface of each extension plate, and a gap is formed between any two adjacent extension plates; Lead the test points of the line routing to the surface of the adapter board and connect them to the corresponding test pads.

6. A chip waveform de-embedding device, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to perform the chip waveform de-embedding method as described in any one of claims 1 to 5.

7. An electronic device, characterized in that: Including the chip waveform de-embedding device as described in claim 6.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the chip waveform de-embedding method according to any one of claims 1 to 5.

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