Development board based on SRB chip

Abstract

The invention provides a development board based on a secure real-time bus SRB chip, and relates to the technical field of power electronics. The development board comprises any one or more of an SRB real-time single-twisted pair 100M Ethernet interface, an SRB real-time standard gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration universal asynchronous receiver / transmitter UART serial port, an ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM JTAG interface and a power supply interface. According to the method, not only is the security bus characteristic test of the SRB chip concerned, but also other key function modules (such as an Ethernet interface, a memory interface, a serial peripheral interface and the like) are covered, so that a developer can more comprehensively evaluate the overall performance and reliability of the SRB chip, not just the security bus part.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a development board based on an SRB chip. Background Art

[0002] With the development of information technology, data security and reliability are becoming more and more important in modern electronic systems. Secure Real-time Bus (SRB) chips can ensure the security and reliability of data transmission, which is crucial for electronic systems that require high security and reliability (such as automotive control systems, aerospace systems, financial transaction systems, etc.).

[0003] In related technologies, in order to ensure the security and reliability of the SRB chip, the SRB test version is usually used to test the SRB chip. The SRB test version contains a series of test items and test cases for the security bus characteristics of the SRB chip, which aims to verify whether the security bus can resist various attacks (such as data tampering, data theft, etc.) during data transmission to ensure the security and reliability of the data.

[0004] However, the existing SRB test version mainly focuses on the testing of the security bus, but ignores other important functional modules of the SRB chip. The security and reliability of these modules also have an important impact on the overall performance of the SRB chip, which limits the evaluation of the overall performance of the SRB chip. Summary of the invention

[0005] Based on the above problems, the present application provides a development board based on the SRB chip, which enables developers to more comprehensively evaluate the overall performance and reliability of the SRB chip.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] The present application discloses a development board based on a secure real-time bus SRB chip, and the development board includes: an SRB real-time single twisted pair 100M Ethernet interface, an SRB real-time standard Gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration configuration universal asynchronous receiver / transmitter UART serial port, an advanced reduced instruction set machine ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM boundary scan technology JTAG interface and a power supply interface. Any one or more.

[0008] Optionally, the SRB real-time single twisted pair 100M Ethernet interface includes a first pin, a second pin, a third pin and a fourth pin, wherein the interface signals of the first pin and the fourth pin are no connection signals, the interface signal of the second pin is a positive polarity signal, and the interface signal of the third pin is a negative polarity signal.

[0009] Optionally, the SRB real-time single twisted pair 100M Ethernet interface and the SRB real-time standard Gigabit Ethernet interface share the same Gigabit Medium Independent RGMI interface.

[0010] Optionally, the SRB EMIF parallel interface includes a data line pin, an address line pin, a control signal pin and a digital ground pin.

[0011] Optionally, the SRB SPI serial interface includes a first pin, a second pin, a third pin and a fourth pin, wherein the interface signal of the first pin is a clock signal, the interface signal of the second pin is an input signal, the interface signal of the third pin is an output signal, and the output signal of the fourth pin is a chip select signal.

[0012] Optionally, the SRB UART serial port, the RS232 serial port and the ARM UART serial port respectively include a first pin, a second pin and a third pin, wherein the interface signal of the first pin is an output signal, the interface signal of the second pin is a digital ground signal, and the interface signal of the third pin is an input signal.

[0013] Optionally, the first pin is used to connect to an input pin of an external device, the second pin is used to connect to a digital ground pin of an external device, and the third pin is used to connect to an output pin of the external device.

[0014] Optionally, the ARM RS422 serial port includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin, wherein the interface signals of the first pin and the sixth pin are digital ground signals, the interface signal of the second pin is a positive output signal, the interface signal of the third pin is a negative output signal, the interface signal of the fourth pin is a negative input signal, and the interface signal of the fifth pin is a positive input signal.

[0015] Optionally, the second pin is used to connect to a positive input pin of an external device, the third pin is used to connect to a negative input pin of the external device, the fourth pin is used to connect to a negative output pin of the external device, and the fifth pin is used to connect to a positive output pin of the external device.

[0016] Optionally, the ARM JTAG interface includes a test reset pin, a power pin, a data input pin, a test mode selection pin, a digital ground pin, a test clock signal pin, a data output signal pin and a non-maskable reset signal pin.

[0017] Compared with the prior art, this application has the following beneficial effects:

[0018] The present application provides a development board based on a secure real-time bus SRB chip, which includes an SRB real-time single twisted pair 100M Ethernet interface, an SRB real-time standard Gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration configuration universal asynchronous receiver and transmitter UART serial port, an ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM JTAG interface, and any one or more of a power supply interface. The present application not only focuses on the security bus feature test of the SRB chip, but also covers other key functional modules (such as Ethernet interface, memory interface, serial peripheral interface, etc.), so that developers can more comprehensively evaluate the overall performance and reliability of the SRB chip, not just the security bus part. In addition, the present application can test the behavior of the SRB chip under various communication protocols by introducing a variety of different types of interfaces (such as 100M and Gigabit Ethernet interfaces, RS422 / RS232 serial ports, CAN interfaces, etc.). This multi-protocol support helps ensure that the chip can still maintain the security and reliability of data transmission in a complex network environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 A hardware block diagram of a development board based on a secure real-time bus SRB chip provided in an embodiment of the present application;

[0021] Figure 2 A hardware layout diagram of a development board based on a secure real-time bus SRB chip provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of a single twisted pair 100M Ethernet interface provided in an embodiment of the present application;

[0023] Figure 4A schematic diagram of a board-to-card interconnection method provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of a real-time standard Gigabit Ethernet interface provided in an embodiment of the present application;

[0025] Figure 6 A connection diagram of an SRB EMIF parallel interface provided in an embodiment of the present application;

[0026] Figure 7 A schematic diagram of an SPI serial interface provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of an SRB UART serial port provided in an embodiment of the present application;

[0028] Fig. 9 A schematic diagram of an ARM RS422 serial port provided in an embodiment of the present application;

[0029] Fig.10 A schematic diagram of an RS232 serial port provided in an embodiment of the present application;

[0030] Fig.11 A schematic diagram of a CAN interface provided in an embodiment of the present application;

[0031] Fig.12 A schematic diagram of an ARM UART serial port provided in an embodiment of the present application;

[0032] Fig.13 A schematic diagram of an ARM 100M network port provided in an embodiment of the present application;

[0033] Fig.14 A schematic diagram of an ARM JTAG interface provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] As described above, in order to ensure the security and reliability of the SRB chip, the SRB test version is usually used to test the SRB chip. The SRB test version contains a series of test items and test cases for the security bus characteristics of the SRB chip, which aims to verify whether the security bus can resist various attacks (such as data tampering, data theft, etc.) during data transmission to ensure the security and reliability of the data.

[0035] However, the existing SRB test version mainly focuses on the testing of the security bus, but ignores other important functional modules of the SRB chip. The security and reliability of these modules also have an important impact on the overall performance of the SRB chip, which limits the evaluation of the overall performance of the SRB chip.

[0036] After research, the inventor proposed a development board based on a secure real-time bus SRB chip, which includes an SRB real-time single twisted pair 100M Ethernet interface, an SRB real-time standard Gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration configuration universal asynchronous receiver and transmitter UART serial port, an ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM JTAG interface, and any one or more of a power supply interface. This application not only focuses on the safety bus feature test of the SRB chip, but also covers other key functional modules (such as Ethernet interface, memory interface, serial peripheral interface, etc.), so that developers can more comprehensively evaluate the overall performance and reliability of the SRB chip, not just the safety bus part. In addition, this application can test the behavior of the SRB chip under various communication protocols by introducing a variety of different types of interfaces (such as 100M and Gigabit Ethernet interfaces, RS422 / RS232 serial ports, CAN interfaces, etc.). This multi-protocol support helps ensure that the chip can still maintain the security and reliability of data transmission in complex network environments. Furthermore, since it includes ARM-related interfaces (such as UART serial port, 100M Ethernet port, JTAG interface), it is conducive to seamless integration of SRB chips with other ARM-based systems, improving the compatibility and interoperability of the entire solution.

[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] See also Figure 1 , which is a schematic diagram of a development board based on a secure real-time bus SRB chip provided in an embodiment of the present application. Figure 2 , this figure is a hardware layout diagram of a development board based on a secure real-time bus SRB chip provided in an embodiment of the present application.

[0039] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip includes the SRB real-time single twisted pair 100M Ethernet interface J7 interface and J8 interface, which support data transmission rates up to 100Mbps through a single twisted pair. Figure 3 , which is a schematic diagram of a single twisted pair 100M Ethernet interface provided by an embodiment of the present application. Figure 3It can be seen that the J7 and J8 interfaces include 4 pins respectively, among which the interface signals of the first and fourth pins are No Connection (NC) signals, which means that these positions are not electrically connected under the current configuration. The interface signal of the second pin is a positive polarity signal TRP, which means that the second pin sends a positive polarity signal. The interface signal of the third pin is a negative polarity signal TRN, which means that the third pin sends a negative polarity signal. In addition, the plug of the single twisted pair cable has a fool-proof design, and both ends can be connected to each other by inserting, ensuring that even non-professionals can correctly insert the cable and avoid problems caused by inserting in the wrong direction.

[0040] See also Figure 4 , which is a schematic diagram of a board-to-board interconnection method provided by an embodiment of the present application. Each SRB real-time single twisted pair 100M Ethernet interface can be configured as either a master or slave mode. Figure 4 As can be seen, the J7 interface is set to master mode and the J8 interface is set to slave mode. And by connecting the master interface (J7) of one development board to the slave interface (J8) of another development board, a redundant ring network structure can be created. This topology helps to improve the reliability and fault tolerance of the system because if any link fails, data can still be transmitted through other paths.

[0041] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes the SRB real-time standard Gigabit Ethernet interface P2 interface and P3 interface. Figure 5 , which is a schematic diagram of a real-time standard Gigabit Ethernet interface provided in an embodiment of the present application. These interfaces comply with the SRB real-time standard, which means that they support high-speed data transmission and may have specific delay guarantees or quality of service characteristics, which is very important for applications that require high bandwidth and low latency.

[0042] In the development board design based on SRB chip, P2 and J7 share one RGMII interface, and P3 and J8 share another RGMII interface. Due to the existence of this sharing mechanism, P2 cannot be used with J7 at the same time, and similarly, P3 cannot be used with J8 at the same time. This is because the RGMII interface can only be configured in one mode at the same time: either for supporting a 100M PHY chip for single twisted pair, or for supporting a standard Gigabit PHY chip.

[0043] In some specific implementations, the development board determines which PHY chip the RGMII interface should be connected to by means of resistor selection welding. Under the current default settings, the RGMII interface is configured to connect to a single twisted pair 100M PHY chip (i.e., J7 and J8 interfaces), so the P2 and P3 interfaces are not available at this time. If you need to enable P2 or P3 as a Gigabit Ethernet interface, you need to adjust the corresponding hardware configuration, that is, change the resistor selection welding state so that the RGMII interface can be connected to a standard Gigabit PHY chip.

[0044] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes an SRB external memory interface (EMIF) parallel interface J12. The SRB EMIF parallel interface J12 is mainly used to connect external devices, such as a host computer or other peripherals. It provides a high-speed data transmission channel, which is suitable for application scenarios that require a large amount of data exchange.

[0045] It should be noted that the SRB EMIF parallel interface J12 generally contains multiple output pins, each of which has a specific function and signal definition. As shown in Table 1, these pins are divided into data lines (such as EMIF_D0 to EMIF_D15, used for actual data storage), address lines (such as EMIF_A0 to EMIF_A13, used to specify the location of data storage) and other control signals (such as EMIF_NCS, select the chip to communicate with; EMIF_NRD, the selection signal during the read operation; EMIF_NWE, the selection signal during the write operation, etc.). In addition, there are multiple GND (digital ground) pins to ensure the stability of the signal, as well as INT0#, INT1# signals, which are real-time data interrupt and non-real-time data interrupt output signals, respectively, used to notify the processor that there is new data to be processed.

[0046] Table 1

[0047]

[0048]

[0049] See Table 2, which is a schematic diagram of an EMIF_AO output pin provided in an embodiment of the present application. This indicates that the EMIF_A0 signal may be set to a ground state in some cases, which may be to simplify circuit design or reduce complexity when not all address lines are needed.

[0050] Connectors Pins Signal Definition illustrate J14 3 EMIF_A0 External GND

[0051] See Table 3, which is a schematic diagram of real-time and non-real-time data interrupt output pins provided in an embodiment of the present application. The two interrupt signals correspond to different priorities and response times, respectively, and are used to distinguish different types of events.

[0052] Connectors Pins Signal Definition illustrate J12 42 INT0# Real-time data interrupt output J14 1 INT1# Non-real-time data interrupt output

[0053] See also Figure 6 , which is a connection diagram of an SRB EMIF parallel interface provided by an embodiment of the present application. When the flexible static memory controller (FSMC) interface mode of the OKE220S chip is used, the real-time data interrupt pin INT0# and the non-real-time data interrupt pin INT1# need to be connected to the corresponding pins of the ARM processor respectively. Figure 6 In the example, Dupont wires are used to achieve this connection: Line 1 (red) represents the connection of the real-time data interrupt line, connecting INT0# to the corresponding interrupt input pin of ARM. Line 2 (green) represents the connection of the non-real-time data interrupt line, connecting INT1# to another interrupt input pin of ARM. This configuration allows the processor on the development board to respond to interrupt requests from external devices in a timely manner, thereby processing data quickly. This is very important for maintaining the responsiveness and efficiency of the system.

[0054] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes the SRB serial peripheral interface (Serial Peripheral Interface, SPI) serial interface J16. Figure 7 , which is a schematic diagram of an SPI serial interface provided by an embodiment of the present application. SRB SPI serial interface J16 is mainly used for SPI communication with a host computer or other external devices. SPI is a synchronous serial communication protocol that allows a microcontroller or processor to exchange data at high speed with one or more peripheral devices. Figure 7 It can be seen that the SPI serial interface J16 includes 4 pins, among which the interface signal of the first pin is CLK (clock signal), which is used to synchronize data transmission between the master device and the slave device. The clock signal is provided by the master device and determines the speed of data transmission. The interface signal of the second pin is MOSI (input signal), and the data on this line is the data stream sent from the master device to the slave device. The interface signal of the third pin is MISO (output signal), and the data on this line is the data stream sent from the slave device back to the master device. The interface signal of the fourth pin is CS (chip select signal), which is used to select the specific slave device to be communicated with at present. When the CS signal is pulled low, the corresponding slave device is activated and ready to communicate.

[0055] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes the SRB configuration configuration Universal Asynchronous Receiver / Transmitter (UART) serial port J6. Figure 8 , which is a schematic diagram of an SRB UART serial port provided in an embodiment of the present application. Figure 8 It can be seen that the SRB UART serial port J6 includes 3 pins, among which the interface signal of the first pin is TX (output signal), which is the output port for sending data from the development board to external devices. The interface signal of the second pin is GND (digital ground signal), which provides a common reference point to ensure the stability and correctness of the signal. The interface signal of the third pin is RX (input signal), which is the data input port received from the external device to the development board.

[0056] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes an ARM RS422 serial port J1. RS422 is a differential signal standard used to achieve long-distance data transmission. It improves anti-interference ability by using differential signals and can maintain a high data transmission rate over a long distance. In the development board based on the SRB chip, the RS422 serial port J1 is mainly used for reliable communication with external devices or systems. See Fig. 9 , which is a schematic diagram of an ARMRS422 serial port provided in an embodiment of the present application. Fig. 9It can be seen that the ARM RS422 serial port J1 includes 6 pins, among which the interface signals of the first and sixth pins are GND (digital ground signal), which provides a common reference point to ensure the stability and correctness of the signal. The interface signal of the second pin is T+ (output signal), which is a positive output port for sending data from the development board to an external device. The interface signal of the third pin is T- (output signal), which is a negative output port for sending data from the development board to an external device. The interface signal of the fourth pin is R- (input signal), which is a negative input port for receiving data from an external device to the development board. The interface signal of the fifth pin is R+ (input signal), which is a positive input port for receiving data from an external device to the development board. It should be noted that in order to establish effective RS422 communication, it is necessary to ensure that these signal lines are correctly connected to the target device. Specifically, the T+ pin of the development board should be connected to the R+ pin of the external device, and the T- pin of the development board should be connected to the R- pin of the external device. The R+ pin of the development board should be connected to the T+ pin of the external device, and the R- pin of the development board should be connected to the T- pin of the external device. Both GND pins of the development board should be connected to the corresponding GND pins of the external device to ensure a common potential reference.

[0057] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes RS232 serial port J17. RS232 is a widely used serial communication interface standard for asynchronous communication between devices. It uses voltage levels to represent logical states (usually + / -12V or + / -5V) and is suitable for short-distance data transmission. In the development board based on the SRB chip, RS232 serial port J17 is mainly used for data exchange with external devices or host computers, such as debugging, configuration, and simple command control. See Fig.10 , which is a schematic diagram of an RS232 serial port provided in an embodiment of the present application. Fig.10 It can be seen that the RS232 serial port J17 includes 3 pins, among which the interface signal of the first pin is TX (output signal), which is the output port for sending data from the development board to the external device. The interface signal of the second pin is GND (digital ground signal), which provides a common reference point to ensure the stability and correctness of the signal. The interface signal of the third pin is RX (input signal), which is the data input port received from the external device to the development board. In order to establish effective RS232 communication, it is necessary to ensure that these signal lines are correctly connected to the target device. Specifically, the TX pin of the development board should be connected to the RX pin of the external device; the GND pin of the development board should be connected to the GND pin of the external device to ensure a common potential reference; the RX pin of the development board should be connected to the TX pin of the external device.

[0058] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes a CAN interface J4. In the development board based on the SRB chip, the CAN interface J4 is mainly used for communication with external devices that support the CAN protocol. Fig.11 , which is a schematic diagram of a CAN interface provided by an embodiment of the present application. Fig.11 It can be seen that the CAN interface J4 includes 3 pins, among which the interface signal of the first pin is CANH, which is a line of the CAN bus and is usually at a dominant level (logic 0) or a recessive level (logic 1). In the dominant state, the CANH voltage is higher than CANL; in the recessive state, the voltages of the two are close. The interface signal of the second pin is CANL, which is another line of the CAN bus and works with CANH. In the dominant state, the CANL voltage is lower than CANH; in the recessive state, the voltages of the two are close. The interface signal of the third pin is GND. The CAN interface J4 uses a pair of wires (CANH and CANL) to send each signal, which can effectively suppress common-mode noise.

[0059] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes an ARM UART serial port J5. Fig.12 , which is a schematic diagram of an ARM UART serial port provided in an embodiment of the present application. Fig.12 It can be seen that the ARM UART serial port J5 includes 3 pins, among which the interface signal of the first pin is TX (output signal), which is the output port for sending data from the development board to external devices. The interface signal of the second pin is GND (digital ground signal), which provides a common reference point to ensure the stability and correctness of the signal. The interface signal of the third pin is RX (input signal), which is the data input port received from the external device to the development board.

[0060] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes the ARM 100M network port P1. Fig.13 , which is a schematic diagram of an ARM 100M network port provided in an embodiment of the present application.

[0061] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes the ARM JTAG interface J11. Fig.14 , which is a schematic diagram of an ARM JTAG interface provided by an embodiment of the present application. Fig.14It can be seen that the ARM JTAG interface J11 includes 10 pins, among which the interface signal of the first pin is TRST, which is a test reset signal, usually controlled by the debugger and used to reset the JTAG logic. The interface signals of the second and fourth pins are VCC3V3, and these two pins provide 3.3V power to the JTAG interface to ensure its normal operation. The interface signal of the third pin is a data input signal (Test Data Input, TDI), which is used to transfer data from the debugger to the target processor. The interface signal of the fifth pin is a test mode select signal (TestMode Select, TMS), which is used to control the state machine of JTAG. The interface signals of the sixth and eighth pins are GND (digital ground). The interface signal of the seventh pin is a test clock signal (Test Clock, TCK), which provides a synchronous clock for JTAG communication. The interface signal of the ninth pin is a data output signal (Test Data Output, TDO), which is used to transfer data from the target processor to the debugger. The interface signal of the tenth pin is a non-maskable reset signal (NRST), which is used to forcibly reset the entire system.

[0062] Depend on Figure 1 and Figure 2 It can be seen that the development board based on the SRB chip also includes a power supply interface. Among them, the development board accepts an external 12V DC power supply through a specific DC power interface (J18), and uses a boat switch (SW5) to control the on and off of the power supply. When SW5 is turned to the "|" position, it means that the switch is on, that is, the power is on. At this time, the 12V power supply will be allowed to flow into the development board to power the circuit. When SW5 is turned to the "0" position, it means that the switch is disconnected, that is, the power is cut off. At this time, the 12V power supply will not flow into the development board, and the circuit is in an unpowered state.

[0063] In summary, the present application discloses a development board based on a secure real-time bus SRB chip, which includes an SRB real-time single twisted pair 100M Ethernet interface, an SRB real-time standard Gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration configuration universal asynchronous receiver and transmitter UART serial port, an ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM JTAG interface, and any one or more of a power supply interface. The present application not only focuses on the safety bus characteristic test of the SRB chip, but also covers other key functional modules (such as Ethernet interface, memory interface, serial peripheral interface, etc.), so that developers can more comprehensively evaluate the overall performance and reliability of the SRB chip, not just the safety bus part. In addition, the present application can test the behavior of the SRB chip under various communication protocols by introducing a variety of different types of interfaces (such as 100M and Gigabit Ethernet interfaces, RS422 / RS232 serial ports, CAN interfaces, etc.). This multi-protocol support helps ensure that the chip can still maintain the security and reliability of data transmission in complex network environments. Furthermore, since it includes ARM-related interfaces (such as UART serial port, 100M Ethernet port, JTAG interface), it is conducive to seamless integration of SRB chips with other ARM-based systems, improving the compatibility and interoperability of the entire solution.

[0064] The "first" and "second" in the names such as "first" and "second" (if any) mentioned in the embodiments of the present application are only used as name identifiers and do not represent the first or second in order.

[0065] Through the description of the above implementation methods, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above-mentioned embodiment method can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment of the present application or some parts of the embodiments.

[0066] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0067] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A development board based on a secure real-time bus SRB chip, characterized in that: The development board includes: any one or more of an SRB real-time single twisted pair 100M Ethernet interface, an SRB real-time standard Gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration configuration universal asynchronous receiver / transmitter UART serial port, an advanced reduced instruction set machine ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM boundary scan technology JTAG interface and a power supply interface.

2. The development board according to claim 1, characterized in that: The SRB real-time single twisted pair 100M Ethernet interface includes a first pin, a second pin, a third pin and a fourth pin, wherein the interface signals of the first pin and the fourth pin are no connection signals, the interface signal of the second pin is a positive polarity signal, and the interface signal of the third pin is a negative polarity signal.

3. The development board according to claim 1, characterized in that: The SRB real-time single twisted pair 100M Ethernet interface and the SRB real-time standard Gigabit Ethernet interface share the same Gigabit Medium Independent RGMI interface.

4. The development board according to claim 1, characterized in that: The SRB EMIF parallel interface includes a data line pin, an address line pin, a control signal pin and a digital ground pin.

5. The development board according to claim 1, characterized in that: The SRB SPI serial interface includes a first pin, a second pin, a third pin and a fourth pin, wherein the interface signal of the first pin is a clock signal, the interface signal of the second pin is an input signal, the interface signal of the third pin is an output signal, and the output signal of the fourth pin is a chip select signal.

6. The development board according to claim 1, characterized in that: The SRB UART serial port, the RS232 serial port and the ARM UART serial port respectively include a first pin, a second pin and a third pin, wherein the interface signal of the first pin is an output signal, the interface signal of the second pin is a digital ground signal, and the interface signal of the third pin is an input signal.

7. The development board according to claim 6, characterized in that: The first pin is used to connect to an input pin of an external device, the second pin is used to connect to a digital ground pin of the external device, and the third pin is used to connect to an output pin of the external device.

8. The development board according to claim 1, characterized in that: The ARM RS422 serial port includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin and a sixth pin, wherein the interface signals of the first pin and the sixth pin are digital ground signals, the interface signal of the second pin is a positive output signal, the interface signal of the third pin is a negative output signal, the interface signal of the fourth pin is a negative input signal, and the interface signal of the fifth pin is a positive input signal.

9. The development board according to claim 8, characterized in that: The second pin is used to connect to the positive input pin of the external device, the third pin is used to connect to the negative input pin of the external device, the fourth pin is used to connect to the negative output pin of the external device, and the fifth pin is used to connect to the positive output pin of the external device.

10. The development board according to claim 1, characterized in that: The ARM JTAG interface comprises a test reset pin, a power pin, a data input pin, a test mode selection pin, a digital ground pin, a test clock signal pin, a data output signal pin and a non-shieldable reset signal pin.

Images