Circuit for locking power supply control state of logic system

Abstract

The invention relates to the technical field of circuits, and discloses a circuit for locking a power supply control state of a logic system, which comprises a logic chip, a latch circuit and a direct-current low-voltage power switch application circuit, the LE end I < O > of the logic chip is connected with the LE end of the latch circuit, the D end I < O > of the logic chip is connected with the D end of the latch circuit, and the Q end I < O > of the latch circuit is connected with the Q end of the direct-current low-voltage power switch application circuit; when the logic system power supply control circuit works, the logic chip presets a target Q output state by operating the D end IO, and the LE end I O outputs a square rising edge to take effect the preset target Q output state; the latch circuit continuously keeps the effective output state of Q and acts the effective output state of Q on the direct-current low-voltage power switch application circuit, and the direct-current low-voltage power switch application circuit outputs a switching value after receiving a Q target signal of the latch circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of circuits, and in particular to a circuit for locking a power supply control state of a logic system. Background Art

[0002] Industrial control boards often use transistors or field effect transistors to control the switch of DC low-voltage power supplies. The front circuit of the transistor or field effect transistor is the IO output of the logic chip (MCU, DSP, FPGA, etc.), and the back circuit of the transistor or field effect transistor is the switch application circuit of the DC low-voltage power supply. In this control circuit, the control signal depends entirely on the IO state of the logic chip (MCU, DSP, FPGA, etc.). When the control program in the logic chip (MCU, DSP, FPGA, etc.) executes the erase process or when the logic chip is reset and restarted, the state of the control IO is uncertain. This uncertainty will affect the switch application circuit of the back-stage DC low-voltage power supply controlled by the transistor or field effect transistor, so that the switch application circuit state of the controlled back-stage DC low-voltage power supply cannot be output as expected; further, if the switch application circuit of the power supply acts on the power-on and power-off control of another logic system in a complex system, it will cause the other logic system to restart unexpectedly or abnormally lose power. Summary of the invention

[0003] The object of the present invention is to provide a circuit for locking the power supply control state of a logic system, aiming to solve the problems in the prior art.

[0004] In a first aspect, the present application provides a circuit for locking a power supply control state of a logic system, including a logic chip, a latch circuit, and a DC low-voltage power switch application circuit;

[0005] The LE terminal IO of the logic chip is connected to the LE terminal of the latch circuit, the D terminal IO of the logic chip is connected to the D terminal of the latch circuit, and the Q terminal IO of the latch circuit is connected to the Q terminal of the DC low-voltage power switch application circuit;

[0006] When the logic system power supply control circuit is working, the logic chip presets the target Q output state by operating the D terminal IO, and the LE terminal IO outputs a square rising edge to make the preset target Q output state effective; the latch circuit will continue to maintain the effective output state of Q, and apply the effective output state of Q to the DC low-voltage power switch application circuit, and the DC low-voltage power switch application circuit outputs the switch value after receiving the Q target signal of the latch circuit;

[0007] When the latch circuit takes effect and latches a target Q output state, the target Q output state will not be changed regardless of whether the logic chip is program erased or restarted. That is, the switching state of the DC low-voltage power switch application circuit is affected, so that the controlled part of the subsequent stage of the control circuit can work stably and reliably as expected without being disturbed by abnormal conditions of the logic chip.

[0008] Furthermore, the model of the logic chip is 74LS75.

[0009] Furthermore, the latch circuit includes a chip U7, the LE end of the chip U7 is electrically connected to a resistor R43, the resistor R43 is electrically connected to the LE end of the logic chip, the resistor R43 is electrically connected to one end of the resistor R37, the other end of the resistor R37 is grounded, the resistor R43 is electrically connected to one end of the capacitor C31, the other end of the capacitor C31 is grounded, the GND end of the chip U7 is grounded, the D end of the chip U7 is electrically connected to a resistor R44, the resistor R44 is electrically connected to the D end of the logic chip, the VCC end of the chip U7 is electrically connected to a resistor R42, the other end of the resistor R42 is grounded, the resistor R42 is connected in parallel with a capacitor C30, and the OE end of the chip U7 is electrically connected to a resistor R38, and the resistor R38 is grounded.

[0010] Furthermore, the model of the chip U7 is SN74LVC1G373DBVR.

[0011] Further, the DC low-voltage power switch application circuit includes a resistor R41, a first end of the resistor R41 is electrically connected to the Q end of the chip U7, a first end of the resistor R41 is electrically connected to a resistor R40, a first end of the resistor R41 is also electrically connected to a resistor R39, a second end of the resistor R41 is electrically connected to a transistor Q6, one pole of the transistor Q6 is grounded, the other pole of the transistor Q6 is electrically connected to a resistor R46, the other pole of the transistor Q6 is electrically connected to a resistor R36, the other pole of the transistor Q6 is also electrically connected to a capacitor C29, the capacitor C29 is grounded, the resistor R46 is electrically connected to a transistor Q8, and the One electrode of the transistor Q8 is grounded, the other electrode of the transistor Q8 is electrically connected to the MOS transistor Q7, the other electrode of the transistor Q8 is also electrically connected to the resistor R47, the first end of the MOS transistor Q7 is grounded, the second end of the MOS transistor Q7 is used to be electrically connected to the positive electrode of the power supply, the second end of the MOS transistor Q7 is also electrically connected to the Schottky diode D2, the Schottky diode D2 is grounded, the second end of the MOS transistor Q7 is also electrically connected to the resistor R45, the resistor R45 is electrically connected to the light emitting diode LED3, the light emitting diode LED3 is electrically connected to the Schottky diode D2, and the Schottky diode D2 is used to be electrically connected to the negative electrode of the power supply.

[0012] Furthermore, the model of the transistor Q6 is SS8050.

[0013] Furthermore, the model of the transistor Q8 is SS8050.

[0014] Furthermore, the model of the MOS tube Q7 is AOD409.

[0015] Compared with the prior art, the circuit for locking the power supply control state of the logic system provided by the present invention has the following advantages: when the circuit is working, the logic chip circuit presets the target Q output state by operating the D-terminal IO, and the LE-terminal IO outputs a square rising edge to make the preset target Q output state effective. The latch circuit will continue to maintain the effective output state of Q, and apply the effective output state of Q to the DC low-voltage power switch application circuit, and the DC low-voltage power switch application circuit outputs the switch quantity after receiving the Q target signal of the latch circuit. After the latch circuit takes effect and latches a target Q output state, no matter whether the logic chip circuit is erased or restarted, the target Q output state will not be changed, that is, the switch state of the DC low-voltage power switch application circuit is affected, so that the controlled part of the rear stage of the control circuit can work stably and reliably as expected, and will not be disturbed by the abnormal situation of the logic chip circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit diagram of a logic chip provided by an embodiment of the present invention;

[0017] Figure 2 is a circuit diagram of a latch circuit provided by an embodiment of the present invention;

[0018] Figure 3 It is a circuit diagram of a DC low-voltage power switch application circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0021] The implementation of the present invention is described in detail below in conjunction with specific embodiments.

[0022] Reference Figure 1-3 As shown, a preferred embodiment of the present invention is provided.

[0023] A circuit for locking the power supply control state of a logic system provided by the present invention comprises a logic chip 1, a latch circuit 2 and a DC low-voltage power switch application circuit 3;

[0024] The LE terminal IO of the logic chip 1 is connected to the LE terminal of the latch circuit 2, the D terminal IO of the logic chip 1 is connected to the D terminal of the latch circuit 2, and the Q terminal IO of the latch circuit 2 is connected to the Q terminal of the DC low-voltage power switch application circuit 3;

[0025] When the logic system power supply control circuit is working, the logic chip 1 presets the target Q output state by operating the D terminal IO, and the LE terminal IO outputs a square rising edge to make the preset target Q output state effective; the latch circuit 2 will continue to maintain the effective output state of Q, and apply the effective output state of Q to the DC low-voltage power switch application circuit 3, and the DC low-voltage power switch application circuit 3 outputs the switch value after receiving the Q target signal of the latch circuit 2;

[0026] When the latch circuit 2 takes effect and latches a target Q output state, the target Q output state will not be changed whether the logic chip 1 is program erased or restarted, that is, the switching state of the DC low-voltage power switch application circuit 3 is affected, so that the controlled part of the subsequent stage of the control circuit can work stably and reliably as expected without being disturbed by the abnormal situation of the logic chip 1.

[0027] Furthermore, the model of the logic chip 1 is 74LS75.

[0028] Furthermore, the latch circuit 2 includes a chip U7, the LE end of the chip U7 is electrically connected to a resistor R43, the resistor R43 is electrically connected to the LE end of the logic chip 1, the resistor R43 is electrically connected to one end of the resistor R37, the other end of the resistor R37 is grounded, the resistor R43 is electrically connected to one end of the capacitor C31, the other end of the capacitor C31 is grounded, the GND end of the chip U7 is grounded, the D end of the chip U7 is electrically connected to a resistor R44, the resistor R44 is electrically connected to the D end of the logic chip 1, the VCC end of the chip U7 is electrically connected to a resistor R42, the other end of the resistor R42 is grounded, the resistor R42 is connected in parallel with a capacitor C30, and the OE end of the chip U7 is electrically connected to a resistor R38, and the resistor R38 is grounded.

[0029] Furthermore, the model of the chip U7 is SN74LVC1 G373DBVR.

[0030] Further, the DC low-voltage power switch application circuit 3 includes a resistor R41, a first end of the resistor R41 is electrically connected to the Q end of the chip U7, a first end of the resistor R41 is electrically connected to a resistor R40, a first end of the resistor R41 is also electrically connected to a resistor R39, a second end of the resistor R41 is electrically connected to a transistor Q6, one pole of the transistor Q6 is grounded, the other pole of the transistor Q6 is electrically connected to a resistor R46, the other pole of the transistor Q6 is electrically connected to a resistor R36, the other pole of the transistor Q6 is also electrically connected to a capacitor C29, the capacitor C29 is grounded, the resistor R46 is electrically connected to a transistor Q8, and the One electrode of the transistor Q8 is grounded, the other electrode of the transistor Q8 is electrically connected to the MOS transistor Q7, the other electrode of the transistor Q8 is also electrically connected to the resistor R47, the first end of the MOS transistor Q7 is grounded, the second end of the MOS transistor Q7 is used to be electrically connected to the positive electrode of the power supply, the second end of the MOS transistor Q7 is also electrically connected to the Schottky diode D2, the Schottky diode D2 is grounded, the second end of the MOS transistor Q7 is also electrically connected to the resistor R45, the resistor R45 is electrically connected to the light emitting diode LED3, the light emitting diode LED3 is electrically connected to the Schottky diode D2, and the Schottky diode D2 is used to be electrically connected to the negative electrode of the power supply.

[0031] Furthermore, the model of the transistor Q6 is SS8050.

[0032] Furthermore, the model of the transistor Q8 is SS8050.

[0033] Furthermore, the model of the MOS tube Q7 is AOD409.

[0034] Compared with the prior art, the circuit for locking the power supply control state of the logic system provided by the present invention has the following advantages: when the circuit is working, the logic chip 1 circuit presets the target Q output state by operating the D-terminal IO, and the LE-terminal IO outputs a square rising edge to make the preset target Q output state effective. The latch circuit 2 will continue to maintain the effective output state of Q, and apply the effective output state of Q to the DC low-voltage power switch application circuit 3, and the DC low-voltage power switch application circuit 3 outputs the switch quantity after receiving the Q target signal of the latch circuit 2. After the latch circuit 2 takes effect and latches a target Q output state, no matter whether the logic chip 1 circuit is program erased or restarted, the target Q output state will not be changed, that is, the switch state of the DC low-voltage power switch application circuit 3 is affected, so that the controlled part of the later stage of the control circuit can work stably and reliably as expected, and will not be disturbed by the abnormal situation of the logic chip 1 circuit.

[0035] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit for locking the power supply control state of a logic system, characterized in that: Including logic chip, latch circuit and DC low voltage power switch application circuit; The LE terminal IO of the logic chip is connected to the LE terminal of the latch circuit, the D terminal IO of the logic chip is connected to the D terminal of the latch circuit, and the Q terminal IO of the latch circuit is connected to the Q terminal of the DC low-voltage power switch application circuit; When the logic system power supply control circuit is working, the logic chip presets the target Q output state by operating the D terminal IO, and the LE terminal IO outputs a square rising edge to make the preset target Q output state effective; the latch circuit will continue to maintain the effective output state of Q, and apply the effective output state of Q to the DC low-voltage power switch application circuit, and the DC low-voltage power switch application circuit outputs the switch value after receiving the Q target signal of the latch circuit; When the latch circuit takes effect and latches a target Q output state, the target Q output state will not be changed regardless of whether the logic chip is program erased or restarted. That is, the switching state of the DC low-voltage power switch application circuit is affected, so that the controlled part of the subsequent stage of the control circuit can work stably and reliably as expected without being disturbed by abnormal conditions of the logic chip.

2. A circuit for locking a power supply control state of a logic system as claimed in claim 1, characterized in that: The model of the logic chip is 74LS75.

3. A circuit for locking the power supply control state of a logic system as claimed in claim 2, characterized in that: The latch circuit includes a chip U7, an LE end of the chip U7 electrically connected to a resistor R43, the resistor R43 is electrically connected to the LE end of the logic chip, the resistor R43 is electrically connected to one end of the resistor R37, the other end of the resistor R37 is grounded, the resistor R43 is electrically connected to one end of a capacitor C31, the other end of the capacitor C31 is grounded, the GND end of the chip U7 is grounded, the D end of the chip U7 is electrically connected to a resistor R44, the resistor R44 is electrically connected to the D end of the logic chip, the VCC end of the chip U7 is electrically connected to a resistor R42, the other end of the resistor R42 is grounded, the resistor R42 is connected in parallel with a capacitor C30, and the OE end of the chip U7 is electrically connected to a resistor R38, and the resistor R38 is grounded.

4. A circuit for locking a power supply control state of a logic system as claimed in claim 3, characterized in that: The model of the chip U7 is SN74LVC1 G373DBVR.

5. A circuit for locking the power supply control state of a logic system as claimed in claim 4, characterized in that: The DC low-voltage power switch application circuit includes a resistor R41, a first end of the resistor R41 is electrically connected to the Q end of the chip U7, a first end of the resistor R41 is electrically connected to a resistor R40, a first end of the resistor R41 is also electrically connected to a resistor R39, a second end of the resistor R41 is electrically connected to a transistor Q6, one pole of the transistor Q6 is grounded, the other pole of the transistor Q6 is electrically connected to a resistor R46, the other pole of the transistor Q6 is electrically connected to a resistor R36, the other pole of the transistor Q6 is also electrically connected to a capacitor C29, the capacitor C29 is grounded, the resistor R46 is electrically connected to a transistor Q8, the transistor One electrode of the transistor Q8 is grounded, the other electrode of the transistor Q8 is electrically connected to the MOS transistor Q7, the other electrode of the transistor Q8 is also electrically connected to the resistor R47, the first end of the MOS transistor Q7 is grounded, the second end of the MOS transistor Q7 is used to be electrically connected to the positive electrode of the power supply, the second end of the MOS transistor Q7 is also electrically connected to the Schottky diode D2, the Schottky diode D2 is grounded, the second end of the MOS transistor Q7 is also electrically connected to the resistor R45, the resistor R45 is electrically connected to the light emitting diode LED3, the light emitting diode LED3 is electrically connected to the Schottky diode D2, and the Schottky diode D2 is used to be electrically connected to the negative electrode of the power supply.

6. A circuit for locking a power supply control state of a logic system as claimed in claim 5, characterized in that: The model of the transistor Q6 is SS8050.

7. A circuit for locking a power supply control state of a logic system as claimed in claim 6, characterized in that: The model of the transistor Q8 is SS8050.

8. A circuit for locking a power supply control state of a logic system as claimed in claim 7, characterized in that: The model of the MOS tube Q7 is AOD409.

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