Implementation method of controller supporting optical fiber and physical interface and controller

Abstract

The invention relates to an implementation method of a controller supporting an optical fiber and a physical interface and the controller. The method comprises the following steps: a controller upper computer completes configuration of a controller interface operation mode, frequency and dead time parameters and issues the parameters to an FPGA (Field Programmable Gate Array); the FPGA receives interface data and performs data verification, and the data collection processing module selects to output optical fiber or physical I / O interface data to the CPU according to configuration information of the upper computer; a control algorithm model is loaded in the controller CPU, and modulation waves are generated according to sampling data and issued to the FPGA; and the FPGA generates a PWM signal, carries out different processing on the PWM signal according to the configuration information, and then sends the processed PWM signal through the optical fiber or the physical I / O interface. Compared with the prior art, free switching of two operation modes of the optical fiber and the physical I / O interface under the same real-time architecture can be realized, the controller application scenes of the optical fiber and the physical I / O interface are adapted according to different modes, and the adaptability of the controller under various interface application scenes is improved.

Description

Technical Field

[0001] The invention relates to the field of rapid prototype control, and in particular to a controller implementation method supporting optical fiber and physical interface and a controller. Background Art

[0002] With the rapid development of industrial automation, power electronics, and embedded systems, controllers need to process larger amounts of data and respond in shorter times, especially in applications such as power system protection, servo control, and real-time simulation, which places higher demands on the interface compatibility, transmission speed, and flexibility of controllers. The high-speed data transmission capability of the fiber optic interface can meet the needs of low-latency, large data volume transmission, while the physical I / O interface is compatible with the access and control of traditional power equipment. Traditional controllers usually only support a single interface (fiber optic or physical I / O), and the controller configuration is usually relatively fixed, making it difficult to flexibly adjust parameters, resulting in the need to replace or redesign hardware in different application scenarios. Summary of the invention

[0003] The purpose of the present invention is to overcome the problem of the single interface mode of the existing controller and to provide a controller implementation method and device that supports optical fiber and physical interface.

[0004] The purpose of the present invention can be achieved by the following technical solutions:

[0005] As a first aspect of the present invention, a controller implementation method supporting optical fiber and physical interface is provided, wherein the controller includes a multi-channel optical fiber interface and a physical I / O interface, an FPGA and a CPU, and the steps of the implementation method include:

[0006] The controller receives the controller interface operation mode configuration and PWM signal generation parameters sent by the host computer, wherein the interface operation mode includes the optical fiber interface operation mode and the physical I / O interface operation mode;

[0007] The controller receives the optical fiber port or physical I / O interface data, and the data collection and processing module in the FPGA deframes the optical fiber data, and uploads the output optical fiber interface data or physical I / O interface data to the CPU through the data upload module according to the interface operation mode configuration sent by the host computer;

[0008] The controller CPU is loaded with a control algorithm model, which generates a modulation wave based on the sampled data uploaded by the FPGA and sends it to the FPGA together with the switching frequency and dead time data;

[0009] FPGA receives data sent by CPU, generates corresponding triangular carrier according to switching frequency and dead time data, and compares the sent modulation wave with triangular carrier to generate PWM signal;

[0010] The PWM signal sending module in the FPGA receives the generated PWM signal and selects the PWM signal sending method according to the interface operation mode: in the optical fiber interface operation mode, the generated PWM signal is framed into optical fiber serial data according to the frame structure and distributed to each optical fiber interface for transmission; in the physical I / O interface operation mode, the generated PWM signal is sent in parallel through the physical I / O port.

[0011] As a preferred technical solution, the FPGA performs bit error and frame loss check on the received optical fiber data. If a frame loss or error frame is detected, the correct data of the previous frame is kept; if the data is correct, the data is refreshed;

[0012] The FPGA performs denoising processing on the received physical I / O interface data, and sends the processed data to the data collection and processing module.

[0013] As a preferred technical solution, the data collection and processing module deframes the optical fiber data, checks whether the frame synchronization packet header and the frame header are correct, and if they are correct, obtains the serial optical fiber data and writes the address into the cache; converts the deframed serial optical fiber data or the original data received by the physical I / O interface into a format recognizable by the CPU;

[0014] The data collection and processing module automatically selects to output the optical fiber port data or the physical I / O port data to the data upload module according to the operation mode configuration signal sent by the host computer.

[0015] As a preferred technical solution, the steps of uploading the FPGA to the CPU through the data upload module are as follows:

[0016] After the FPGA data upload module detects that the data is ready, it writes the base address of the data collection processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission;

[0017] The CPU polls the data upload module status bit to assert or wait for the data upload module to generate an output interrupt; if based on an interrupt, the interrupt source is determined and the data upload module starts preparing for the next transmission.

[0018] As a preferred technical solution, the steps of generating a PWM signal by the FPGA are as follows:

[0019] The data receiving module in the FPGA receives the modulation wave, dead time, and switching frequency data sent by the CPU, and sends the data to the PWM signal generating module; the PWM signal generating module generates a corresponding triangular carrier according to the switching frequency and dead time data sent by the data receiving module, and compares the modulation wave with the triangular carrier to generate a PWM signal.

[0020] As a preferred technical solution, in the optical fiber interface operation mode, the generated PWM signal is added with a frame header and a frame synchronization packet header according to the optical fiber communication protocol, and is framed into optical fiber serial data and distributed to each optical fiber port for transmission; a single PhaseLeg is 4 bits of data, the first two bits are complementary PWM signals of the upper and lower bridge arms, the third bit is an enable bit, and if it is not enabled, the IGBT is not triggered, and the fourth bit is vacant; every 16 PhaseLeg pulse signals form a 64-bit data, which is sent to the external device via the optical fiber.

[0021] As a second aspect of the present invention, a controller supporting optical fiber and physical interface is provided, the controller comprising:

[0022] Multiple fiber optic interfaces and multiple physical I / O interfaces;

[0023] The FPGA is respectively connected with the multi-channel optical fiber interface and the physical I / O interface signals, includes a data acquisition unit and a signal sending unit, and has an optical fiber interface operation mode and a physical IO interface operation mode;

[0024] The data acquisition unit receives data from the corresponding optical fiber interface or physical I / O interface based on the set interface operation mode, and uploads the sampled data after aggregating and processing the received data;

[0025] The signal sending unit receives the modulated wave and PWM parameter data sent down, generates a PWM signal; according to the set interface operation mode, adopts the corresponding PWM signal sending mode, and sends data through the corresponding optical fiber interface or physical I / O interface;

[0026] The CPU is loaded with a control program. The CPU receives the sampled data uploaded by the FPGA and generates a modulation wave, which is sent to the FPGA together with the PWM parameter data.

[0027] As a preferred technical solution, the data acquisition unit includes:

[0028] The check module performs bit error and frame loss check on the received optical fiber data. If frame loss or error frame is detected, the correct data of the previous frame is kept; if the data is correct, the data is refreshed; the checked data is sent to the data collection and processing module;

[0029] The denoising module performs denoising on the received physical I / O interface data and sends the denoised data to the data collection and processing module;

[0030] The data collection and processing module deframes the optical fiber data, checks whether the frame synchronization packet header and frame header are correct, and if correct, obtains the serial optical fiber data and writes the address into the cache; converts the deframed serial optical fiber data or the original data received by the physical I / O interface into a format recognizable by the CPU; automatically selects to output the optical fiber port data or the physical I / O port data to the data upload module according to the operation mode configuration signal sent by the host computer;

[0031] After detecting that the data is ready, the data upload module writes the base address of the data collection processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission; if the data upload module generates an output interrupt, the interrupt source is determined (transmission completion or transmission error), and the data upload module starts preparing for the next transmission.

[0032] As a preferred technical solution, the signal sending unit includes:

[0033] The data receiving module receives the modulation wave, dead time, and switching frequency data sent by the CPU and sends them to the PWM signal generating module;

[0034] The PWM signal generation module generates a corresponding triangular carrier according to the switching frequency and dead time data received by the data receiving module, and compares the modulated wave with the triangular carrier to generate a PWM signal;

[0035] The PWM signal sending module receives the generated PWM signal and selects the PWM signal sending mode according to the interface operation mode: in the optical fiber interface operation mode, the generated PWM signal is framed into optical fiber serial data according to the frame structure and distributed to each optical fiber port for sending; in the physical I / O interface operation mode, the generated PWM signal is sent in parallel through the physical I / O port.

[0036] As a preferred technical solution, the PWM signal sending module, in the optical fiber interface operation mode, adds a frame header and a frame synchronization packet header to the optical fiber data according to the optical fiber communication protocol, frames it into optical fiber serial data and distributes it to each optical fiber port for sending;

[0037] A single PhaseLeg is 4 bits of data. The first two bits are complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit. If it is not enabled, the IGBT will not be triggered, and the fourth bit is vacant. Every 16 PhaseLeg pulse signals form a 64-bit data, which is sent to the external device via optical fiber.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention configures the interface mode through the host computer without switching versions or bitstream files. It is compatible with optical fiber and physical I / O interfaces under the same real-time architecture, can realize free switching between the two operating modes of optical fiber and physical I / O interfaces under the same real-time architecture, can use optical fiber or physical I / O interface to receive electrical quantities and send PWM signals to control power electronic system objects, and can adapt to the application scenarios of optical fiber and physical I / O controllers according to different modes, thereby improving the adaptability of the controller in various interface application scenarios, solving the problems of single interface and low data transmission efficiency of traditional controllers, and providing efficient, flexible and reliable solutions for the fields of industrial control, power electronics and real-time simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A flowchart of a controller implementation method and device supporting optical fiber and physical interface of the present invention;

[0041] Figure 2 It is a schematic diagram of the controller device in the present invention;

[0042] Figure 3 The following is a workflow diagram of the data collection and processing module in the present invention;

[0043] Figure 4 This is a working diagram of the PWM signal sending module in the present invention;

[0044] Figure 5 A topological diagram of a five-level H-bridge cascaded high-voltage inverter system in one embodiment of the present invention;

[0045] Figure 6 This is a grid-side current simulation waveform diagram in the operation mode of the optical fiber interface of a five-stage H-bridge cascade high-voltage inverter in one embodiment of the present invention;

[0046] Figure 7 This is a grid-side current simulation waveform diagram of a five-level H-bridge cascaded high-voltage inverter in physical I / O interface operation mode in one embodiment of the present invention. DETAILED DESCRIPTION

[0047] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0048] Example 1

[0049] The present invention aims to solve the problem that the existing controller interface mode is single and free switching between optical fiber and physical IO interface cannot be realized in the same real-time architecture. A controller implementation method and a controller device supporting optical fiber and physical interface are proposed. The solution provided by the present invention does not require the user to switch bit streams or change versions. A controller that can support high-speed and low-latency data interaction of massive electrical data by optical fiber and hardware-in-the-loop testing of full physical I / O interfaces can be realized in the same real-time architecture.

[0050] like Figure 1 As shown, the controller implementation method supporting optical fiber and physical interface proposed by the present invention includes the following steps:

[0051] Step 1: The controller host computer completes the configuration of the controller interface operation mode: optical fiber mode or physical I / O interface mode; and configures parameters such as switching frequency and dead time;

[0052] Specifically, in step 1, the user configures the controller interface operating mode. If the user configuration information Mode is set to 0, the optical fiber mode is selected. If the user configuration information Mode is set to 1, the physical I / O interface mode is selected. The configuration data will be sent to the FPGA. The user sets the carrier frequency and dead time. In this embodiment, the carrier frequency setting range is 1 to 1 MHz, and the dead time setting range is 0 to 10 us.

[0053] Step 2: The controller receives the data from the optical fiber port or physical I / O interface. The FPGA performs error and frame loss check on the optical fiber data and performs noise removal on the physical I / O interface data. The processed data is sent to the data collection and processing module. Specifically, step 2 includes the following steps:

[0054] Step 2a: The controller receives serial optical fiber data or physical I / O interface data;

[0055] Step 2b: FPGA performs bit error and frame loss check on the received optical fiber data, and keeps the correct data of the previous frame when checking for frame loss or error frames. If the data is correct, the data is refreshed; and denoising is performed on the received physical I / O interface data;

[0056] Step 2c: FPGA writes the verified and pre-processed data into the data collection and processing module.

[0057] Step 3: If Figure 2 As shown, the data collection and processing module in the FPGA deframes the optical fiber data, and automatically selects to output the optical fiber port data or the physical I / O port data to the data upload module according to the operation mode configuration signal sent by the host computer. Specifically, step 3 includes the following steps:

[0058] Step 3a: If Figure 3 As shown, the data collection and processing module deframes the optical fiber data, checks whether the frame synchronization packet header and the frame header are correct, and if they are correct, obtains the serial optical fiber data, writes the address into the cache, and converts the deframed optical fiber data or the original data received by the physical I / O port into a format recognizable by the CPU (32-bit floating point number or integer), performs data type matching, and ensures that the data uploaded by the FPGA is consistent with the CPU processing requirements;

[0059] Step 3b: The data collection and processing module automatically selects to output fiber port data or physical I / O port data to the subsequent module according to the operation mode configuration signal sent by the host computer; when the Mode value sent by the host computer is 0, the fiber port data is output, and when the Mode is 1, the physical I / O port data is output.

[0060] Step 4: The data upload module in the FPGA uploads the data sent by the data collection and processing module to the CPU; including the following steps:

[0061] Step 4a: After the FPGA data upload module detects that the data is ready, it writes the base address of the data collection processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission;

[0062] Step 4b: The CPU polls the IDLE status bit of the data upload module to assert and wait for the data upload module to generate an output interrupt; an interrupt occurs when the IDLE status bit is pulled high; if an output interrupt occurs, the interrupt source is determined (transmission completed or error occurs), and the data upload module starts preparing for the next transmission. The specific steps are as follows:

[0063] 4b.1). Verify IDLE=1 and program the IDLE bit to the transmission start state (IDLE=0).

[0064] 4b.2). Program the IOC_En bit to the transmission start state (IOC_En=0) and set the error interrupt enable (ERR_En).

[0065] 4b.3). Write the transfer base address into the base address register. The transfer data of this source address must be valid and ready for transmission.

[0066] 4b.4). Write the transfer target address into the target address register.

[0067] 4b.5). Write the number of bytes to be transferred. A maximum of 8,388,607 (8M) bytes can be specified for one transfer. Write to the BTT register to start data transfer.

[0068] 4b.6). Poll the IDLE bit to assert (IDLE=1) and wait for an output interrupt to be generated (IOC_En=1).

[0069] 4b.7). If interrupted, determine the interrupt source: transfer completed or error occurred (ERR_En=1).

[0070] 4b.8). Prepare for another transmission and return to step 4b.1.

[0071] Step 5: The user loads the control algorithm model into the controller CPU. The CPU generates a modulation wave based on the sampled data and sends it to the FPGA. The modulation wave is updated once every CPU cycle.

[0072] Step 6: Each FPGA receives the data sent by the CPU, generates a corresponding triangular carrier according to the switching frequency, dead time and other data sent by the CPU, and compares the modulation wave sent by the CPU with the triangular carrier to generate a PWM signal;

[0073] like Figure 2 As shown, in step 6, the data receiving module in the FPGA receives the modulation wave, dead time, switching frequency and other data sent by the CPU, and sends the data to the PWM signal generating module; the PWM signal generating module generates a corresponding triangular carrier according to the switching frequency and dead time and other data sent by the data receiving module, and compares the modulation wave with the triangular carrier to generate a PWM signal.

[0074] Step 7: The PWM signal sending module in the FPGA receives the generated PWM signal and switches the PWM signal sending mode according to different modes: in the optical fiber mode, the generated PWM signal is framed into optical fiber serial data according to the frame structure and distributed to each optical fiber port for sending; in the physical I / O mode, the generated PWM signal is sent in parallel through the physical I / O port.

[0075] like Figure 4 As shown in the figure, the PWM signal sending module in the FPGA switches the PWM signal sending mode according to different modes: when Mode is 0, that is, in the optical fiber mode, the optical fiber data is added with a frame header and a frame synchronization packet header according to the optical fiber communication protocol, and is framed into optical fiber serial data and distributed to each optical fiber port for sending; a single bridge arm PhaseLeg is 4 bits of data, the first two bits are complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit, if not enabled, the IGBT is not triggered, and the fourth bit is vacant; every 16 PhaseLeg pulse signals form a 64-bit data, a single optical fiber sends 13 64-bit data, which are sent to the external device through the optical fiber, and the frame structure is shown in the following table.

[0076] Table 1 Single fiber frame format

[0077]

[0078] Table 2 Single Phaseleg trigger pulse format

[0079]

[0080]

[0081] When Mode is 1, that is, in the physical IO interface mode, the generated PWM signals are sent in parallel through the physical IO ports. The DO daughter board has 32 channels, a total of 4 DO daughter boards, and supports 128 PWM signals sent by the physical I / O interface.

[0082] Example 2

[0083] As another implementation manner of the present invention, this embodiment provides a controller supporting optical fiber and physical interface constructed by using the above controller implementation method, the controller comprising:

[0084] Multiple fiber optic interfaces and multiple physical I / O interfaces;

[0085] The FPGA is respectively connected with the multi-channel optical fiber interface and the physical I / O interface signals, includes a data acquisition unit and a signal sending unit, and has an optical fiber interface operation mode and a physical IO interface operation mode;

[0086] The data acquisition unit receives data from the corresponding optical fiber interface or physical I / O interface based on the set interface operation mode, and uploads the sampled data after aggregating and processing the received data;

[0087] The signal sending unit receives the modulated wave and PWM parameter data sent down, generates a PWM signal; according to the set interface operation mode, adopts the corresponding PWM signal sending method, and sends data through the corresponding optical fiber interface or physical I / O interface;

[0088] The CPU is loaded with a control program. The CPU receives the sampled data uploaded by the FPGA and generates a modulation wave, which is sent to the FPGA together with the PWM parameter data.

[0089] Specifically, the data acquisition unit includes:

[0090] The check module performs bit error and frame loss check on the received optical fiber data. If frame loss or error frame is detected, the correct data of the previous frame is kept; if the data is correct, the data is refreshed; the checked data is sent to the data collection and processing module;

[0091] The denoising module performs denoising on the received physical I / O interface data and sends the denoised data to the data collection and processing module;

[0092] The data collection and processing module deframes the optical fiber data, checks whether the frame synchronization packet header and frame header are correct, and if correct, obtains the serial optical fiber data and writes the address into the cache; converts the deframed serial optical fiber data or the original data received by the physical I / O interface into a format recognizable by the CPU; automatically selects to output the optical fiber port data or the physical I / O port data to the data upload module according to the operation mode configuration signal sent by the host computer;

[0093] After detecting that the data is ready, the data upload module writes the base address of the data collection processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission; if the data upload module generates an output interrupt, the interrupt source is determined, and the data upload module starts preparing for the next transmission.

[0094] Specifically, the signal sending unit includes:

[0095] The data receiving module receives the modulation wave, dead time, and switching frequency data sent by the CPU and sends them to the PWM signal generating module;

[0096] The PWM signal generation module generates a corresponding triangular carrier according to the switching frequency and dead time data received by the data receiving module, and compares the modulated wave with the triangular carrier to generate a PWM signal;

[0097] The PWM signal sending module receives the generated PWM signal and selects the PWM signal sending mode according to the interface operation mode: in the optical fiber interface operation mode, the generated PWM signal is framed into optical fiber serial data according to the frame structure and distributed to each optical fiber port for sending; in the physical I / O interface operation mode, the generated PWM signal is sent in parallel through the physical I / O port.

[0098] Specifically, the PWM signal sending module, under the optical fiber interface operation mode, adds a frame header and a frame synchronization packet header to the optical fiber data according to the optical fiber communication protocol, frames it into optical fiber serial data and distributes it to each optical fiber port for transmission; a single PhaseLeg is 4 bits of data, the first two bits are complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit, if not enabled, the IGBT is not triggered, and the fourth bit is vacant; every 16 PhaseLeg pulse signals form a 64-bit data, a single optical fiber has a total of 13 64-bit data, which are sent to external devices via the optical fiber.

[0099] Example 3

[0100] This embodiment provides an example of real-time simulation of a five-level H-bridge cascade high-voltage inverter using the controller implementation method described in the above embodiment to verify the performance of the solution proposed in the present invention.

[0101] Simulation model parameters: The input voltage is 6KV medium voltage grid, the grid frequency is 50Hz, and the power unit is connected in series. Each power module in the front stage uses a diode for full-wave rectification, and is filtered by a large capacitor in the middle to make the voltage waveform smoother and more DC; the back stage uses an IGBT inverter bridge to convert DC into a pulse width modulated voltage output, and control the fundamental amplitude and frequency in the output voltage waveform. No boost and filtering device is required, and it can directly drive an ordinary medium voltage motor. A single power unit is an H bridge, which requires 2 Phaseleg signals. The five-level H bridge high-voltage frequency conversion requires a total of 60 PWM signal inputs, which can be controlled by two interface operation modes: optical fiber or physical I / O interface. Using a controller implementation method that supports optical fiber and physical interface provided by this patent, the controller interface operation mode can be freely switched on the host computer under the same real-time architecture, and the optical fiber or physical I / O interface can be used to receive electrical quantities and send PWM signals to control the high-voltage inverter system.

[0102] like Figure 5 As shown in the figure, it is a topology diagram of a five-level H-bridge cascaded high-voltage inverter system. Figure 6 , 7 The grid-side current waveforms are respectively obtained by sampling the optical fiber interface operation mode and the physical I / O interface operation mode by the controller host computer. Figure 6 It can be seen that the use of this controller can realize the free switching of the two operating modes of optical fiber and physical I / O interface under the same real-time architecture. According to the application scenarios of the controller that adapts optical fiber and physical I / O in different modes, the quality of the grid-side current waveform of the high-voltage inverter is good in both interface operating modes, and the error is small. Therefore, a controller implementation method and device that supports optical fiber and physical interface is adopted, and the interface mode is configured by the host computer to realize the free switching of the two interface operating modes, adapt to the requirements of different equipment and process flows, and solve the shortcomings of existing controllers in data transmission and interface adaptation.

[0103] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A controller implementation method supporting optical fiber and physical interface, characterized in that: The controller includes a multi-channel optical fiber interface and a physical I / O interface, an FPGA and a CPU, and the steps of the implementation method include: The controller receives the controller interface operation mode configuration and PWM signal generation parameters sent by the host computer, wherein the interface operation mode includes the optical fiber interface operation mode and the physical I / O interface operation mode; The controller receives the optical fiber port or physical I / O interface data, and the data collection and processing module in the FPGA deframes the optical fiber data, and uploads the output optical fiber interface data or physical I / O interface data to the CPU through the data upload module according to the interface operation mode configuration sent by the host computer; The controller CPU is loaded with a control algorithm model, which generates a modulation wave based on the sampled data uploaded by the FPGA and sends it to the FPGA together with the switching frequency and dead time data; FPGA receives data sent by CPU, generates corresponding triangular carrier according to switching frequency and dead time data, and compares the sent modulation wave with triangular carrier to generate PWM signal; The PWM signal sending module in the FPGA receives the generated PWM signal and selects the PWM signal sending method according to the interface operation mode: in the optical fiber interface operation mode, the generated PWM signal is framed into optical fiber serial data according to the frame structure and distributed to each optical fiber interface for transmission; in the physical I / O interface operation mode, the generated PWM signal is sent in parallel through the physical I / O port.

2. A controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that: The FPGA performs bit error and frame loss check on the received optical fiber data. If frame loss or error frame is detected, the correct data of the previous frame is kept; if the data is correct, the data is refreshed; The FPGA performs denoising processing on the received physical I / O interface data, and sends the processed data to the data collection and processing module.

3. A controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that: The data collection and processing module deframes the optical fiber data, checks whether the frame synchronization packet header and the frame header are correct, and if they are correct, obtains the serial optical fiber data and writes the address into the cache; converts the deframed serial optical fiber data or the original data received by the physical I / O interface into a format recognizable by the CPU; The data collection and processing module automatically selects to output the optical fiber port data or the physical I / O port data to the data upload module according to the operation mode configuration signal sent by the host computer.

4. A controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that: The steps of uploading the FPGA to the CPU through the data upload module are as follows: After the FPGA data upload module detects that the data is ready, it writes the base address of the data collection processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission; The CPU polls the data upload module status bit to assert and waits for the data upload module to generate an output interrupt; if an output interrupt occurs, the interrupt source is determined and the data upload module starts preparing for the next transmission.

5. The method for implementing a controller supporting optical fiber and physical interface according to claim 1, characterized in that: The steps of generating PWM signal by FPGA are as follows: The data receiving module in the FPGA receives the modulation wave, dead time, and switching frequency data sent by the CPU, and sends the data to the PWM signal generating module; the PWM signal generating module generates a corresponding triangular carrier according to the switching frequency and dead time data sent by the data receiving module, and compares the modulation wave with the triangular carrier to generate a PWM signal.

6. A controller implementation method supporting optical fiber and physical interface according to claim 1, characterized in that: In the optical fiber interface operation mode, the generated PWM signal is added with a frame header and a frame synchronization packet header according to the optical fiber communication protocol, and is framed into optical fiber serial data and distributed to each optical fiber port for transmission; a single bridge arm PhaseLeg is 4 bits of data, the first two bits are complementary PWM signals of the upper and lower bridge arms, the third bit is the enable bit, which is not triggered if not enabled, and the fourth bit is vacant; every 16 bridge arm PhaseLeg pulse signals form a 64-bit data, which is sent to the external device via optical fiber.

7. A controller supporting optical fiber and physical interface, characterized in that: The controller comprises: Multiple fiber optic interfaces and multiple physical I / O interfaces; The FPGA is respectively connected with the multi-channel optical fiber interface and the physical I / O interface signals, includes a data acquisition unit and a signal sending unit, and has an optical fiber interface operation mode and a physical IO interface operation mode; The data acquisition unit receives data from the corresponding optical fiber interface or physical I / O interface based on the set interface operation mode, and uploads the sampled data after aggregating and processing the received data; The signal sending unit receives the modulated wave and PWM parameter data sent down, generates a PWM signal; according to the set interface operation mode, adopts the corresponding PWM signal sending mode, and sends data through the corresponding optical fiber interface or physical I / O interface; The CPU is loaded with a control program. The CPU receives the sampled data uploaded by the FPGA and generates a modulation wave, which is sent to the FPGA together with the PWM parameter data.

8. A controller supporting optical fiber and physical interface according to claim 7, characterized in that: The data acquisition unit comprises: The check module performs bit error and frame loss check on the received optical fiber data. If frame loss or error frame is detected, the correct data of the previous frame is kept; if the data is correct, the data is refreshed; the checked data is sent to the data collection and processing module; The denoising module performs denoising on the received physical I / O interface data and sends the denoised data to the data collection and processing module; The data collection and processing module deframes the optical fiber data, checks whether the frame synchronization packet header and frame header are correct, and if correct, obtains the serial optical fiber data and writes the address into the cache; converts the deframed serial optical fiber data or the original data received by the physical I / O interface into a format recognizable by the CPU; automatically selects to output the optical fiber port data or the physical I / O port data to the data upload module according to the operation mode configuration signal sent by the host computer; After detecting that the data is ready, the data upload module writes the base address of the data collection processing module and the CPU memory target address into the address register, configures the transmission data length and the corresponding interface name, and starts data transmission; if the data upload module generates an output interrupt, the interrupt source is determined, and the data upload module starts preparing for the next transmission.

9. A controller supporting optical fiber and physical interface according to claim 7, characterized in that: The signal sending unit comprises: The data receiving module receives the modulation wave, dead time, and switching frequency data sent by the CPU and sends them to the PWM signal generating module; The PWM signal generation module generates a corresponding triangular carrier according to the switching frequency and dead time data received by the data receiving module, and compares the modulated wave with the triangular carrier to generate a PWM signal; The PWM signal sending module receives the generated PWM signal and selects the PWM signal sending mode according to the interface operation mode: in the optical fiber interface operation mode, the generated PWM signal is framed into optical fiber serial data according to the frame structure and distributed to each optical fiber port for sending; in the physical I / O interface operation mode, the generated PWM signal is sent in parallel through the physical I / O port.

10. A controller supporting optical fiber and physical interface according to claim 9, characterized in that: The PWM signal sending module, in the optical fiber interface operation mode, adds a frame header and a frame synchronization packet header to the optical fiber data according to the optical fiber communication protocol, frames it into optical fiber serial data and distributes it to each optical fiber port for sending; A single bridge arm PhaseLeg is 4 bits of data. The first two bits are complementary PWM signals of the upper and lower bridge arms respectively. The third bit is the enable bit. If it is not enabled, it will not be triggered. The fourth bit is vacant. Every 16 PhaseLeg pulse signals form a 64-bit data, which is sent to the external device via optical fiber.

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