Data reading method and memory controller

Abstract

This invention discloses a data reading method and a memory controller. The method includes: storing multiple read commands into cache pools corresponding to different chip enable pins; when preset conditions are met, performing a pre-sorting operation on the read commands in the cache pools to group the read commands into multiple read command groups, where the read commands in each group correspond to different planes and the storage units belong to the same storage unit type; generating an execution command sequence based on the read command groups; and completing parallel read operations based on the execution command sequence. This invention improves the read speed and data channel utilization of SSDs by optimizing the sorting and grouping of read commands.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more specifically to a data reading method and memory controller based on AIPR (Asynchronous Independent Plane Read) applicable to storage devices configured with rewritable non-volatile memory modules. Background Technology

[0002] Non-volatile memory refers to computer memory that retains its data even when the current is cut off. It has advantages such as non-volatile data, low power consumption, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is memory configured with NAND flash (such as solid-state drives), which has the characteristics of high read and write speeds and no need for mechanical structures to access data.

[0004] The storage organization of flash memory chips typically includes Die / LUN (Logical Unit Number), Plane, Block, and Page. Among these, the LUN is the smallest unit in flash memory that independently executes commands. A Die / LUN can contain multiple planes, each consisting of hundreds or even thousands of blocks.

[0005] Currently, SSDs primarily perform read, write, and erase operations on flash memory using a command + address approach. For read operations, the mainstream methods include Single-plane read (SP), Multi-plane read (MP), and Asynchronous Independent Plane Read (AIPR).

[0006] SP read operations perform read operations on only one plane within a single chip at a time. While MP operations can perform operations on multiple planes within a chip, they require setting the same page address. AIPR is a more advanced MP read operation that can perform independent read operations on different pages across multiple planes of the same chip, significantly improving SSD read speeds compared to MP read operations. However, maximizing the utilization of AIPR remains a pressing issue for the industry. Summary of the Invention

[0007] The purpose of this invention is to provide a data reading method and a memory controller, which aims to solve the problem of low AIPR command execution efficiency in the prior art, fully utilize the multi-plane concurrent reading capability of flash memory chips, and improve the command execution rate and data channel utilization of the storage device.

[0008] One or more embodiments of the present invention provide a data reading method based on Asynchronous Independent Plane Read (AIPR), applicable to storage devices configured with rewritable non-volatile memory modules. The method includes: storing multiple read commands from a host system into one or more cache pools, wherein the one or more cache pools correspond to different chip enable pins; when a preset condition is met, performing a pre-sorting operation on multiple first read commands in a first cache pool to group the multiple first read commands into multiple read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the same chip in the storage device, and the storage cells corresponding to each of the one or more second read commands belong to the same storage cell type; generating an execution command sequence corresponding to the first cache pool based on the multiple read command groups in the first cache pool; and executing the multiple commands according to the execution command sequence to complete parallel read operations corresponding to the multiple first read commands.

[0009] In one or more embodiments of the present invention, the preset condition includes at least one of the following: the number of the plurality of first read commands stored in the first cache pool reaches a predetermined threshold; or the waiting time of the earliest first read command stored in the first cache pool reaches a predetermined time threshold.

[0010] In one or more embodiments of the present invention, the method further includes: obtaining the physical address of each read command based on the recorded mapping information; and obtaining the physical characteristics of the physical address of the read command based on the physical address of the read command, wherein the physical characteristics include the chip enable pin, the plane, the chip, and the memory cell type.

[0011] In one or more embodiments of the present invention, the step of performing the pre-sorting operation includes: grouping the plurality of first read commands according to the memory cell type corresponding to each of the plurality of first read commands to obtain one or more memory cell type command groups, wherein the one or more first read commands belonging to the same memory cell type command group correspond to the same memory cell type; grouping the one or more first read commands within the same memory cell type command group according to the chip corresponding to each of the one or more first read commands within the same memory cell type command group to obtain one or more chip command groups, wherein the one or more first read commands belonging to the same chip command group correspond to the same chip; and compiling one or more second read commands pointing to different planes within each chip command group into the same read command group to obtain the plurality of read command groups, wherein the processing order of the one or more second read commands within each read command group is set based on the order of the corresponding planes.

[0012] In one or more embodiments of the present invention, the multiple commands within the execution command sequence include the following types: read trigger command, polling command, and data access command. The step of generating the execution command sequence includes: performing a command sequence generation operation sequentially on each read command group according to the compilation order of the multiple read command groups, wherein when performing the command sequence generation operation on the current read command group among the multiple read command groups, the read trigger command, the polling command, and the data access command corresponding to each current second read command are generated according to the processing order of one or more current second read commands of the current read command group to obtain a first command sequence corresponding to the current read command group; and storing the generated first command sequence into the execution command sequence.

[0013] In one or more embodiments of the present invention, the method further includes: when performing the command sequence generation operation on the current read command group among the plurality of read command groups, checking the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state; and adjusting the processing order of the one or more next second read commands according to the working state of the plane pointed to by the one or more next second read commands.

[0014] In one or more embodiments of the present invention, the step of obtaining the plane pointed to by each of the one or more next second read commands in the next read command group and the working state of the plane includes: if a first plane pointed to by one of the one or more next second read commands is not pointed to by the one or more current second read commands in the current read command group, determining that the working state of the first plane is the idle state; and if a second plane pointed to by one of the one or more next second read commands is pointed to by the one or more current second read commands in the current read command group, determining that the working state of the second plane is the busy state.

[0015] In one or more embodiments of the present invention, the step of adjusting the processing order of the one or more next second read commands includes: prioritizing the processing of the target next second read command of the second plane corresponding to the idle state in the one or more next second read commands.

[0016] In one or more embodiments of the present invention, the method further includes: when performing the command sequence generation operation on the current read command group in the plurality of read command groups, checking the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state; obtaining the target next second read command of the target plane corresponding to the idle state in the one or more next second read commands; generating a target read trigger command, a target polling command, and a target data access command corresponding to the target next second read command; inserting the target read trigger command into the first command sequence; and inserting the target polling command and the target data access command after the first command sequence.

[0017] In one or more embodiments of the present invention, the method further includes: when performing the command sequence generation operation on the current read command group in the plurality of read command groups, checking the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group; and when the target plane pointed to by the target next second read command in the one or more next second read commands is different from the plane corresponding to each of the current second read commands, generating a target read trigger command, a target polling command, and a target data access command corresponding to the target next second read command; inserting the target read trigger command into the first command sequence; and inserting the target polling command and the target data access command after the first command sequence.

[0018] In one or more embodiments of the present invention, the step of generating the read trigger command, the polling command, and the data access command corresponding to each current second read command according to the processing order of the one or more current second read commands of the current read command group includes: generating a first read trigger command corresponding to each current second read command one by one according to the processing order of the one or more current second read commands; generating a pair of first polling commands and a first data access command corresponding to each current second read command one by one according to the processing order of the one or more current second read commands; and storing one or more of the first read trigger commands, one or more pairs of first polling commands, and the first data access commands of the one or more current second read commands as the first command sequence in the execution command sequence.

[0019] In one or more embodiments of the present invention, the step of storing the generated first command sequence into the execution command sequence includes: checking whether there is a previous read command group ordered before the current read command group. If the previous read command group exists, the following steps are performed: obtaining a second command sequence of the previous read command group, wherein the second command sequence includes one or more second read trigger commands, one or more pairs of second polling commands and second data access commands corresponding to one or more previous second read commands of the previous read command group; sequentially inserting the one or more first read trigger commands after the second data access commands corresponding to the same plane according to the processing order of the one or more current second read commands; and sequentially storing the one or more pairs of first polling commands and first data access commands according to the processing order of the one or more current second read commands.

[0020] In one or more embodiments of the present invention, performing the command sequence generation operation on the plurality of read command groups includes: performing command conversion on each second read command of each read command group according to the compilation order of the plurality of read command groups, wherein the command conversion includes generating a read trigger command, a polling command, and a data access command according to the corresponding second read command. Specifically, for the current read command group undergoing command conversion: for each current second read instruction in the current read command group that has not yet undergone command conversion, a read trigger command corresponding to the current second read instruction is generated; a corresponding polling command and data access command are generated for each read trigger command; for each read trigger command, the plane corresponding to the read trigger command is obtained, and it is checked whether there is a target read command pointing to the same plane in the next read command group; if there is a target read command pointing to the same plane, a corresponding target read trigger command is generated based on the target read command in the next read command group, the target read trigger command is inserted after the data access command corresponding to the read trigger command, and a target polling command and target data access command corresponding to the target read trigger command are generated; and if there is no target read command pointing to the same plane, the command conversion of all current second read instructions in the current read command group is completed, and the next read command group is used as the new current read command group to perform the corresponding command conversion, wherein if it is found that there is no next read command group, the generation of the execution command sequence is completed.

[0021] In one or more embodiments of the present invention, performing the command sequence generation operation on the plurality of read command groups includes: according to the compilation order of the plurality of read command groups, performing command conversion on each second read command of each read command group, wherein the command conversion includes generating a read trigger command, a polling command, and a data access command according to the corresponding second read command. Specifically, for the current read command group undergoing command conversion: for each current second read instruction in the current read command group that has not yet undergone command conversion, performing the command conversion includes: if the read trigger command for the current second read instruction undergoing command conversion has not yet been generated, generating a read trigger command corresponding to the current second read command, and generating a corresponding polling command and a data access command for the read trigger command; if the read trigger command for the current second read instruction undergoing command conversion has been generated, generating a corresponding polling command and a data access command for the read trigger command; after generating the corresponding polling command and data access command, obtaining the plane corresponding to the read trigger command, and... Check if there is a target read command pointing to the same plane in the next read command group; if there is a target read command pointing to the same plane, generate a corresponding target read trigger command based on the target read command in the next read command group, insert the target read trigger command after the data access command corresponding to the read trigger command, and complete the command conversion of the current second read instruction; and if there is no target read command pointing to the same plane, complete the command conversion of the current second read command, set the next read command group as the new current read command group, and repeat the above steps to perform the command conversion on the new current read command.

[0022] One or more embodiments of the present invention provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; a data management circuit for electrically connecting to a connection interface circuit of the storage device, for receiving data and commands from a host system via the connection interface circuit; a buffer memory for buffering data; and a processor for electrically connecting to the memory interface control circuit, the data management circuit, and the buffer memory. The processor is configured to: store the plurality of read commands from the host system into one or more cache pools of the buffer memory, wherein the one or more cache pools correspond to different chip enable pins, and the plurality of read commands in the same cache pool all point to the chip enable pin corresponding to their respective cache pool; when a preset condition is met, perform a pre-sorting operation on the plurality of first read commands in the first cache pool of the one or more cache pools to group the plurality of first read commands into a plurality of read command groups, wherein the plurality of second read commands belonging to the same read command group correspond to different planes of the storage device of the rewritable non-volatile memory module and the storage cells corresponding to the plurality of second read commands each belong to the same storage cell type; generate an execution command sequence corresponding to the first cache pool according to the plurality of read command groups in the first cache pool; and execute the plurality of commands according to the generated execution command sequence to complete the parallel read operation corresponding to the plurality of first read commands.

[0023] Based on the above, the data reading method and memory controller provided in this embodiment of the invention can achieve the following beneficial effects: by pre-sorting and grouping the read commands, the parallel reading capability of AIPR technology is fully utilized, thereby improving the read speed of the SSD; by generating an optimized execution command sequence, the utilization rate of the data channel is improved; by considering the storage unit type of the storage unit, performance loss caused by the difference in read time of different types of storage units is avoided; and by dynamically adjusting the command execution order, the utilization rate of the free plane is improved, further optimizing the overall read performance. Attached Figure Description

[0024] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0025] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention;

[0026] Figure 2This is a flowchart illustrating a data reading method according to an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram illustrating the caching of multiple read commands into multiple cache pools according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram illustrating a pre-sorting operation according to an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram illustrating command conversion according to an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram illustrating the process of converting a group of read commands into a first command sequence according to an embodiment of the present invention.

[0031] Figure 7 This is a schematic diagram illustrating the command sequence from the AIPR command of the insert read command group to the previous read command group, as shown in an embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram illustrating the sequence of polling commands and data access commands to execution commands in the storage and read command group, as shown in an embodiment of the present invention.

[0033] Figure 9 This is a command execution timing diagram illustrating the command sequence according to an embodiment of the present invention;

[0034] Figure 10 This is a schematic diagram illustrating the generation of a corresponding execution command sequence based on multiple read command groups according to an embodiment of the present invention;

[0035] Figure 11 This is a schematic diagram illustrating the generation of a corresponding execution command sequence based on multiple read command groups according to another embodiment of the present invention;

[0036] Figure 12 This is a command execution timing diagram illustrating the execution command sequence according to another embodiment of the present invention.

[0037] Explanation of icon numbers

[0038] 10: Host System

[0039] 20: Storage device

[0040] 211: First Processor

[0041] 110: Second Processor

[0042] 120: Host memory

[0043] 130: Data transmission interface circuit

[0044] 210: Memory controller

[0045] 212: Data Management Circuit

[0046] 213: Memory Interface Control Circuit

[0047] 214: Buffer memory

[0048] 220: Rewritable Non-volatile Memory Module

[0049] 230: Connection interface circuit

[0050] S210~S240: Flowchart of the data reading method

[0051] 214(1), 214(2)~214(N): Cache pool

[0052] RC, RC1(1)~RC1(P), RC2(1)~RC2(Q), RCN(1)~RC(R): Read command

[0053] A41: Arrow (First step of grouping)

[0054] A42: Arrow (Second step grouping)

[0055] A43: Arrow (Third step grouping)

[0056] 411: SLC command group

[0057] 412: TLC command group

[0058] 421: SLC_D0 command group

[0059] 422: SLC_D1 command group

[0060] 423: TLC_D0 command group

[0061] 424: TLC_D1 command group

[0062] RP1, RP2: Result pools

[0063] A51: Arrow (Pre-sorting operation)

[0064] A52: Arrow (First read command group command sequence generation operation)

[0065] A53: Arrow (Second read command group command sequence generation operation)

[0066] A54, A55: Arrow (Command sequence stored in the execution command sequence)

[0067] CQ1~CQ5: Execution command sequence

[0068] A611~A614: Arrows (generated by AIPR command)

[0069] A61: Arrow (Generation of polling command and data access command pairs)

[0070] A621~A624: Arrows (corresponding to the generation of AIPR polling commands and data access commands for each plane)

[0071] A62: Arrow (Command sequence generation and storage)

[0072] A71: Arrow (Inserted using AIPR command)

[0073] A721~A724: Arrows (inserted using the AIPR command corresponding to each plane)

[0074] A72: Arrow (Get the command sequence to execute CQ2)

[0075] A81: Arrow (Generates polling and data access commands corresponding to AIPR commands)

[0076] A821~A824: Arrows (Each read command generates corresponding polling command and data access command pairs)

[0077] A83: Arrow (for storing polling commands and data access commands)

[0078] P1: Block (representing the location where polling commands and data access commands are stored)

[0079] A84: Arrow (Get the final execution command sequence CQ3)

[0080] A91: Arrow (Execute command sequence CQ3)

[0081] A111~A114: Arrows (generated by the first read command group AIPR command)

[0082] A115~A118: Arrows (Generation of the first read command group polling command and data access command)

[0083] A121~A124: Arrow (Insert AIPR command in the second read command group)

[0084] A125~A128: Arrows (Generation of the second read command group polling command and data access command)

[0085] A1210: Arrow (Execute command sequence CQ5)

[0086] A1220: Arrow (Reads command "7" related commands to be executed in advance)

[0087] tR1~tR8: Data preparation time Detailed Implementation

[0088] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0089] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0090] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0091] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0092] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0093] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0094] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0095] In this embodiment, the host memory 120 is used to temporarily store commands or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0096] The memory controller 210 is used to execute multiple logic gates or control commands implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the commands of the host system 10.

[0097] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control commands / program codes, and these control commands / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control commands / program codes can also be executed to implement the data reading method provided by this invention. The control commands / program codes corresponding to the data reading method can also be implemented as hardware circuit units to implement the data reading method provided by this invention.

[0098] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and the present invention is not limited thereto.

[0099] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0100] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation according to a write command from the host system 10). Another example is reading data from one or more physical units of the rewritable non-volatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213 and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation according to a read command from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0101] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform write (also known as programming) operations, read operations, or erase operations on the rewritable non-volatile memory module 220.

[0102] Furthermore, data to be written to the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the rewritable non-volatile memory module 220, the processor 211 transmits a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these command sequences may include a write command sequence indicating the writing of data, a read command sequence indicating the reading of data, an erase command sequence indicating the erasure of data, and corresponding command sequences for indicating various memory operations. These command sequences may include one or more signals, or data on the bus. These signals or data may include command codes or program codes. For example, a read command sequence may include information such as the read identification code, memory address, and physical address.

[0103] In this invention, the execution command sequence (also known as the AIPR command sequence) is a specially optimized read command sequence generated by the processor and transmitted to the memory interface control circuit. This command sequence fully utilizes the characteristics of Asynchronous Independent Plane Read (AIPR) technology, enabling simultaneous read operations on different pages of multiple planes. Specifically, the execution command sequence includes multiple AIPR commands (also known as read trigger commands), polling commands, and Direct Memory Access (DMA) commands. Each AIPR command contains specific command codes, target plane identifiers, physical page addresses, and other information. Polling commands are used to check the completion status of the read operation, while DMA commands (also known as data access commands) are used to transfer the read data to the specified memory location. These commands are carefully ordered and organized to maximize parallel read efficiency. For example, the AIPR command sequence may first send multiple AIPR commands for different planes, and then alternately send polling and DMA commands to achieve overlapping execution of read operations and data transfers. Upon receiving this optimized AIPR command sequence, the memory interface control circuit converts it into specific signals and timings acceptable to the rewritable non-volatile memory module, thereby enabling efficient parallel read operations. The generation of the AIPR command sequence provided by the data read method of the present invention will be described below with reference to several embodiments and corresponding figures.

[0104] In this invention, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages, or logical columns) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages, physical columns) configured for the rewritable non-volatile memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to find the physical unit mapped to a logical unit (e.g., find the physical page mapped to a logical page; find the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to find the logical unit mapped to a physical unit (e.g., find the logical page mapped to a physical page; find the logical address mapped to a physical address).

[0105] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and commands from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, address lists, multiple cache pools caching multiple read commands, result pools storing pre-sorted results, one or more AIPR command sequences, and other information associated with this method), so that the processor 211 can quickly access the data, commands, or system data from the buffer memory 214.

[0106] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store data written by the host system 10.

[0107] In this embodiment, the rewritable non-volatile memory module 220 has multiple word lines, each of which is electrically connected to multiple memory cells, also called columns (or entity columns). Multiple columns on the same word line form an entity programming unit (also called an entity page). Each entity page corresponds to an entity address to record the location of the data stored in the entity page. Furthermore, multiple entity pages can form an entity block (also called an entity erase unit). Each memory die (chip) in the multiple memory dies of the rewritable non-volatile memory module has multiple planes, and each plane has multiple entity blocks. It should be noted that the present invention is not limited to the size of each entity page and logical page.

[0108] The Channel (CH) pin (also known as the physical channel) is a set of physical pins in the rewritable non-volatile memory module 220, which is responsible for receiving and transmitting data and commands.

[0109] The Chip enable (CE) pin is used to select or deselect a memory chip. Each CE pin corresponds to a physical chip (memory chip). If a chip enable pin is active, the corresponding physical chip is selected.

[0110] In the architecture of flash memory, the die (chip) is the most basic physical unit, typically corresponding to an independent storage area on the chip. Each chip can contain one or more LUNs (Logical Unit Numbers), which are the smallest units that can independently execute commands. Each LUN is further divided into multiple planes, which are the basic units of parallel operations, enabling simultaneous read and write operations to improve performance.

[0111] The cell type represents the number of bits that can be stored in each cell. Common types include SLC (Single-level Cell, 1 bit per cell), MLC (Multi-level Cell, 2 bits per cell), and TLC (Triple-level Cell, 3 bits per cell). Different cell types vary in storage density, read / write speed, and endurance, affecting the overall performance and characteristics of flash memory.

[0112] In the hierarchical structure of flash memory, the Chip Enable pin (CE) is used to select and activate a specific memory chip. Each CE can control one or more dies (chips). Each chip is an independent physical memory cell, which can contain one or more LUNs (Logical Unit Numbers). A LUN is the smallest unit capable of independently executing commands, and each LUN is further divided into multiple planes for parallel operations. A plane consists of multiple blocks, and each block contains multiple pages. A page is the basic unit for read and write operations, composed of multiple memory cells. The type of memory cell (e.g., SLC, MLC, TLC) determines the number of bits that each cell can store. This hierarchical structure allows flash memory to perform parallel operations at different levels, thereby improving overall performance. For example, AIPR technology allows independent read operations to be performed simultaneously on different planes of the same LUN, fully utilizing this structural characteristic.

[0113] Figure 2 This is a flowchart illustrating a data reading method according to an embodiment of the present invention.

[0114] Please refer to Figure 2 This invention provides a data reading method based on Asynchronous Independent Plane Read (AIPR), which includes the following main steps:

[0115] Step S210: Store the multiple read commands from the host system into one or more cache pools, wherein the one or more cache pools correspond to different chip enable pins, and all read commands in each cache pool point to the chip enable pin corresponding to the cache pool.

[0116] In this embodiment, the memory controller 210 receives multiple read commands from the host system 10 and allocates these commands to different cache pools according to the chip enable pin corresponding to each read command. These cache pools may be part of the buffer memory 214. When the number of commands in a certain cache pool reaches a predetermined threshold or the waiting time of the earliest stored command reaches a predetermined time threshold, the processor 211 of the memory controller 210 performs a pre-sorting operation on the commands in that cache pool.

[0117] Figure 3 This is a schematic diagram illustrating the caching of multiple read commands into multiple cache pools according to an embodiment of the present invention. In one embodiment, the present invention provides a method for caching multiple read commands into multiple cache pools. Figure 3 As shown, the method involves the interaction between the host system 10 and the buffer memory 214 of the memory controller 210 of the storage device 20.

[0118] The host system 10 sends multiple read commands (RCs) to the storage device 20. The buffer memory 214 contains multiple cache pools, each corresponding to a specific chip enable pin (CE). Specifically, cache pool 214(1) corresponds to chip enable pin CE1, cache pool 214(2) corresponds to chip enable pin CE2, and so on, until cache pool 214(N) corresponds to chip enable pin CEN. This one-to-one mapping ensures that read commands stored in each cache pool point to the same chip enable pin.

[0119] When the memory controller 210 receives a read command, it stores these commands into the corresponding buffer pool according to the chip enable pin corresponding to each read command. For example, the read commands RC1(1), RC1(2), ..., RC1(P) related to CE1 are stored in buffer pool 214(1). Similarly, the read commands RC2(1), RC2(2), ..., RC2(Q) related to CE2 are stored in buffer pool 214(2), and so on.

[0120] This storage method has several important advantages:

[0121] (1) Command isolation: Commands for enable pins of different chips are stored separately to avoid confusion and conflict.

[0122] (2) Parallel processing preparation: This lays the foundation for subsequent AIPR operations, as commands in each cache pool can be pre-sorted and optimized independently.

[0123] (3) Resource allocation: Allows the memory controller 210 to manage and allocate resources more efficiently because it can handle the command queue of each chip enable pin individually.

[0124] (4) Flexibility: This structure supports the dynamic addition or removal of chip enable pins, simply by increasing or decreasing the cache pool accordingly.

[0125] In one embodiment, the data reading method of the present invention further includes a step of detailed processing and analysis of the reading commands to prepare for subsequent pre-sorting operations and the generation of AIPR command sequences. Specifically, the method includes the following steps:

[0126] First, when multiple read commands are stored in one or more cache pools, the memory controller 210 assigns a unique sequence number to each read command in each cache pool. For example, for read commands in cache pool 214(1), sequence numbers may be assigned in the order RC1(1), RC1(2), ..., RC1(P) (e.g., "1", "2", ..., "P"). This sequence number allocation mechanism helps to track the order in which commands are received and maintain the timing relationship of commands in subsequent processing.

[0127] Next, the processor 211 obtains the physical address of each read command based on the recorded mapping information (e.g., a logical-to-physical mapping table). This step involves the process of converting logical addresses to physical addresses, typically performed by the flash translation layer (FTL). The mapping information is usually stored in buffer memory 214 or in a dedicated cache of the processor 211.

[0128] Finally, based on the obtained physical address, the processor 211 further obtains the physical characteristics of that physical address. These physical characteristics include:

[0129] Chip enable pin (CE): Indicates the CE corresponding to this physical address.

[0130] Plane: Identifies the specific planar location of this physical address within the chip.

[0131] Die: Indicates the chip where this physical address is located.

[0132] Storage cell type: Indicates the type of storage cell corresponding to this physical address, such as SLC, MLC or TLC.

[0133] Chip enable pins and chip information help determine which specific physical device a command should be sent to. Plane information is crucial for the parallel execution of AIPR operations because it allows the system (memory controller 210) to access different planes on the same chip simultaneously. Memory cell type information helps optimize read timing, as different types of memory cells require different read times.

[0134] The preprocessing steps described above provide an informational basis for subsequent pre-sorting operations. For example, during pre-sorting, commands pointing to different planes can be grouped based on plane information, while also considering storage unit types to ensure that commands within the same group have similar read times. This not only improves the parallelism of AIPR operations but also optimizes overall read efficiency.

[0135] Furthermore, this information provides the necessary parameters for generating AIPR command sequences. When generating AIPR commands, the system can precisely specify the read command, target chip, plane, and read timing.

[0136] Please return Figure 2 In step S220, when the preset conditions are met, the processor 211 performs a pre-sorting operation on the multiple first read commands in the first cache pool of the one or more cache pools to group the multiple first read commands into multiple read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the same chip in the storage device and the storage units corresponding to the one or more second read commands belong to the same storage unit type.

[0137] The purpose of pre-sorting is to group read commands so that commands within the same group correspond to different planes, and the memory cells corresponding to these commands belong to the same memory cell type (such as SLC, MLC, or TLC). This grouping strategy can fully utilize the parallel read capability of AIPR technology while taking into account the read characteristics of different memory cell types.

[0138] In one embodiment, the step of performing the pre-sorting operation includes: grouping the plurality of first read commands according to the memory cell type corresponding to each of the plurality of first read commands to obtain one or more memory cell type command groups, wherein the one or more first read commands belonging to the same memory cell type command group correspond to the same memory cell type; grouping the one or more first read commands within the same memory cell type command group according to the chip corresponding to each of the one or more first read commands within the same memory cell type command group to obtain one or more chip command groups, wherein the one or more first read commands belonging to the same chip command group correspond to the same chip; and compiling one or more second read commands pointing to different planes within each chip command group into the same read command group to obtain the plurality of read command groups, wherein the processing order of the one or more second read commands within each read command group is set based on the order of the corresponding planes. This multi-level grouping strategy ensures that commands within the same group have similar execution characteristics, which is beneficial for subsequent AIPR operations.

[0139] The following uses Figure 4 The pre-sorting operation shown is used as an example to explain this process in detail. Figure 4 This is a schematic diagram illustrating a pre-sorting operation according to an embodiment of the present invention.

[0140] exist Figure 4In the context of the cache pool 214(1), assuming the preset conditions are met, the cache pool contains eight read commands RC1(1) to RC1(8), each command having a sequence number and a corresponding physical characteristic. The physical characteristic includes the chip number (D0 or D1), the plane number (P0 or P1), and the memory cell type (SLC or TLC). For example, the physical characteristic "D0_P1_SLC" of the read command RC1(1) indicates that the physical address corresponding to the read command RC1(1) points to chip D0 and plane P1 within chip D0, and the memory cell type of this physical address is SLC.

[0141] The first step of the pre-sorting operation (indicated by arrow A41) is to group the data according to the storage cell type. In one embodiment, the present invention further optimizes the pre-sorting operation, taking into account the different time (tR) required for read operations of different flash memory types. This maximizes the utilization of each plane and avoids affecting the overall command execution efficiency due to excessively long read times in one plane. Specific implementation details are as follows:

[0142] (1) Flash memory type identification:

[0143] When grouping and sorting read commands, the system first determines which type of flash memory (e.g., SLC, MLC, TLC, etc.) the physical address pointed to by each read command belongs to.

[0144] (2) Grouping by the same type:

[0145] Only read commands belonging to the same flash memory type are grouped into the same command set. For example,

[0146] SLC command group 411 contains read commands RC1(1), RC1(2), RC1(3), RC1(7) and RC1(8), the physical addresses of which all correspond to the SLC memory cell type.

[0147] TLC command group 412 contains read commands RC1(4), RC1(5) and RC1(6), the physical addresses of which all correspond to the SLC memory cell type.

[0148] The second step (indicated by arrow A42) is to group the memory cell types according to the chip:

[0149] SLC command group 411 can be further divided into SLC_D0 command group 421 and SLC_D1 command group 422. For example:

[0150] SLC_D0 command group 421 contains read commands RC1(1) and RC1(8), the physical addresses of which all correspond to chip D0.

[0151] SLC_D1 command group 422 contains read commands RC1(2), RC1(3) and RC1(7), the physical addresses of which all correspond to chip D1.

[0152] For TLC command group 412, it can be further divided into TLC_D0 command group 423 and TLC_D1 command group 424. For example:

[0153] The TLC_D0 command group 423 contains read commands RC1(4) and RC1(5), the physical addresses of which all correspond to chip D0.

[0154] The TLC_D1 command group 424 contains the read command RC1(6), the physical address of which corresponds to chip D1.

[0155] The third step (indicated by arrow A43) is to compile the commands pointing to different planes into the same read command group within each chip command group:

[0156] In the SLC_D0 command group 421, the read commands RC1(1) and RC1(8) point to planes P1 and P0 respectively, so they can be compiled into a read command group. It is worth mentioning that, according to the order of planes P0 and P1, the processing order of the read command RC1(8) (used to process the generation of the corresponding AIPR sequence) can be set to take precedence over the read command RC1(1).

[0157] In the SLC_D1 command group 422, the read commands RC1(2) and RC1(3) point to planes P0 and P1 respectively, and can be compiled into a read command group; the remaining read command RC1(7) is grouped separately.

[0158] In the TLC_D0 command group 423, read commands RC1(4) and RC1(5) point to planes P1 and P0 respectively, and can be compiled into a read command group. It is worth mentioning that, according to the order of planes P0 and P1, the processing order of read command RC1(5) can be set to take precedence over read command RC1(4).

[0159] In the TLC_D1 command group 424, the remaining read commands RC1(6) are grouped separately.

[0160] Ultimately, these read command groups form result pool RP1 (for example, a cache memory 214 can be allocated a cache area as result pool RP1), which contains command groups optimized and sorted according to memory cell type, chip, and plane. For example, {"8", "1"} represents a read command group containing two read commands with serial numbers 8 and 1, which correspond to different planes but belong to the same chip and memory cell type.

[0161] It should be noted that {"8", "1"} also indicates that the processing order of the read command "8" can take precedence over the read command "1".

[0162] Furthermore, in another embodiment, the first step grouping and the second step grouping described above can also be interchanged.

[0163] Please return Figure 2 In step S230, the processor 211 generates an AIPR command sequence corresponding to the first cache pool based on the plurality of read command groups of the first cache pool.

[0164] Specifically, in one embodiment, the step of generating the AIPR command sequence includes: sequentially performing a command sequence generation operation on each of the plurality of read command groups according to their compilation order; wherein, when performing the command sequence generation operation on the current read command group among the plurality of read command groups, the AIPR command, the polling command, and the DMA command corresponding to each current second read command are generated according to the processing order of one or more current second read commands of the current read command group to obtain a first command sequence corresponding to the current read command group; and storing the generated first command sequence into the AIPR command sequence. The generation of the command sequence for each read command group can also be referred to as the command transformation of that read command group.

[0165] Figure 5 This is a schematic diagram illustrating command conversion according to an embodiment of the present invention. The following utilizes... Figure 5 This section details the command conversion process. Please refer to [link / reference]. Figure 5 The cache pool 214(1) contains eight read commands RC1(1) to RC1(8), each command having a sequence number and a corresponding physical characteristic. The physical characteristic includes the chip number (all are D0 in this example for ease of explanation), the plane number (P0, P1, P2 or P3) and the memory cell type (all are SLC in this example for ease of explanation).

[0166] As shown by arrow A51, after the pre-sorting operation, these 8 read commands will be divided into two read command groups, forming result pool RP2: the first group: {"1", "2", "3", "4"}, which contains read commands (these grouped read commands are also called the second read commands) "1" to "4"; the second group: {"5", "6", "7", "8"}, which contains read commands "5" to "8".

[0167] Next, the processor 211 performs command sequence generation operations on the two read command groups respectively.

[0168] As shown by arrow A52, the command sequence generated for the first read command group (also known as the current read command group) includes:

[0169] For the read command (also known as the current second read command) RC1(1), an AIPR command is generated, as well as a polling command and a DMA command corresponding to the AIPR command, corresponding to plane P0.

[0170] For the read command RC1(2), an AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command, are generated, corresponding to plane P1.

[0171] For the read command RC1(3), an AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command are generated, corresponding to plane P2.

[0172] For the read command RC1(4), an AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command, are generated, corresponding to plane P3.

[0173] As shown by arrow A53, the command sequence generated for the second read command group (i.e., the next current read command group) includes:

[0174] For the read command RC1(5), an AIPR command, a polling command and a DMA command corresponding to the AIPR command are generated, corresponding to plane P0.

[0175] For the read command RC1(6), an AIPR command, as well as a polling command and a DMA command corresponding to the AIPR command, are generated, corresponding to plane P1.

[0176] For the read command RC1(7), an AIPR command, a polling command and a DMA command corresponding to the AIPR command are generated, corresponding to plane P2.

[0177] For the read command RC1(8), an AIPR command, a polling command and a DMA command corresponding to the AIPR command are generated, corresponding to plane P3.

[0178] Next, as shown by arrows A54 and A55, the generated command sequence (corresponding to the AIPR command, polling command, and DMA command for each read command group) will be stored in the AIPR command sequence CQ1.

[0179] In one embodiment, the steps for generating the AIPR command sequence are as follows:

[0180] First, based on the processing order of the current second read command (i.e., the read commands in the current read command group), the corresponding first AIPR command is generated one by one. These AIPR commands are used to initiate read operations on a specific plane.

[0181] Next, following the same processing order as the current second read command, a corresponding pair of first polling commands and first DMA commands are generated for each AIPR command. The polling command is used to check the completion status of the read operation, while the DMA command is used to transfer the read data to the specified memory location.

[0182] Finally, all the generated first AIPR commands, first polling commands, and first DMA commands are combined in a specific order to form a first command sequence, which is then stored in the AIPR command sequence.

[0183] The following is even more Figure 6 Taking the command conversion process shown as an example, this article details the process of converting the read command group to generate and store the first command sequence.

[0184] Figure 6 For a schematic diagram illustrating the command conversion of the read command group to generate the first command sequence according to an embodiment of the present invention, please refer to... Figure 6 , Figure 6 This demonstrates a read command group containing four read commands ("1", "2", "3", and "4"), each corresponding to one of four different planes (P0, P1, P2, and P3). The processing order from most to least important is "1", "2", "3", and "4". The command conversion process is as follows:

[0185] (1) AIPR command generation (as shown by arrows A611-A614): Generate the AIPR command corresponding to plane P0 for read command "1"; generate the AIPR command corresponding to plane P1 for read command "2"; generate the AIPR command corresponding to plane P2 for read command "3"; generate the AIPR command corresponding to plane P3 for read command "4".

[0186] (2) Generate polling command and DMA command pairs: After obtaining the AIPR command for each read command in this read command group, you can start generating polling command and DMA command pairs for each AIPR command (as shown by arrow A61).

[0187] For example, as shown by arrow A621: Based on the read command "1", the polling command and DMA command for the AIPR command corresponding to plane P0 are generated; as shown by arrow A622: Based on the read command "2", the polling command and DMA command for the AIPR command of plane P1 are generated; as shown by arrow A623: Based on the read command "3", the polling command and DMA command for the AIPR command of plane P2 are generated; as shown by arrow A624: Based on the read command "4", the polling command and DMA command for the AIPR command of plane P3 are generated.

[0188] (3) Command sequence generation and storage (as shown by arrow A62):

[0189] All the commands generated earlier are combined in the optimized order (in this example, the planar order) to form the first command sequence, and stored in the AIPR command sequence CQ1.

[0190] Processor 211 can execute multiple commands sequentially based on the order of this AIPR command sequence CQ1:

[0191] First, issue all AIPR commands in sequence (corresponding to read commands "1", "2", "3", and "4" respectively) to start parallel read operations on the four planes.

[0192] Then, the polling and DMA commands for each plane are executed in an interleaved manner, for example, the polling and DMA commands for plane P0; the polling and DMA commands for plane P1; the polling and DMA commands for plane P2; and the polling and DMA commands for plane P3.

[0193] In one embodiment, the present invention provides an optimized method for storing a newly generated first command sequence into an AIPR command sequence. This method considers the relationship between the current read command group and previously existing read command groups to achieve more efficient command execution. The specific steps are as follows:

[0194] First, the processor 211 checks if there is a previous read command group that is ordered before the current read command group. This step ensures the continuity and correctness of the command sequence.

[0195] If a previous read command group exists, processor 211 will perform the following operations:

[0196] (1) Obtain the second command sequence of the previous read command group. This sequence contains the second AIPR command, the second polling command, and the second DMA command corresponding to the previous read command group.

[0197] (2) Based on the processing order of each current second read command in the current read command group, the processor 211 inserts the newly generated first AIPR command into the previous command sequence. Specifically, each first AIPR command is inserted after the second DMA command corresponding to the same plane. This insertion method ensures that a new AIPR read operation (also known as a parallel read operation) on the same plane can begin immediately after the previous AIPR read operation completes data transfer.

[0198] (3) Finally, the processor 211 will store the newly generated first polling command and first DMA command pair into the AIPR command sequence according to the processing order of the current second read command.

[0199] This method not only ensures the continuity of command execution, but also maximizes the parallel operation capability of the flash memory chip by optimizing the command insertion position.

[0200] The following uses Figure 7 Let me explain this process in detail. Figure 7 This is a schematic diagram illustrating the command sequence from the AIPR command in the insert read command group to the previous read command group, as shown in an embodiment of the present invention. Please refer to... Figure 7 , Figure 7 This demonstrates how to insert a newly generated command sequence when the previous read command group (CQ1) already exists in the AIPR command sequence.

[0201] (1) Initial state:

[0202] The AIPR command sequence CQ1 already contains the command sequence of the previous read command group, including the AIPR commands (also known as the second AIPR commands) corresponding to read commands "1", "2", "3", and "4" respectively, as well as the corresponding 4 pairs of polling commands (also known as the second polling commands) and DMA commands (also known as the second DMA commands).

[0203] (2) AIPR commands to generate new command sequences:

[0204] As shown by arrows A711 to A714, new AIPR commands (also known as the first AIPR commands) corresponding to the read commands "5", "6", "7", and "8" are generated for the current read command group {"5", "6", "7", and "8"}.

[0205] (3) Insert using the AIPR command (as shown by arrow A71):

[0206] As shown by arrow A721: Insert the corresponding read command "5" AIPR command after the DMA command "1" which corresponds to the same plane (P0).

[0207] As shown by arrow A72: Insert the corresponding read command "6" AIPR command after the DMA command "2" which corresponds to the same plane (P1).

[0208] As shown by arrow A73: Insert the corresponding read command "7" AIPR command after the DMA command "3" which is in the same plane (P2).

[0209] As shown by arrow A74: Insert the corresponding read command "8" AIPR command after the DMA command of read command "4" in the same plane (P3).

[0210] Next, as shown by arrow A72, following the steps described above, after determining whether the planes are the same, and inserting the AIPR commands "5", "6", "7", "8" of the current read command group {"5", "6", "7", "8"} into the AIPR command sequence CQ1, the AIPR command sequence CQ2 is obtained.

[0211] After inserting the AIPR commands "5", "6", "7", and "8" of the current read command group {"5", "6", "7", and "8"} into the AIPR command sequence CQ1, it is also necessary to generate and store a pair of polling commands (also called the first polling command) and DMA commands (also called the first DMA command) corresponding to the AIPR commands of each of the read commands "5", "6", "7", and "8" to complete the operation of generating and storing the command sequence corresponding to the current read command group {"5", "6", "7", and "8"}.

[0212] The following continues Figure 7 Examples, combined Figure 8 Let me explain this process in detail. Figure 8 This is a schematic diagram illustrating the sequence of polling commands and DMA commands to AIPR commands in the storage / read command group, as shown in an embodiment of the present invention. Please refer to... Figure 8 , Figure 8 This demonstrates how, after inserting the AIPR command of the current read command group {"5", "6", "7", "8"} into the AIPR command sequence CQ1, the corresponding polling command and DMA command are generated and stored.

[0213] Assume that the AIPR commands corresponding to read commands "5", "6", "7", and "8" have been inserted after the DMA commands of the corresponding planes, forming the intermediate AIPR command sequence CQ2.

[0214] (1) Generate the corresponding AIPR polling command and DMA command (as shown by arrow A81):

[0215] As shown by arrow A821: Generate the corresponding polling command and DMA command pair for the read command "5"; as shown by arrow A822: Generate the corresponding polling command and DMA command pair for the read command "6"; as shown by arrow A823: Generate the corresponding polling command and DMA command pair for the read command "7"; as shown by arrow A824: Generate the corresponding polling command and DMA command pair for the read command "8".

[0216] (2) Polling commands and DMA commands are stored (as shown by arrow A83):

[0217] The polling commands and DMA commands generated in steps A821-A824 are stored sequentially at the end of the AIPR command sequence CQ2 in the order of processing "5", "6", "7", and "8" (as shown in block P1).

[0218] (3) The final AIPR command sequence is formed (as shown in step A84 with arrow):

[0219] After storing these pairs of polling and DMA commands, obtain the final AIPR command sequence CQ3.

[0220] The above embodiments have illustrated that, when the AIPR command sequence has a command sequence from the previous read command group, the command sequence corresponding to the current read command group is generated and stored in the AIPR command sequence. In the AIPR command sequence CQ3: AIPR commands "5", "6", "7", and "8" are inserted after the previous DMA command in the corresponding plane, and the newly generated polling commands and DMA command pairs are arranged sequentially at the end of the sequence (P1).

[0221] Please return Figure 2 In step S240, the processor 211 executes the plurality of commands according to the generated AIPR command sequence to complete the AIPR read operation corresponding to the plurality of first read commands.

[0222] Based on the pre-sorted command group, processor 211 generates an AIPR command sequence. This sequence contains AIPR commands, polling commands, and direct memory access (DMA) commands, which are generated and stored within the AIPR command sequence according to this method to achieve optimal parallel read performance.

[0223] Finally, the memory interface control circuit 213 executes the corresponding commands according to the generated AIPR command sequence to complete the AIPR read operation on the rewritable non-volatile memory module 220. This method significantly improves the efficiency of data reading, especially in scenarios with a large number of random read requests.

[0224] Figure 9 This is a timing diagram of the AIPR command sequence according to an embodiment of the present invention. Please refer to... Figure 9 In one embodiment, the AIPR command sequence CQ3 is actually executed as follows:

[0225] (1) AIPR command execution:

[0226] First, the system (processor 211) simultaneously sends AIPR commands with corresponding read commands "1", "2", "3", and "4" to the four planes (P0, P1, P2, P3) to initiate parallel read operations.

[0227] (2) Data preparation time:

[0228] Each AIPR command is followed by a corresponding data preparation time (tR1, tR2, tR3, tR4). During this period, each plane independently performs data reading operations.

[0229] (3) Interleave polling and DMA commands:

[0230] After the data preparation time tR1 of the read command "1" for the corresponding plane P0 ends, the system executes the polling command and DMA command for the read command "1".

[0231] After the DMA command is executed on plane P0, the system sends the AIPR command "5" to plane P0 to start the next round of reading on plane P0 (data preparation time tR6 for the AIPR command "5").

[0232] During the data preparation time tR5 of the AIPR command for read command "5", the operation of the next plane P1 can be executed. More specifically, since the data preparation time tR2 of the read command "2" for the next plane P1 has ended, the polling command and DMA command for read command "2" can be executed.

[0233] After the DMA command is executed on plane P1, the system sends the AIPR command "6" to plane P1 to start the next round of reading on plane P1 (the data preparation time tR6 for the AIPR command "6" is entered).

[0234] During the data preparation time tR6 of the AIPR command for read command "6", the system continues to execute the operation of the next plane P2. More specifically, because the data preparation time tR3 of the read command "3" for plane P2 has ended, the system executes the polling command and DMA command for read command "3".

[0235] After the DMA command is executed on plane P2, the system sends the AIPR command "7" to plane P2 to start the next round of reading on plane P2 (the data preparation time tR7 for the AIPR command "7" is entered).

[0236] During the data preparation time tR7 of the AIPR command for read command "7", the system switches to processing the operation of the last plane P3. Since the data preparation time tR4 of the read command "4" for plane P3 has ended, the system executes the polling command and DMA command for read command "4".

[0237] After the DMA command is executed on plane P3, the system sends the AIPR command "8" to plane P3 to start the next round of reading on plane P3 (the data preparation time tR8 for the AIPR command "8" is entered).

[0238] At this point, the system has completed the first round of read operations on all four planes and has started the second round of read operations. Next, the system will return to plane P0 to check if the data for read command "5" is ready. If the data preparation time tR5 has ended, the polling command and DMA command for read command "5" will be executed. Similarly, after the corresponding data preparation times tR6-tR8 have ended, the polling commands and DMA commands for the corresponding read commands "6" to "8" will be executed.

[0239] This iterative process continues until all read commands have been executed. This highly optimized interleaved execution method maximizes the utilization of each plane of the flash memory for read operations, significantly improving the parallelism and efficiency of data reading.

[0240] In one embodiment, the present invention provides another method for generating AIPR command sequences. This method performs command transformation on each second read command within each read command group, following the order in which the read command groups are organized. The command transformation process considers not only the current read command group but also the next read command group. The specific steps are as follows:

[0241] (1) Generate AIPR commands for each second read command (also known as the current second read command) that has not yet been converted in the current read command group.

[0242] (2) Generate corresponding polling and DMA commands for each AIPR command.

[0243] (3) For each AIPR command, check its corresponding plane and see if there is a target read command pointing to the same plane in the next read command group.

[0244] (4) If there is a target read command pointing to the same plane, generate the corresponding target AIPR command and insert it after the DMA command corresponding to the current AIPR command (AIPR command of the same plane), and generate the target polling command and the target DMA command.

[0245] (5) If there is no target read command pointing to the same plane, complete all command conversions in the current read command group and set the next read command group as the new current read command group.

[0246] It should be noted that if there is no next read command group, the entire AIPR command sequence for this cache pool is generated.

[0247] The following uses Figure 10 Let me explain this process in detail. Figure 10 This is a schematic diagram illustrating the generation of corresponding AIPR command sequences based on multiple read command groups according to an embodiment of the present invention.

[0248] Please refer to Figure 10 , Figure 10 This demonstrates how two read command groups ({"1", "2", "3", "4"} and {"5", "6", "7", "8"}) generate the corresponding AIPR command sequence CQ4.

[0249] (1) Process the first group of read commands:

[0250] As shown by arrows A111 to A114, AIPR commands are generated for reading commands "1", "2", "3", and "4" and stored in the AIPR command sequence. Since there are no command sequences for reading command groups within the AIPR command sequence, the generated AIPR commands can be stored directly (without considering the previous reading command groups).

[0251] As shown by arrows A115 to A118, corresponding polling and DMA commands are generated for these AIPR commands.

[0252] (2) Process the second read command group and interleave it with the first read command group:

[0253] As shown by arrow A121, it is found that the read command "5" corresponds to plane P0, which is the same as the read command "1". Therefore, the AIPR command corresponding to the read command "5" is generated and inserted after the DMA command of the read command "1".

[0254] Similarly, as shown by arrows A122 to A124, the AIPR commands for reading commands "6", "7", and "8" are inserted after the DMA commands for reading commands "2", "3", and "4" that correspond to the same plane.

[0255] The polling and DMA commands corresponding to the read commands "1", "2", "3", and "4" and the AIPR commands corresponding to the read commands "5", "6", "7", and "8" generated above are all stored in the AIPR command sequence CQ4.

[0256] As shown by arrows A125 to A128, the corresponding polling and DMA commands for the read commands "5", "6", "7", and "8" are generated and inserted into the end of the sequence in order.

[0257] In another embodiment, performing the command sequence generation operation on the plurality of read command groups includes: performing command conversion on each second read command of each read command group according to the compilation order of the plurality of read command groups, wherein the command conversion includes generating an AIPR command, a polling command, and a DMA command based on the corresponding second read command.

[0258] Specifically, for the current read command group that performs the command conversion:

[0259] For each current second read instruction in the current read command group that has not yet undergone the command translation, the command translation is performed, including the following steps:

[0260] If the AIPR command for the current second read instruction that performs the command conversion has not yet been generated, generate the AIPR command corresponding to the current second read instruction, and generate the corresponding polling command and DMA command for the AIPR command;

[0261] If the AIPR command for the current second read instruction that performs the command conversion has been generated, generate the corresponding polling command and DMA command for the AIPR command;

[0262] After generating the corresponding polling command and DMA command, obtain the plane corresponding to the AIPR command, and check whether there is a target read command pointing to the same plane in the next read command group;

[0263] If a target read command pointing to the same plane exists, a corresponding target AIPR command is generated based on the target read command in the next read command group. This target AIPR command is then inserted after the DMA command corresponding to the AIPR command, and the command conversion for the current second read instruction is completed.

[0264] If there is no target read command pointing to the same plane, the command conversion of the current second read command is completed, and the above steps are repeated to perform the command conversion for the next current read command.

[0265] The following uses Figure 10 To illustrate this concept. Based on... Figure 10 As shown by arrows A111 to A128, we can describe the generation and storage order of each command as follows:

[0266] As shown by arrow A111, generate the AIPR command corresponding to the read command "1" and store it in the AIPR command sequence CQ4;

[0267] As shown by arrow A112, generate the AIPR command corresponding to the read command "2" and store it in the AIPR command sequence CQ4;

[0268] As shown by arrow A113, generate the AIPR command corresponding to the read command "3" and store it in the AIPR command sequence CQ4;

[0269] As shown by arrow A114, generate the AIPR command corresponding to the read command "4" and store it in the AIPR command sequence CQ4;

[0270] As shown by arrow A115, the polling command and DMA command corresponding to the read command "1" are generated and stored in the AIPR command sequence CQ4 to complete the command conversion of the read command "1".

[0271] As shown by arrow A121, after completing the command conversion of read command "1", it is found that the read command "5" of the next read command group points to the same plane P0. The AIPR command corresponding to read command "5" is generated and inserted after the DMA command corresponding to read command "1".

[0272] As shown by arrow A116, the polling command and DMA command corresponding to the read command "2" are generated and stored in the AIPR command sequence CQ4 to complete the command conversion of the read command "2".

[0273] As shown by arrow A122, after completing the command conversion of read command "2", it is found that the read command "6" of the next read command group points to the same plane P1. The AIPR command corresponding to read command "6" is generated and inserted after the DMA command corresponding to read command "2".

[0274] As shown by arrow A117, the polling command and DMA command corresponding to the read command "3" are generated and stored in the AIPR command sequence CQ4 to complete the command conversion of the read command "3".

[0275] As shown by arrow A123, after completing the command conversion of read command "3", it is found that the read command "7" of the next read command group points to the same plane P2. The AIPR command corresponding to read command "7" is generated and inserted after the DMA command corresponding to read command "3".

[0276] As shown by arrow A118, the polling command and DMA command corresponding to the read command "4" are generated and stored in the AIPR command sequence CQ4, thus completing the command conversion of the read command "4".

[0277] As shown by arrow A124, after completing the command conversion of read command "4", it is found that the read command "8" of the next read command group points to the same plane P3. The AIPR command corresponding to read command "8" is generated and inserted after the DMA command corresponding to read command "4".

[0278] As shown by arrow A125, the polling command and DMA command corresponding to the read command "5" are generated and stored at the end of the AIPR command sequence CQ4 to complete the command conversion of the read command "5". After the command conversion of the read command "5" is completed, it is checked that there is no read command pointing to the next read command group of the same plane P0, and it is determined that the next read command "6" can be processed.

[0279] As shown by arrow A126, the polling command and DMA command corresponding to the read command "6" are generated and stored at the end of the AIPR command sequence CQ4. The command conversion of the read command "6" is completed. After the command conversion of the read command "6" is completed, it is checked that there is no read command pointing to the next read command group of the same plane P1, and it is determined that the next read command "7" can be processed.

[0280] As shown by arrow A127, the polling command and DMA command corresponding to the read command "7" are generated and stored at the end of the AIPR command sequence CQ4 to complete the command conversion of the read command "7". After the command conversion of the read command "7" is completed, it is checked that there is no read command pointing to the next read command group of the same plane P2, and it is determined that the next read command "7" can be processed.

[0281] As shown by arrow A128, the polling command and DMA command corresponding to the read command "8" are generated and stored at the end of the AIPR command sequence CQ4. The command conversion of the read command "8" is completed. After the command conversion of the read command "8" is completed, it is checked that there is no read command pointing to the next read command group of the same plane P3, and it is determined that the next read command "8" can be processed.

[0282] In this other embodiment, the command generation and storage order ensures efficient execution of AIPR commands while maximizing the potential of parallel read operations. By inserting the AIPR commands of the second set of read commands after the DMA commands of the first set of commands, the system can begin the next read operation immediately after the data transfer of the previous read operation is completed, thereby significantly improving the read efficiency of the flash memory.

[0283] Based on the above embodiments, the AIPR command sequence generation method of the present invention has several advantages:

[0284] (1) Maximize parallel execution: By inserting the next set of AIPR commands in advance, the system can start a new read operation immediately after the previous read operation has completed data transmission.

[0285] (2) Reduce latency: This method minimizes the idle time between planes, ensuring that each plane can work continuously.

[0286] (3) Dynamic adjustment: This method can dynamically adjust the command sequence according to the actual situation to adapt to different reading modes and workloads.

[0287] (4) Forward-looking optimization: By considering the next read command group, a longer-term optimization strategy is implemented.

[0288] In another embodiment, the present invention also provides a method for dynamically optimizing AIPR command sequence generation. This method, when processing the current read command group, proactively considers the next read command group and adjusts the processing order of multiple commands in the next read command group according to the working state of the plane. The specific steps are as follows:

[0289] (1) Check the next read command group:

[0290] When performing a command sequence generation operation on the current read command group, the system checks the next read command group that follows it. The purpose of this step is to obtain the plane pointed to by each second read command in the next group and its working state.

[0291] (2) Determine the working state of the plane:

[0292] The system determines the working state of the plane using the following rules:

[0293] (a) If the plane pointed to by a second read command in the next read command group (referred to as the first plane) is not pointed to by any command in the current read command group, then the first plane is determined to be in an idle state.

[0294] (b) If the plane pointed to by a second read command in the next read command group (referred to as the second plane) is already pointed to by a command in the current read command group, then the second plane is determined to be busy.

[0295] (3) Adjust the command processing order:

[0296] Based on the above judgment, the system will adjust the processing order of commands in the next read command group. Specifically, the system will prioritize processing read commands that correspond to the idle state plane.

[0297] For example, suppose the current read command group contains commands pointing to planes P0 and P1, and the next read command group contains commands pointing to planes P0, P1, P2, and P3.

[0298] (1) The system first processes the commands in the current read command group.

[0299] (2) When generating the AIPR command sequence for the current read command group, the system checks the commands for the next read command group:

[0300] Planes P0 and P1 are determined to be busy (because the current read command group is already in use).

[0301] Planes P2 and P3 are determined to be in an idle state.

[0302] (3) The system adjusts the processing order of the next read command group:

[0303] Original order: P0, P1, P2, P3

[0304] After adjustment: P2, P3, P0, P1

[0305] In this way, commands pointing to the free planes P2 and P3 are processed in advance.

[0306] (4) When generating the AIPR command sequence, the system will:

[0307] After generating and storing the AIPR commands for the corresponding planes P0 and P1 of the current read command group, generate and store the AIPR commands for the corresponding planes P2 and P3 of the next read command group.

[0308] After the polling command and DMA command for the corresponding plane P0 in the current read command group are stored, the AIPR command for the corresponding plane P0 in the next read command group is immediately inserted.

[0309] After the polling command and DMA command corresponding to plane P1 in the current read command group are stored, immediately insert the AIPR command corresponding to plane P1 in the next read command group.

[0310] Since all read commands in the current read command group have completed command translation, the generation and storage of the next polling command and DMA command will be processed. It should be noted that the polling command and DMA command for the read commands corresponding to planes P2 and P3 will be generated and stored first.

[0311] The following uses Figure 11 To explain. Figure 11 This is a schematic diagram illustrating the generation of a corresponding AIPR command sequence based on multiple read command groups, according to another embodiment of the present invention.

[0312] Please refer to Figure 11 Let's take two read command groups as an example for explanation.

[0313] The first set of read command groups contains three SLC type commands {"1", "2", "3"}, corresponding to planes P0, P1, and P2 respectively. The second set of read command groups contains four TLC type commands {"4", "5", "6", "7"}, corresponding to planes P0, P1, P2, and P3 respectively. The processing procedure is as follows:

[0314] (1) Process the first group of read commands:

[0315] As shown by arrows A111, A112, and A113, the system first generates and stores the AIPR commands for reading commands "1", "2", and "3".

[0316] (2) Check the second read command group:

[0317] When processing the first group of read commands, the system checks the plane that each of the second group of read commands points to and its operating status:

[0318] The planes P0, P1, and P2 pointed to by read commands "4", "5", and "6" are determined to be busy because they have been used by read commands "1", "2", and "3" of the first read command group.

[0319] The plane P3 pointed to by the read command "7" is determined to be in an idle state because the first read command group did not use plane P3.

[0320] (3) Adjust the processing order of the second group of commands:

[0321] Based on the above judgment, the system adjusts the processing order of the second read command group from the original {"4", "5", "6", "7"} to {"7", "4", "5", "6"}, prioritizing the read command "7" pointing to the free plane P3.

[0322] (4) Generate the optimized AIPR command sequence:

[0323] As indicated by arrow A121, processor 211 first generates and inserts the AIPR command for read command "7", which follows the AIPR command of the first read command group.

[0324] Next, as indicated by arrows A115, A116, and A117, processor 211 generates and stores the corresponding polling and DMA commands for read commands "1", "2", and "3". At this point, the command conversion and storage of the command sequence for the first read command group are complete.

[0325] Meanwhile, as indicated by arrows A122, A123 and A124, processor 211 then generates and inserts AIPR commands for read commands "4", "5" and "6" after the DMA commands for the corresponding read commands "1", "2" and "3".

[0326] As indicated by arrows A125, A126, A127, and A128, processor 211 finally generates and stores the polling and DMA commands "7", "4", "5", and "6" for the read commands. At this point, the command conversion and storage of the command sequence for the second read command group are complete.

[0327] Finally, obtain the AIPR command sequence CQ5.

[0328] This method offers the following advantages:

[0329] (1) Improve parallelism: By prioritizing the processing of commands on the idle plane, the parallel operation capability of flash memory is maximized.

[0330] (2) Reduce waiting time: The idle plane can start a new read operation immediately without waiting for all commands in the current group to complete.

[0331] (3) Dynamic optimization: The command sequence is adjusted according to the real-time plane status, making it more adaptable.

[0332] (4) Improve overall efficiency: Intelligent scheduling reduces the idle time of the plane and improves the overall throughput of the storage system.

[0333] Figure 12 This is a command execution timing diagram illustrating an AIPR command sequence according to another embodiment of the present invention. Please refer to... Figure 12 , continuing Figure 11 For example, as shown by arrow A1210, the execution status of the AIPR command sequence CQ5 could be:

[0334] (1) AIPR command execution:

[0335] First, the system simultaneously sends AIPR commands corresponding to the SLC type read commands "1", "2", and "3" to three planes (P0, P1, and P2) to initiate parallel read operations.

[0336] (2) Data preparation time:

[0337] Each AIPR command is followed by a corresponding data preparation time (tR1, tR2, tR3). During this period, each plane independently performs SLC-type data read operations.

[0338] (3) Check the next read command group: The processor 211 determines the read command "7" with the corresponding free plane P3 in the next read command group. The processor 211 generates and inserts the AIPR command for the read command "7" (the processing order of the read command "7" has been advanced because the processing order of the second read command group before the adjustment was "4", "5", "6", "7").

[0339] (4) Interleave the current read command group's polling and DMA commands:

[0340] After the data preparation time tR1 for the read command "1" on the corresponding plane P0 has ended, the system executes the polling command and DMA command for read command "1". It should be noted that this step is executed after the AIPR command for inserting read command "7".

[0341] After the DMA command for read command "1" is executed on plane P0, the processor 211 detects that the next read command group has a read command "4" on the same plane P0, and sends the AIPR command for the read command "4" of the next read command group to plane P0, starting the next round of reading on plane P0 (entering the data preparation time tR4 of the AIPR command for read command "4").

[0342] During the data preparation time tR4 of the AIPR command for read command "4", the system executes the operation of plane P1. Since the data preparation time tR2 of the read command "2" for plane P1 has ended, the system executes the polling command and DMA command for read command "2".

[0343] After the DMA command "2" is executed on plane P1, the system sends the AIPR command "5" to plane P1 to start the next round of reading on plane P1 (data preparation time tR5 for the AIPR command "5").

[0344] During the data preparation time tR5 of the AIPR command for read command "5", the system continues to execute the operation of plane P2. Since the data preparation time tR3 of the read command "3" for plane P2 has ended, the system executes the polling command and DMA command for read command "3".

[0345] After the DMA command "3" is executed on plane P2, the system sends the AIPR command "6" to plane P2 to start the next round of reading on plane P2 (data preparation time tR6 for the AIPR command "6").

[0346] During the data preparation time tR6 of the AIPR command for read command "6", the system continues to execute the operation of plane P3. Since the data preparation time tR7 of the read command "7" for plane P3 has ended, the system executes the polling command and DMA command for read command "7".

[0347] Next, as the data preparation time tR4 to tR6 for the corresponding read commands "4" to "6" ends, the system executes the polling command and DMA command for the corresponding read commands "4" to "6", completing the execution of the entire AIPR command sequence CQ5.

[0348] It is worth noting that, as shown by arrow A1220, the AIPR command, polling command, and DMA command corresponding to read command "7" are executed in advance. This is because the system detects that plane P3 is idle, and therefore prioritizes the processing of read command "7" pointing to P3.

[0349] This invention significantly improves the read efficiency of flash memory through this highly optimized AIPR command sequence execution method, especially in complex scenarios involving mixed memory types and different planar states. This method not only maximizes the advantages of parallel reads but also ensures optimal utilization of system resources through intelligent scheduling.

[0350] It should be noted that in this embodiment, the SLC read command group will be processed first because its overall processing time is faster.

[0351] In one embodiment, the present invention provides a method for further optimizing AIPR command sequence generation. This method reduces command transmission overhead and improves overall reading efficiency by identifying consecutive read operations and merging multiple AIPR commands. The specific steps are as follows:

[0352] (1) Identify continuous read operations:

[0353] When generating the target command sequence, the system analyzes the physical addresses of the read commands. If multiple read commands are found to point to consecutive pages on the same plane, these commands are identified as consecutive read operations.

[0354] (2) Merge AIPR commands:

[0355] For identified consecutive read operations, the system no longer generates a separate AIPR command for each read command, but instead merges them into a single multi-page AIPR command.

[0356] (3) Generate multi-page AIPR command:

[0357] The multi-page AIPR command contains the starting address and number of consecutive pages, enabling the flash controller to initiate read operations on multiple pages at once.

[0358] (4) Adjust polling and DMA commands:

[0359] Accordingly, the system will adjust subsequent polling and DMA commands to accommodate multi-page read operations.

[0360] This method offers the following advantages:

[0361] (1) Reduce command transmission overhead:

[0362] By combining multiple AIPR commands into one, the number of command transfers is significantly reduced, thus lowering bus usage and processor load.

[0363] (2) Improve reading efficiency:

[0364] The flash memory controller can initiate reads of multiple pages at once, reducing latency between individual page reads.

[0365] (3) Simplify command sequences:

[0366] The merged command sequence is more concise and easier to manage and execute.

[0367] Finally, this embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is run in the processor of a host system, the processor executes the steps of the memory simulator and storage device testing method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0368] Based on the above, the data reading method and memory controller provided in the embodiments of the present invention can achieve the following effects:

[0369] (1) Improved efficiency of parallel reading:

[0370] This invention significantly improves parallel read efficiency by optimizing the generation and execution of AIPR command sequences and fully utilizing the multi-plane structure of flash memory. By sending AIPR commands to multiple planes simultaneously, the system can initiate multiple read operations concurrently, greatly improving data access speed.

[0371] (2) Dynamic scheduling optimization:

[0372] This invention introduces a dynamic scheduling mechanism that adjusts the processing order of read commands based on the real-time operating status of the plane. By prioritizing commands pointing to idle planes, the system reduces the idle time of the planes, improves resource utilization, and thus further enhances overall read performance.

[0373] (3) Support for hybrid storage types:

[0374] This invention can simultaneously process read commands from different types of storage units (such as SLC and TLC). By taking into account the characteristics of different storage types, the system can specifically optimize the command execution order, demonstrating excellent performance when handling complex hybrid storage structures.

[0375] (4) Minimize delay:

[0376] By interleaving the execution of AIPR commands, polling commands, and DMA commands, this invention minimizes the waiting time between various operations. For example, while performing data transfer on one plane, the system can simultaneously begin read operations on other planes, effectively reducing overall read latency.

[0377] (5) Maximize resource utilization:

[0378] The method of this invention ensures efficient utilization of each plane in the flash memory. Through intelligent scheduling and dynamic adjustment, the system can maximize the number of active planes at any given time, thereby improving overall throughput.

[0379] (6) Adaptability and flexibility:

[0380] The method of this invention can adapt to various reading modes and workloads. Whether reading continuously or randomly, the system can dynamically adjust its strategy to achieve optimal performance. This flexibility allows the invention to remain highly efficient in various application scenarios.

[0381] (7) Command queue optimization:

[0382] By pre-sorting and dynamically adjusting, this invention optimizes the structure of AIPR command sequences. This not only improves the efficiency of command execution but also reduces the overhead of command transmission and processing.

[0383] (8) Improved data transmission efficiency:

[0384] By optimizing the timing of DMA command execution, this invention ensures the continuity and efficiency of data transmission. This reduces interruptions and waiting times during data transmission, thereby improving overall data throughput.

[0385] It should be noted that in the above embodiments, the target AIPR command is also called the target read trigger command; the target DMA command is also called the target data access command; the first AIPR command and the second AIPR command are also called the first read trigger command and the second read trigger command, respectively; the first DMA command and the second DMA command are also called the first data access command and the second data access command, respectively.

[0386] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, applicable to a storage device configured with a rewritable non-volatile memory module, wherein the storage device supports asynchronous independent plane reading, characterized in that, The method includes: Multiple read commands from the host system are stored in one or more cache pools, wherein the one or more cache pools correspond to different chip enable pins, and all read commands in each cache pool point to the chip enable pin corresponding to the cache pool. When the preset conditions are met, a pre-sorting operation is performed on the multiple first read commands in the first cache pool of the one or more cache pools to group the multiple first read commands into multiple read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the same chip in the storage device, and the storage units corresponding to the one or more second read commands each belong to the same storage unit type. Based on the plurality of read command groups in the first cache pool, generate an execution command sequence corresponding to the first cache pool; and According to the execution command sequence, multiple commands in the execution command sequence are executed to complete the parallel reading operation corresponding to the multiple first read commands.

2. The data reading method according to claim 1, characterized in that, The preset conditions include at least one of the following: The number of the plurality of first read commands stored in the first cache pool reaches a predetermined threshold; or The waiting time for the first read command, which was the earliest stored in the first cache pool, reaches a predetermined time threshold.

3. The data reading method according to claim 1, characterized in that, The method further includes: Based on the recorded mapping information, obtain the physical address of each read command; and Based on the physical address of the read command, obtain the physical characteristics of the physical address of the read command, wherein the physical characteristics include the chip enable pin, the plane, the chip, and the memory cell type.

4. The data reading method according to claim 3, characterized in that, The steps for performing the pre-sorting operation include: Based on the storage unit type corresponding to each of the plurality of first read commands, the plurality of first read commands are grouped to obtain one or more storage unit type command groups, wherein one or more first read commands belonging to the same storage unit type command group correspond to the same storage unit type; Based on the chip corresponding to each of the one or more first read commands within the same memory cell type command group, group the one or more first read commands within the same memory cell type command group to obtain one or more chip command groups, wherein the one or more first read commands belonging to the same chip command group correspond to the same chip; as well as Each chip command group contains one or more second read commands that point to different planes, which are then compiled into the same read command group to obtain the multiple read command groups. The processing order of one or more second read commands in each read command group is set based on the order of the corresponding planes.

5. The data reading method according to claim 3, characterized in that, The multiple commands within the execution command sequence include the following types: read trigger command, polling command, and data access command, wherein the step of generating the execution command sequence includes: Based on the compilation order of the multiple read command groups, a command sequence generation operation is performed sequentially for each read command group. When performing the command sequence generation operation on the current read command group among the plurality of read command groups, the read trigger command, the polling command, and the data access command corresponding to each current second read command are generated according to the processing order of one or more current second read commands in the current read command group, so as to obtain the first command sequence corresponding to the current read command group; as well as The generated first command sequence is stored in the execution command sequence.

6. The data reading method according to claim 5, characterized in that, The method further includes: When performing the command sequence generation operation on the current read command group among the plurality of read command groups, the next read command group sorted after the current read command group is checked to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state; and The processing order of the one or more next second read commands is adjusted according to the working state of the plane to which each of the one or more next second read commands points.

7. The data reading method according to claim 6, characterized in that, The steps of obtaining the plane pointed to by each of the one or more next second read commands in the next read command group and the working state of the plane include: If the first plane pointed to by one of the one or more next second read commands is not pointed to by the one or more current second read commands in the current read command group, the working state of the first plane is determined to be the idle state; and If the second plane pointed to by one of the next second read commands is already pointed to by the current second read commands in the current read command group, the working state of the second plane is determined to be the busy state.

8. The data reading method according to claim 7, characterized in that, The steps of adjusting the processing order of the one or more next second read commands include: Prioritize processing the next second read command for the target of the second plane that is in an idle state in one or more next second read commands.

9. The data reading method according to claim 5, characterized in that, The method further includes: When performing the command sequence generation operation on the current read command group among the plurality of read command groups, the next read command group sorted after the current read command group is checked to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state. Obtain the next second read command for the target plane in the idle state from the one or more next second read commands; Generate a target read trigger command, a target polling command, and a target data access command corresponding to the next second read command for the target; Insert the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

10. The data reading method according to claim 5, characterized in that, The method further includes: When performing the command sequence generation operation on the current read command group among the plurality of read command groups, check the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group; as well as When the target plane pointed to by the one or more next second read commands is different from the plane corresponding to each of the current second read commands, Generate a target read trigger command, a target polling command, and a target data access command corresponding to the next second read command for the target; Insert the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

11. The data reading method according to claim 5, characterized in that, The step of generating the read trigger command, the polling command, and the data access command corresponding to each current second read command, based on the processing order of the one or more current second read commands in the current read command group, includes: Based on the processing order of the one or more current second read commands, generate a first read trigger command corresponding to each current second read command in turn; Based on the processing order of the one or more current second read commands, generate a pair of first polling commands and first data access commands corresponding to each current second read command; and The first read trigger command, the first polling command, and the first data access command are stored as the first command sequence in the execution command sequence.

12. The data reading method according to claim 11, characterized in that, The step of storing the generated first command sequence into the execution command sequence includes: Check if there exists a previous read command group that is ordered before the current read command group; If the aforementioned previous read command group exists, perform the following steps: Obtain the second command sequence of the previous read command group, wherein the second command sequence includes one or more second read trigger commands, one or more pairs of second polling commands and second data access commands corresponding to one or more previous second read commands of the previous read command group; According to the processing order of the one or more current second read commands, the one or more first read trigger commands are sequentially inserted after the second data access commands corresponding to the same plane; and According to the processing order of the one or more current second read commands, the one or more pairs of the first polling commands and the first data access commands are stored sequentially.

13. The data reading method according to claim 5, characterized in that, Performing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the multiple read command groups, each second read command in each read command group is converted into a command. The command conversion includes generating a read trigger command, a polling command, and a data access command based on the corresponding second read command. Specifically, for the current read command group that performs the command conversion: For each current second read instruction in the current read command group that has not yet undergone the command conversion, generate a read trigger command corresponding to the current second read instruction; Generate corresponding polling commands and data access commands for each read trigger command; For each read trigger command, obtain the plane corresponding to the read trigger command, and check whether there is a target read command pointing to the same plane in the next read command group; If a target read command pointing to the same plane exists, a corresponding target read trigger command is generated based on the target read command in the next read command group. This target read trigger command is then inserted after the data access command corresponding to the read trigger command, and a target polling command and a target data access command corresponding to the target read trigger command are generated. If no target read command points to the same plane, then the command conversion of all current second read commands in the current read command group is completed, and the next read command group is taken as the new current read command group for corresponding command conversion. If it is found that there is no next read command group, the generation of the execution command sequence is completed.

14. The data reading method according to claim 5, characterized in that, Performing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the multiple read command groups, each second read command in each read command group is converted into a command. The command conversion includes generating a read trigger command, a polling command, and a data access command based on the corresponding second read command. Specifically, for the current read command group that performs the command conversion: For each current second read instruction in the current read command group that has not yet undergone the command translation, the command translation is performed, including: If the read trigger command for the current second read instruction that performs the command conversion has not yet been generated, generate the read trigger command corresponding to the current second read command, and generate the corresponding polling command and data access command for the read trigger command; If the read trigger command for the current second read instruction that performs the command conversion has been generated, generate a corresponding polling command and data access command for the read trigger command; After generating the corresponding polling command and data access command, obtain the plane corresponding to the read trigger command, and check whether there is a target read command pointing to the same plane in the next read command group; If a target read command pointing to the same plane exists, a corresponding target read trigger command is generated based on the target read command in the next read command group. This target read trigger command is then inserted after the data access command corresponding to the read trigger command, and the command conversion for the current second read instruction is completed. If there is no target read command pointing to the same plane, the command conversion of the current second read command is completed, the next read command group is set as the new current read command group, and the above steps are repeated to perform the command conversion on the new current read command.

15. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is used to electrically connect to the rewritable non-volatile memory module; A data management circuit, electrically connected to the connection interface circuit of the storage device, is used to receive data and commands from the host system via the connection interface circuit; Buffer memory, used to cache data; and A processor electrically connected to the memory interface control circuit, the data management circuit, and the buffer memory, wherein the processor is configured to: Multiple read commands from the host system are stored in one or more cache pools of the buffer memory, wherein the one or more cache pools correspond to different chip enable pins, and all read commands of each cache pool point to the chip enable pin corresponding to its respective cache pool; When the preset conditions are met, a pre-sorting operation is performed on the multiple first read commands in the first cache pool of the one or more cache pools to group the multiple first read commands into multiple read command groups, wherein one or more second read commands belonging to the same read command group correspond to different planes of the storage device of the rewritable non-volatile memory module and the storage units corresponding to each of the one or more second read commands belong to the same storage unit type. Based on the plurality of read command groups in the first cache pool, generate an execution command sequence corresponding to the first cache pool; and Based on the generated execution command sequence, multiple commands in the execution command sequence are executed to complete the parallel reading operation corresponding to the multiple first read commands.

16. The memory controller according to claim 15, characterized in that, The preset conditions include at least one of the following: The number of the plurality of first read commands stored in the first cache pool reaches a predetermined threshold; or The waiting time for the first read command, which was the earliest stored in the first cache pool, reaches a predetermined time threshold.

17. The memory controller according to claim 15, characterized in that, The processor is also configured to: Based on the recorded mapping information, obtain the physical address of each read command; and Based on the physical address of the read command, obtain the physical characteristics of the physical address of the read command, wherein the physical characteristics include the chip enable pin, the plane, the chip, and the memory cell type.

18. The memory controller according to claim 17, characterized in that, The steps for performing the pre-sorting operation include: Based on the storage unit type corresponding to each of the plurality of first read commands, the plurality of first read commands are grouped to obtain one or more storage unit type command groups, wherein one or more first read commands belonging to the same storage unit type command group correspond to the same storage unit type; Based on the chip corresponding to each of the one or more first read commands within the same memory cell type command group, group the one or more first read commands within the same memory cell type command group to obtain one or more chip command groups, wherein the one or more first read commands belonging to the same chip command group correspond to the same chip; as well as Each chip command group contains one or more second read commands that point to different planes, which are then compiled into the same read command group to obtain the multiple read command groups. The processing order of one or more second read commands in each read command group is set based on the order of the corresponding planes.

19. The memory controller according to claim 18, characterized in that, The multiple commands within the execution command sequence include the following types: read trigger command, polling command, and data access command, wherein the step of generating the execution command sequence includes: Based on the compilation order of the multiple read command groups, a command sequence generation operation is performed sequentially for each read command group. When performing the command sequence generation operation on the current read command group among the plurality of read command groups, the read trigger command, the polling command, and the data access command corresponding to each current second read command are generated according to the processing order of one or more current second read commands in the current read command group, so as to obtain the first command sequence corresponding to the current read command group; as well as The generated first command sequence is stored in the execution command sequence.

20. The memory controller according to claim 19, characterized in that, The processor is also configured to: When performing the command sequence generation operation on the current read command group among the plurality of read command groups, the next read command group sorted after the current read command group is checked to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state. as well as The processing order of the one or more next second read commands is adjusted according to the working state of the plane to which each of the one or more next second read commands points.

21. The memory controller according to claim 20, characterized in that, The steps of obtaining the plane pointed to by each of the one or more next second read commands in the next read command group and the working state of the plane include: If the first plane pointed to by one of the one or more next second read commands is not pointed to by the one or more current second read commands in the current read command group, the working state of the first plane is determined to be the idle state; and If the second plane pointed to by one of the next second read commands is already pointed to by the current second read commands in the current read command group, the working state of the second plane is determined to be the busy state.

22. The memory controller according to claim 21, characterized in that, The steps of adjusting the processing order of the one or more next second read commands include: Prioritize processing the next second read command for the target of the second plane that is in an idle state in one or more next second read commands.

23. The memory controller according to claim 19, characterized in that, The processor is also configured to: When performing the command sequence generation operation on the current read command group among the plurality of read command groups, the next read command group sorted after the current read command group is checked to obtain the plane pointed to by one or more next second read commands in the next read command group and the working state of the plane, wherein the working state includes an idle state and a busy state. Obtain the next second read command for the target plane in the idle state from the one or more next second read commands; Generate a target read trigger command, a target polling command, and a target data access command corresponding to the next second read command for the target; Insert the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

24. The memory controller according to claim 19, characterized in that, The processor is also configured to: When performing the command sequence generation operation on the current read command group among the plurality of read command groups, check the next read command group sorted after the current read command group to obtain the plane pointed to by one or more next second read commands in the next read command group; as well as When the target plane pointed to by the one or more next second read commands is different from the plane corresponding to each of the current second read commands, Generate a target read trigger command, a target polling command, and a target data access command corresponding to the next second read command for the target; Insert the target read trigger command into the first command sequence; as well as The target polling command and the target data access command are inserted after the first command sequence.

25. The memory controller according to claim 19, characterized in that, The step of generating the read trigger command, the polling command, and the data access command corresponding to each current second read command, based on the processing order of the one or more current second read commands in the current read command group, includes: Based on the processing order of the one or more current second read commands, generate a first read trigger command corresponding to each current second read command in turn; Based on the processing order of the one or more current second read commands, generate a pair of first polling commands and first data access commands corresponding to each current second read command; and The first read trigger command, the first polling command, and the first data access command are stored as the first command sequence in the execution command sequence.

26. The memory controller according to claim 25, characterized in that, The step of storing the generated first command sequence into the execution command sequence includes: Check if there exists a previous read command group that is ordered before the current read command group; If the aforementioned previous read command group exists, perform the following steps: Obtain the second command sequence of the previous read command group, wherein the second command sequence includes one or more second read trigger commands, one or more pairs of second polling commands and second data access commands corresponding to one or more previous second read commands of the previous read command group; According to the processing order of the one or more current second read commands, the one or more first read trigger commands are sequentially inserted after the second data access commands corresponding to the same plane; and According to the processing order of the one or more current second read commands, the one or more pairs of the first polling commands and the first data access commands are stored sequentially.

27. The memory controller according to claim 19, characterized in that, Performing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the multiple read command groups, each second read command in each read command group is converted into a command. The command conversion includes generating a read trigger command, a polling command, and a data access command based on the corresponding second read command. Specifically, for the current read command group that performs the command conversion: For each current second read instruction in the current read command group that has not yet undergone the command conversion, generate a read trigger command corresponding to the current second read instruction; Generate corresponding polling commands and data access commands for each read trigger command; For each read trigger command, obtain the plane corresponding to the read trigger command, and check whether there is a target read command pointing to the same plane in the next read command group; If a target read command pointing to the same plane exists, a corresponding target read trigger command is generated based on the target read command in the next read command group. This target read trigger command is then inserted after the data access command corresponding to the read trigger command, and a target polling command and a target data access command corresponding to the target read trigger command are generated. If no target read command points to the same plane, then the command conversion of all current second read commands in the current read command group is completed, and the next read command group is taken as the new current read command group for corresponding command conversion. If it is found that there is no next read command group, the generation of the execution command sequence is completed.

28. The memory controller according to claim 19, characterized in that, Performing the command sequence generation operation on the plurality of read command groups includes: According to the compilation order of the multiple read command groups, each second read command in each read command group is converted into a command. The command conversion includes generating a read trigger command, a polling command, and a data access command based on the corresponding second read command. Specifically, for the current read command group that performs the command conversion: For each current second read instruction in the current read command group that has not yet undergone the command translation, the command translation is performed, including: If the read trigger command for the current second read instruction that performs the command conversion has not yet been generated, generate the read trigger command corresponding to the current second read command, and generate the corresponding polling command and data access command for the read trigger command; If the read trigger command for the current second read instruction that performs the command conversion has been generated, generate a corresponding polling command and data access command for the read trigger command; After generating the corresponding polling command and data access command, obtain the plane corresponding to the read trigger command, and check whether there is a target read command pointing to the same plane in the next read command group; If a target read command pointing to the same plane exists, a corresponding target read trigger command is generated based on the target read command in the next read command group. This target read trigger command is then inserted after the data access command corresponding to the read trigger command, and the command conversion for the current second read instruction is completed. If there is no target read command pointing to the same plane, the command conversion of the current second read command is completed, the next read command group is set as the new current read command group, and the above steps are repeated to perform the command conversion on the new current read command.

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