Miller-rabin algorithm acceleration method and device based on software and hardware fusion

Abstract

The invention relates to a Miller-Rabin algorithm acceleration method and device based on software and hardware fusion. When the Miller-Rabin algorithm is executed, to-be-verified target data is loaded to the data splitting hardware unit, the data splitting hardware unit is used for performing data splitting on the target data, a decomposition array matched with the target data is generated after data splitting, modular exponentiation operation object data is generated based on the decomposition array, and the modular exponentiation operation object data is sent to the data splitting hardware unit. The modular exponentiation hardware unit is used for executing modular exponentiation on the modular exponentiation object data, the logic judgment unit is used for carrying out logic judgment on the first modular exponentiation result value and the second modular exponentiation result value, and the modular exponentiation object data is obtained based on the corresponding logic judgment states of the first modular exponentiation result value and the second modular exponentiation result value. And generating a data verification state corresponding to the target data. According to the method, the efficiency of large-batch prime number judgment by utilizing the Miller-Robin algorithm can be effectively improved, the computing power requirement for operating the Miller-Robin algorithm is reduced, and the prime number judgment and generation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to an acceleration method and device, in particular to a Miller-Rabin algorithm acceleration method and device based on software and hardware fusion. Background Art

[0002] The Miller-Rabin algorithm is a randomization algorithm used to determine whether a number is prime. It is widely used in cryptography, number theory and other fields. In privacy computing, the determination of prime numbers is very important. For example, in the RSA encryption algorithm, two large prime numbers need to be generated. At this time, the Miller-Rabin algorithm can be used to quickly determine whether the generated number is prime, thereby improving the efficiency of generating prime numbers.

[0003] When executing the Miller-Rabin algorithm, it involves the splitting of large numbers and multiple exponentiation and modulo processing. These processing operations are very time-consuming. At present, when judging whether the data is a prime number, more program scripts are written to execute the Miller-Rabin algorithm.

[0004] From the above description, it can be seen that the current implementation of the Miller-Rabin algorithm relies heavily on the operation of software programs. Once a large number of prime numbers need to be judged, it will lead to insufficient computing power, affecting the judgment and generation efficiency of prime numbers. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a method and device for accelerating the Miller-Rabin algorithm based on software and hardware fusion, which can effectively improve the efficiency of large-scale prime number judgment using the Miller-Rabin algorithm, reduce the computing power requirements for running the Miller-Rabin algorithm, and improve the judgment and generation efficiency of prime numbers.

[0006] According to the technical solution provided by the present invention, a method for accelerating the Miller-Rabin algorithm based on software and hardware fusion is provided, and the method for accelerating the Miller-Rabin algorithm comprises:

[0007] At least a data splitting hardware unit for performing data splitting, a modular exponentiation hardware unit for performing modular exponentiation, and a logic judgment unit for performing logic judgment are configured, wherein:

[0008] When executing the Miller-Rabin algorithm, the target data to be verified is loaded into the data splitting hardware unit, so as to use the data splitting hardware unit to perform data splitting on the target data, and generate a decomposition array matching the target data after the data splitting, wherein the decomposition array includes at least a first decomposition radix and a second decomposition radix;

[0009] Generate modular exponentiation object data based on the decomposed array, and use a modular exponentiation hardware unit to perform modular exponentiation on the modular exponentiation object data, wherein when executing the Miller-Rabin algorithm, the modular exponentiation performed by the modular exponentiation hardware unit includes at least a first modular exponentiation and a second modular exponentiation in one round of judgment, and after performing the first modular exponentiation, a first modular exponentiation result value is generated, and after performing the second modular exponentiation, a second modular exponentiation result value is generated;

[0010] A logic judgment unit is used to perform logic judgment on the first modular exponentiation result value and the second modular exponentiation result value, and based on the corresponding logic judgment states of the first modular exponentiation result value and the second modular exponentiation result value, a data verification state corresponding to the target data is generated, wherein the data verification state includes whether the target data is a prime number or a composite number.

[0011] The data splitting hardware unit includes a first decomposition radix generation circuit and a second decomposition radix generation circuit, wherein:

[0012] The first decomposition radix generation circuit is adaptively connected to the second decomposition radix generation circuit;

[0013] The first decomposition radix generation circuit receives the target data, and solves the data status information of the target data based on the first reference number, and generates the first decomposition radix based on the target data, the first reference number and the data status information of the target data, wherein the data status information of the target data includes whether the target data is an odd number or an even number;

[0014] The second decomposition radix generation circuit receives the second reference number and generates a corresponding second decomposition radix based on the data state information, wherein the first reference number and the second reference number are mutually exclusive one-bit binary numbers;

[0015] When executing the Miller-Rabin algorithm, based on the update control signal and the data status information of the target data, the first decomposition base and the second decomposition base are cyclically updated until the data splitting termination condition is reached;

[0016] When the first decomposition target cardinality and the second decomposition target cardinality are formed based on the updated first decomposition cardinality and the second decomposition cardinality, respectively, then: p = 2 r *u, p is the target data, r is the first decomposition target cardinality, and u is the second decomposition target cardinality.

[0017] When executing the Miller-Rabin algorithm, the data is split into hardware units, and then:

[0018] Subtract the target data from the first reference number to generate a data state judgment base number, where:

[0019] When the data state judgment radix is ​​an odd number, the data state information of the target data is determined to be an even number, the first decomposition radix output by the first decomposition radix generation circuit is maintained as a first preset constant, and the second decomposition radix output by the second radix split generation circuit is maintained as a second preset constant;

[0020] When the data state judgment cardinality is an even number, the data state information of the target data is judged to be an odd number, and the data state judgment cardinality is used as the initial value for cyclic updating of the first decomposition cardinality generating circuit;

[0021] When the first decomposition radix generation circuit is controlled to update the first decomposition radix based on the update control signal, the first decomposition radix after each update is half of the current first decomposition radix;

[0022] At the same time, when the second decomposition radix generation circuit is controlled to update the second decomposition radix based on the update control signal, the current second decomposition radix and the second reference number are accumulated, and the second decomposition radix is ​​updated to the accumulated value of the current second decomposition radix and the second reference number.

[0023] The first decomposition radix generation circuit includes a data state judgment circuit and a first decomposition radix generation main circuit adaptively connected to the data state judgment circuit, wherein:

[0024] The data state judgment circuit at least includes a subtractor and a data state judgment base transmission circuit, wherein the subtractor receives the target data and the first reference number at the same time, and uses the difference between the target data and the first reference number calculated by the subtractor as the data state judgment base, wherein the first reference number is 1;

[0025] The data state judgment radix transfer circuit transfers the data state judgment radix to the first decomposition radix generation main circuit under the update control signal;

[0026] When the data state information of the target data is an even number, the first decomposition base generation main circuit maintains the generated first decomposition base as a first preset constant under the data state judgment base;

[0027] When the data status information of the target data is an odd number, the data status judgment radix is ​​loaded into the first decomposition radix generation circuit under the update control signal, and the data status judgment radix is ​​used as the initial value of the first decomposition radix. Thereafter, the first decomposition radix generation main circuit cyclically updates the first decomposition radix.

[0028] The first decomposition radix generation main circuit includes an initial value transfer circuit, a trigger CF1, a data splitting right shift circuit and a first decomposition radix judgment circuit, wherein:

[0029] The initial value transfer circuit receives the data state judgment base, and transfers the data state judgment base to the PRE pre-trigger terminal of the trigger CF1 in the update control signal;

[0030] The CLR clearing terminal of the flip-flop CF1 is connected to the output terminal of the data state judgment base transfer circuit;

[0031] The Q terminal of the flip-flop CF1 is connected to the data splitting right shift circuit and the first decomposition radix judgment circuit, the data splitting right shift circuit is connected to the D terminal of the flip-flop CF1, the output of the first decomposition radix judgment circuit is connected to the CE terminal of the flip-flop CF1, and the C clock terminal of the flip-flop CF1 receives the clock signal clk1;

[0032] When the data state information of the target data is an even number, the flip-flop CF1 is cleared by using the data state judgment base loaded into the CLR clear terminal of the flip-flop CF1, so that the Q terminal of the flip-flop CF1 outputs a first preset constant of 0;

[0033] When the data state of the target data is an odd number, the data state judgment base is transmitted to the PRE pre-trigger terminal of the trigger CF1 through the initial value transmission circuit to serve as the initial value of the first decomposition base;

[0034] The data splitting right shift circuit performs right shift processing on the first decomposition base outputted from the Q terminal of the flip-flop CF1, and updates the first decomposition base under the clock signal clk1;

[0035] The first decomposition radix judgment circuit is used for the lowest bit state of the current first decomposition radix, wherein the lowest bit state of the first decomposition radix is ​​0 or 1.

[0036] When the lowest bit state of the first decomposition radix is ​​1, the first decomposition radix outputted by the Q terminal of the flip-flop CF1 is maintained, and the second decomposition radix generation circuit stops updating the second decomposition radix;

[0037] When the state of the least significant bit of the first decomposition radix is ​​0, the second decomposition radix generating circuit is configured to update the second decomposition radix under the clock signal clk1.

[0038] The second decomposition radix generation circuit comprises at least an adder and a trigger CF2, wherein:

[0039] A first input terminal of the adder is connected to the Q terminal of the flip-flop CF2, and a second input terminal of the adder is connected to a second reference number;

[0040] The CLR clearing terminal of the flip-flop CF2 is connected to the update control signal, the C terminal of the flip-flop CF2 is connected to the clock signal clk1, and the CE terminal of the flip-flop CF2 is connected to the output terminal of the first decomposition cardinality judgment circuit.

[0041] The modular exponentiation hardware unit includes a fast exponentiation hardware circuit and a modulo hardware circuit connected in series with the fast exponentiation circuit, wherein:

[0042] In one round of judgment of the Miller-Rabin algorithm, the first modular exponentiation operation and the second modular exponentiation operation are sequentially performed by the modular exponentiation hardware unit;

[0043] When performing the first modular exponentiation operation, the first decomposition base is used as the target exponentiation, and the fast exponentiation hardware circuit performs the exponentiation operation on the target base and the target exponentiation to generate a first fast exponentiation operation result, and then the modulo hardware circuit performs the modulo operation on the first fast exponentiation operation result to generate a first modular exponentiation operation result value;

[0044] When performing the second modular exponentiation operation, the result value of the first modular exponentiation operation is used as the target base, and the fast exponentiation hardware circuit performs an exponentiation operation on the target base and the target power to generate a second fast modular operation result. Thereafter, the modulo hardware circuit performs a modulo operation on the second fast exponentiation operation result to generate a second modular exponentiation operation result value.

[0045] The fast exponentiation hardware circuit includes an exponentiation processing circuit and a base operation circuit adaptively connected to the exponentiation processing circuit, wherein:

[0046] The power processing circuit at least receives the target power and processes the target power, wherein the processing of the target power at least includes state determination processing and power right shift update processing;

[0047] After executing a state judgment process on the lowest bit data of the target power, a first control signal for the base operation corresponding to the lowest bit data of the target power is generated, and the power right shift update process is executed only when and only when the state judgment of the lowest bit data of the target power is 0;

[0048] When performing the power right shift update process, the target power is right shifted by one bit to update the target power, and a second control signal of the base operation corresponding to the updated target power is generated;

[0049] When the lowest bit data of the updated target power is determined to be 1 after the state judgment process, the power processing circuit stops processing the target power;

[0050] The base operation circuit receives at least a target base, and controls the base multiplication operation on the target base based on a base operation first control signal and a base operation second control signal, so as to generate a corresponding fast power operation result after performing the base multiplication operation, wherein:

[0051] A base multiplication operation performed on the target base, including at least a base square operation and a base multiplication operation;

[0052] When the power processing circuit stops processing the target power, the generated fast power operation result is output.

[0053] The power processing circuit includes a state judgment circuit, a power right shift operation circuit and a D flip-flop D5, wherein:

[0054] The target power is loaded to the first input terminal of the state judgment circuit, the state judgment circuit is connected to the D terminal of the D flip-flop D5 through the power right shift operation circuit, and the Q terminal of the D flip-flop D5 is feedback connected to the first input terminal of the state judgment circuit;

[0055] Performing state judgment processing on the lowest bit data of the target power through a state judgment circuit, and generating a first control signal for base operation through an output terminal of the state judgment circuit;

[0056] Performing power right shift update processing on the base operation first control signal through the power right shift operation circuit, and generating a base operation second control signal, and loading the updated target power to the D terminal of the D flip-flop D5;

[0057] The clock terminal of the D flip-flop D5 is connected to the clock signal clk, so as to feed back the updated target power to the first input terminal of the state judgment circuit under the clock signal clk.

[0058] A Miller-Rabin algorithm acceleration device based on software and hardware integration, the Miller-Rabin algorithm acceleration device comprising:

[0059] A data splitting hardware unit performs data splitting on the target data and generates a decomposition array matching the target data after the data splitting, wherein the decomposition array at least includes a first decomposition radix and a second decomposition radix;

[0060] A modular exponentiation hardware unit performs modular exponentiation on the exponentiation object data based on the decomposed array to generate the module, wherein when the Miller-Rabin algorithm is executed, the modular exponentiation performed by the modular exponentiation hardware unit includes at least a first modular exponentiation and a second modular exponentiation in one round of judgment, and generates a first modular exponentiation result value after executing the first modular exponentiation, and generates a second modular exponentiation result value after executing the second modular exponentiation;

[0061] The algorithm executes a control unit to perform logical judgment on the first modular exponentiation result value and the second modular exponentiation result value, and based on the corresponding logical judgment states of the first modular exponentiation result value and the second modular exponentiation result value, generates a data verification state corresponding to the target data, wherein the data verification state includes that the target data is a prime number or that the target data is a composite number.

[0062] The advantages of the present invention are as follows: when executing the Miller-Rabin algorithm, the target data is split by using the data splitting hardware unit, and a first splitting radix and a second splitting radix are generated; for the decomposed array formed by the splitting, the modular exponentiation operation unit can be used to perform the modular exponentiation operation involved in the Miller-Rabin algorithm, and a first modular exponentiation operation result value and a second modular exponentiation operation result value are sequentially generated; the first modular exponentiation operation result value and the second modular exponentiation operation result value are logically judged by using the logic judgment unit, and a data verification state corresponding to the target data can be generated; that is, the data splitting hardware unit and the modular exponentiation operation unit can be used to accelerate the operation of the Miller-Rabin algorithm, thereby effectively improving the efficiency of using the Miller-Rabin algorithm to judge a large number of prime numbers, reducing the computing power requirements for running the Miller-Rabin algorithm, and improving the judgment and generation efficiency of prime numbers. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of an embodiment of the Miller-Rabin algorithm acceleration method of the present invention.

[0064] Figure 2 The figure is a circuit diagram of an embodiment of the data splitting hardware unit of the present invention.

[0065] Figure 3 The figure is a circuit block diagram of an embodiment of the modular exponentiation hardware unit of the present invention.

[0066] Figure 4 The figure is a circuit diagram of an embodiment of the fast exponentiation hardware circuit of the present invention. DETAILED DESCRIPTION

[0067] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0068] It should be noted that when using the Miller-Rabin method to determine whether a number is prime, it is generally based on the following mathematical principles: First, a prime number p greater than 2 must be an odd number, then p-1 is an even number, which can be decomposed into the form of 2r*d. At the same time, based on Fermat's Little Theorem: If p is a prime number, a p-1 ≡1(mod p), and the quadratic detection theorem: for any positive integer x less than p, if a non-trivial root of 1(mod p) is found, then p is a composite number.

[0069] Based on the above description, a p-1 ≡1(mod p) can be transformed into A d Considered as k, we have: Therefore, we need to find x 2 ≡1(modp), and this x exists In the process of change, therefore, the core idea of ​​Miller Rabin algorithm is to 2rdAs long as it is equal to 1 or p-1, it means p is a prime number; but if it is not equal to 1 or p-1, then p has a probability of being a composite number.

[0070] It can be seen from the description of the above background technology that when executing the Miller-Rabin algorithm in the prior art, the software program is mostly relied on to execute the above judgment process, which will be time-consuming and have low execution efficiency. In order to effectively improve the efficiency of using the Miller-Rabin algorithm to judge large quantities of prime numbers and reduce the computing power requirements of running the Miller-Rabin algorithm, the present invention provides a Miller-Rabin algorithm acceleration method based on software and hardware fusion. Specifically, the Miller-Rabin algorithm acceleration method includes:

[0071] Step S1, at least configure a data splitting hardware unit for performing data splitting, a modular exponentiation hardware unit for performing modular exponentiation, and a logic judgment unit for performing logic judgment, wherein:

[0072] Step S2, when executing the Miller-Rabin algorithm, the target data to be verified is loaded into the data splitting hardware unit, so as to use the data splitting hardware unit to perform data splitting on the target data, and generate a decomposition array matching the target data after the data splitting, wherein the decomposition array includes at least a first decomposition radix and a second decomposition radix;

[0073] Step S3, generating modular exponentiation object data based on the decomposed array, and performing modular exponentiation on the modular exponentiation object data using a modular exponentiation hardware unit, wherein when executing the Miller-Rabin algorithm, the modular exponentiation performed by the modular exponentiation hardware unit includes at least a first modular exponentiation and a second modular exponentiation in one round of judgment, and generating a first modular exponentiation result value after performing the first modular exponentiation, and generating a second modular exponentiation result value after performing the second modular exponentiation;

[0074] Step S4, using a logic judgment unit to perform logic judgment on the first modular exponentiation result value and the second modular exponentiation result value, and based on the corresponding logic judgment states of the first modular exponentiation result value and the second modular exponentiation result value, generate a data verification state corresponding to the target data, wherein the data verification state includes whether the target data is a prime number or the target data is a composite number.

[0075] Figure 1An embodiment of the Miller Rabin algorithm acceleration method of the present invention is shown in FIG. It can be understood that when the present invention accelerates the Miller Rabin algorithm, the principle of the Miller Rabin algorithm is consistent with that of the existing Miller Rabin algorithm. The difference is that the present invention uses a data splitting hardware unit to perform the data splitting process in the Miller Rabin algorithm, uses a modular exponentiation hardware unit to perform the modular exponentiation operation in the Miller Rabin algorithm process, and uses a logic judgment unit to perform logic judgment; it can be seen that the corresponding operation processes of data splitting and modular exponentiation operation are all implemented by hardware circuits. Compared with the prior art that uses software programs to implement the corresponding processes, it can effectively accelerate the operation of the Miller Rabin algorithm, improve the efficiency of using the Miller Rabin algorithm to perform large-scale prime number judgment, and reduce the computing power requirements for running the Miller Rabin algorithm.

[0076] It should be noted that the logic judgment unit can still use the existing commonly used software program method. Of course, the logic judgment unit can also use hardware circuits to perform corresponding logic judgments. The present invention does not limit the implementation method of the logic judgment unit performing logic judgments.

[0077] Depend on Figure 1 It can be seen that when the data splitting hardware unit is used for data splitting, the target data is mainly split, and the corresponding decomposition array is generated after the splitting, wherein the target data is the data to be judged by the Miller Rabin algorithm, that is, it is necessary to judge whether the target data is a prime number. Generally, in order to meet the modular exponentiation and logical judgment of the Miller Rabin algorithm, the decomposition array should include a first decomposition base and a second decomposition base. The data splitting hardware unit splits the target data and generates the decomposition array. The method and process can refer to the following corresponding description.

[0078] After using the data splitting hardware unit to split and generate the decomposition array, it is necessary to use the modular exponentiation unit to perform modular exponentiation. When performing modular exponentiation, it is necessary to use the decomposition array to generate the corresponding modular exponentiation object data. The situation of generating the modular exponentiation object data shall be based on whether it can meet the requirements of modular exponentiation in the Miller Rabin algorithm. The situation of generating the modular exponentiation object data can refer to the following corresponding instructions. According to the principle of the Miller Rabin algorithm, in one round of judgment, the decomposition array generated by the data splitting hardware unit should remain unchanged, and the modular exponentiation hardware unit includes at least the first modular exponentiation and the second modular exponentiation. When executing the Miller Rabin algorithm, generally multiple rounds of judgment should be carried out until it is completed to judge whether the target data is a prime number.

[0079] In one round of judgment, the corresponding first modular exponentiation result value can be generated after the first modular exponentiation operation; and the second modular exponentiation result value can be generated after the second modular exponentiation operation. It should be noted that when the logic judgment unit performs logic judgment, it specifically refers to judging the first modular exponentiation result value and the second modular exponentiation result value. As can be seen from the above description, during the logic judgment, the correspondence between the first modular exponentiation result value, the second modular exponentiation result value and 1 and / or p-1 is mainly judged, where p is the target data. The way in which the logic judgment unit performs logic judgment can be consistent with the existing one. It can be understood that after one or more rounds of logic judgment, a data verification state corresponding to the target data can be generated. As can be seen from the above description, the data verification state includes whether the target data is a prime number or the target data is a composite number.

[0080] It should be noted that when executing a round of judgment, the logic judgment unit is generally used to perform logic judgment on the first modular exponentiation result value first, and then the logic judgment unit is used to perform logic judgment on the second modular exponentiation result value. The order and form of the logic judgment unit's logical judgment on the first modular exponentiation result value and the second modular exponentiation result value can refer to the principles of the existing Miller-Rabin algorithm, and shall be based on whether it can meet the verification of the target data.

[0081] From the above description, it can be seen that when executing the Miller-Rabin algorithm, the data splitting hardware unit can be used to perform data splitting of the target data, the modular exponentiation hardware unit can be used to perform the modular exponentiation operation involved in the Miller-Rabin algorithm, and the logic judgment unit can be used to perform logic judgment, thereby realizing software and hardware fusion. Based on the characteristics of software and hardware fusion, it can be seen that the difficulty and cost of hardware design can be balanced, while maximizing the acceleration of the operation of the Miller-Rabin algorithm.

[0082] In one embodiment of the present invention, the data splitting hardware unit includes a first decomposition radix generation circuit and a second decomposition radix generation circuit, wherein:

[0083] The first decomposition radix generation circuit is adaptively connected to the second decomposition radix generation circuit;

[0084] The first decomposition radix generation circuit receives the target data, and solves the data status information of the target data based on the first reference number, and generates the first decomposition radix based on the target data, the first reference number and the data status information of the target data, wherein the data status information of the target data includes whether the target data is an odd number or an even number;

[0085] The second decomposition radix generation circuit receives the second reference number and generates a corresponding second decomposition radix based on the data state information, wherein the first reference number and the second reference number are mutually exclusive one-bit binary numbers;

[0086] When executing the Miller-Rabin algorithm, based on the update control signal and the data status information of the target data, the first decomposition base and the second decomposition base are cyclically updated until the data splitting termination condition is reached;

[0087] When the first decomposition target cardinality and the second decomposition target cardinality are formed based on the updated first decomposition cardinality and the second decomposition cardinality, respectively, then: p = 2 r *u, p is the target data, r is the first decomposition target cardinality, and u is the second decomposition target cardinality.

[0088] It can be seen from the above description that when the target data is split using a data splitting hardware circuit, a first decomposition radix and a second decomposition radix can generally be obtained. In order to be able to split and obtain the first decomposition radix and the second decomposition radix, in one embodiment of the present invention, the data splitting hardware unit may include a first decomposition radix generation circuit and a second decomposition radix generation circuit, and the first decomposition radix generation circuit should be adaptively connected to the second decomposition radix generation circuit.

[0089] When performing data splitting on the target data, the target data should be loaded into the first decomposition radix generation circuit. In addition, the first decomposition radix generation circuit also needs to receive a first reference number so that the data status information of the target data can be solved using the first reference number. Thereafter, the first decomposition radix can be generated based on the target data, the first reference number and the data status information of the target data. The process of generating the first decomposition radix by the first decomposition radix generation circuit will be illustrated below.

[0090] In order to generate the second decomposition radix, the second decomposition radix generation circuit should receive the second reference number, wherein the first reference number and the second reference number can be the same, such as the first reference number and the second reference number can both be 1 in binary. When the second decomposition radix generation circuit generates the second decomposition radix, it should be related to the data state information of the target data. The specific method and process of generating the second decomposition radix will be described in detail below.

[0091] From the above description, it can be seen that when executing the Miller-Rabin algorithm, multiple rounds of judgment will be carried out. In the current round of judgment, the first decomposition base and the second decomposition base should remain unchanged, but in the next round of judgment, it is necessary to update the first decomposition base and the second decomposition base based on the update control signal and the data status information of the target data.

[0092] When the first decomposition radix and the second decomposition radix are cyclically updated, the termination condition of the cyclic update is at least that the data cannot be split to obtain new first decomposition radix and second decomposition radix. It can be understood that when the first decomposition radix and the second decomposition radix are subjected to the above-mentioned modular exponentiation operation to generate corresponding first modular exponentiation operation result values ​​and second modular exponentiation operation result values; when the corresponding logical judgment conditions are met through the logical judgment unit, the current first decomposition radix forms the first decomposition target radix, and the current second decomposition radix forms the second decomposition target radix.

[0093] In the specific implementation, the condition of satisfying the logical judgment specifically refers to satisfying the condition of judging that the target data is a prime number. The condition of satisfying the logical judgment is consistent with the existing Miller Rabin algorithm and will not be repeated here. In one embodiment of the present invention, for the first decomposition target base and the second decomposition target base obtained, then: p = 2 r *u, p is the target data, r is the first decomposition target cardinality, and u is the second decomposition target cardinality.

[0094] As can be seen from the above description, when executing the Miller-Rabin algorithm, before obtaining the first decomposition target cardinality and the second decomposition target cardinality, if the data splitting hardware unit can still be used to implement data splitting, the data splitting should continue until the data splitting hardware unit cannot perform data splitting. At this time, the data splitting termination condition is reached, and the Miller-Rabin algorithm for the target data should be terminated. When the Miller-Rabin algorithm runs to the point where the data splitting hardware unit cannot perform data splitting and terminates, the target data can be obtained as a non-prime number or a prime number according to the situation of the logical judgment condition.

[0095] In one embodiment of the present invention, when executing the Miller Rabin algorithm, the data splitting hardware unit has:

[0096] Subtract the target data from the first reference number to generate a data state judgment base number, where:

[0097] When the data state judgment radix is ​​an odd number, the data state information of the target data is determined to be an even number, the first decomposition radix output by the first decomposition radix generation circuit is maintained as a first preset constant, and the second decomposition radix output by the second radix split generation circuit is maintained as a second preset constant;

[0098] When the data state judgment cardinality is an even number, the data state information of the target data is judged to be an odd number, and the data state judgment cardinality is used as the initial value for cyclic updating of the first decomposition cardinality generating circuit;

[0099] When the first decomposition radix generation circuit is controlled to update the first decomposition radix based on the update control signal, the first decomposition radix after each update is half of the current first decomposition radix;

[0100] At the same time, when the second decomposition radix generation circuit is controlled to update the second decomposition radix based on the update control signal, the current second decomposition radix and the second reference number are accumulated, and the second decomposition radix is ​​updated to the accumulated value of the current second decomposition radix and the second reference number.

[0101] As can be seen from the above description, the data state information of the target data can be obtained according to the target data and the first reference number. In order to obtain the data state information of the target data, the target data and the first reference number are subtracted, and a data state judgment base can be generated based on the difference. Thereafter, the data state information of the target data can be generated according to the data state judgment base. For example, when the data state judgment base is an odd number, the data state information of the target data is determined to be an even number, or, when the data state judgment base is an even number, the data state information of the target data is determined to be an odd number.

[0102] In specific implementation, when it is determined that the data state information of the target data is an even number, the first decomposition base output by the first decomposition base generation circuit is maintained as the first preset constant, and the second decomposition base output by the second base splitting generation circuit is maintained as the second preset constant. The first preset constant and the second preset constant can be selected and determined according to actual needs. For example, both the first preset constant and the second preset constant can be constants such as 0. The first preset constant and the second preset constant will be illustrated below. It can be understood that if the data state information of the target data is an even number, it can be determined that the target data is not a prime number. Therefore, when splitting the target data, the first decomposition base is maintained as the first preset constant, and the second decomposition base is maintained as the second preset constant. Then, the operation of the Miller-Rabin algorithm can be terminated by maintaining the first decomposition base and the second decomposition base as constants.

[0103] When the data state information of the target data is determined to be an odd number, it is still impossible to determine whether the target data is a prime number. Therefore, it is necessary to judge through the process of data splitting, modular exponentiation operation and logical judgment. Specifically, when the data state information of the target data is an odd number, the data state judgment base should be used as the initial value of the first decomposition base generation circuit for cyclic update; when the first decomposition base is cyclically updated, in one embodiment of the present invention, the first decomposition base after each update is configured as half of the current first decomposition base; at the same time, when the second decomposition base is updated, the current second decomposition base is accumulated with the second reference number to update the second decomposition base based on the accumulated sum of the second decomposition base and the second reference number, that is, the accumulated value of the second decomposition base and the second reference number is used as the new second decomposition base.

[0104] It should be noted that, during an update, the first decomposition base and the second decomposition base should be updated simultaneously, that is, after the update, a new decomposition array will be generated. During the subsequent modular exponentiation calculation, modular exponentiation operation object data is generated based on the new decomposition array.

[0105] In one embodiment of the present invention, the first decomposition radix generation circuit includes a data state judgment circuit and a first decomposition radix generation main circuit adaptively connected to the data state judgment circuit, wherein:

[0106] The data state judgment circuit at least includes a subtractor and a data state judgment base transmission circuit, wherein the subtractor receives the target data and the first reference number at the same time, and uses the difference between the target data and the first reference number calculated by the subtractor as the data state judgment base, wherein the first reference number is 1;

[0107] The data state judgment radix transfer circuit transfers the data state judgment radix to the first decomposition radix generation main circuit under the update control signal;

[0108] When the data state information of the target data is an even number, the first decomposition base generation main circuit maintains the generated first decomposition base as a first preset constant under the data state judgment base;

[0109] When the data status information of the target data is an odd number, the data status judgment radix is ​​loaded into the first decomposition radix generation circuit under the update control signal, and the data status judgment radix is ​​used as the initial value of the first decomposition radix. Thereafter, the first decomposition radix generation main circuit cyclically updates the first decomposition radix.

[0110] In a specific implementation, the first decomposition radix generation circuit at least includes a data state judgment circuit and a first decomposition radix generation main circuit, wherein the data state judgment circuit may include a subtractor and a data state judgment radix transmission circuit. Figure 2 A circuit schematic diagram of an embodiment of the first decomposition radix generation circuit is shown in the figure, where sub is a subtractor. The subtractor can be used to calculate the difference between the target data and the first reference number, that is, the data state judgment radix can be obtained through the output end of the subtractor. Thereafter, the data state judgment radix can be loaded into the first decomposition radix generation main circuit through the data state judgment radix transfer circuit.

[0111] Figure 2An embodiment of the first reference number is also shown in the figure. In the figure, the first reference number is selected as 1. At this time, the data state judgment cardinality is the difference between the target data and 1. It can be understood that the data state of the target data can be judged according to the data state judgment cardinality, and the corresponding data state information can be obtained. For example, when the lowest bit of the data state judgment cardinality is 1, according to the calculation and generation method of the data judgment state cardinality, it can be known that the target cardinality should be an even number; if the lowest bit of the data state judgment cardinality is 0, according to the calculation and generation method of the data judgment state cardinality, it can be known that the target cardinality should be an odd number.

[0112] After the data state judgment radix is ​​calculated, the data state judgment radix should be transmitted to the first decomposition radix generation main circuit through the data state judgment radix transmission circuit. Figure 2 An embodiment of a data state judgment radix transfer circuit is shown in FIG. In the figure, the data state judgment radix transfer circuit can use a multiplexer. Figure 2 In the embodiment, MUX1 is the data state judgment base transfer circuit, and the reset signal is the update control signal. Figure 2 In the embodiment, the first input terminal of the multiplexer MUX1 is connected to the input terminal of the subtractor, the second input terminal of the multiplexer MUX1 receives the constant 1, the reset signal is loaded to the control terminal of the multiplexer MUX1, and the output terminal of the multiplexer MUX1 is connected to the first decomposition radix generation main circuit.

[0113] When the reset signal is in a valid state, the first input terminal of the multiplexer MUX1 is selected to output, and at this time, the data state judgment radix can be transmitted to the first decomposition radix generation main circuit, and the data splitting state of the first decomposition radix generation main circuit is controlled based on the data state judgment radix transmitted by the multiplexer MUX1. Generally, the reset signal is high level effective, and during the data splitting process, the reset signal remains in a valid state, that is, the update control signal remains in a valid state during the data splitting process.

[0114] It can be seen from the above description that when the data status information of the target data is an even number, the first decomposition radix generation main circuit will maintain the generated first decomposition radix as a first preset constant under the data status judgment radix. As described above, the first preset constant is generally 0; when the data status information of the target data is an odd number, the first decomposition radix generation main circuit will use the data status judgment radix as the initial value of the first decomposition radix under the update control signal. Thereafter, the first decomposition radix generation main circuit cyclically updates the first decomposition radix.

[0115] In one embodiment of the present invention, the first decomposition radix generation main circuit includes an initial value transfer circuit, a trigger CF1, a data splitting right shift circuit and a first decomposition radix judgment circuit, wherein:

[0116] The initial value transfer circuit receives the data state judgment base, and transfers the data state judgment base to the PRE pre-trigger terminal of the trigger CF1 in the update control signal;

[0117] The CLR clearing terminal of the flip-flop CF1 is connected to the output terminal of the data state judgment base transfer circuit;

[0118] The Q terminal of the flip-flop CF1 is connected to the data splitting right shift circuit and the first decomposition radix judgment circuit, the data splitting right shift circuit is connected to the D terminal of the flip-flop CF1, the output of the first decomposition radix judgment circuit is connected to the CE terminal of the flip-flop CF1, and the C clock terminal of the flip-flop CF1 receives the clock signal clk1;

[0119] When the data state information of the target data is an even number, the flip-flop CF1 is cleared by using the data state judgment base loaded into the CLR clear terminal of the flip-flop CF1, so that the Q terminal of the flip-flop CF1 outputs a first preset constant of 0;

[0120] When the data state of the target data is an odd number, the data state judgment base is transmitted to the PRE pre-trigger terminal of the trigger CF1 through the initial value transmission circuit to serve as the initial value of the first decomposition base;

[0121] The data splitting right shift circuit performs right shift processing on the first decomposition base outputted from the Q terminal of the flip-flop CF1, and updates the first decomposition base under the clock signal clk1;

[0122] The first decomposition radix judgment circuit is used for the lowest bit state of the current first decomposition radix, wherein the lowest bit state of the first decomposition radix is ​​0 or 1.

[0123] When the lowest bit state of the first decomposition radix is ​​1, the first decomposition radix outputted by the Q terminal of the flip-flop CF1 is maintained, and the second decomposition radix generation circuit stops updating the second decomposition radix;

[0124] When the state of the least significant bit of the first decomposition radix is ​​0, the second decomposition radix generating circuit is configured to update the second decomposition radix under the clock signal clk1.

[0125] Specifically, the initial value transfer circuit is used to transfer the data state judgment base to the PRE pre-trigger terminal of the trigger CF1. Figure 2An embodiment of the first decomposition radix generation main circuit is shown in FIG. In the figure, the initial value transfer circuit includes an inverter INV1 and a multiplexer MUX2, wherein the input end of the inverter INV1 is connected to the output end of the subtractor, the output end of the inverter INV1 is connected to the first input end of the multiplexer MUX2, the second input end of the multiplexer MUX2 is connected to the constant 1, the update control signal is loaded to the control end of the multiplexer MUX2, and the output end of the multiplexer MUX2 is connected to the PRE pre-trigger end of the trigger CF1. When the update control signal is in a valid state, the first input end of the multiplexer MUX2 is selected to output, thereby transferring the data state judgment radix to the PRE pre-trigger end of the trigger CF1.

[0126] It should be noted that the trigger CF1 can adopt an existing commonly used form. Figure 2 An embodiment of the trigger CF1 is shown in the figure. As can be seen from the figure, the trigger CF1 includes a PRE pre-trigger terminal, a CLR clear terminal, a C clock terminal, a CE terminal and a Q terminal. As can be seen from the figure, the PRE pre-trigger terminal can invert the loaded data. Therefore, according to the description of the above-mentioned initial value transfer circuit, it can be seen that the data state judgment base can be effectively loaded into the trigger CF1 through the above-mentioned initial value transfer circuit, and used as the initial value of the first decomposition base.

[0127] The CLR clear terminal is in a high-level valid state. Therefore, when the lowest bit of the data status judgment base loaded by the multiplexer MUX1 is 1, the CLR clear terminal will be triggered to be valid, and the output of the Q terminal of the trigger CF1 will be cleared; and when the lowest bit of the data status judgment base loaded by the multiplexer MUX1 is 0, the CLR clear terminal will not be triggered to be valid, and it will not affect the first decomposition base generation main circuit to cyclically update the first decomposition base.

[0128] The Q terminal of the trigger CF1 is connected to the input terminal of the data split right shift circuit. Figure 2 In the figure, SF1 is a data splitting right shift circuit. The data splitting right shift circuit can adopt an existing commonly used shift circuit. Generally, the data splitting right shift circuit can right shift the input data to implement the operation of input data / 2 and rounding. Figure 2 In the embodiment, the data splitting right shift circuit has three input terminals, the other two input terminals of the data splitting right shift circuit are connected to the constant 1, and the output terminal of the data splitting right shift circuit is connected to the D terminal of the trigger CF1, thereby the first decomposition base after each update can be configured to be half of the current first decomposition base.

[0129] Figure 2An embodiment of the first decomposition radix judgment circuit is shown in the figure. As can be seen from the figure, the first decomposition radix judgment circuit may include an AND gate circuit AND1 and a data buffer RAM1, wherein one input terminal of the AND gate circuit AND1 is connected to the Q terminal of the trigger CF1, the other input terminal of the AND gate circuit AND1 is connected to the constant 1, and the output terminal of the AND gate circuit AND1 is connected to the data memory RAM1, and is connected to the CE terminal of the trigger CF1 through the data memory RAM1.

[0130] In specific implementation, the first decomposition radix judgment circuit mainly judges the first decomposition radix output from the Q terminal of the trigger CF1, that is, judges the lowest bit of the first decomposition radix output from the trigger CF1. For example, when the lowest bit state of the first decomposition radix is ​​0, the output terminal of the AND gate circuit AND1 is 0, and then the data cached in the data buffer RAM1 is 0. At this time, the data loaded to the CE terminal of the trigger CF1 is invalid, that is, it will not affect the operation of the trigger CF1. When the lowest bit state of the first decomposition radix is ​​1, the output terminal of the AND gate circuit AND1 is 1, and then the data cached in the data buffer RAM1 is 1. At this time, the data loaded to the CE terminal of the trigger CF1 is valid, and the Q terminal output of the trigger CF1 will be maintained. Thereafter, the Q terminal of the trigger CF1 remains unchanged.

[0131] From the above description, it can be seen that when the lowest bit state of the first decomposition cardinality is 0, it means that the first decomposition cardinality is not 1; when the lowest bit state of the first decomposition cardinality is 1, it means that the first decomposition cardinality is 1. At this time, the first decomposition cardinality cannot be further updated, that is, the data splitting termination condition is reached.

[0132] It can be seen from the above description that when the PRE pre-trigger end of the trigger CF1 is triggered effectively, the working state of the trigger CF1 is independent of the PRE pre-trigger end, that is, the trigger CF1 is related to the clock signal clk1 at the C end, the first decomposition base updated at the D end, and the input at the CE end in subsequent work. The corresponding working process of the first decomposition base generation circuit is specifically described below.

[0133] In one embodiment of the present invention, a subtractor subtracts the target data from the first reference number to generate a data state judgment base. When the update control signal is valid, the data state judgment base is loaded to the CLR clearing terminal of the trigger CF1 through the multiplexer MUX1. At the same time, the data state judgment base is loaded to the PRE pre-trigger terminal of the trigger CF1 through the multiplexer MUX2 to trigger the PRE trigger terminal of the trigger CF1.

[0134] It can be understood that the rhythm of updating the first decomposition base can be controlled by the clock signal clk1. For example, when the lowest bit of the data state judgment base is 0, the data state judgment base of the PRE pre-trigger end can be transmitted to the Q end of the trigger CF1 through the trigger CF1. After that, the first decomposition base outputted from the Q end of the trigger CF1 is right-shifted by the data splitting right shift circuit; at the same time, the lowest bit of the current first decomposition base is determined by the first decomposition base judgment circuit. When the lowest bit of the first decomposition base is not 1, wait for the next clock signal clk1.

[0135] When the second clock signal clk1 is valid, the data of the D terminal of the trigger CF1 will be transferred to the Q terminal of the trigger CF1. After that, the data splitting right shift circuit needs to be used to right shift the first decomposition base outputted from the Q terminal of the trigger CF1. At the same time, the first decomposition base judgment circuit is used to judge the lowest bit of the current first decomposition base. When the lowest bit of the first decomposition base is not 1, wait for the next clock signal clk1.

[0136] It can be seen from the above description that when splitting the data, the above process is repeated through the clock signal clk1 until the lowest first decomposition base is 1, so as to achieve the splitting of the target data. Figure 2 In the figure, r is the first decomposition base output from the Q terminal of the flip-flop CF1.

[0137] In one embodiment of the present invention, the second decomposition radix generation circuit comprises at least an adder and a flip-flop CF2, wherein:

[0138] A first input terminal of the adder is connected to the Q terminal of the flip-flop CF2, and a second input terminal of the adder is connected to a second reference number;

[0139] The CLR clearing terminal of the flip-flop CF2 is connected to the update control signal, the C terminal of the flip-flop CF2 is connected to the clock signal clk1, and the CE terminal of the flip-flop CF2 is connected to the output terminal of the first decomposition cardinality judgment circuit.

[0140] Figure 2 An embodiment of the second decomposition radix generation circuit is shown in FIG. In the figure, ADD1 is an adder, CF2 is a trigger CF2, and the trigger CF2 can be of the same type as the above-mentioned trigger CF1. The difference is that compared with the trigger CF1, the trigger CF2 can omit the PRE pre-trigger terminal of the trigger CF1. At this time, the clearing method of the CLR clearing terminal of the trigger CF2 is different from that of the trigger CF1. When the level of the CLR clearing terminal of the trigger CF2 is low, the trigger CF2 performs a clearing operation. The rest is similar to the working principle of the trigger CF2. The working principle of the trigger CF2 can be specifically referred to the description of the above-mentioned trigger CF1. Figure 2In the example, u is the second decomposition base outputted from the Q terminal of the flip-flop CF2. Figure 2 , which shows the case where the second reference number is 1, that is, when the second decomposition base is updated, an accumulation operation of 1 is performed each time.

[0141] The CE terminal of the trigger CF2 is connected to the output terminal of the first decomposition radix judgment circuit, that is, the second decomposition radix generation circuit is adapted to the first decomposition radix generation circuit. In order to achieve the connection with the trigger CF2, Figure 2 In the first decomposition cardinality judgment circuit, the data buffer RAM2 is further included, the output end of the data buffer RAM2 is connected to the output end of the AND gate circuit AND1, and the output end of the data buffer RAM2 is connected to the CE end of the trigger CF2. It can be understood that, in a specific implementation, the CE end of the trigger CF2 can also be directly connected to the output end of the data buffer RAM1.

[0142] As can be seen from the above description, when the update control signal is valid at a high level, the flip-flop CF2 will not be cleared. When the second decomposition base number generation circuit is working, the adder will add the Q-end output of the flip-flop CF2 and the second reference number, and load the generated addition result data to the D-end of the flip-flop CF2.

[0143] When the first clock signal clk1 is valid, the output of the adder is 1, and the flip-flop CF2 will output the data of D. At this time, the second decomposition base obtained at the Q end of the flip-flop CF2 is 1. Thereafter, the adder will accumulate the second decomposition base and the second reference number, and the output of the adder is 2. When the second clock signal clk1 is valid, the adder is loaded to the D end data output of the flip-flop CF2. It can be seen that the second decomposition base of the number at the Q end of the flip-flop CF2 should be 2 at this time.

[0144] When the update control signal is valid, and the first decomposition radix determination circuit determines that the lowest bit of the first decomposition radix is ​​not 1, the above-mentioned cumulative update operation is continued until the first decomposition radix determination circuit determines that the lowest bit of the first decomposition radix is ​​1, so that the second decomposition radix output from the Q end of the flip-flop CF2 is maintained. It can be understood that the corresponding cyclic updates of the first decomposition radix generation circuit and the second decomposition radix generation circuit are controlled by the clock signal clk1, so when the generated first decomposition radix is ​​updated, the second decomposition radix is ​​also updated at the same time.

[0145] Figure 2 As well as an embodiment of the data splitting hardware unit shown above, it can be understood that the data splitting hardware unit can also adopt other hardware circuit forms, specifically based on whether it can meet the needs of splitting the target data and generating the corresponding first decomposition base and second decomposition base at the same time, and no further examples will be given here.

[0146] In one embodiment of the present invention, the modular exponentiation hardware unit includes a fast exponentiation hardware circuit and a modulo hardware circuit connected in series with the fast exponentiation circuit, wherein:

[0147] In one round of judgment of the Miller-Rabin algorithm, the first modular exponentiation operation and the second modular exponentiation operation are sequentially performed by the modular exponentiation hardware unit;

[0148] When performing the first modular exponentiation operation, the first decomposition base is used as the target exponentiation, and the fast exponentiation hardware circuit performs the exponentiation operation on the target base and the target exponentiation to generate a first fast exponentiation operation result, and then the modulo hardware circuit performs the modulo operation on the first fast exponentiation operation result to generate a first modular exponentiation operation result value;

[0149] When performing the second modular exponentiation operation, the result value of the first modular exponentiation operation is used as the target base, and the fast exponentiation hardware circuit performs an exponentiation operation on the target base and the target power to generate a second fast modular operation result. Thereafter, the modulo hardware circuit performs a modulo operation on the second fast exponentiation operation result to generate a second modular exponentiation operation result value.

[0150] Figure 3 An embodiment of the modular exponentiation hardware unit of the present invention is shown in the figure. In the figure, the modular exponentiation hardware unit includes a fast exponentiation hardware circuit and a modulo hardware circuit. The fast exponentiation hardware circuit and the modulo hardware circuit are connected in series. The fast exponentiation hardware circuit can be used to implement exponentiation, and the modulo hardware circuit can be used to implement modulo operation. That is, in the modular exponentiation process, the exponentiation operation must be performed first, and the modulo operation must be performed after the exponentiation operation.

[0151] It can be seen from the above description that in one round of judgment of the Miller-Rabin algorithm, there will be a first modular exponentiation operation and a second modular exponentiation operation, wherein the first modular exponentiation operation should be performed first, and after the first modular exponentiation operation, the second modular exponentiation operation should be performed. It can be seen from the above description that before performing the second modular exponentiation operation, the logic judgment unit should perform a logic judgment on the first modular exponentiation operation result value generated after the first modular exponentiation operation.

[0152] The first decomposition base generated by the data splitting circuit should be loaded into the fast exponentiation hardware circuit and used as the target exponentiation of the fast exponentiation hardware circuit. After that, the fast exponentiation hardware circuit can perform exponentiation operation on the target base and the target exponentiation to generate a first fast exponentiation result. After the first fast exponentiation result is generated, the modulo hardware circuit should be used to perform modulo operation on the first fast exponentiation result to generate a first modulo exponentiation result value. It can be seen from the above description that when the modulo hardware circuit performs modulo operation on the first fast exponentiation result, it mainly performs 1 (mod p) operation. The modulo hardware circuit can adopt the existing commonly used hardware circuit, and the specific implementation of the modulo operation shall prevail.

[0153] In addition, when performing the second modular exponentiation operation, the first modular exponentiation operation result value is used as the target base, and the fast exponentiation hardware circuit performs an exponentiation operation on the target base and the target power to generate a second fast modular operation result. Thereafter, the modulo operation is performed on the second fast exponentiation operation result using the modulo hardware circuit to generate a second modular exponentiation operation result value.

[0154] It can be seen from the above description that when generating modular exponentiation object data based on the decomposed array, it includes generating the target power of the first modular exponentiation operation from the first decomposition base, and using the result value of the first modular exponentiation operation as the target base used for the second modular exponentiation operation.

[0155] In one embodiment of the present invention, the fast exponentiation hardware circuit includes an exponentiation processing circuit and a base operation circuit adaptively connected to the exponentiation processing circuit, wherein:

[0156] The power processing circuit at least receives the target power and processes the target power, wherein the processing of the target power at least includes state determination processing and power right shift update processing;

[0157] After executing a state judgment process on the lowest bit data of the target power, a first control signal for the base operation corresponding to the lowest bit data of the target power is generated, and the power right shift update process is executed only when and only when the state judgment of the lowest bit data of the target power is 0;

[0158] When performing the power right shift update process, the target power is right shifted by one bit to update the target power, and a second control signal of the base operation corresponding to the updated target power is generated;

[0159] When the lowest bit data of the updated target power is determined to be 1 after the state judgment process, the power processing circuit stops processing the target power;

[0160] The base operation circuit receives at least a target base, and controls the base multiplication operation on the target base based on a base operation first control signal and a base operation second control signal, so as to generate a corresponding fast power operation result after performing the base multiplication operation, wherein:

[0161] A base multiplication operation performed on the target base, including at least a base square operation and a base multiplication operation;

[0162] When the power processing circuit stops processing the target power, the generated fast power operation result is output.

[0163] From the above description, it can be seen that the fast exponent hardware circuit mainly calculates the value of the target base under the target power. For example, when the target base is base and the target power is exponent, the fast exponent hardware circuit calculates base exponentCorresponding values, therefore, for a fast exponentiation hardware circuit, when performing an exponentiation operation, at least a target exponent and a target base need to be obtained.

[0164] In specific implementation, the fast exponentiation hardware circuit may include an exponentiation processing circuit and a base operation circuit, wherein the exponentiation processing circuit at least receives a target exponent, and the base operation circuit at least receives a target base. The exponentiation processing circuit at least performs a state judgment process and a power right shift update process on the received target exponent. As described above, in the first modular exponentiation operation, the first decomposition base is used as the target exponent. At this time, the first decomposition base as the target exponent is respectively subjected to a state judgment process and a power right shift update process. In the second modular exponentiation operation, 2 can be used as the target exponent. At this time, the target exponent can be subjected to a state judgment process and a power right shift update process. The base operation circuit is mainly used to operate on the base. It should be noted that in the first modular exponentiation operation, the target base can be selected as needed; in the second modular exponentiation operation, the result of the first modular exponentiation operation is used as the target base.

[0165] It should be noted that, when performing fast exponentiation, based on the above description, it can be known that the target exponents are all greater than 0. Therefore, when performing state judgment processing on the target exponent, it mainly refers to performing state judgment processing on the lowest bit data of the target exponent. For example, when the target exponent is 2, the corresponding binary is 10, and the lowest bit of the target exponent is "0". When performing state judgment processing, it is to determine whether the lowest bit of the target data is "0" or "1". Only when the state of the lowest bit data of the target exponent is judged to be 0, the exponent right shift update processing is performed, wherein the state of the lowest bit data of the target exponent is judged to be 0, which specifically means that after the state judgment processing, the lowest bit data is determined to be 0.

[0166] Specifically, when performing the power right shift update process, the target power should be right shifted by one bit to update the target power, and a second control signal for the base operation corresponding to the updated target power is generated. For example, when the target power is 2, after the right shift by one dimension, the target power is updated to 01, and the second control signal for the base operation is generated based on the target power of 01. In addition, when the lowest bit data of the updated target power is determined to be 1 after the state judgment process, the power processing circuit stops processing the target power. Stopping the processing of the target power specifically means that the power processing circuit completes the processing of the target power.

[0167] The base operation circuit at least receives the target base, and controls the base multiplication operation to be performed on the target base based on the base operation first control signal and the base operation second control signal, so as to generate a corresponding fast power operation result after performing the base multiplication operation. Specifically, the base multiplication operation performed on the target base includes at least a base square operation and a base multiplication operation. When the power processing circuit stops processing the target power, the generated fast power operation result is output, and the fast power operation result is output, that is, a fast power operation is completed. It can be understood that during the power processing circuit processing the power, the base operation circuit will cyclically perform the base multiplication operation on the target base, thereby meeting the above-mentioned fast power operation requirements.

[0168] In one embodiment of the present invention, the power processing circuit includes a state judgment circuit, a power right shift operation circuit and a D flip-flop D5, wherein:

[0169] The target power is loaded to the first input terminal of the state judgment circuit, the state judgment circuit is connected to the D terminal of the D flip-flop D5 through the power right shift operation circuit, and the Q terminal of the D flip-flop D5 is feedback connected to the first input terminal of the state judgment circuit;

[0170] Performing state judgment processing on the lowest bit data of the target power through a state judgment circuit, and generating a first control signal for base operation through an output terminal of the state judgment circuit;

[0171] Performing power right shift update processing on the base operation first control signal through the power right shift operation circuit, and generating a base operation second control signal, and loading the updated target power to the D terminal of the D flip-flop D5;

[0172] The clock terminal of the D flip-flop D5 is connected to the clock signal clk2 so as to feed back the updated target power to the first input terminal of the state judgment circuit under the clock signal clk2.

[0173] Specifically, the power processing circuit may include a state judgment circuit, a power right shift operation circuit and a D flip-flop D5. Figure 4 An embodiment of a power processing circuit is shown in FIG. 1 , and an embodiment of an AND gate circuit AND2 is shown in the figure. SF2 is a power right shift operation circuit. The power right shift operation circuit can perform a one-bit right shift operation. When the state judgment circuit adopts the AND gate circuit AND2, the power processing circuit should also receive a third reference number. At this time, the two input terminals of the AND gate circuit AND2 respectively form the first input terminal and the second input terminal of the state judgment circuit. Figure 4 In the example, the third reference number may be 1, the third reference number and the target exponent are both loaded to the input end of the AND gate circuit AND2, and exponent is the target exponent.

[0174] The AND gate circuit AND2 is used to perform bitwise AND processing on the third reference number and the lowest bit data of the target power number to realize the state judgment of the lowest bit data of the target power number. When the state judgment circuit adopts the AND gate circuit AND2, the output end of the AND gate circuit AND2 generates the first control signal of the base operation. For example, when the target power number is 10, the lowest bit data of the target power number and the third reference number are bitwise AND processed, and the result generated after the bitwise AND processing is 10, then the first control signal of the base operation can be 10; if the target power number is 01, the result generated after the bitwise AND processing is 01, then the first control signal of the base operation can be 01. When the target power number is other cases, the state of the base operation control signal generated by the state judgment circuit can refer to the description here, and no examples are given one by one.

[0175] As can be seen from the above description, after the first control signal of the base operation is generated, the power right shift operation circuit can be used to perform power right shift update processing on the first control signal of the base operation, and generate the corresponding second control signal of the base operation. For example, when the above-mentioned first control signal of the base operation is 10, then after passing through the power right shift operation circuit, the second control signal of the base operation of 01 can be obtained; if the above-mentioned first control signal of the base operation is 01, then after passing through the power right shift operation circuit, the second control signal of the base operation of 00 can be obtained. The way in which the power right shift operation circuit performs the right shift operation on the first control signal of the base operation can be referred to the description here, and examples will not be given one by one here.

[0176] During specific implementation, the second control signal of the base operation will be loaded into the D terminal of the D flip-flop D5. The clock terminal of the D flip-flop D5 receives the clock signal clk2. When the clock signal clk2 is valid, the current second control signal of the base operation can be fed back to the first input terminal of the state judgment circuit via the Q terminal of the D flip-flop D5. At this time, the second control signal of the base operation is fed back to the first input terminal of the state judgment circuit as the updated target power.

[0177] After the updated target power is fed back to the first input terminal of the state judgment circuit, the above-mentioned state judgment processing and power right shift operation update processing are repeated until the state of the least significant bit data of the updated target power is judged to be 1.

[0178] In one embodiment of the present invention, the base operation circuit includes a first multiplier, a second multiplier, a fourth multiplexer, a fifth multiplexer, a D flip-flop D6 and a D flip-flop D7, wherein:

[0179] The output terminal of the first multiplier is connected to the first input terminal of the fourth multiplexer, the first input terminal of the first multiplier receives the first intermediate number, and the second input terminal of the first multiplier is connected to the output terminal of the D flip-flop D7;

[0180] The second input terminal of the fourth multiplexer receives the first intermediate number, the selection control terminal of the fourth multiplexer receives the first control signal of the base operation, the output terminal of the fourth multiplexer is connected to the second input terminal of the fifth multiplexer and the D terminal of the D flip-flop D6, and the output terminal of the D flip-flop D6 is connected to the first input terminal of the first multiplier;

[0181] The first input terminal of the fifth multiplexer receives the third preset constant, the selection control terminal of the fifth multiplexer receives the second control signal of the base operation, and the clock terminal of the D flip-flop D6 and the clock terminal of the D flip-flop D7 both receive the clock signal clk2;

[0182] The D terminal of the D flip-flop D7 is connected to the output terminal of the second multiplier, the first input terminal and the second input terminal of the second multiplier both receive the target base, and the output terminal of the D flip-flop D7 is also simultaneously feedback-connected to the first input terminal of the second multiplier and the second input terminal of the second multiplier;

[0183] The output terminal of the fifth multiplexer serves as the output terminal of the fast exponentiation hardware circuit.

[0184] Figure 4 An embodiment of the base operation circuit is shown in FIG. 1 , in which MU1 is the first multiplier, MU2 is the second multiplier, MX4 is the fourth multiplexer, MX5 is the fifth multiplexer, D6 is the D flip-flop D6, and D7 is the D flip-flop D7. In the figure, res is the first intermediate number. Initially, the first intermediate constant res can take a value of 1, and the 0 loaded to the first input terminal of the fifth multiplexer is the third preset constant, and base is the target base.

[0185] right Figure 4 The base operation circuit described above, when initially working, uses the first multiplier to calculate the product of the first intermediate number res and the target base to form a first product value, and loads the first product value to the first input terminal of the fourth multiplexer, wherein the expression of the first product value can be res*base; at the same time, uses the second multiplier to calculate the square of the target base, and loads the square value of the target base to the D terminal of the D flip-flop D7, wherein the expression of the square value of the target base is base 2 .

[0186] When the state judgment circuit determines that the state of the lowest bit data of the target power is 1, the first input end of the fourth multiplexer is selected for output, that is, the first product value is selected for output, that is, when the lowest bit data of the first control signal of the base is 1, the corresponding data of the first input end of the fourth multiplexer is selected for output; when the lowest bit data of the first control signal of the base is 0, the corresponding data of the second input end of the fourth multiplexer is selected for output.

[0187] For the second control signal of the base operation, when the value corresponding to the second control signal of the base operation is less than or equal to 0, the data at the second input end of the fifth multiplexer is selected and output; otherwise, the data at the first input end of the fifth multiplexer is selected and output.

[0188] If the target power is 2, the generated first control signal of the base operation is 10, and the first intermediate number res loaded to the second input terminal of the fourth multiplexer is selected and output, and the first intermediate number res is loaded to the second input terminal of the fifth multiplexer and the D terminal of the D flip-flop D6. At the same time, the second control signal of the base operation generated by the first control signal of the base operation through the power right shift operation circuit should be 01. At this time, the second control signal of the base operation is not less than 0, and the value output by the fifth multiplexer is the third preset constant, that is, 0.

[0189] When the first clock signal clk2 is valid, the second control signal of the base operation is fed back to the first input terminal of the state judgment circuit as the updated target power through the D flip-flop D5; at the same time, the target base square value is transmitted to the Q terminal of the D flip-flop D7 and loaded to the second input terminal of the first multiplier, the first input terminal of the first multiplier and the second input terminal of the first multiplier. At this time, the first product value that can be obtained through the first multiplier is res*base 2 , the second product value obtained by the second multiplier can be base 4 , then the data loaded into the first input terminal of the fourth multiplexer is the first product value of res*base 2 The data loaded into the second input terminal of the fourth multiplexer is the first intermediate number res, and the data loaded into the D terminal of the D flip-flop D7 is base 4 .

[0190] From the above description, it can be seen that the updated target power should be 01. Then, after the state judgment circuit performs state judgment processing on the lowest bit data of the current target power, the lowest bit of the generated base first control signal should be 1. Then, the first product value loaded to the second input terminal of the fourth multiplexer is res*base. 2 Select output, thus we can know that the data loaded into the second input terminal of the fifth multiplexer is res*base 2 , the data loaded into the D-side of D flip-flop D6 is also res*base 2 .

[0191] When the base operation first control signal is 01, the base operation second control signal generated by the power right shift operation circuit should be 00. At this time, the base operation second control signal is 0. At this time, the second input terminal of the fifth multiplexer selects the output, that is, res*base 2, since res is 1, the data output by the fifth multiplexer is base 2 From the above description, it can be seen that when the lowest bit data of the updated target power is determined to be 1 after the state judgment process, the power processing circuit stops processing the target power, that is, the fifth multiplexer outputs base 2 , which is the fast exponentiation result output by the fast exponentiation hardware circuit.

[0192] When the target power is other values, the method and process of using the fast power hardware circuit to perform fast power operation on the target base can refer to the above corresponding description, which will not be repeated here. It should be noted that the above clock signal clk2 and clock signal clk1 can be generated by the same clock source, and the timing between the clock signal clk1 and the clock signal clk2 should be based on meeting the specific working requirements of the data splitting hardware unit and the fast power hardware circuit, and can accelerate the operation of the Miller Rabin algorithm.

[0193] From the above description, a Miller-Rabin algorithm acceleration device based on software and hardware fusion can be obtained. In one embodiment of the present invention, the Miller-Rabin algorithm acceleration device includes:

[0194] A data splitting hardware unit performs data splitting on the target data and generates a decomposition array matching the target data after the data splitting, wherein the decomposition array at least includes a first decomposition radix and a second decomposition radix;

[0195] A modular exponentiation hardware unit performs modular exponentiation on the exponentiation object data based on the decomposed array to generate the module, wherein when the Miller-Rabin algorithm is executed, the modular exponentiation performed by the modular exponentiation hardware unit includes at least a first modular exponentiation and a second modular exponentiation in one round of judgment, and generates a first modular exponentiation result value after executing the first modular exponentiation, and generates a second modular exponentiation result value after executing the second modular exponentiation;

[0196] The algorithm executes a control unit to perform logical judgment on the first modular exponentiation result value and the second modular exponentiation result value, and based on the corresponding logical judgment states of the first modular exponentiation result value and the second modular exponentiation result value, generates a data verification state corresponding to the target data, wherein the data verification state includes that the target data is a prime number or that the target data is a composite number.

[0197] Specifically, the corresponding situations of the data splitting hardware unit and the modular exponentiation hardware unit, as well as the process of performing data splitting and modular exponentiation, can refer to the corresponding descriptions above. It can be understood that the algorithm execution control unit is the hardware carrier of the above-mentioned logic judgment unit, and the algorithm execution control unit can implement the above-mentioned logic judgment. The algorithm execution control unit can be an existing commonly used computer or microprocessor, and the specific logic judgment when the Miller-Rabin algorithm is running shall prevail.

Claims

1. A Miller-Rabin algorithm acceleration method based on software and hardware fusion, characterized in that: The acceleration method of the Miller-Rabin algorithm includes: At least a data splitting hardware unit for performing data splitting, a modular exponentiation hardware unit for performing modular exponentiation, and a logic judgment unit for performing logic judgment are configured, wherein: When executing the Miller-Rabin algorithm, the target data to be verified is loaded into the data splitting hardware unit, so as to use the data splitting hardware unit to perform data splitting on the target data, and generate a decomposition array matching the target data after the data splitting, wherein the decomposition array includes at least a first decomposition radix and a second decomposition radix; Generate modular exponentiation object data based on the decomposed array, and use a modular exponentiation hardware unit to perform modular exponentiation on the modular exponentiation object data, wherein when executing the Miller-Rabin algorithm, the modular exponentiation performed by the modular exponentiation hardware unit includes at least a first modular exponentiation and a second modular exponentiation in one round of judgment, and after performing the first modular exponentiation, a first modular exponentiation result value is generated, and after performing the second modular exponentiation, a second modular exponentiation result value is generated; A logic judgment unit is used to perform logic judgment on the first modular exponentiation result value and the second modular exponentiation result value, and based on the corresponding logic judgment states of the first modular exponentiation result value and the second modular exponentiation result value, a data verification state corresponding to the target data is generated, wherein the data verification state includes whether the target data is a prime number or a composite number.

2. The Miller-Rabin algorithm acceleration method based on software and hardware fusion according to claim 1 is characterized in that: The data splitting hardware unit includes a first decomposition radix generation circuit and a second decomposition radix generation circuit, wherein: The first decomposition radix generation circuit is adaptively connected to the second decomposition radix generation circuit; The first decomposition radix generation circuit receives the target data, and solves the data status information of the target data based on the first reference number, and generates the first decomposition radix based on the target data, the first reference number and the data status information of the target data, wherein the data status information of the target data includes whether the target data is an odd number or an even number; The second decomposition radix generation circuit receives the second reference number and generates a corresponding second decomposition radix based on the data state information, wherein the first reference number and the second reference number are mutually exclusive one-bit binary numbers; When executing the Miller-Rabin algorithm, based on the update control signal and the data status information of the target data, the first decomposition base and the second decomposition base are cyclically updated until the data splitting termination condition is reached; When the first decomposition target cardinality and the second decomposition target cardinality are formed based on the updated first decomposition cardinality and the second decomposition cardinality, respectively, then: p = 2 r *u, p is the target data, r is the first decomposition target cardinality, and u is the second decomposition target cardinality.

3. The Miller-Rabin algorithm acceleration method based on software and hardware fusion according to claim 2 is characterized in that: When executing the Miller-Rabin algorithm, the data is split into hardware units, and then: Subtract the target data from the first reference number to generate a data state judgment base number, where: When the data state judgment radix is ​​an odd number, the data state information of the target data is determined to be an even number, the first decomposition radix output by the first decomposition radix generation circuit is maintained as a first preset constant, and the second decomposition radix output by the second radix split generation circuit is maintained as a second preset constant; When the data state judgment cardinality is an even number, the data state information of the target data is judged to be an odd number, and the data state judgment cardinality is used as the initial value for cyclic updating of the first decomposition cardinality generating circuit; When the first decomposition radix generation circuit is controlled to update the first decomposition radix based on the update control signal, the first decomposition radix after each update is half of the current first decomposition radix; At the same time, when the second decomposition radix generation circuit is controlled to update the second decomposition radix based on the update control signal, the current second decomposition radix and the second reference number are accumulated, and the second decomposition radix is ​​updated to the accumulated value of the current second decomposition radix and the second reference number.

4. The Miller-Rabin algorithm acceleration method based on software and hardware fusion according to claim 3 is characterized in that: The first decomposition radix generation circuit includes a data state judgment circuit and a first decomposition radix generation main circuit adaptively connected to the data state judgment circuit, wherein: The data state judgment circuit at least includes a subtractor and a data state judgment base transmission circuit, wherein the subtractor receives the target data and the first reference number at the same time, and uses the difference between the target data and the first reference number calculated by the subtractor as the data state judgment base, wherein the first reference number is 1; The data state judgment radix transfer circuit transfers the data state judgment radix to the first decomposition radix generation main circuit under the update control signal; When the data state information of the target data is an even number, the first decomposition base generation main circuit maintains the generated first decomposition base as a first preset constant under the data state judgment base; When the data status information of the target data is an odd number, the data status judgment radix is ​​loaded into the first decomposition radix generation circuit under the update control signal, and the data status judgment radix is ​​used as the initial value of the first decomposition radix. Thereafter, the first decomposition radix generation main circuit cyclically updates the first decomposition radix.

5. The Miller-Rabin algorithm acceleration method based on software and hardware fusion according to claim 4 is characterized in that: The first decomposition radix generation main circuit includes an initial value transfer circuit, a trigger CF1, a data splitting right shift circuit and a first decomposition radix judgment circuit, wherein: The initial value transfer circuit receives the data state judgment base, and transfers the data state judgment base to the PRE pre-trigger terminal of the trigger CF1 in the update control signal; The CLR clearing terminal of the flip-flop CF1 is connected to the output terminal of the data state judgment base transfer circuit; The Q terminal of the flip-flop CF1 is connected to the data splitting right shift circuit and the first decomposition radix judgment circuit, the data splitting right shift circuit is connected to the D terminal of the flip-flop CF1, the output of the first decomposition radix judgment circuit is connected to the CE terminal of the flip-flop CF1, and the C clock terminal of the flip-flop CF1 receives the clock signal clk1; When the data state information of the target data is an even number, the flip-flop CF1 is cleared by using the data state judgment base loaded into the CLR clear terminal of the flip-flop CF1, so that the Q terminal of the flip-flop CF1 outputs a first preset constant of 0; When the data state of the target data is an odd number, the data state judgment base is transmitted to the PRE pre-trigger terminal of the trigger CF1 through the initial value transmission circuit to serve as the initial value of the first decomposition base; The data splitting right shift circuit performs right shift processing on the first decomposition base outputted from the Q terminal of the flip-flop CF1, and updates the first decomposition base under the clock signal clk1; The first decomposition radix judgment circuit is used for the lowest bit state of the current first decomposition radix, wherein the lowest bit state of the first decomposition radix is ​​0 or 1. When the lowest bit state of the first decomposition radix is ​​1, the first decomposition radix outputted by the Q terminal of the flip-flop CF1 is maintained, and the second decomposition radix generation circuit stops updating the second decomposition radix; When the state of the least significant bit of the first decomposition radix is ​​0, the second decomposition radix generating circuit is configured to update the second decomposition radix under the clock signal clk1.

6. The Miller-Rabin algorithm acceleration method based on software and hardware fusion according to claim 4 is characterized in that: The second decomposition radix generation circuit comprises at least an adder and a trigger CF2, wherein: A first input terminal of the adder is connected to the Q terminal of the flip-flop CF2, and a second input terminal of the adder is connected to a second reference number; The CLR clearing terminal of the flip-flop CF2 is connected to the update control signal, the C terminal of the flip-flop CF2 is connected to the clock signal clk1, and the CE terminal of the flip-flop CF2 is connected to the output terminal of the first decomposition cardinality judgment circuit.

7. The Miller-Rabin algorithm acceleration method based on software-hardware fusion according to any one of claims 1 to 6, characterized in that: The modular exponentiation hardware unit includes a fast exponentiation hardware circuit and a modulo hardware circuit connected in series with the fast exponentiation circuit, wherein: In one round of judgment of the Miller-Rabin algorithm, the first modular exponentiation operation and the second modular exponentiation operation are sequentially performed by the modular exponentiation hardware unit; When performing the first modular exponentiation operation, the first decomposition base is used as the target exponentiation, and the fast exponentiation hardware circuit performs the exponentiation operation on the target base and the target exponentiation to generate a first fast exponentiation operation result, and then the modulo hardware circuit performs the modulo operation on the first fast exponentiation operation result to generate a first modular exponentiation operation result value; When performing the second modular exponentiation operation, the result value of the first modular exponentiation operation is used as the target base, and the fast exponentiation hardware circuit performs an exponentiation operation on the target base and the target power to generate a second fast modular operation result. Thereafter, the modulo hardware circuit performs a modulo operation on the second fast exponentiation operation result to generate a second modular exponentiation operation result value.

8. The Miller-Rabin algorithm acceleration method based on software and hardware fusion according to claim 7 is characterized in that: The fast exponentiation hardware circuit includes an exponentiation processing circuit and a base operation circuit adaptively connected to the exponentiation processing circuit, wherein: The power processing circuit at least receives the target power and processes the target power, wherein the processing of the target power at least includes state determination processing and power right shift update processing; After executing a state judgment process on the lowest bit data of the target power, a first control signal for the base operation corresponding to the lowest bit data of the target power is generated, and the power right shift update process is executed only when and only when the state judgment of the lowest bit data of the target power is 0; When performing the power right shift update process, the target power is right shifted by one bit to update the target power, and a second control signal of the base operation corresponding to the updated target power is generated; When the lowest bit data of the updated target power is determined to be 1 after the state judgment process, the power processing circuit stops processing the target power; The base operation circuit receives at least a target base, and controls the base multiplication operation on the target base based on a base operation first control signal and a base operation second control signal, so as to generate a corresponding fast power operation result after performing the base multiplication operation, wherein: A base multiplication operation performed on the target base, including at least a base square operation and a base multiplication operation; When the power processing circuit stops processing the target power, the generated fast power operation result is output.

9. The Miller-Rabin algorithm acceleration method based on software and hardware fusion according to claim 8 is characterized in that: The power processing circuit includes a state judgment circuit, a power right shift operation circuit and a D flip-flop D5, wherein: The target power is loaded to the first input terminal of the state judgment circuit, the state judgment circuit is connected to the D terminal of the D flip-flop D5 through the power right shift operation circuit, and the Q terminal of the D flip-flop D5 is feedback connected to the first input terminal of the state judgment circuit; Performing state judgment processing on the lowest bit data of the target power through a state judgment circuit, and generating a first control signal for base operation through an output terminal of the state judgment circuit; Performing power right shift update processing on the base operation first control signal through the power right shift operation circuit, and generating a base operation second control signal, and loading the updated target power to the D terminal of the D flip-flop D5; The clock terminal of the D flip-flop D5 is connected to the clock signal clk, so as to feed back the updated target power to the first input terminal of the state judgment circuit under the clock signal clk.

10. A Miller-Rabin algorithm acceleration device based on software and hardware fusion, characterized in that: The Miller Rabin algorithm acceleration device comprises: A data splitting hardware unit performs data splitting on the target data and generates a decomposition array matching the target data after the data splitting, wherein the decomposition array at least includes a first decomposition radix and a second decomposition radix; A modular exponentiation hardware unit performs modular exponentiation on the exponentiation object data based on the decomposed array to generate the module, wherein when the Miller-Rabin algorithm is executed, the modular exponentiation performed by the modular exponentiation hardware unit includes at least a first modular exponentiation and a second modular exponentiation in one round of judgment, and generates a first modular exponentiation result value after executing the first modular exponentiation, and generates a second modular exponentiation result value after executing the second modular exponentiation; The algorithm executes a control unit to perform logical judgment on the first modular exponentiation result value and the second modular exponentiation result value, and based on the corresponding logical judgment states of the first modular exponentiation result value and the second modular exponentiation result value, generates a data verification state corresponding to the target data, wherein the data verification state includes that the target data is a prime number or that the target data is a composite number.

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