Miller-rabin algorithm acceleration method and device based on hardware and software fusion

Abstract

The application relates to a Miller-Rabin algorithm acceleration method and device based on software and hardware fusion. When the Miller-Rabin algorithm is executed, target data to be verified is loaded into a data splitting hardware unit, the target data is subjected to data splitting by using the data splitting hardware unit, and a decomposition array matched with the target data is generated after data splitting; the decomposition array is used to generate modulus power operation object data, the modulus power operation object data is subjected to modulus power operation by using a modulus power operation hardware unit, a logic judgment unit is used to perform logic judgment on a first modulus power operation result value and a second modulus power operation result value, and a data verification state corresponding to the target data is generated based on the logic judgment state of the first modulus power operation result value and the second modulus power operation result value. The application can effectively improve the efficiency of large-batch prime number judgment by using the Miller-Rabin algorithm, reduce the algorithm power requirement of running the Miller-Rabin algorithm, and improve the prime number judgment and generation efficiency.

Description

TECHNICAL FIELD

[0001] The application relates to an acceleration method and device, in particular to a Miller-Rabin algorithm acceleration method and device based on software and hardware fusion. BACKGROUND

[0002] The Miller-Rabin algorithm is a randomized algorithm for determining whether a number is a prime number, and is widely used in the fields of cryptography and number theory. In private computing, the determination of a prime number is very important. For example, in the RSA encryption algorithm, two large prime numbers need to be generated. At this time, the Miller-Rabin algorithm can be used to quickly determine whether the generated number is a prime number, thereby improving the efficiency of generating prime numbers.

[0003] When the Miller-Rabin algorithm is executed, splitting processing operations of large numbers and multiple power operation modulo processing operations are involved, which are very time-consuming. At present, when determining whether data is a prime number, some program scripts are written to execute the Miller-Rabin algorithm.

[0004] As can be seen from the above description, the implementation of the Miller-Rabin algorithm currently relies on the running of software programs. When a large number of prime numbers need to be determined, the computing power is not enough, which affects the determination and generation efficiency of prime numbers. SUMMARY

[0005] The application aims to overcome the deficiencies in the prior art and provide a Miller-Rabin algorithm acceleration method and device based on software and hardware fusion, which can effectively improve the efficiency of determining a large number of prime numbers by using the Miller-Rabin algorithm, reduce the computing power requirement of running the Miller-Rabin algorithm, and improve the determination and generation efficiency of prime numbers.

[0006] According to the technical scheme provided by the application, a Miller-Rabin algorithm acceleration method based on software and hardware fusion comprises:

[0007] At least a data splitting hardware unit for performing data splitting, a modulo power operation hardware unit for performing modulo power operation, and a logic judgment unit for performing logic judgment are configured, wherein

[0008] When the Miller-Rabin algorithm is executed, the target data to be verified is loaded into the data splitting hardware unit to split the target data by using the data splitting hardware unit, and a decomposition array matching the target data is generated after data splitting, wherein the decomposition array at least includes a first decomposition base and a second decomposition base;

[0009] The modulo exponentiation object data is generated based on the decomposition array, and the modulo exponentiation hardware unit is used to perform modulo exponentiation on the modulo exponentiation object data, wherein when the Miller-Rabin algorithm is executed, the modulo exponentiation performed by the modulo exponentiation hardware unit at least includes a first modulo exponentiation and a second modulo exponentiation in a round of judgment, a first modulo exponentiation result value is generated after the first modulo exponentiation is executed, and a second modulo exponentiation result value is generated after the second modulo exponentiation is executed;

[0010] The first modulo exponentiation result value and the second modulo exponentiation result value are logically judged by using the logical judgment unit, and the data verification state corresponding to the target data is generated based on the corresponding logical judgment state of the first modulo exponentiation result value and the second modulo exponentiation result value, wherein the data verification state includes that the target data is a prime number or the target data is a composite number.

[0011] The data splitting hardware unit includes a first decomposition base generating circuit and a second decomposition base generating circuit, wherein,

[0012] The first decomposition base generating circuit and the second decomposition base generating circuit are adaptively connected;

[0013] The first decomposition base generating circuit receives the target data, and calculates the data state information of the target data based on the first reference number, and generates the first decomposition base based on the target data, the first reference number and the data state information of the target data, wherein the data state information of the target data includes that the target data is an odd number or an even number;

[0014] The second decomposition base generating circuit receives the second reference number, and generates the corresponding second decomposition base based on the data state information, wherein the first reference number and the second reference number are mutually exclusive one-bit binary numbers;

[0015] When the Miller-Rabin algorithm is executed, the first decomposition base and the second decomposition base are cyclically updated based on the update control signal and the data state information of the target data until a data splitting termination condition is reached;

[0016] When the first decomposition base and the second decomposition base are updated, the first decomposition target base and the second decomposition target base are formed based on the updated first decomposition base and the second decomposition base, respectively, and then p=2 r u, p is the target data, r is the first decomposition target base, and u is the second decomposition target base.

[0017] When the Miller-Rabin algorithm is executed, the data splitting hardware unit is used, and then

[0018] The target data is subtracted from the first reference number to generate a data state judgment base, wherein,

[0019] When the data state judgment base number is odd, the data state information of the target data is determined as even, the first decomposition base number output by the first decomposition base number generation circuit is kept as a first preset constant, and the second decomposition base number output by the second base number decomposition generation circuit is kept as a second preset constant;

[0020] When the data state judgment base number is even, the data state information of the target data is determined as odd, and the data state judgment base number is used as the initial value of the first decomposition base number generation circuit for cyclic updating;

[0021] When the first decomposition base number generation circuit is controlled to update the first decomposition base number based on the update control signal, the first decomposition base number after each update is half of the current first decomposition base number;

[0022] Meanwhile, when the second decomposition base number generation circuit is controlled to update the second decomposition base number based on the update control signal, the current second decomposition base number is accumulated with the second reference number, and the second decomposition base number is updated to the accumulated value of the current second decomposition base number and the second reference number.

[0023] The first decomposition base number generation circuit comprises a data state judgment circuit and a first decomposition base number generation main circuit connected to the data state judgment circuit,

[0024] The data state judgment circuit comprises at least a subtractor and a data state judgment base number transmission circuit, wherein the subtractor receives the target data and the first reference number at the same time, and the difference between the target data and the first reference number calculated by the subtractor is used as the data state judgment base number, wherein the first reference number is 1;

[0025] The data state judgment base number transmission circuit transmits the data state judgment base number to the first decomposition base number generation main circuit under the update control signal;

[0026] When the data state information of the target data is even, the first decomposition base number generated by the first decomposition base number generation main circuit under the data state judgment base number is kept as a first preset constant;

[0027] When the data state information of the target data is odd, the data state judgment base number is loaded to the first decomposition base number generation circuit under the update control signal, and the data state judgment base number is used as the initial value of the first decomposition base number, and thereafter, the first decomposition base number generation main circuit cyclically updates the first decomposition base number.

[0028] The first decomposition base number generation main circuit comprises an initial value transmission circuit, a flip-flop CF1, a data splitting right shift circuit, and a first decomposition base number judgment circuit,

[0029] The initial value transmission circuit receives the data state judgment base, and transmits the data state judgment base to the PRE pretrigger end of the flip-flop CF1 under the update control signal;

[0030] The CLR clear end of the flip-flop CF1 is connected with the output end of the data state judgment base transmission circuit;

[0031] The Q end of the flip-flop CF1 is connected with the data split right shift circuit and the first decomposition base judgment circuit, the data split right shift circuit is connected with the D end of the flip-flop CF1, the output of the first decomposition base judgment circuit is connected with the CE end of the flip-flop CF1, and the C clock end of the flip-flop CF1 receives the clock signal clk1;

[0032] When the data state information of the target data is even, the data state judgment base loaded to the CLR clear end of the flip-flop CF1 is used to perform the clear operation on the flip-flop CF1, so that the Q end of the flip-flop CF1 outputs the first preset constant of 0;

[0033] When the data state of the target data is odd, the data state judgment base is transmitted to the PRE pretrigger end of the flip-flop CF1 by the initial value transmission circuit, to serve as the initial value of the first decomposition base;

[0034] The data split right shift circuit performs the right shift processing on the first decomposition base output by the Q end of the flip-flop CF1, and updates the first decomposition base under the clock signal clk1;

[0035] The first decomposition base judgment circuit is used for the lowest bit state of the current first decomposition base, wherein the lowest bit state of the first decomposition base is 0 or 1,

[0036] When the lowest bit state of the first decomposition base is 1, the first decomposition base output by the Q end of the flip-flop CF1 is maintained, and the update of the second decomposition base by the second decomposition base generation circuit is stopped;

[0037] When the lowest bit state of the first decomposition base is 0, the second decomposition base generation circuit is configured to update the second decomposition base under the clock signal clk1.

[0038] The second decomposition base generation circuit at least includes an adder and a flip-flop CF2, wherein,

[0039] The first input end of the adder is connected with the Q end of the flip-flop CF2, and the second input end of the adder is connected with the second reference number;

[0040] The CLR clear end of the flip-flop CF2 is connected with the update control signal, the C end of the flip-flop CF2 is connected with the clock signal clk1, and the CE end of the flip-flop CF2 is connected with the output end of the first decomposition base judgment circuit.

[0041] The modular exponentiation hardware unit comprises a fast power hardware circuit and a modulo hardware circuit connected in series with the fast power hardware circuit, wherein

[0042] In a round of the Miller-Rabin algorithm, the first modular exponentiation and the second modular exponentiation are executed in sequence by the modular exponentiation hardware unit;

[0043] When the first modular exponentiation is executed, the first decomposition base is taken as a target exponent, the fast power hardware circuit executes the power operation on the target base and the target exponent to generate a first fast power operation result, and then the modulo hardware circuit executes the modulo operation on the first fast power operation result to generate a first modular exponentiation result value;

[0044] When the second modular exponentiation is executed, the first modular exponentiation result value is taken as a target base, the fast power hardware circuit executes the power operation on the target base and the target exponent to generate a second fast power operation result, and then the modulo hardware circuit executes the modulo operation on the second fast power operation result to generate a second modular exponentiation result value.

[0045] The fast power hardware circuit comprises an exponent processing circuit and a base operation circuit connected to the exponent processing circuit, wherein

[0046] The exponent processing circuit receives at least a target exponent and processes the target exponent, wherein the processing of the target exponent at least comprises state judgment processing and exponent right shift update processing;

[0047] After the state judgment processing is performed on the least significant bit data of the target exponent, a base operation first control signal corresponding to the least significant bit data of the target exponent is generated, and the exponent right shift update processing is performed only when the state of the least significant bit data of the target exponent is judged to be 0;

[0048] When the exponent right shift update processing is executed, the target exponent is right shifted by one bit to update the target exponent, and a base operation second control signal corresponding to the updated target exponent is generated;

[0049] When the least significant bit data of the updated target exponent is determined to be 1 after the state judgment processing, the exponent processing circuit stops processing the target exponent;

[0050] The base operation circuit receives at least a target base and controls the base multiplication operation on the target base based on the base operation first control signal and the base operation second control signal to generate a corresponding fast power operation result after the base multiplication operation is executed, wherein

[0051] The base multiplication operation performed on the target base at least comprises base squaring operation and base multiplication operation;

[0052] When the exponent processing circuit stops processing the target exponent, the generated fast power operation result is outputted.

[0053] The exponent processing circuit comprises a state judging circuit, an exponent right shift operation circuit and a D flip-flop D5.

[0054] The target exponent is loaded to a first input terminal of the state judging circuit, the state judging circuit is connected with the exponent right shift operation circuit and a D terminal of the D flip-flop D5, and a Q terminal of the D flip-flop D5 is feedback connected to the first input terminal of the state judging circuit.

[0055] The state judging circuit performs state judging processing on the lowest bit data of the target exponent, and generates a first control signal for base operation through an output terminal of the state judging circuit.

[0056] The exponent right shift operation circuit performs exponent right shift updating processing on the first control signal for base operation, and generates a second control signal for base operation, and loads the updated target exponent to the D terminal of the D flip-flop D5.

[0057] The clock terminal of the D flip-flop D5 is connected with a clock signal clk, so that the updated target exponent is fed back to the first input terminal of the state judging circuit under the clock signal clk.

[0058] A Miller-Rabin algorithm acceleration device based on software and hardware fusion, the Miller-Rabin algorithm acceleration device comprises:

[0059] A data splitting hardware unit splits target data, and generates a decomposition array matching the target data after data splitting, wherein the decomposition array comprises at least a first decomposition base and a second decomposition base.

[0060] A modulus power operation hardware unit performs modulus power operation on modulus power operation object data generated based on the decomposition array, wherein when the Miller-Rabin algorithm is executed, the modulus power operation performed by the modulus power operation hardware unit comprises at least a first modulus power operation and a second modulus power operation in a round of judgment, a first modulus power operation result value is generated after the first modulus power operation is executed, and a second modulus power operation result value is generated after the second modulus power operation is executed.

[0061] An algorithm execution control unit performs logical judgment on the first modulus power operation result value and the second modulus power operation result value, and generates a data verification state corresponding to the target data based on the corresponding logical judgment state of the first modulus power operation result value and the second modulus power operation result value, wherein the data verification state comprises that the target data is a prime number or the target data is a composite number.

[0062] The advantages of the present application are as follows: when the Miller-Rabin algorithm is executed, the target data is split by the data splitting hardware unit, and the first split base and the second split base are generated; the split array formed by splitting is used to perform the modulus power operation involved in the Miller-Rabin algorithm by using the modulus power operation unit, and the first modulus power operation result value and the second modulus power operation result value are generated in sequence; the first modulus power operation result value and the second modulus power operation result value are logically judged by using the logical judgment unit, and the data verification state corresponding to the target data can be generated; that is, the data splitting hardware unit and the modulus power operation unit can be used to accelerate the operation of the Miller-Rabin algorithm, so that the efficiency of large-scale prime number judgment by using the Miller-Rabin algorithm can be effectively improved, the computing power requirement of the Miller-Rabin algorithm can be reduced, and the judgment and generation efficiency of prime numbers can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 An embodiment schematic diagram of the Miller-Rabin algorithm acceleration method of the present application.

[0064] Figure 2 A circuit schematic diagram of an embodiment of the data splitting hardware unit of the present application.

[0065] Figure 3 A circuit block diagram of an embodiment of the modulus power operation hardware unit of the present application.

[0066] Figure 4 A circuit schematic diagram of an embodiment of the fast power hardware circuit of the present application. DETAILED DESCRIPTION

[0067] The present application will be further described below in combination with specific drawings and embodiments.

[0068] It should be noted that when the Miller-Rabin method is used to judge whether a number is a prime number, the following mathematical principles are generally used: first, a prime number p greater than 2 must be an odd number, so p-1 can be split into the form of 2r*d, and then based on Fermat's little theorem: if p is a prime number, a p-1 ≡1(mod p), and the quadratic detection theorem: for any positive integer x less than p, if a non-trivial root of 1(mod p) exists, then p is a composite number.

[0069] Based on the above description, a p-1 ≡1(mod p) can be transformed into a d is regarded as k, and the following equation is obtained: Therefore, it is necessary to find x 2 ≡1(mod p), and this x exists in the change process of a 2rdIn the process of determining the changes, if it is equal to 1 or p-1, it means that p is a prime number; but if it is not equal to 1 or p-1, p has a probability of being a composite number.

[0070] From the above description of the background art, it can be seen that in the prior art, the Miller-Rabin algorithm is executed, and the above-mentioned determination process is mainly performed by software programs, which may have the problems of time-consuming and low execution efficiency. In order to effectively improve the efficiency of large-scale prime number determination using the Miller-Rabin algorithm and reduce the algorithmic requirement of running the Miller-Rabin algorithm, the present application provides a Miller-Rabin algorithm acceleration method based on software and hardware fusion. Specifically, the acceleration method of the Miller-Rabin algorithm comprises:

[0071] Step S1, at least a data splitting hardware unit for performing data splitting, a modular exponentiation hardware unit for performing modular exponentiation, and a logical judgment unit for performing logical judgment are configured, wherein,

[0072] Step S2, when executing the Miller-Rabin algorithm, the target data to be verified is loaded into the data splitting hardware unit to split the target data by using the data splitting hardware unit, and a decomposition array matching the target data is generated after data splitting, wherein the decomposition array at least includes a first decomposition base and a second decomposition base;

[0073] Step S3, based on the decomposition array, modular exponentiation object data is generated, and the modular exponentiation hardware unit is used to perform modular exponentiation on the modular exponentiation object data, wherein when the Miller-Rabin algorithm is executed, the modular exponentiation performed by the modular exponentiation hardware unit at least includes a first modular exponentiation and a second modular exponentiation in a round of judgment, a first modular exponentiation result value is generated after the first modular exponentiation is performed, and a second modular exponentiation result value is generated after the second modular exponentiation is performed;

[0074] Step S4, the logical judgment unit is used to perform logical judgment on the first modular exponentiation result value and the second modular exponentiation result value, and based on the corresponding logical judgment state of the first modular exponentiation result value and the second modular exponentiation result value, a data verification state corresponding to the target data is generated, wherein the data verification state includes that the target data is a prime number or the target data is a composite number.

[0075] Figure 1An embodiment of the Miller-Rabin algorithm acceleration method of the present application is shown in the figure. It can be understood that, when accelerating the Miller-Rabin algorithm, the principle of the Miller-Rabin algorithm is consistent with that of the existing Miller-Rabin algorithm, except that the present application uses a data splitting hardware unit to perform the data splitting process in the Miller-Rabin algorithm, uses a modular exponentiation hardware unit to perform the modular exponentiation in the Miller-Rabin algorithm process, and uses a logical judgment unit to perform logical judgment. Therefore, the corresponding operation processes of data splitting and modular exponentiation are all implemented by hardware circuits, which can effectively accelerate the operation of the Miller-Rabin algorithm, improve the efficiency of large-scale prime number judgment using the Miller-Rabin algorithm, and reduce the algorithmic requirement for running the Miller-Rabin algorithm.

[0076] It should be noted that the logical judgment unit can still use the existing common software program method, of course, the logical judgment unit can also use a hardware circuit to perform the corresponding logical judgment, and the present application does not limit the implementation method of the logical judgment unit for performing logical judgment.

[0077] By Figure 1 It can be seen that, when using the data splitting hardware unit to split data, the target data is mainly split, and the corresponding decomposition array is generated after splitting. The target data is the data to be judged by the Miller-Rabin algorithm, that is, it is necessary to judge whether the target data is a prime number. Generally, in order to meet the modular exponentiation and logical judgment of the Miller-Rabin algorithm, the decomposition array should include the first decomposition base and the second decomposition base. The way and process of the data splitting hardware unit splitting the target data and generating the decomposition array can be referred to the corresponding description below.

[0078] After the data splitting hardware unit splits to generate the decomposition array, the modular exponentiation unit is used to perform the modular exponentiation. When performing the modular exponentiation, the decomposition array is used to generate the corresponding modular exponentiation object data. The condition for generating the modular exponentiation object data is that it can meet the demand of the modular exponentiation in the Miller-Rabin algorithm. The condition for generating the modular exponentiation object data can be referred to the corresponding description below. According to the principle of the Miller-Rabin algorithm, the decomposition array generated by the data splitting hardware unit should remain unchanged in one round of judgment. The modular exponentiation hardware unit includes at least the first modular exponentiation and the second modular exponentiation. When performing the Miller-Rabin algorithm, it generally should go through multiple rounds of judgment until the judgment of whether the target data is a prime number is completed.

[0079] In a round of judgment, a first modular exponentiation operation can generate a corresponding first modular exponentiation result value, and a second modular exponentiation operation can generate a second modular exponentiation result value. It should be noted that when the logic judgment unit performs logic judgment, it specifically refers to judging the first modular exponentiation result value and the second modular exponentiation result value. As mentioned above, when performing logic judgment, the main judgment is the corresponding relationship between the first modular exponentiation result value, the second modular exponentiation result value and 1 and / or p-1, where p is the target data. The logic judgment unit can perform logic judgment in a manner consistent with the prior art. It can be understood that after one or more rounds of logic judgment, a data verification state corresponding to the target data can be generated. As mentioned above, the data verification state includes that the target data is a prime number or the target data is a composite number.

[0080] It should be noted that when performing a round of judgment, the logic judgment unit is generally used to first perform logic judgment on the first modular exponentiation result value, and then the logic judgment unit is used to perform logic judgment on the second modular exponentiation result value. The order and form of the logic judgment unit performing logic judgment on the first modular exponentiation result value and the second modular exponentiation result value can refer to the principle of the existing Miller-Rabin algorithm, and the specific implementation can satisfy the verification of the target data.

[0081] As mentioned above, when performing the Miller-Rabin algorithm, the data splitting hardware unit can be used to perform data splitting of the target data, the modular exponentiation hardware unit can be used to perform modular exponentiation involved in the Miller-Rabin algorithm, and the logic judgment unit can be used for logic judgment. Therefore, the software and hardware can be integrated, and based on the characteristics of the software and hardware integration, the hardware design difficulty and cost can be balanced, and the operation of the Miller-Rabin algorithm can be maximized.

[0082] In an embodiment of the present application, the data splitting hardware unit includes a first decomposition base generating circuit and a second decomposition base generating circuit, wherein,

[0083] The first decomposition base generating circuit and the second decomposition base generating circuit are adaptively connected;

[0084] The first decomposition base generating circuit receives the target data, and calculates data state information of the target data based on a first reference number, and generates a first decomposition base based on the target data, the first reference number and the data state information of the target data, wherein the data state information of the target data includes whether the target data is an odd number or an even number.

[0085] The second decomposition base generating circuit receives a second reference number and generates a corresponding second decomposition base based on the data state information, wherein the first reference number and the second reference number are mutually exclusive one-bit binary numbers.

[0086] In the execution of the Miller-Rabin algorithm, the first decomposition base and the second decomposition base are updated cyclically based on the updated control signal and the data state information of the target data until a data splitting termination condition is reached.

[0087] When the first decomposition base and the second decomposition base are updated, the first decomposition target base and the second decomposition target base are formed based on the updated first decomposition base and the second decomposition base, and thus p = 2. r u, p are target data, r is the first decomposition target base, and u is the second decomposition target base.

[0088] As can be seen from the above description, when the target data is split by the data splitting hardware circuit, the first decomposition base and the second decomposition base can generally be obtained. In order to obtain the first decomposition base and the second decomposition base, the data splitting hardware unit in an embodiment of the present application can include a first decomposition base generation circuit and a second decomposition base generation circuit, and the first decomposition base generation circuit is connected to the second decomposition base generation circuit.

[0089] When the target data is split, the target data should be loaded into the first decomposition base generation circuit. In addition, the first decomposition base generation circuit also needs to receive a first reference number to calculate the data state information of the target data using the first reference number. Thereafter, the first decomposition base can be generated based on the target data, the first reference number and the data state information of the target data. The process of generating the first decomposition base by the first decomposition base generation circuit will be described below.

[0090] In order to generate the second decomposition base, the second decomposition base generation circuit should receive a second reference number, wherein the first reference number and the second reference number can be the same, such as 1 in binary. The second decomposition base generation circuit should be related to the data state information of the target data when generating the second decomposition base. The specific way and process of generating the second decomposition base will be described below.

[0091] As can be seen from the above description, in the execution of the Miller-Rabin algorithm, multiple rounds of judgment are performed. In the current round of judgment, the first decomposition base and the second decomposition base should remain unchanged, but in the next round of judgment, the first decomposition base and the second decomposition base need to be updated based on the updated control signal and the data state information of the target data.

[0092] When the first decomposition base and the second decomposition base are cyclically updated, the termination condition of the cyclic update is at least that new first decomposition base and second decomposition base cannot be obtained by data splitting, and it can be understood that when the first decomposition base and the second decomposition base are subjected to the above-mentioned modular exponentiation to generate corresponding first modular exponentiation result values and second modular exponentiation result values, and when the corresponding logical judgment condition is satisfied by the logical judgment unit, the current first decomposition base forms the first decomposition target base, and the current second decomposition base forms the second decomposition target base.

[0093] In a specific implementation, the condition satisfying the logical judgment refers to a condition satisfying that the target data is a prime number, and the condition satisfying the logical judgment is consistent with the existing Miller-Rabin algorithm, which will not be described herein again. In an embodiment of the present application, the first decomposition target base and the second decomposition target base obtained are p = 2 r u, p are target data, r is the first decomposition target base, and u is the second decomposition target base.

[0094] As can be known from the above description, when the Miller-Rabin algorithm is executed, before the first decomposition target base and the second decomposition target base are obtained, if data splitting can still be implemented by using the data splitting hardware unit, data splitting should be continued until the data splitting hardware unit cannot perform data splitting, at which time the data splitting termination condition is reached, and the Miller-Rabin algorithm for the target data should be terminated. When the Miller-Rabin algorithm is terminated because the data splitting hardware unit cannot perform data splitting, the target data can be obtained to be a prime number or a non-prime number according to the logical judgment condition.

[0095] In an embodiment of the present application, when the Miller-Rabin algorithm is executed, the data splitting hardware unit has the following relationship:

[0096] The target data is subtracted from the first reference number to generate a data state judgment base, wherein

[0097] When the data state judgment base is an odd number, it is determined that the data state information of the target data is an even number, the first decomposition base output by the first decomposition base generation circuit is maintained as a first preset constant, and the second decomposition base output by the second base splitting generation circuit is maintained as a second preset constant;

[0098] When the data state judgment base is an even number, it is determined that the data state information of the target data is an odd number, and the data state judgment base is used as an initial value for cyclic update of the first decomposition base generation circuit;

[0099] When the first decomposition base generation circuit is controlled to update the first decomposition base based on the update control signal, the first decomposition base after each update is half of the current first decomposition base;

[0100] Meanwhile, when the second decomposition base is updated based on the update control signal, the current second decomposition base is accumulated with the second reference number, and the second decomposition base is updated as the accumulated value of the current second decomposition base and the second reference number.

[0101] As can be seen from the above description, the data state information of the target data can be obtained according to the target data and the first reference number. In order to obtain the data state information of the target data, the target data is subtracted from the first reference number, and the data state judgment base can be generated based on the difference value. Thereafter, the data state information of the target data can be generated according to the data state judgment base, for example, when the data state judgment base is odd, it is determined that the data state information of the target data is even, or when the data state judgment base is even, it is determined that the data state information of the target data is odd.

[0102] In a specific implementation, when it is determined that the data state information of the target data is even, the first decomposition base output by the first decomposition base generation circuit is maintained as a first preset constant, and the second decomposition base output by the second base splitting generation circuit is maintained as a second preset constant. The first preset constant and the second preset constant can be selected and determined according to actual needs, for example, the first preset constant and the second preset constant can be 0 or other constants. The first preset constant and the second preset constant will be illustrated below. It can be understood that when the data state information of the target data is even, it can be determined that the target data is not a prime number. Therefore, when the target data is split, the first decomposition base is maintained as the first preset constant, and the second decomposition base is maintained as the second preset constant. The first decomposition base and the second decomposition base maintained as constants can prompt that the operation of the Miller-Rabin algorithm should be terminated.

[0103] When it is determined that the data state information of the target data is odd, it cannot be determined whether the target data is a prime number, and therefore, it needs to be determined through the processes of data splitting, modular exponentiation and logical judgment. Specifically, when the data state information of the target data is odd, the data state judgment base should be used as the initial value of the first decomposition base generation circuit for cyclic updating. In an embodiment of the present application, the first decomposition base after each update is configured as half of the current first decomposition base. Meanwhile, when the second decomposition base is updated, the current second decomposition base is accumulated with the second reference number, so as to update the second decomposition base based on the accumulated sum of the second decomposition base and the second reference number, that is, the accumulated value of the second decomposition base and the second reference number is used as the new second decomposition base.

[0104] It should be noted that, in one update, the first decomposition base and the second decomposition base are updated at the same time, that is, after the update, a new decomposition array is generated. In subsequent modulus power calculation, the modulus power operation object data is generated based on the new decomposition array.

[0105] In one embodiment of the application, the first decomposition base generating circuit includes a data state judgment circuit and a first decomposition base generating main circuit connected to the data state judgment circuit.

[0106] The data state judgment circuit includes at least a subtracter and a data state judgment base transfer circuit, wherein the subtracter receives the target data and the first reference number at the same time, and the difference between the target data and the first reference number calculated by the subtracter is the data state judgment base, wherein the first reference number is 1.

[0107] The data state judgment base transfer circuit transfers the data state judgment base to the first decomposition base generating main circuit under the update control signal.

[0108] When the data state information of the target data is even, the first decomposition base generating main circuit keeps the generated first decomposition base as a first preset constant under the data state judgment base.

[0109] When the data state information of the target data is odd, the data state judgment base is loaded to the first decomposition base generating circuit under the update control signal, and the data state judgment base is used as the initial value of the first decomposition base. Thereafter, the first decomposition base generating main circuit updates the first decomposition base cyclically.

[0110] In specific implementation, the first decomposition base generating circuit includes at least a data state judgment circuit and a first decomposition base generating main circuit, wherein the data state judgment circuit can include a subtracter and a data state judgment base transfer circuit, Figure 2 An embodiment circuit principle diagram of the first decomposition base generating circuit is shown in FIG. 1, wherein sub in the figure is a subtracter. The difference between the target data and the first reference number can be calculated by using the subtracter, that is, the data state judgment base can be obtained through the output end of the subtracter. Thereafter, the data state judgment base can be loaded to the first decomposition base generating main circuit through the data state judgment base transfer circuit.

[0111] Figure 2An embodiment of the first reference number is shown in the figure, in which the first reference number is selected as 1, and at this time, the data state judgment base is the difference between the target data and 1. It can be understood that the data state of the target data can be judged according to the data state judgment base, and the corresponding data state information can be obtained. For example, if the lowest bit of the data state judgment base is 1, it can be known from the calculation generation mode of the data state judgment base that the target base should be an even number. For example, if the lowest bit of the data state judgment base is 0, it can be known from the calculation generation mode of the data state judgment base that the target base should be an odd number.

[0112] After the data state judgment base is calculated, the data state judgment base should be transmitted to the first decomposition base generation main circuit through the data state judgment base transmission circuit. Figure 2 An embodiment of the data state judgment base transmission circuit is shown in the figure, in which the data state judgment base transmission circuit can adopt a multiplexer, Figure 2 In the figure, MUX1 is the data state judgment base transmission circuit, and the reset signal is the update control signal. Figure 2 In the figure, the first input end of the multiplexer MUX1 is connected with the input end of the subtractor, the second input end of the multiplexer MUX1 receives the constant 1, the reset signal is loaded to the control end of the multiplexer MUX1, and the output end of the multiplexer MUX1 is connected with the first decomposition base generation main circuit.

[0113] When the reset signal is in the effective state, the first input end of the multiplexer MUX1 is selected to output, at this time, the data state judgment base can be transmitted to the first decomposition base generation main circuit, and the data splitting state of the first decomposition base generation main circuit can be controlled based on the data state judgment base transmitted by the multiplexer MUX1. Generally, the reset signal is high and effective, and the reset signal remains in the effective state during the data splitting process, that is, the update control signal remains in the effective state during the data splitting process.

[0114] As can be known from the above description, when the data state information of the target data is an even number, the first decomposition base generated by the first decomposition base generation main circuit under the data state judgment base is maintained as the first preset constant. As described above, the first preset constant is generally 0. When the data state information of the target data is an odd number, the data state judgment base is taken as the initial value of the first decomposition base under the update control signal, and thereafter, the first decomposition base generation main circuit updates the first decomposition base in a loop.

[0115] In an embodiment of the application, the first decomposition base generation main circuit includes an initial value transmission circuit, a flip-flop CF1, a data splitting right shift circuit and a first decomposition base judgment circuit, wherein,

[0116] The initial value transmission circuit receives the data state judgment base and transmits the data state judgment base to the PRE pretrigger end of the flip-flop CF1 under the update control signal;

[0117] The CLR clear end of the flip-flop CF1 is connected with the output end of the data state judgment base transmission circuit;

[0118] The Q end of the flip-flop CF1 is connected with the data split right shift circuit and the first decomposition base judgment circuit, the data split right shift circuit is connected with the D end of the flip-flop CF1, the output of the first decomposition base judgment circuit is connected with the CE end of the flip-flop CF1, and the C clock end of the flip-flop CF1 receives the clock signal clk1;

[0119] When the data state information of the target data is even, the data state judgment base loaded to the CLR clear end of the flip-flop CF1 is used to perform the clear operation on the flip-flop CF1, so that the Q end of the flip-flop CF1 outputs the first preset constant of 0;

[0120] When the data state of the target data is odd, the data state judgment base is transmitted to the PRE pretrigger end of the flip-flop CF1 by the initial value transmission circuit to serve as the initial value of the first decomposition base;

[0121] The data split right shift circuit performs the right shift processing on the first decomposition base output by the Q end of the flip-flop CF1, and updates the first decomposition base under the clock signal clk1;

[0122] The first decomposition base judgment circuit is used for the lowest bit state of the current first decomposition base, wherein the lowest bit state of the first decomposition base is 0 or 1,

[0123] When the lowest bit state of the first decomposition base is 1, the first decomposition base output by the Q end of the flip-flop CF1 is maintained, and the update of the second decomposition base by the second decomposition base generation circuit is stopped;

[0124] When the lowest bit state of the first decomposition base is 0, the second decomposition base generation circuit is configured to update the second decomposition base under the clock signal clk1.

[0125] Specifically, the initial value transmission circuit is used to transmit the data state judgment base to the PRE pretrigger end of the flip-flop CF1, Figure 2An embodiment of the first decomposition base generating main circuit is shown in FIG. 1, wherein the initial value transfer circuit comprises an inverter INV1 and a multiplexer MUX2, the input terminal of the inverter INV1 is connected with the output terminal of the subtractor, the output terminal of the inverter INV1 is connected with the first input terminal of the multiplexer MUX2, the second input terminal of the multiplexer MUX2 is connected with the constant 1, the update control signal is loaded to the control terminal of the multiplexer MUX2, and the output terminal of the multiplexer MUX2 is connected with the PRE pre-trigger terminal of the flip-flop CF1. When the update control signal is in the active state, the first input terminal of the multiplexer MUX2 is selected to output, so that the data state judgment base can be transferred to the PRE pre-trigger terminal of the flip-flop CF1.

[0126] It should be noted that the flip-flop CF1 can adopt the existing common form, Figure 2 An embodiment of the flip-flop CF1 is shown in FIG. 2, which comprises a PRE pre-trigger terminal, a CLR clear terminal, a C clock terminal, a CE terminal and a Q terminal. As shown in the figure, the PRE pre-trigger terminal can invert the loaded data, so according to the above description of the initial value transfer circuit, the data state judgment base can be effectively loaded into the flip-flop CF1 through the above initial value transfer circuit, and used as the initial value of the first decomposition base.

[0127] The CLR clear terminal is in the high level active state, so when the least significant bit of the data state judgment base loaded by the multiplexer MUX1 is 1, the CLR clear terminal will be triggered to be active, and the output of the Q terminal of the flip-flop CF1 will be cleared. When the least significant bit of the data state judgment base loaded by the multiplexer MUX1 is 0, the CLR clear terminal will not be triggered to be active, and the first decomposition base generating main circuit will not be affected to update the first decomposition base in a loop.

[0128] The Q terminal of the flip-flop CF1 is connected with the input terminal of the data split right shift circuit, Figure 2 In FIG. 3, SF1 is the data split right shift circuit, which can adopt the existing common shift circuit. Generally, the data split right shift circuit can perform right shift on the input data to realize the operation of input data / 2 and rounding. Figure 2 In FIG. 3, the data split right shift circuit has three input terminals, the other two input terminals of the data split right shift circuit are connected with the constant 1, and the output terminal of the data split right shift circuit is connected with the D terminal of the flip-flop CF1, so that the first decomposition base updated each time can be configured as half of the current first decomposition base.

[0129] Figure 2An embodiment of the first decomposition base judging circuit is shown in Fig. 1. As shown in the figure, the first decomposition base judging circuit can include an AND gate circuit AND1 and a data buffer RAM1. One input terminal of the AND gate circuit AND1 is connected with the Q terminal of the flip-flop CF1, the other input terminal of the AND gate circuit AND1 is connected with a constant 1, the output terminal of the AND gate circuit AND1 is connected with the data buffer RAM1, and the data buffer RAM1 is connected with the CE terminal of the flip-flop CF1.

[0130] In a specific implementation, the first decomposition base judging circuit mainly judges the first decomposition base outputted by the Q terminal of the flip-flop CF1, that is, judges the least significant bit of the first decomposition base outputted by the flip-flop CF1. When the least significant bit of the first decomposition base is 0, the output terminal of the AND gate circuit AND1 is 0, and the data buffered in the data buffer RAM1 is 0. At this time, the data loaded to the CE terminal of the flip-flop CF1 is invalid, that is, will not affect the work of the flip-flop CF1. When the least significant bit of the first decomposition base is 1, the output terminal of the AND gate circuit AND1 is 1, and the data buffered in the data buffer RAM1 is 1. At this time, the data loaded to the CE terminal of the flip-flop CF1 is valid, and will keep the output of the Q terminal of the flip-flop CF1. After that, the Q terminal of the flip-flop CF1 keeps unchanged.

[0131] As can be seen from the above description, when the least significant bit of the first decomposition base is 0, it indicates that the first decomposition base is not 1; when the least significant bit of the first decomposition base is 1, it indicates that the first decomposition base is 1. At this time, the first decomposition base cannot be continuously updated, that is, the data decomposition termination condition is reached.

[0132] As can be seen from the above description, after the PRE pre-trigger terminal of the flip-flop CF1 is triggered valid, the working state of the flip-flop CF1 is irrelevant to the PRE pre-trigger terminal, that is, the flip-flop CF1 is relevant to the clock signal clk1 of the C terminal, the updated first decomposition base of the D terminal and the input of the CE terminal in the subsequent work. The corresponding working process of the first decomposition base generating circuit is described in detail below.

[0133] In an embodiment of the present application, the subtracter subtracts the target data from the first reference number to generate a data state judging base. When the update control signal is valid, the data state judging base is loaded to the CLR clear terminal of the flip-flop CF1 through the multiplexer MUX1, and the data state judging base is loaded to the PRE pre-trigger terminal of the flip-flop CF1 through the multiplexer MUX2, so as to realize the triggering of the PRE trigger terminal of the flip-flop CF1.

[0134] It can be understood that the rhythm of the first decomposition base update can be controlled by the clock signal clk1, when the lowest bit of the data state judgment base is 0, the data state judgment base at the PRE pre-trigger end can be transmitted to the Q end of the flip-flop CF1 through the flip-flop CF1, and then the first decomposition base output from the Q end of the flip-flop CF1 is right-shifted by using the data splitting right shift circuit; at the same time, the lowest bit of the current first decomposition base is judged by using the first decomposition base judgment circuit. When the lowest bit of the first decomposition base is not 1, the next clock signal clk1 is waited.

[0135] When the second clock signal clk1 is valid, the data at the D end of the flip-flop CF1 is transmitted to the Q end of the flip-flop CF1, and then the first decomposition base output from the Q end of the flip-flop CF1 is right-shifted by using the data splitting right shift circuit; at the same time, the lowest bit of the current first decomposition base is judged by using the first decomposition base judgment circuit. When the lowest bit of the first decomposition base is not 1, the next clock signal clk1 is waited.

[0136] It can be understood that, in the data splitting, the above process is repeated by the clock signal clk1 until the lowest bit of the first decomposition base is 1, so as to realize the splitting of the target data. Figure 2 In the formula, r is the first decomposition base output from the Q end of the flip-flop CF1.

[0137] In an embodiment of the present application, the second decomposition base generation circuit at least includes an adder and a flip-flop CF2, wherein,

[0138] The first input end of the adder is connected with the Q end of the flip-flop CF2, and the second input end of the adder is connected with the second reference number.

[0139] The CLR clear end of the flip-flop CF2 is connected with the update control signal, the C end of the flip-flop CF2 is connected with the clock signal clk1, and the CE end of the flip-flop CF2 is connected with the output end of the first decomposition base judgment circuit.

[0140] Figure 2 An embodiment of the second decomposition base generation circuit is shown in the formula, wherein ADD1 is an adder, and CF2 is a flip-flop CF2. The flip-flop CF2 can adopt the same type as the flip-flop CF1, and the difference is that the PRE pre-trigger end of the flip-flop CF1 can be omitted compared with the flip-flop CF1. At this time, the clear mode of the CLR clear end of the flip-flop CF2 is different from that of the flip-flop CF1, when the level of the CLR clear end of the flip-flop CF2 is low, the flip-flop CF2 performs the clear operation, and the other working principles are similar to those of the flip-flop CF2. The working principle of the flip-flop CF2 can be referred to the above description of the flip-flop CF1, Figure 2In the embodiment, u is the second decomposition base number outputted from the Q terminal of the flip-flop CF2. In addition, Figure 2 The second reference number is 1, that is, the second decomposition base number is updated, and the add operation is performed each time.

[0141] The CE terminal of the flip-flop CF2 is connected with the output terminal of the first decomposition base number judging circuit, that is, the second decomposition base number generating circuit is connected with the first decomposition base number generating circuit. In order to realize the connection with the flip-flop CF2, Figure 2 In the embodiment, the first decomposition base number judging circuit further comprises a data buffer RAM2, the output terminal of the data buffer RAM2 is connected with the output terminal of the AND gate circuit AND1, and the output terminal of the data buffer RAM2 is connected with the CE terminal of the flip-flop CF2. It can be understood that the CE terminal of the flip-flop CF2 can also be directly connected with the output terminal of the data buffer RAM1 in the specific implementation.

[0142] It can be known from the above description that the flip-flop CF2 will not be cleared when the update control signal is effective at the high level. When the second decomposition base number generating circuit works, the adder will perform the addition operation on the Q terminal output of the flip-flop CF2 and the second reference number, and load the generated addition operation result data to the D terminal of the flip-flop CF2.

[0143] When the first clock signal clk1 is effective, the output terminal of the adder is 1, and the flip-flop CF2 will output the data of D. At this time, the second decomposition base number obtained from the Q terminal of the flip-flop CF2 is 1. Thereafter, the adder will add the second decomposition base number and the second reference number, and the output of the adder is 2. When the second clock signal clk1 is effective, the data output of the adder is loaded to the D terminal of the flip-flop CF2. It can be known that the second decomposition base number of the Q terminal of the flip-flop CF2 at this time should be 2.

[0144] When the update control signal is effective, and the first decomposition base number judging circuit judges that the lowest bit of the first decomposition base number is not 1, the above-mentioned addition update operation is continued until the first decomposition base number judging circuit judges that the lowest bit of the first decomposition base number is 1, and the second decomposition base number outputted from the Q terminal of the flip-flop CF2 is kept. It can be understood that the corresponding cyclic update of the first decomposition base number generating circuit and the second decomposition base number generating circuit is controlled by the clock signal clk1. Therefore, when the generated first decomposition base number is updated, the second decomposition base number is also updated.

[0145] Figure 3 In addition, the above-mentioned embodiment shows the data splitting hardware unit, and it can be understood that the data splitting hardware unit can also adopt other hardware circuit forms. The specific implementation is subject to the condition that the target data can be split and the corresponding first decomposition base number and second decomposition base number can be generated. Here, the specific implementation is not illustrated one by one.

[0146] In one embodiment of the present application, the modular exponentiation hardware unit comprises a fast power hardware circuit and a modulo hardware circuit connected in series with the fast power hardware circuit, wherein,

[0147] In one round of the Miller-Rabin algorithm, the first modular exponentiation and the second modular exponentiation are executed by the modular exponentiation hardware unit in sequence.

[0148] In the execution of the first modular exponentiation, the first decomposition base is taken as the target exponent, the fast power hardware circuit executes the power operation on the target base and the target exponent to generate the first fast power operation result, and then the modulo hardware circuit executes the modulo operation on the first fast power operation result to generate the first modular exponentiation result value.

[0149] In the execution of the second modular exponentiation, the first modular exponentiation result value is taken as the target base, the fast power hardware circuit executes the power operation on the target base and the target exponent to generate the second fast power operation result, and then the modulo hardware circuit executes the modulo operation on the second fast power operation result to generate the second modular exponentiation result value.

[0150] Figure 4 An embodiment of the modular exponentiation hardware unit of the present application is shown in FIG. 1. In the figure, the modular exponentiation hardware unit comprises a fast power hardware circuit and a modulo hardware circuit connected in series, wherein the fast power hardware circuit can implement the power operation and the modulo hardware circuit can implement the modulo operation, i.e. in the modular exponentiation process, the power operation is performed first and then the modulo operation is performed.

[0151] As can be seen from the above description, in one round of the Miller-Rabin algorithm, the first modular exponentiation and the second modular exponentiation exist, wherein the first modular exponentiation should be performed first and then the second modular exponentiation is performed. As can be seen from the above description, before the second modular exponentiation is performed, the logic judgment unit should perform the logic judgment on the first modular exponentiation result value generated after the first modular exponentiation.

[0152] The first decomposition base generated by the above data splitting circuit should be loaded into the fast power hardware circuit and taken as the target exponent of the fast power hardware circuit, and then the fast power hardware circuit can execute the power operation on the target base and the target exponent to generate the first fast power operation result. After the first fast power operation result is generated, the modulo hardware circuit should execute the modulo operation on the first fast power operation result to generate the first modular exponentiation result value. As can be seen from the above description, when the modulo hardware circuit executes the modulo operation on the first fast power operation result, the operation of 1(mod p) is mainly performed, and the modulo hardware circuit can adopt the existing common hardware circuit, which is specifically subject to the condition of being able to implement the modulo operation.

[0153] Further, when performing the second modular exponentiation, the first modular exponentiation result value is taken as a target base number, and the target base number and a target exponent number are subjected to the exponentiation by the fast power hardware circuit to generate a second fast modular exponentiation result, and then the second fast modular exponentiation result is subjected to the modulo operation by the modulo hardware circuit to generate the second modular exponentiation result value.

[0154] As can be seen from the above description, when generating the modular exponentiation object data based on the decomposition array, the target exponent number for the first modular exponentiation is generated by the first decomposition base, and the first modular exponentiation result value is taken as the target base number for the second modular exponentiation.

[0155] In an embodiment of the present application, the fast power hardware circuit comprises an exponent number processing circuit and a base number operation circuit connected to the exponent number processing circuit.

[0156] The exponent number processing circuit receives at least the target exponent number and processes the target exponent number, wherein the processing of the target exponent number at least comprises state judgment processing and exponent number right shift updating processing.

[0157] After the state judgment processing of the least significant bit data of the target exponent number, a base number operation first control signal corresponding to the least significant bit data of the target exponent number is generated, and the exponent number right shift updating processing is performed only when the state judgment of the least significant bit data of the target exponent number is 0.

[0158] When the exponent number right shift updating processing is performed, the target exponent number is right shifted by one bit to update the target exponent number, and a base number operation second control signal corresponding to the updated target exponent number is generated.

[0159] When the state judgment processing of the least significant bit data of the updated target exponent number is determined to be 1, the exponent number processing circuit stops processing the target exponent number.

[0160] The base number operation circuit receives at least the target base number and controls the base number multiplication operation of the target base number based on the base number operation first control signal and the base number operation second control signal to generate the corresponding fast power operation result after the base number multiplication operation.

[0161] The base number multiplication operation of the target base number at least comprises base number squaring operation and base number multiplication operation.

[0162] When the exponent number processing circuit stops processing the target exponent number, the generated fast power operation result is outputted.

[0163] As can be seen from the above description, the fast power hardware circuit mainly calculates the value of the target base number under the target exponent number. For example, when the target base number is base and the target exponent number is exponent, the fast power hardware circuit calculates base exponentCorresponding values, therefore, for the fast power hardware circuit, at least need to obtain the target exponent and the target base when performing power operation.

[0164] In implementation, the fast power hardware circuit can include an exponent processing circuit and a base operation circuit, wherein the exponent processing circuit at least receives the target exponent, and the base operation circuit at least receives the target base. The exponent processing circuit at least performs state judgment processing and exponent right shift update processing on the received target exponent. As described above, in the first modular exponentiation operation, the first decomposition base is the target exponent, at this time, the first decomposition base as the target exponent is subjected to state judgment processing and exponent right shift update processing respectively. In the second modular exponentiation operation, 2 can be taken as the target exponent, at this time, the target exponent can be subjected to state judgment processing and exponent right shift update processing. The base operation circuit is mainly used for operation on the base. It needs to be noted that in the first modular exponentiation operation, the target base can be selected as needed; in the second modular exponentiation operation, the result of the first modular exponentiation operation is taken as the target base.

[0165] It needs to be noted that in the execution of the fast power operation, based on the above description, the target exponent is greater than 0, therefore, in the state judgment processing of the target exponent, it is mainly to perform state judgment processing on the least significant bit data of the target exponent. For example, when the target exponent is 2, the corresponding binary is 10, the least significant bit of the target exponent is "0", in the state judgment processing, it is to judge whether the least significant bit of the target data is "0" or "1", only when the least significant bit data of the target exponent is judged as 0, the exponent right shift update processing is performed, wherein the least significant bit data of the target exponent is judged as 0, which specifically means that after the state judgment processing, it is determined that the least significant bit data is 0.

[0166] Specifically, in the execution of the exponent right shift update processing, the target exponent should be right shifted by one bit to update the target exponent, and generate the base operation second control signal corresponding to the updated target exponent. For example, when the target exponent is 2, after right shifting by one bit, the target exponent is updated to 01, and the base operation second control signal is generated based on the target exponent of 01. In addition, when the least significant bit data of the updated target exponent is determined as 1 after the state judgment processing, the exponent processing circuit stops processing the target exponent, which specifically means that the exponent processing circuit completes the processing of the target exponent.

[0167] The base number operation circuit receives at least a target base number, and controls to perform a base number multiplication operation on the target base number based on a base number operation first control signal and a base number operation second control signal, so as to generate a corresponding fast power operation result after performing the base number multiplication operation. Specifically, the base number multiplication operation performed on the target base number at least includes a base number squaring operation and a base number multiplication operation. When the exponent processing circuit stops processing the target exponent, the generated fast power operation result is outputted, and the fast power operation result is outputted, that is, one fast power operation is completed. It can be understood that during the processing of the exponent by the exponent processing circuit, the base number operation circuit will cyclically perform the base number multiplication operation on the target base number, so as to meet the demand of the fast power operation.

[0168] In an embodiment of the present application, the exponent processing circuit comprises a state judgment circuit, an exponent right shift operation circuit and a D flip-flop D5, wherein,

[0169] The target exponent is loaded to a first input terminal of the state judgment circuit, the state judgment circuit is connected with the D flip-flop D5 through the exponent right shift operation circuit, and a Q terminal of the D flip-flop D5 is feedback connected to the first input terminal of the state judgment circuit.

[0170] The state judgment circuit performs state judgment processing on the lowest bit data of the target exponent, and generates a base number operation first control signal through an output terminal of the state judgment circuit;

[0171] The exponent right shift operation circuit performs an exponent right shift update processing on the base number operation first control signal, and generates a base number operation second control signal, and loads the updated target exponent to a D terminal of the D flip-flop D5.

[0172] A clock terminal of the D flip-flop D5 is connected with a clock signal clk2, so as to feedback the updated target exponent to the first input terminal of the state judgment circuit under the clock signal clk2.

[0173] Specifically, the exponent processing circuit can comprise a state judgment circuit, an exponent right shift operation circuit and a D flip-flop D5, Figure 4 An embodiment of the exponent processing circuit is shown in FIG. 2, wherein an embodiment of the state judgment circuit can adopt an AND gate circuit AND2, SF2 is the exponent right shift operation circuit, and the exponent right shift operation circuit can perform a right shift operation by one bit. When the state judgment circuit adopts the AND gate circuit AND2, the exponent processing circuit should also receive a third reference number, at this time, two input terminals of the AND gate circuit AND2 form a first input terminal and a second input terminal of the state judgment circuit, Figure 4 In FIG. 2, the third reference number can be 1, the third reference number and the target exponent are loaded to the input terminals of the AND gate circuit AND2, and the exponent is the target exponent.

[0174] The third reference number is used to perform a bit-by-bit AND operation with the lowest bit data of the target base number by using an AND gate circuit AND2, so as to realize the state judgment of the lowest bit data of the target base number. When the state judgment circuit uses the AND gate circuit AND2, the output end of the AND gate circuit AND2 generates the base operation first control signal. When the target base number is 10, the lowest bit data of the target base number is subjected to the bit-by-bit AND operation with the third reference number, and the result generated after the bit-by-bit AND operation is 10, so that the base operation first control signal can be 10. When the target base number is 01, the result generated after the bit-by-bit AND operation is 01, so that the base operation first control signal can be 01. When the target base number is in other cases, the state of the base operation control signal generated by the state judgment circuit can be referred to the description herein, and will not be exemplified one by one.

[0175] As can be known from the above description, after the base operation first control signal is generated, the base operation first control signal can be subjected to a base number right shift update operation by using a base number right shift operation circuit, and a corresponding base operation second control signal is generated. When the base operation first control signal is 10, the base operation second control signal of 01 can be obtained after the base number right shift operation circuit. When the base operation first control signal is 01, the base operation second control signal of 00 can be obtained after the base number right shift operation circuit. The right shift operation of the base number right shift operation circuit on the base operation first control signal can be referred to the description herein, and will not be exemplified one by one.

[0176] In specific implementation, the base operation second control signal is loaded to the D end of the D flip-flop D5, the clock end of the D flip-flop D5 receives the clock signal clk2, and when the clock signal clk2 is valid, the current base operation second control signal can be fed back to the first input end of the state judgment circuit through the Q end of the D flip-flop D5. At this time, the base operation second control signal is fed back to the first input end of the state judgment circuit as the updated target base number.

[0177] After the updated target base number is fed back to the first input end of the state judgment circuit, the above-mentioned state judgment process and the base number right shift operation update process are repeated until the state of the lowest bit data of the updated target base number is 1.

[0178] In an embodiment of the present application, the base operation circuit comprises a first multiplier, a second multiplier, a fourth multiplexer, a fifth multiplexer, a D flip-flop D6 and a D flip-flop D7, wherein,

[0179] The output end of the first multiplier is connected with the first input end of the fourth multiplexer, the first input end of the first multiplier receives a first intermediate number, and the second input end of the first multiplier is connected with the output end of the D flip-flop D7;

[0180] The second input end of the fourth multiplexer receives the first intermediate number, the selection control end of the fourth multiplexer receives the first base operation control signal, and the output end of the fourth multiplexer is connected with the second input end of the fifth multiplexer and the D end of the D flip-flop D6, and the output end of the D flip-flop D6 is connected with the first input end of the first multiplier;

[0181] The first input end of the fifth multiplexer receives the third preset constant, the selection control end of the fifth multiplexer receives the second base operation control signal, the clock end of the D flip-flop D6 and the clock end of the D flip-flop D7 receive the clock signal clk2;

[0182] The D end of the D flip-flop D7 is connected with the output end of the second multiplier, the first input end of the second multiplier is connected, the second input end receives the target base, and the output end of the D flip-flop D7 is also simultaneously fed back to the first input end of the second multiplier and the second input end of the second multiplier;

[0183] The output end of the fifth multiplexer is the output end of the fast power hardware circuit.

[0184] Figure 4 An embodiment of the base operation circuit is shown in the figure, in which MU1 is the first multiplier, MU2 is the second multiplier, MX4 is the fourth multiplexer, MX5 is the fifth multiplexer, D6 is the D flip-flop D6, and D7 is the D flip-flop D7. In the figure, res is the first intermediate number, the first intermediate constant res can be 1 at the initial time, 0 loaded into the first input end of the fifth multiplexer is the third preset constant, and base is the target base.

[0185] To ​ The first intermediate number res and the target base are multiplied by using the first multiplier to form the first product value, and the first product value is loaded into the first input end of the fourth multiplexer, and the expression of the first product value can be res*base, when the base operation circuit is initially operated, and meanwhile, the square of the target base is calculated by using the second multiplier, and the square value of the target base is loaded into the D end of the D flip-flop D7, and the expression of the square value of the target base is base 2 .

[0186] When the state of the lowest bit data of the target exponent is determined to be 1 by the state judgment circuit, the first input end of the fourth multiplexer is selected to output, that is, the first product value is selected to output, that is, when the lowest bit data of the base first control signal is 1, the corresponding data of the first input end of the fourth multiplexer is selected to output, and when the lowest bit data of the base first control signal is 0, the corresponding data of the second input end of the fourth multiplexer is selected to output.

[0187] For the second control signal of the base operation, if the value corresponding to the second control signal of the base operation is less than or equal to 0, the data at the second input terminal of the fifth multiplexer will be selected and output; otherwise, the data at the first input terminal of the fifth multiplexer will be selected and output.

[0188] If the target exponent is 2, the generated base operation first control signal is 10. The first intermediate number res, loaded onto the second input of the fourth multiplexer, will be selected as the output. The first intermediate number res will also be loaded onto the second input of the fifth multiplexer and the D terminal of the D flip-flop D6. Simultaneously, the base operation second control signal generated by the right-shift exponentiation circuit from the first base operation control signal should be 01. Since the second base operation second control signal is not less than 0, the output value of the fifth multiplexer will be the third preset constant, which is 0.

[0189] When the first clock signal clk2 is valid, the second control signal for base operation is used as the updated target exponent and fed back to the first input of the state judgment circuit via D flip-flop D5. Simultaneously, the target base square value is transmitted to the Q input of D flip-flop D7 and loaded onto the second input of the first multiplier, the first input of the first multiplier, and the second input of the first multiplier. At this point, the first product value obtainable by the first multiplier is res*base. 2 The second product value obtained by the second multiplier can be the base. 4 Then the data loaded into the first input of the fourth multiplexer is the first product value res*base. 2 The data loaded to the second input of the fourth multiplexer is the first intermediate number res, and the data loaded to the D input of the D flip-flop D7 is base. 4 .

[0190] As explained above, the updated target exponent should be 0 or 1. After the state judgment circuit processes the state of the least significant bit of the current target exponent, the least significant bit of the generated base first control signal should be 1. Therefore, the first product value loaded onto the second input of the fourth multiplexer is res*base. 2 By selecting the output, we can deduce that the data loaded into the second input of the fifth multiplexer is res*base. 2 The data loaded into the D terminal of D flip-flop D6 is also res*base. 2 .

[0191] When the first control signal for base operation is 01, the second control signal for base operation generated by the right shift exponentiation circuit should be 00. At this time, the second control signal for base operation is 0. Therefore, the second input of the fifth multiplexer is selected as the output, i.e., res*base. 2Since res is 1, the data output by the fifth multiplexer is base 2 As can be seen from the above description, when the lowest bit data of the updated target exponent is determined as 1 after the state judgment processing, the exponent processing circuit stops processing the target exponent, that is, the base 2 output by the fifth multiplexer is the fast power operation result output by the fast power hardware circuit.

[0192] When the target exponent is other values, the mode and process of performing fast power operation on the target base by the fast power hardware circuit can refer to the corresponding description above, which will not be repeated here. It should be noted that the clock signal clk2 and the clock signal clk1 can be generated by the same clock source, and the timing between the clock signal clk1 and the clock signal clk2 should meet the specific working requirements of the data splitting hardware unit and the fast power hardware circuit, and can accelerate the operation of the Miller-Rabin algorithm.

[0193] As can be seen from the above description, a Miller-Rabin algorithm acceleration device based on software and hardware fusion is obtained. In an embodiment of the present application, the Miller-Rabin algorithm acceleration device comprises:

[0194] The data splitting hardware unit splits the target data and generates a decomposition array matching the target data after data splitting, wherein the decomposition array at least includes a first decomposition base and a second decomposition base;

[0195] The modular exponentiation hardware unit performs modular exponentiation on the modular exponentiation object data generated based on the decomposition array, wherein when the Miller-Rabin algorithm is executed, the modular exponentiation performed by the modular exponentiation hardware unit at least includes a first modular exponentiation and a second modular exponentiation in a round of judgment, a first modular exponentiation result value is generated after the first modular exponentiation is executed, and a second modular exponentiation result value is generated after the second modular exponentiation is executed;

[0196] The algorithm execution control unit logically judges the first modular exponentiation result value and the second modular exponentiation result value, and generates a data verification state corresponding to the target data based on the corresponding logical judgment state of the first modular exponentiation result value and the second modular exponentiation result value, wherein the data verification state includes that the target data is a prime number or the target data is a composite number.

[0197] Specifically, the corresponding conditions of the data splitting hardware unit and the modular exponentiation hardware unit, and the process of performing data splitting and modular exponentiation can refer to the corresponding description above. It can be understood that the algorithm execution control unit is the hardware carrier of the logical judgment unit, the algorithm execution control unit can realize the logical judgment described above, and the algorithm execution control unit can be a commonly used computer or microprocessor, which specifically meets the logical judgment when the Miller-Rabin algorithm is running.

Claims

1. A method for accelerating the Miller-Rabin algorithm based on hardware and software integration, characterized in that, The acceleration methods for the Miller-Rabin algorithm include: At least a data splitting hardware unit for performing data splitting, a modular exponentiation hardware unit for performing modular exponentiation, and a logical judgment unit for performing logical judgments are configured, wherein, When executing the Miller-Rabin algorithm, the target data to be verified is loaded into the data splitting hardware unit to split the target data using the data splitting hardware unit, and a decomposition array matching the target data is generated after the data splitting. The decomposition array includes at least a first decomposition cardinality and a second decomposition cardinality. Based on the decomposition of arrays to generate modular exponentiation object data, modular exponentiation operation hardware unit is used to perform modular exponentiation operation on modular exponentiation object data. When executing Miller-Rabin algorithm, the modular exponentiation operation hardware unit performs at least the first modular exponentiation operation and the second modular exponentiation operation in one round of judgment. After executing the first modular exponentiation operation, the first modular exponentiation operation result value is generated. After executing the second modular exponentiation operation, the second modular exponentiation operation result value is generated. The logic judgment unit performs logical judgment on the result value of the first modular exponentiation operation and the result value of the second modular exponentiation operation, and generates a data verification state corresponding to the target data based on the corresponding logical judgment state of the result value of the first modular exponentiation operation and the result value of the second modular exponentiation operation. The data verification state includes whether the target data is a prime number or the target data is a composite number.

2. The Miller-Rabin algorithm acceleration method based on hardware and software integration according to claim 1, characterized in that: The data splitting hardware unit includes a first decomposition radix generation circuit and a second decomposition radix generation circuit, wherein... The first decomposition radix generation circuit and the second decomposition radix generation circuit are adapted and connected; The first decomposition base generation circuit receives the target data, calculates the data status information of the target data based on the first reference number, and generates the first decomposition base based on the target data, the first reference number, and the data status information of the target data, wherein the data status information of the target data includes whether the target data is odd or even. The second decomposition radix generation circuit receives the second reference number and generates the corresponding second decomposition radix based on the data status information, wherein the first reference number and the second reference number are mutually exclusive one-bit binary numbers; When executing the Miller-Rabin algorithm, the first decomposition cardinality and the second decomposition cardinality are updated cyclically based on the update control signal and the data state information of the target data until the data splitting termination condition is reached. When the first and second decomposition target bases are formed based on the updated first and second decomposition bases, respectively, then: p=2 r *u, p represents the target data, r represents the target cardinality for the first decomposition, and u represents the target cardinality for the second decomposition.

3. The Miller-Rabin algorithm acceleration method based on hardware and software integration according to claim 2, characterized in that, When executing the Miller-Rabin algorithm, the data is split into hardware units, then: The difference between the target data and the first reference number is used to generate the data state judgment base, where, When the data status judgment base is odd, the data status information of the target data is determined to be even. The first decomposition base output by the first decomposition base generation circuit is kept as the first preset constant, and the second decomposition base output by the second decomposition base generation circuit is kept as the second preset constant. When the data status judgment base is even, the data status information of the target data is judged to be odd, and the data status judgment base is used as the initial value for the first decomposition base generation circuit to update cyclically. When the first decomposition base generation circuit updates the first decomposition base based on the update control signal, the first decomposition base after each update is half of the current first decomposition base. Meanwhile, when the second decomposition base generation circuit updates the second decomposition base based on the update control signal, the current second decomposition base and the second reference number are accumulated, and the second decomposition base is updated to the accumulated value of the current second decomposition base and the second reference number.

4. The Miller-Rabin algorithm acceleration method based on hardware-software integration according to claim 3, characterized in that, The first decomposition radix generation circuit includes a data state judgment circuit and a first decomposition radix generation main circuit adapted and connected to the data state judgment circuit, wherein... The data status determination circuit includes at least a subtractor and a data status determination base transfer circuit. The subtractor simultaneously receives the target data and the first reference number, and uses the difference between the target data and the first reference number calculated by the subtractor as the data status determination base. The first reference number is 1. The data status judgment base transfer circuit transmits the data status judgment base to the first decomposition base generation main circuit under the update control signal; When the data status information of the target data is even, the first decomposition base generation main circuit will maintain the first decomposition base generated under the data status judgment base as the first preset constant; When the data status information of the target data is odd, the data status judgment base is loaded into the first decomposition base generation circuit under the update control signal, and the data status judgment base is used as the initial value of the first decomposition base. Thereafter, the first decomposition base generation main circuit cyclically updates the first decomposition base.

5. The Miller-Rabin algorithm acceleration method based on hardware-software integration according to claim 4, characterized in that, The first decomposition radix generation main circuit includes an initial value passing circuit, a flip-flop CF1, a data splitting right shift circuit, and a first decomposition radix determination circuit, wherein, The initial value transmission circuit receives the data state judgment base and, under the update control signal, transmits the data state judgment base to the PRE pre-trigger terminal of flip-flop CF1; The CLR clear terminal of flip-flop CF1 is connected to the output terminal of the data status judgment base transfer circuit; The Q terminal of flip-flop CF1 is connected to the data splitting right shift circuit and the first decomposition radix judgment circuit. The data splitting right shift circuit is connected to the D terminal of flip-flop CF1. The output of the first decomposition radix judgment circuit is connected to the CE terminal of flip-flop CF1. The C clock terminal of flip-flop CF1 receives the clock signal clk1. When the data status information of the target data is even, the data status judgment base loaded into the CLR clear terminal of the flip-flop CF1 is used to clear the flip-flop CF1, so that the Q output of the flip-flop CF1 is 0, which is a first preset constant. When the data status information of the target data is odd, the data status judgment base is passed to the PRE pre-trigger terminal of the flip-flop CF1 through the initial value transmission circuit, so as to serve as the initial value of the first decomposition base; The data splitting right shift circuit performs right shifting on the first decomposition base output by the Q terminal of flip-flop CF1, and updates the first decomposition base under the clock signal clk1; The first decomposition radix determination circuit is used to determine the least significant bit state of the current first decomposition radix, where the least significant bit state of the first decomposition radix is ​​either 0 or 1. When the least significant bit of the first decomposition base is 1, the first decomposition base output by the Q terminal of flip-flop CF1 is maintained, and the second decomposition base generation circuit stops updating the second decomposition base. When the least significant bit of the first decomposition base is 0, the second decomposition base generation circuit is configured to update the second decomposition base under the clock signal clk1.

6. The Miller-Rabin algorithm acceleration method based on hardware-software integration according to claim 4, characterized in that, The second decomposed radix generation circuit includes at least an adder and a flip-flop CF2, wherein, The first input of the adder is connected to the Q input of the flip-flop CF2, and the second input of the adder is connected to the second reference number. The CLR clearing terminal of flip-flop CF2 is connected to the update control signal, the C terminal of flip-flop CF2 is connected to the clock signal clk1, and the CE terminal of flip-flop CF2 is connected to the output terminal of the first decomposed base judgment circuit.

7. The Miller-Rabin algorithm acceleration method based on hardware-software fusion according to any one of claims 1 to 6, characterized in that, The modular exponentiation hardware unit includes a fast exponentiation hardware circuit and a modulo-taking hardware circuit connected in series with the fast exponentiation hardware circuit, wherein... In one round of judgment in the Miller-Rabin algorithm, the first modular exponentiation operation and the second modular exponentiation operation are executed sequentially using the modular exponentiation operation hardware unit; When performing the first modular exponentiation operation, the first decomposition base is used as the target power. The fast exponentiation hardware circuit performs exponentiation operation on the target base and the target power to generate the first fast exponentiation operation result. Then, the modulo operation is performed on the first fast exponentiation operation result by the modulo hardware circuit to generate the first modular exponentiation operation result value. When performing the second modular exponentiation, the result of the first modular exponentiation is used as the target base. The fast exponentiation hardware circuit performs exponentiation on the target base and the target exponent to generate the second fast modular exponentiation result. Then, the modulo-taking hardware circuit performs modulo-taking on the second fast exponentiation result to generate the second modular exponentiation result value.

8. The Miller-Rabin algorithm acceleration method based on hardware-software integration according to claim 7, characterized in that, The fast exponentiation hardware circuit includes an exponentiation processing circuit and a base calculation circuit adapted and connected to the exponentiation processing circuit, wherein... The power processing circuit receives at least the target power and processes the target power, wherein the processing of the target power includes at least state judgment processing and power right shift update processing. After performing state judgment processing on the least significant bit data of the target power, a first control signal for base operation corresponding to the least significant bit data of the target power is generated. The power right shift update processing is performed only when the state judgment of the least significant bit data of the target power is 0. When performing the right shift update process, the target exponent is shifted one bit to the right to update the target exponent, and a second control signal for base operation corresponding to the updated target exponent is generated; If the least significant bit of the updated target exponent is determined to be 1 after the state judgment process, the exponent processing circuit will stop processing the target exponent. The base arithmetic circuit receives at least the target base and, based on the first and second base arithmetic control signals, controls the execution of base multiplication on the target base to generate the corresponding fast exponentiation result after the base multiplication operation. The base multiplication operation performed on the target base includes at least the base squaring operation and the base multiplication operation; When the exponentiation processing circuit stops processing the target exponentiation, it outputs the generated fast exponentiation result.

9. The Miller-Rabin algorithm acceleration method based on hardware-software integration according to claim 8, characterized in that, The exponentiation processing circuit includes a state judgment circuit, a right-shift exponentiation operation circuit, and a D flip-flop D5, wherein... The target power is loaded onto the first input terminal of the state judgment circuit. The state judgment circuit is connected to the D terminal of the D flip-flop D5 through the power right shift operation circuit. The Q terminal of the D flip-flop D5 is fed back to the first input terminal of the state judgment circuit. The state judgment circuit performs state judgment processing on the least significant bit of the target exponent data, and generates the first control signal for base operation through the output of the state judgment circuit. The right-shift power operation circuit performs a right-shift power update process on the first control signal of the base operation, generates the second control signal of the base operation, and loads the updated target power into the D terminal of the D flip-flop D5. The clock input of D5, a D flip-flop, is connected to the clock signal clk, so that the updated target exponent is fed back to the first input of the state judgment circuit under the clock signal clk.

10. A Miller-Rabin algorithm acceleration device based on hardware and software integration, characterized in that, The Miller-Rabin algorithm acceleration device includes: A data splitting hardware unit splits target data and generates a decomposition array that matches the target data after splitting. The decomposition array includes at least a first decomposition base and a second decomposition base. The modular exponentiation hardware unit performs modular exponentiation on the modular exponentiation object data generated based on the decomposed array. When executing the Miller-Rabin algorithm, the modular exponentiation performed by the modular exponentiation hardware unit includes at least a first modular exponentiation and a second modular exponentiation in one round of judgment. After performing the first modular exponentiation, a first modular exponentiation result value is generated. After performing the second modular exponentiation, a second modular exponentiation result value is generated. The algorithm execution control unit performs logical judgments on the results of the first and second modular exponentiation operations, and generates a data verification state corresponding to the target data based on the corresponding logical judgment states of the first and second modular exponentiation results. The data verification state includes whether the target data is a prime number or a composite number.

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