Instruction processing method, readable storage medium, program product and electronic equipment

Abstract

The invention relates to the technical field of computers, in particular to an instruction processing method, a readable storage medium, a program product and electronic equipment. The instruction processing method is applied to the electronic equipment, by means of the instruction processing method, in a sequential execution assembly line, a current instruction is paused in an emission stage, and if a running unit executed by the instruction in an execution stage is different from a running unit of a current instruction running in the execution stage, the instruction is paused. And if the instruction has no dependency relationship with the instruction with the previous execution sequence, the current instruction can be transmitted to the corresponding operation unit for operation. Therefore, even if the assembly line is paused, the current instruction can continue to run, so that the delay of the assembly line is reduced, and the processing efficiency of the assembly line is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction processing method, a readable storage medium, a program product, and an electronic device. Background Art

[0002] Pipeline technology is an important method to improve processor performance. Based on pipeline technology, the instruction execution process can be divided into multiple stages, each stage is processed in parallel (that is, instructions are executed in each stage) and occupies at least one clock cycle on the pipeline. In other words, in one clock cycle, each stage of a pipeline can run simultaneously to reduce the waiting time for instruction execution, thereby reducing processor latency and improving processor efficiency and performance.

[0003] However, in some pipelines, if the clock cycle of the instruction on the older stage (the stage that is relatively close to the end of the pipeline) is longer, the instruction on the younger stage (the stage that is relatively close to the beginning of the pipeline) will be suspended, causing pipeline delay. If the clock cycle occupied by the younger instruction in the next stage is longer, the pipeline delay will be further increased, reducing the efficiency and performance of the processor. Summary of the invention

[0004] Embodiments of the present application provide an instruction processing method, a readable storage medium, a program product, and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides an instruction processing method, which is applied to an electronic device, and the method includes: detecting that a first instruction in a first pipeline is paused in a first pipeline stage; determining that the execution process of the first instruction does not depend on instructions that are executed before the first instruction in an order, the instructions before the first instruction include a second instruction, and the first instruction is executed in a first running unit in the second pipeline stage, wherein the second pipeline stage is the next stage of the first pipeline stage, and the second running unit where the second instruction currently running in the second pipeline stage is located is not the same running unit as the first running unit; sending the first instruction to the first running unit for execution.

[0006] Exemplarily, in some embodiments of the present application, the first pipeline is a sequentially executed pipeline, that is, the instructions need to be executed in sequence during the execution of the first pipeline. Therefore, if the second instruction in the previous execution order is in the second pipeline stage for a long time, the instruction in the first pipeline stage will be suspended. In an embodiment of the present application, if the first operation unit corresponding to the first instruction in the second pipeline stage is not the same operation unit as the second operation unit of the second instruction currently in the second pipeline stage, the first instruction can be sent to the first operation unit for execution after the first pipeline stage is completed. In this way, even if the first pipeline is suspended, it will not affect the operation of the first instruction in the first pipeline stage, thereby improving the processing efficiency of the first pipeline and reducing the delay of the first pipeline.

[0007] In a possible implementation of the first aspect, the first pipeline is a three-stage pipeline and includes the following pipeline stages: an instruction fetch stage, a decoding stage, and an execution stage; the first pipeline stage is the decoding stage, and the second pipeline stage is the execution stage.

[0008] In some embodiments of the present application, the electronic device can decode the instruction in the decoding stage to obtain the operand corresponding to the instruction. Therefore, the clock cycle occupied by the decoding stage is shorter, and in the execution stage, the operation unit in the electronic device operates the operand corresponding to the instruction according to the operation code of the instruction. Therefore, the execution stage may occupy a longer clock cycle. That is to say, after the first instruction in the decoding stage is completed, the second instruction in the execution stage may still be running, so that the first pipeline enters a pause and the first instruction cannot enter the execution stage. Therefore, in an embodiment of the present application, the electronic device can first send the first instruction to the first operation unit for execution. That is to say, the first instruction is still in the decoding stage, but it has been running in the first operation unit, so that the delay of the first pipeline can be reduced.

[0009] In a possible implementation of the first aspect, the above-mentioned detection that the first instruction in the first pipeline is paused in the first pipeline stage includes: detecting that the first instruction has completed execution in the first pipeline stage, and instructions whose execution order is before the first instruction are running.

[0010] Illustratively, in some embodiments of the present application, after the first instruction completes execution in the first pipeline stage, if any instruction in the execution order of the first instruction is currently being executed, the first instruction will enter the pause stage.

[0011] In a possible implementation of the first aspect, the first pipeline is a sequentially executed pipeline.

[0012] In a possible implementation of the first aspect above, the above-mentioned determination that the running process of the first instruction does not depend on the second instruction whose execution order is before the first instruction includes: obtaining a first address accessed by the first instruction, and a second address storing the operation result of the second instruction; corresponding to the mismatch between the first address and the second address, determining that the running process of the first instruction does not depend on the second instruction whose execution order is before the first instruction.

[0013] For example, in some embodiments of the present application, if the first instruction is suspended, before sending the first instruction to the first execution unit, it is necessary to check whether there is a dependency relationship between the first instruction and the instruction in the previous execution order. For example, in the decoding stage, the electronic device can obtain the storage address that each instruction needs to access. If the first address that the first instruction needs to access is not the same as the second address used by the instruction in the previous execution order to store the operation result, it can be determined that the first instruction has no dependency relationship with the instruction in the previous execution order.

[0014] In other embodiments, the electronic device may further detect whether the first instruction depends on the execution result of the instruction preceding the execution order during the execution process. If the execution process of the first instruction does not require the execution result of the instruction preceding the execution order, it may be determined that there is no dependency between the first instruction and the instruction preceding the execution order.

[0015] In a possible implementation of the first aspect above, the first instruction includes a first instruction code, which indicates that the first instruction enters the first running unit in the second pipeline stage to run, and the second instruction includes a second instruction code, which indicates that the second instruction enters the second running unit in the second pipeline stage to run; a method for determining that the second running unit where the second instruction currently running in the second pipeline stage is located is not the same running unit as the first running unit includes: based on the first instruction code and the second instruction code, determining that the second running unit is not the same running unit as the first running unit.

[0016] In some embodiments of the present application, during the decoding stage of each instruction, the electronic device can obtain the operation code of each instruction, and the first operating unit indicated by the operation code of the first instruction and the second operating unit indicated by the operation code of the second instruction are not the same operating unit, so it can be determined that the second operating unit is not the same operating unit as the first operating unit.

[0017] In a possible implementation of the first aspect, the first instruction is a load instruction or a store instruction, the second instruction is an arithmetic logic instruction, the first execution unit is a load or store unit, and the second execution unit is an arithmetic logic unit.

[0018] In a second aspect, the present application provides an electronic device, comprising: a memory for storing instructions; and at least one processor for executing instructions so that the device implements the first aspect and any possible implementation method of the first aspect. The beneficial effects that can be achieved in the second aspect can refer to the beneficial effects of the method provided in any implementation of the first aspect, and will not be repeated here.

[0019] In a third aspect, the present application provides a computer-readable storage medium, in which instructions are stored, and when the instructions are executed by a device, the computer implements the method provided in the first aspect and any possible implementation of the first aspect. The beneficial effects that can be achieved in the third aspect can refer to the beneficial effects of the method provided in any implementation of the first aspect, and will not be repeated here.

[0020] In a fourth aspect, the present application provides a computer program product, which, when running on a device, enables the device to implement the method provided in the first aspect and any possible implementation of the first aspect. The beneficial effects that can be achieved in the fourth aspect can refer to the beneficial effects of the method provided in any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram showing an electronic device entering a screen-on state is shown;

[0022] Figure 2 The operation process of a three-stage pipeline is shown;

[0023] Figure 3 According to some embodiments of the present application, a schematic diagram of a micro-architecture of a processor is shown;

[0024] Figure 4 According to some embodiments of the present application, a flowchart of an implementation of an instruction processing method is shown;

[0025] Figure 5 According to some embodiments of the present application, a process of executing an instruction in a three-stage pipeline is shown;

[0026] Figure 6 According to some embodiments of the present application, a schematic diagram of another execution process of a three-stage pipeline is shown;

[0027] Figure 7 According to some embodiments of the present application, a schematic structural diagram of an electronic device 100 is shown. DETAILED DESCRIPTION

[0028] The illustrative embodiments of the present application include, but are not limited to, a data processing method, a readable storage medium, a program product, and an electronic device.

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0030] As shown in the background art, if an instruction on a younger stage is paused (cannot continue to run), and the instruction takes a longer clock cycle to run in the next stage, the pipeline delay will increase, reducing the efficiency and performance of the processor.

[0031] To facilitate understanding, some of the terms and related technologies involved in this application are explained below.

[0032] 1. Pipeline

[0033] Processors can usually be divided into three-stage pipelines and five-stage pipelines according to their designs and structures. Among them, the three-stage pipeline can divide the execution process of instructions into stages such as instruction fetch (IF), decoding (ID), and execution (EX). Each stage has a dedicated hardware unit to handle it. When an instruction enters the pipeline, its different stages will occupy different hardware units in turn to form a pipeline process. Therefore, in the same clock cycle, a three-stage pipeline can execute three instructions at the same time. Therefore, by processing each stage of the instruction in parallel, the pipeline of the processor (such as the central processing unit (CPU)) can complete more computing tasks in the same clock cycle, thereby improving computing efficiency.

[0034] 2. Cache

[0035] Cache refers to a storage device that can exchange data at high speed. It exchanges data with the processor before the main memory does, so the speed is very fast. The setting of cache is one of the important factors for the high performance of computer systems.

[0036] Cache is based on the principle of program locality, that is, when a program is executed, it often accesses certain data or instructions repeatedly. By storing this data or instruction in the cache, the processor's access speed can be accelerated, the number of memory accesses can be reduced, and the system performance can be improved.

[0037] In computer systems, caches are usually divided into multiple levels to provide different levels of performance optimization. Common cache hierarchies include:

[0038] Level 1 cache (L1 cache): The cache closest to the processor, usually divided into two parts: data cache and instruction cache. L1 cache has very fast access speed but relatively small capacity.

[0039] Second level cache (L2 cache): Slightly larger than L1 cache and slightly slower to access, but still much faster than RAM. L2 cache is usually integrated into the CPU or located on a separate chip.

[0040] Level 3 cache (L3 cache): has a larger capacity and a relatively slower access speed, but is still faster than RAM. L3 cache is often used in multi-core CPUs to improve the efficiency of data exchange between multi-core processors in a shared cache manner.

[0041] For example, the access speeds of the L1 cache, L2 cache, and L3 cache decrease in sequence, but their capacities increase in sequence. When the processor needs to read data, it will first look in the L1 cache, then in the L2 cache, and finally in the L3 cache. If the data exists in any of the first-level caches (i.e., a cache hit), the processor can read the data directly from the cache without accessing the memory. This can significantly increase the speed of data reading.

[0042] However, if the data is not in the cache (i.e., a cache miss), the processor needs to access the memory to read the data. The access speed of the memory is relatively slow, so this will increase the waiting time of the processor.

[0043] Since the access speed in L1 cache is the fastest, if the processor misses in L1 cache, it needs to search for data in L2 cache, which increases the clock cycle of processor access data. Similarly, if there is a miss in L2 cache, the processor can continue to access data in the next level of cache until the data is accessed from memory.

[0044] 3. Load instruction (load) / store instruction (store)

[0045] The load instruction may include the following stages in a three-stage pipeline:

[0046] Instruction Fetch (IF): The processor reads the address of the instruction to be executed from the program counter and stores it in the instruction register. At the same time, the program counter is updated with the address of the next instruction.

[0047] Decoding stage (ID): The decoder in the processor can obtain instructions from the instruction register, decode the instructions, and identify relevant information of the instructions.

[0048] For load instructions / store instructions, these related information may include, for example, an opcode (such as "load" or "store"), a source register address (for a load instruction, it may be a memory address where data is stored; for a store instruction, it may be a register address where data is to be stored), a target register address (for a load instruction, it is the register address where data is to be stored after loading), etc.

[0049] The decoder of the processor sends the relevant information of the load instruction or the store instruction to the instruction queue, and the transmitter module in the processor selects the instruction from the instruction queue and sends it to the load store unit (LSU) for execution.

[0050] Execution stage (EX): For load instructions (such as the "load" instruction), the task of the execution stage is to read data from the specified memory address and store the data in the target register. This usually involves the following steps:

[0051] Memory access: The LSU can access the memory (or data cache) to read the required data based on the memory address determined in the decoding stage. It can be understood that the processor's LSU can access the cache first, thereby increasing the speed of obtaining data. If the required data is not in the cache (i.e., a cache miss), the processor's LSU needs to access the memory to read the data. The access speed of the memory is relatively slow, so this will increase the waiting time of the processor.

[0052] Data reading: After reading data from the memory, the data will be temporarily stored somewhere inside the processor for subsequent processing.

[0053] Data storage: Finally, the read data is stored in the destination register for use by subsequent instructions.

[0054] For storage instructions (such as the "store" instruction), the task of the execution stage is to store the data in the register to the specified memory address. This also involves several key steps:

[0055] Data preparation: Before the execution phase begins, the data in the source registers should have been prepared and stored somewhere inside the processor.

[0056] Memory access: Based on the memory address determined in the decoding stage, the store instruction accesses the main memory (or data cache) to prepare for storing data.

[0057] Data storage: Write the data in the source register to the specified memory address. This usually involves transferring the data from within the processor to the main memory (or data cache).

[0058] 4. Load and Store Unit (LSU)

[0059] The LSU is a dedicated execution unit in the processor that is responsible for executing all load and store instructions. These instructions are usually used to load data from memory or store data back to memory. The LSU generates virtual addresses for load and store operations and completes the execution of these instructions through a series of complex operations (such as address calculation, address translation, data access, etc.).

[0060] When a load instruction is recognized by the processor and is ready to be executed, it will proceed step by step in the order of the pipeline. In the issue stage, the instruction is sent to the preparation queue of the corresponding operation unit to wait for execution. However, for the load instruction, its actual execution involves reading data, which is usually the responsibility of the LSU.

[0061] The following describes the process of loading data into an electronic device.

[0062] For example, Figure 1 A schematic diagram of an electronic device entering a screen-on state is shown.

[0063] It should be noted that the electronic device in the embodiment of the present application can also be referred to as a terminal (termina1), a user terminal, a mobile terminal, a user equipment (UE), a terminal device, a mobile station, a mobile terminal (mobile terminal, MT), etc. The terminal device can be a mobile phone, a smart TV, a wearable device, a tablet computer (Pad), a computer with a wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a terminal in industrial control (industrial control), a terminal in self-driving (self driving), a terminal in a smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a terminal in a smart city (smart city), a terminal in a smart home (smart home), and other terminal devices. The following will be explained by taking a mobile phone as an example. However, it can be understood that the technical solution described in the present application is applicable to the above-mentioned various electronic devices based on pipeline processing instructions, not limited to mobile phones.

[0064] Exemplarily, the process of the processor of the electronic device 100 executing the loading instruction is introduced below by taking the electronic device 100 waking up the display screen as an example.

[0065] like Figure 1As shown, after the electronic device 100 detects the operation of waking up the display screen, it enters the screen-on state, and then displays the desktop 10 and the icons of various applications on the desktop 10.

[0066] In this process, when the electronic device 100 needs to display an image interface, it needs to read data related to the image from the memory, which may include pixel information, color information, size information, etc. of the image.

[0067] Then, the processor of the electronic device 100 loads the data from the memory into the register or cache of the processor by executing the load instruction for subsequent processing and rendering.

[0068] The following describes the process of executing instructions by an electronic device, taking loading instructions as an example.

[0069] For example, Figure 2 The operation process of a three-stage pipeline is shown.

[0070] For example, Figure 2 As shown, the three-stage pipeline includes an instruction fetch stage (IF), a decode stage (ID), and an execute stage (EX), wherein a transmit stage (RF) transition is also included between the decode stage and the execute stage.

[0071] For example, a three-stage pipeline processes instruction Inst1, load instruction Load0, instruction Inst2, instruction Inst3 and instruction Inst4 in the order of instructions. Among them, instruction Inst1, instruction Inst2, instruction Inst3 and instruction Inst4 are non-load instructions, and the execution stage (EX) is run in the arithmetic logic unit (ALU), and the execution stage (EX) of the load instruction Load0 is run in the LSU. The ALU is mainly responsible for performing various arithmetic operations (such as addition, subtraction, multiplication, division, etc.) and logical operations (such as AND, OR, NOT, XOR, etc.) in the processor.

[0072] In the T0 clock cycle, the EX stage of the three-stage pipeline runs instruction Inst1, the ID stage runs the load instruction Load0, and the IF stage runs the instruction Inst2. In addition, there is no dependency between the load instruction Load0, instruction Inst1, instruction Inst2, instruction Inst3, and instruction Inst4 (for example, the execution process of an instruction does not require the execution results of other instructions).

[0073] It can be understood that in the T0 clock cycle of the three-stage pipeline, relative to the instruction Inst1, the load instruction Load0 and the instruction Inst2 are both younger instructions. That is, in the three-stage pipeline, the execution order of the instruction Inst1 is before the load instruction Load0 and the instruction Inst1, the instruction Inst1 is an older instruction, and the load instruction Load0 and the instruction Inst2 are younger instructions relative to the instruction Inst1. Similarly, the load instruction Load0 is an older instruction relative to the instruction Inst2, and the instruction Inst2 is a younger instruction relative to the load instruction Load0.

[0074] In some cases, the execution time of instruction Inst1 in the EX stage is relatively long and may occupy a long clock cycle. Therefore, if instruction 1 on the three-stage pipeline is executed in the EX stage, and the load instruction Load0 and the instruction Inst2 are executed in their respective stages, the load instruction Load0 and the instruction Inst2 will be suspended, that is, the load instruction Load0 and the instruction Inst2 enter the suspended state.

[0075] For example, refer to Figure 2 In the T0 clock cycle of the three-stage pipeline, the EX stage of instruction Inst1 is executed in the ALU, and the load instruction Load0 has prepared relevant data (such as operands and opcodes) in the ID stage, waiting for the launch module to launch the load instruction Load0 to the LSU unit for execution, and the instruction Inst2 also completes the corresponding operation in the instruction fetch stage. It can be understood that since the instruction Inst1 has not yet completed the operation in the ALU unit. In the T1 clock cycle, the instruction Inst1 continues to run in the EX stage, while the load instruction Load0 and the instruction Inst2 will be suspended, so the instruction execution pipeline will be delayed.

[0076] Continue to refer to Figure 2 In the clock cycle of Tn, instruction Inst1 completes execution in the EX stage and leaves the instruction execution pipeline. At this time, the loading instruction Load0 and instruction Inst2 can enter the next stage of the instruction execution pipeline. In the IF stage, the new instruction Inst3 is added. For example, in the clock cycle of Tn, the loading instruction Load0 enters the EX stage, the instruction Inst2 enters the ID stage, and the instruction Inst3 enters the IF stage. It can be understood that since instruction Inst1 takes n clock cycles in the EX stage, other instructions cannot run within n clock cycles, so the pipeline is delayed by n clock cycles.

[0077] In the Tn clock cycle of the three-stage pipeline, the load instruction Load0 runs in the EX stage, that is, the transmitting module transmits the load instruction Load0 to the LSU for execution. The LSU can search the L1 cache of the processor to see whether there is data that the load instruction Load0 needs to access. If the cache does not hit, the LSU can enter the L2 cache to continue to search for the data that the load instruction Load0 needs to access, but this will take a long clock cycle to access the data corresponding to the load instruction Load0. If the LSU still misses in the L2 cache, it needs to find the data from the next level cache. If the LSU does not find the data corresponding to the load instruction Load0 in the cache, it needs to find the corresponding data from the memory according to the address provided by the load instruction Load0, but finding the data from the memory will take a longer clock cycle. Therefore, in the EX stage of the load instruction Load0, if a cache miss occurs, it will take a long clock cycle to determine the address of the data that the load instruction Load0 needs to access. It can be understood that since the storage space of the L1 cache is small, when the processor of the electronic device processes a large amount of data, the data corresponding to the load instruction Load0 is likely not in the L1 cache, and the L1 cache miss is prone to occur. Therefore, the CPU needs to spend a longer clock cycle to search for data in the next level cache.

[0078] Continue to refer to Figure 2 In the Tn clock cycle of the three-stage pipeline, the load instruction Load0 enters the EX stage, and the load instruction Load0 is launched by the launch module to the LSU pipeline for execution. A cache miss occurs, and the load instruction Load0 takes m clock cycles to complete the EX stage. The three-stage pipeline needs to pause for another m clock cycles.

[0079] For example, in the clock cycle of Tn+1, the instructions Inst2 and Inst3 are younger instructions than the load instruction Load0. Therefore, when the load instruction Load0 is running, the instructions Inst2 and Inst3 will also be suspended for m clock cycles (the instructions Inst2 and Inst3 have completed the execution of their respective stages in the clock cycle of Tn).

[0080] It can be understood that until the clock cycle Tn+m, the load instruction Load0 is completed in the EX stage. At this time, the load instruction Load0 is executed in the three-stage pipeline, and the instruction Inst2 enters the EX stage to run. The emission module in the processor emits the instruction Inst2 to the ALU for execution. The instruction Inst3 enters the ID stage to run, and in the IF stage, the new instruction Inst4 is added.

[0081] It can be understood that in the process of the above three-stage pipeline running instructions, instruction Inst1 caused a delay of n clock cycles in the EX stage. During the n clock cycles, the load instruction Load0 was in the ID stage and did not enter the LSU for execution. It was not until the load instruction Load0 entered the EX stage that it entered the LSU pipeline to access the data corresponding to the load instruction Load0 through the LSU. However, the load instruction Load0 caused a delay of m clock cycles in the EX stage due to a cache miss, so the three-stage pipeline was delayed by a total of m+n clock cycles.

[0082] In summary, in the processor of the electronic device, when the instructions corresponding to the relatively older stage need to spend a long clock cycle to run, the instructions corresponding to the relatively younger stage will be suspended. If the instructions corresponding to the relatively younger stage take a long clock cycle to run in the next stage, the pipeline delay will be further extended, resulting in a decrease in the efficiency of the pipeline.

[0083] In some embodiments of the present application, different instructions have different corresponding execution units during the execution of each stage of the pipeline. For example, taking the load / store instruction as an example, in the stage where the load / store instruction needs to access the register (such as the execution stage), it can enter the LSU for execution. Corresponding to some instructions that perform arithmetic operations or logical operations, they can enter the ALU for execution in the execution stage.

[0084] In order to solve the above problems, the present application proposes an instruction processing method, in which it is detected in the pipeline that the first instruction of the first pipeline stage (for example, the decoding stage) enters a pause state, wherein the first instruction (for example, the load / store instruction) has no dependency relationship with the instruction preceding the execution stage, and the first instruction can enter the first running unit (for example, the LSU unit) in the second pipeline stage (for example, the execution stage) for execution, and the second instruction of the second pipeline stage (for example, the instruction for performing calculations) is executed in the second running unit (for example, the ALU unit), and the first running unit and the second running unit are not the same running unit; the first instruction is transferred to the first unit for execution, wherein the second pipeline stage is the next stage of the first pipeline stage.

[0085] Through the above scheme, after a delay occurs in the pipeline, if the first operation unit that the first instruction can enter in the second pipeline stage is not the same as the second operation unit where the current second instruction is running in the second pipeline stage, the first instruction can be transferred to the first operation unit for execution in advance. It can be understood that the operation of the second execution stage of the first instruction does not occupy the resources of the current second instruction running in the second execution stage. Therefore, even if the pipeline is paused, it will not affect the operation of the first instruction in the first operation unit. If the first instruction needs to spend a longer clock cycle to run in the second execution stage, the clock cycle can be overlapped with the clock cycle where the current delay occurs, thereby reducing the delay time of the pipeline and improving the execution efficiency of the pipeline.

[0086] For example, in Figure 2 In the pipeline shown, at the clock cycle of T1, the load instruction Load0 is paused, and the load instruction Load0 is transferred to the LSU for execution. After n clock cycles, the instruction Inst1 completes the execution of the EX stage and leaves the pipeline. If the clock cycle m of the load instruction Load0 executing in the LSU is less than n, then at the clock cycle Tn+1, the load instruction Load0 can complete the execution in the three-stage pipeline. If the clock cycle m of the load instruction Load0 executing in the EX stage is greater than n, then at the clock cycle Tm, the load instruction Load0 can complete the execution. In other words, the delay of the pipeline is MAX(m, n) clock cycles, that is, the delay of the pipeline is the largest one between m and n, so the delay of the pipeline can be reduced.

[0087] The following introduces the architecture of the pipeline in the processor in some application embodiments.

[0088] For example, Figure 3 According to some embodiments of the present application, a schematic diagram of a micro-architecture of a processor is shown.

[0089] like Figure 3 As shown, the microarchitecture of the processor includes:

[0090] The program counter is used to store the address of the currently executed instruction (or instruction pointer). As instructions are executed, the value of the program counter is incremented according to the length and order of the instructions to point to the next instruction to be executed.

[0091] For example, in some embodiments of the present application, the program counter includes the address of the first instruction and the address of the second instruction, and the address of the first instruction is after the address of the second instruction, so the execution order of the second instruction comes first.

[0092] The front-end module is used to obtain the instruction address from the program counter in the instruction fetch stage, obtain the instruction from the cache or memory according to the instruction address, and store the instruction in an instruction set, which may be a register for storing instructions, for example.

[0093] For example, in some embodiments of the present application, in the instruction fetching stage of the pipeline, after the front-end module obtains the address of the second instruction, it can obtain the second instruction from the address corresponding to the second instruction and store the second instruction in the instruction set. Then the front-end module continues to obtain the address of the first instruction from the program counter, and obtains the first instruction from the memory or cache according to the address of the first instruction. Then the first instruction is stored in the instruction set.

[0094] The decoder is used to obtain instructions from the instruction set during the decoding stage and parse the instructions to obtain relevant data, which may include, for example, opcodes, operands, or addresses of operands. The decoder can send the opcode to the instruction queue and wait for the instruction to be executed after the data is ready. The decoder can directly parse out the operands according to the instructions. For example, for load / store instructions, the decoder can parse out the operands from the instructions, such as the source register address, the target register address, etc. For some instructions for arithmetic or logical operations, the decoder can parse out the address of the register corresponding to the operand from the instruction, and send the address of the operand to the register stack, which then obtains the corresponding operand.

[0095] For example, in some embodiments of the present application, the decoder can decode the second instruction in the decoding stage of the pipeline to obtain the operation code and the address of the operand of the second instruction, and the operation code of the second instruction indicates that the second instruction is used to perform an arithmetic operation. The decoder can send the operation code of the second instruction to the instruction queue, and send the address of the operand of the second instruction to the register file for subsequent operation of the register file instruction.

[0096] After receiving the first instruction, the decoder can also decode the first instruction. The operation code of the first instruction, for example, indicates that the first instruction is a load instruction. After the decoder completes decoding of the first instruction, it can parse out the corresponding operand, which can be, for example, a source register address, a target register address, etc. The decoder can directly send the operation code and operand of the first instruction to the instruction queue.

[0097] The register file is used to read the corresponding operand from the corresponding register according to the address of the operand and send the operand to the instruction queue.

[0098] The register file obtains the operand from the corresponding register according to the address of the operand of the second instruction, and sends the operand to the instruction queue.

[0099] The instruction queue, also known as the instruction queue buffer or instruction buffer register, is a set of registers used to temporarily store instructions. It follows the "first in, first out" principle for read and write operations. The transmitter module can read instructions from the instruction queue and parse out the opcode and operand. The existence of the instruction queue ensures that the transmitter module can stably obtain instructions.

[0100] Exemplarily, in some embodiments of the present application, after receiving the opcode of the first instruction, the instruction queue can temporarily store the first instruction. After the register stack sends the operand of the first instruction to the instruction queue, it can be determined that the relevant data of the first instruction has been prepared, and the transmission module can transmit the first instruction to the ALU for execution.

[0101] Similarly, after receiving the operation code and operand of the second instruction, the instruction queue can determine that the relevant data of the second instruction is ready, and the transmitting module can transmit the second instruction to the LSU for execution.

[0102] The transmission module can receive instruction information that has been decoded by the decoder from the instruction queue, and further process and prepare the information so that it can be sent to the operation unit for execution. The transmission module is also used to detect the dependency relationship between the instructions in the instruction queue to ensure the correct execution of the instructions and avoid data conflicts and resource conflicts.

[0103] In some embodiments of the present application, the transmitting module may also determine whether the execution unit corresponding to the instruction in the current execution stage is the same as the execution unit of the next instruction in the instruction queue. If they are not the same, and the next instruction has no dependency relationship with the previous instruction in the execution order, the transmitting module may also send the next instruction to the corresponding execution unit in advance for execution. This improves the operation efficiency of the pipeline.

[0104] Illustratively, in some embodiments of the present application, after relevant data of the first instruction is prepared in the instruction queue, the transmitting module may transmit the first instruction to the ALU for execution.

[0105] It can be understood that in the pipeline, when the second instruction runs to the execution stage, the first instruction is in the instruction fetch stage. After the transmitting module sends the first instruction to the ALU for execution, the first instruction can enter the execution stage. At this time, the first instruction can enter the decoding stage. However, the second instruction may take a long clock cycle to run in the execution stage. Therefore, until the first instruction has prepared relevant data in the instruction queue, the second instruction may still be running. At this time, the transmitting module detects whether there is a dependency relationship between the first instruction and the second instruction, and the first instruction is transmitted to the LSU for execution in the execution stage, and does not belong to the same operation unit as the second instruction. The transmitting module can transmit the first instruction to the LSU for execution.

[0106] In some embodiments of the present application, the execution units of the micro-architecture in the processor include ALU, LSU, etc. Different execution units can execute the same instructions in the same time period.

[0107] For example, during the execution of the second instruction in the ALU, the relevant data of the first instruction has been prepared, and there is no dependency between the first instruction and the second instruction. The first instruction is executed in the LSU during the execution phase and does not belong to the same execution unit as the second instruction. The microarchitecture of the processor can allow the ALU and LSU to run the first instruction and the second instruction in parallel.

[0108] Through the above-mentioned micro-architecture of the processor, if the first instruction and the second instruction have different execution units, there is no dependency between the first instruction and the second instruction, and the execution order of the second instruction is before the first instruction, if the second instruction occupies a longer clock cycle, the transmitting module can send the first instruction to the corresponding LSU for execution in advance. If the first instruction also needs to occupy a longer clock cycle, the clock cycle occupied by the first instruction in the LSU and the clock cycle occupied by the second instruction in the ALU can overlap, thereby reducing the delay of the pipeline to improve the performance of the pipeline.

[0109] Next, an instruction processing method in an embodiment of the present application is introduced.

[0110] For example, Figure 4 According to some embodiments of the present application, a flowchart of an implementation of an instruction processing method is shown.

[0111] It should be noted that the electronic device in the embodiment of the present application may be called a terminal (termina1), a user terminal, a mobile terminal, a user equipment (UE), a terminal device, a mobile station, a mobile terminal (mobile terminal, MT), etc. The terminal device may be a mobile phone, a wearable device, a tablet computer (Pad), a computer with a wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a terminal in industrial control (industrial control), a terminal in self-driving (selfdriving), a terminal in a smart grid (smart grid), a terminal in transportation safety (transportation safety), a terminal in a smart city (smart city), a terminal in a smart home (smart home), and other electronic devices.

[0112] like Figure 4 As shown, the process includes:

[0113] S401, detecting that the first instruction in the pipeline is paused in the first pipeline stage.

[0114] For example, in some embodiments of the present application, a transmitting module in a pipeline of a processor of an electronic device can detect that a first instruction in an instruction queue is ready to be executed in a second pipeline stage in a first pipeline stage, but an instruction in the pipeline that is executed before the first instruction is being executed, and the instruction has not entered the next pipeline stage for execution. Therefore, the pipeline enters a pause state, the first instruction cannot enter the second pipeline stage, and the first instruction is paused in the first pipeline stage.

[0115] For example, Figure 5 According to some embodiments of the present application, a process of executing instructions in a three-stage pipeline is shown.

[0116] like Figure 5 As shown, the execution order of the second instruction is before the first instruction. In the clock cycle T0, the second instruction enters the instruction fetch stage of the pipeline, after which the address of the first instruction is located at the top of the program counter, and the front-end module can obtain the address of the first instruction the next time it fetches an instruction.

[0117] In the clock cycle of T1, the second instruction enters the decoding stage, the front-end module obtains the address of the first instruction, and obtains the first instruction according to the address of the first instruction, that is, the first instruction enters the instruction fetching stage.

[0118] In the clock cycle T2, after the transmitting module sends the second instruction to the ALU, the second instruction enters the execution stage. At this time, the decoder decodes the first instruction and sends the operand and operation code of the first instruction to the instruction queue.

[0119] In the clock cycle of T3, the first instruction has prepared the corresponding data and can enter the execution stage, but the second instruction is still running in the ALU. Therefore, the first instruction is suspended in the decoding stage (as an example of the first pipeline stage). It can be understood that in the embodiment of the present application, the three-stage pipeline is a sequentially executed pipeline, that is, the instructions of each stage of the pipeline are executed one by one in sequence. Therefore, when the second instruction continues to run in the execution stage, the first instruction arranged after the second instruction will not enter the next pipeline stage, that is, the first instruction is suspended.

[0120] S402, determining whether the running process of the first instruction is independent of instructions that are executed before the first instruction in order, and whether the first instruction can be run in the first running unit in the second pipeline stage, wherein the second pipeline stage is the next stage of the first pipeline stage, and the second running unit where the second instruction currently running in the second pipeline stage is located is different from the first running unit.

[0121] Exemplarily, in some embodiments of the present application, the first instruction is paused in the first pipeline stage, and the transmitting module can detect the dependency between the first instruction and the instruction preceding it in the execution order, and determine whether the first running unit executed by the first instruction in the second pipeline stage and the second running unit where the second instruction currently in the second pipeline stage is located belong to the same running unit.

[0122] If the judgment result is yes, then S403 is executed to send the first instruction to the first execution unit for execution.

[0123] If the judgment result is no, S404 is executed to wait for the instruction before the first instruction in the execution order to complete the operation of the corresponding pipeline stage, and then the first instruction is sent to the second pipeline stage.

[0124] By way of example, in some embodiments of the present application, after the decoder completes decoding of the first instruction, it can obtain the first address that the first instruction needs to access. For example, when the first instruction is a load instruction, the first address can be the source register address of the loaded data. Similarly, when the second instruction is in the decoding stage, the decoder can also parse the second instruction to obtain the second address for storing the running result of the second instruction. After determining that the first address and the second address are not the same address, the transmitting module can determine that there is no dependency between the first instruction and the second instruction. By way of example, in other embodiments, the transmitting module can track the data flow of the first instruction and the second instruction to determine whether there is a dependency between the first instruction and the second instruction. The present application does not limit the manner in which the transmitting module determines whether there is a dependency between the first instruction and the second instruction.

[0125] In some embodiments of the present application, after decoding the first instruction and the second instruction, the decoder can determine that the operation code of the first instruction indicates that the first instruction is executed in the first operation unit (for example, in the LSU), and determine that the operation code of the second instruction indicates that the second instruction is executed in the second operation unit (for example, in the ALU). Since the execution order of the second instruction is first, the transmission module can send the second instruction to the second operation unit for execution according to the operation code of the second instruction. If the transmission module detects that the data of the first instruction has been prepared, but the second instruction is still executed in the execution stage, the transmission module can also determine whether the first instruction and the second instruction are executed in the same operation unit in the execution stage according to the operation code of the first instruction and the operation code of the second instruction.

[0126] S403: Send the first instruction to a first execution unit for execution.

[0127] Exemplarily, in some embodiments of the present application, if the first execution unit and the second execution unit do not belong to the same execution unit, and the first instruction has no dependency on the instruction preceding the execution order, the transmission module may transmit the first instruction to the first execution unit for execution.

[0128] For example, continue to refer to Figure 5 , since the second instruction is executed in the ALU (as an example of the second operation unit) during the execution stage (as an example of the second pipeline stage), the emission module can send the first instruction to the LSU (as an example of the first operation unit) for execution at the clock cycle of T3. At this time, the ALU and LSU in the microarchitecture of the processor run in parallel, thereby improving the efficiency of the pipeline.

[0129] S404, after waiting for instructions that are executed before the first instruction to complete the execution of the corresponding pipeline stage, send the first instruction to the second pipeline stage.

[0130] Exemplarily, in some embodiments of the present application, if the execution process of the first instruction depends on the execution result of the instruction preceding the execution order, or the first execution unit corresponding to the first instruction and the second execution unit corresponding to the second instruction are the same execution unit, the transmitting module cannot transmit the first instruction to the first execution unit, and the first instruction needs to wait for the instruction preceding the execution order to complete execution in the corresponding pipeline stage before it can enter the second pipeline stage.

[0131] Exemplarily, if the first instruction can be sent to the first execution unit in advance for execution after being paused in the first pipeline stage, the first instruction can be executed simultaneously with the second instruction, so the clock cycle occupied by the second instruction can overlap with the clock cycle occupied by the first instruction, thereby improving the operating efficiency of the processor.

[0132] For example, continue to refer to Figure 5 In the clock cycle of Tn+2, the first instruction is completed in the LSU, that is, the first instruction takes n clock cycles (from the clock cycle of T3 to the clock cycle of Tn+2, n+2≥3) to run in the LSU, but the second instruction is still running in the ALU. Therefore, the first instruction is still in the ID stage, and the second instruction is still in the EX stage. It is not until the clock cycle of Tm+1 (n<m) that the second instruction is completed in the EX stage, that is, the second instruction takes m clock cycles in the ALU. However, the first instruction has completed its execution in the clock cycle of Tm+1, so the pipeline will no longer take n clock cycles to execute the first instruction. The delay of the entire pipeline is m clock cycles, so the delay of the pipeline is reduced by n clock cycles.

[0133] In other embodiments, if the clock cycle occupied by the second instruction in the ALU is smaller than the clock cycle occupied by the first instruction in the LSU, the pipeline delay can be reduced by m clock cycles. That is, within the clock cycle in which the first instruction runs in the LSU, the second instruction can complete the execution in the ALU, which can also reduce the pipeline delay.

[0134] For example, Figure 6 According to some embodiments of the present application, a schematic diagram of the execution process of another three-stage pipeline is shown.

[0135] like Figure 6 As shown, Figure 6 Example and Figure 5 The difference between the embodiments is that in the clock cycle of Tm+1, the second instruction has completed its execution and has left the pipeline. That is to say, the second instruction takes m clock cycles to execute in the ALU. At this time, the first instruction enters the EX stage, and the first instruction continues to execute in the LSU until the clock cycle corresponding to Tn+2, when the first instruction completes its execution. It can be understood that the first instruction takes n clock cycles (n>m) in the LSU. It can be understood that the m clock cycles occupied by the second instruction when it is executed overlap with the n clock cycles occupied by the first instruction when it is executed. That is, when the second instruction has executed m clock cycles in the EX stage, the first instruction has been sent to the LSU and has executed m clock cycles at the same time. After the second instruction has completed its execution in the EX stage, the first instruction enters the EX stage and executes nm clock cycles. Therefore, in the process of executing the first instruction and the second instruction, the pipeline delay is only n clock cycles, which can also reduce the pipeline delay.

[0136] The electronic devices involved in the above embodiments are introduced below.

[0137] For example, Figure 7 According to some embodiments of the present application, a schematic structural diagram of an electronic device 100 is shown.

[0138] The electronic device 100 can be used to implement the instruction processing methods provided in the aforementioned embodiments.

[0139] like Figure 7 As shown, the electronic device 100 includes one or more processors 101, a system memory 102, a non-volatile memory (NVM) 103, a communication interface 104, an input / output device 105, and a system control logic 106 for coupling the processor 101, the system memory 102, the non-volatile memory 103, the communication interface 104 and the input / output (I / O) device 105. Among them:

[0140] The processor 101 may include one or more processing units, for example, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a microprocessor (MCU), an artificial intelligence (AI) processor or a programmable logic device (field programmable gate array, FPGA), a neural network processor (neural-network processing unit, NPU), etc. The processing module or processing circuit may include one or more single-core or multi-core processors. In some embodiments, the micro-architecture in the aforementioned embodiments may also be configured in the processor to perform instruction operations.

[0141] The system memory 102 is a volatile memory, such as a random-access memory (RAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc. The system memory is used to temporarily store data and / or instructions. For example, in some embodiments, the system memory 102 can be used to store operands corresponding to instructions, and can also be used to store instructions of the instruction processing methods provided in the aforementioned embodiments.

[0142] The non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 103 may include any suitable non-volatile memory such as a flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 103 may also be a removable storage medium, such as a secure digital (SD) memory card, etc. In other embodiments, the non-volatile memory 103 may be used to store instructions of the instruction processing method provided in the aforementioned embodiments, etc.

[0143] In particular, the system memory 102 and the non-volatile memory 103 may respectively include: a temporary copy and a permanent copy of the instruction 107. The instruction 107 may include: when executed by at least one of the processors 101, the electronic device 100 implements the instruction processing method provided in each embodiment of the present application.

[0144] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby communicating with any other suitable device through one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104.

[0145] The input / output (I / O) device 105 may include input devices such as a keyboard, a mouse, etc., and output devices such as a display, etc. A user may interact with the electronic device 100 through the input / output (I / O) device 105 .

[0146] System control logic 106 may include any suitable interface controller to provide any suitable interface with other modules of electronic device 100. For example, in some embodiments, system control logic 106 may include one or more memory controllers to provide interfaces to system memory 102 and non-volatile memory 103.

[0147] In some embodiments, at least one of the processors 101 may be packaged together with the logic of one or more controllers for the system control logic 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101 may also be integrated with the logic of one or more controllers for the system control logic 106 on the same chip to form a system-on-chip (SoC).

[0148] Understandably, Figure 7 The structure of the electronic device 100 shown is only an example. In other embodiments, the electronic device 100 may include more or fewer components than shown, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0149] It is understandable that the electronic device 100 can be any electronic device, including but not limited to a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, etc., and the embodiments of the present application are not limited thereto.

[0150] The embodiments of the present application also provide a program product, which, when executed on an electronic device, can enable the electronic device to implement the methods provided in the aforementioned embodiments.

[0151] An embodiment of the present application further provides a readable storage medium, in which one or more programs are stored. When the one or more programs are executed by an electronic device, the electronic device implements the methods provided in the aforementioned embodiments.

[0152] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device and at least one output device.

[0153] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor, a microcontroller, an application specific integrated circuit, or a microprocessor.

[0154] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0155] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, the machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy disks, optical disks, optical discs, compact disc-read only memory (CD-ROMs), magneto-optical disks, read-only memory (ROM), random-access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or tangible machine-readable storage for transmitting information using the Internet in electrical, optical, acoustic or other forms of propagation signals (e.g., carrier waves, infrared signals, digital signals, etc.). Therefore, the machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0156] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0157] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0158] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0159] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. A command processing method, applied to an electronic device, characterized in that: The method comprises: detecting that a first instruction in a first pipeline is paused in a first pipeline stage; Determining that the execution process of the first instruction does not depend on instructions that are executed before the first instruction in an order of execution, the instructions before the first instruction include a second instruction, and the first instruction is executed in a first execution unit in a second pipeline stage, wherein the second pipeline stage is a stage next to the first pipeline stage, and a second execution unit where the second instruction currently executed in the second pipeline stage is located is not the same execution unit as the first execution unit; The first instruction is sent to the first execution unit for execution.

2. The method according to claim 1, characterized in that The first pipeline is a three-stage pipeline and includes the following pipeline stages: Instruction fetch stage, decoding stage, execution stage; The first pipeline stage is a decoding stage, and the second pipeline stage is an execution stage.

3. The method according to claim 1, characterized in that The detecting that the first instruction in the first pipeline is paused in the first pipeline stage includes: It is detected that the first instruction has finished executing in the first pipeline stage, and instructions that are executed before the first instruction are currently executing.

4. The method according to claim 1, characterized in that The first pipeline is a sequentially executed pipeline.

5. The method according to claim 2, characterized in that: Determining that the execution process of the first instruction does not depend on a second instruction that is executed before the first instruction includes: Obtaining a first address accessed by the first instruction and a second address storing an operation result of the second instruction; Corresponding to the mismatch between the first address and the second address, it is determined that the execution process of the first instruction does not depend on the second instruction that is executed before the first instruction.

6. The method according to claim 1, characterized in that The first instruction includes a first instruction code, the first instruction code indicates that the first instruction enters the first execution unit in the second pipeline stage for execution, and the second instruction includes a second instruction code, the second instruction code indicates that the second instruction enters the second execution unit in the second pipeline stage for execution; The method of determining that the second execution unit where the second instruction currently executed in the second pipeline stage is located is not the same as the first execution unit includes: Based on the first instruction code and the second instruction code, it is determined that the second operating unit is not the same operating unit as the first operating unit.

7. The method according to claim 1, characterized in that The first instruction is a load instruction or a store instruction, the second instruction is an arithmetic logic instruction, the first execution unit is a load or store unit, and the second execution unit is an arithmetic logic unit.

8. An electronic device, characterized in that: include: A memory for storing instructions; At least one processor is used to execute the instructions so that the electronic device implements the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: The readable storage medium stores instructions, and when the instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 7.

10. A computer program product, characterized in that When the computer program product is executed on a device, the device is caused to perform the method according to any one of claims 1 to 7.

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