Data verification methods and devices, electronic devices for programming operations

Abstract

This application relates to the field of semiconductor digital verification technology, and discloses a data verification method for programming operations, comprising: determining the width of verification data according to the organization of the flash array; setting multiple sets of data patterns of the same length according to the width of the verification data; wherein each set of data patterns includes multiple programming data; verifying each set of data patterns sequentially and obtaining verification results; wherein the verification results indicate whether the address corresponding to the programming data in the data pattern needs to be programmed; executing programming instructions on the addresses that need to be programmed to perform data verification, until all data patterns have been verified. This method makes data verification more comprehensive and improves verification efficiency. This application also discloses a data verification device and electronic device for programming operations.

Description

Technical Field

[0001] This application relates to the field of semiconductor digital verification technology, such as a data verification method and apparatus for programming operations, and electronic equipment. Background Technology

[0002] In the current field of FLASH storage technology, the execution of programming operations relies on sophisticated control logic, involving precise management of the internal state machine of the FLASH memory and strict control of the data transmission process. The state machine is responsible for controlling various operational states of the FLASH memory, such as idle, programming, erasing, and reading, ensuring that these states transition correctly in a predetermined order. The data transmission process involves transferring data from the main controller to the FLASH chip, and also includes data buffering, error detection, and verification. To ensure the correctness and reliability of programming operations in the FLASH memory, a series of verification steps must be performed.

[0003] To verify the correctness of programming operations, a verification scheme is disclosed, which includes sending a data chain with random width and random value during programming; after the programming operation is completed, reading out these data chains and checking whether they are consistent.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] The random values ​​are not constrained, resulting in most being non-8'hff random values, requiring programming and data validation afterward. This only triggers a very small portion of the state machine, with most state transitions not being triggered, and the presence of bugs is uncertain. Although the random data changes each time, it cannot necessarily cover other state transitions.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a data verification method, apparatus, and electronic device for programming operations, which makes data verification more comprehensive and improves verification efficiency.

[0009] In some embodiments, the data verification method for programming operations includes: determining the width of verification data according to the organization of the flash array; setting multiple sets of data patterns of the same length according to the width of the verification data; wherein each set of data patterns includes multiple sets of programming data; verifying each set of data patterns sequentially and obtaining verification results; wherein the verification results indicate whether the address corresponding to the programming data in the data pattern needs to be programmed; executing programming instructions on the addresses that need to be programmed to perform data verification, until all data patterns have been verified.

[0010] Optionally, each data pattern is verified sequentially to obtain the verification result, including: determining whether the data pattern is all-f data; if the data pattern is all-f data, the verification result is that all bytes of the data pattern pass; if the data pattern is not all-f data, the verification result is that the non-f bytes in the data pattern fail.

[0011] Optionally, determining whether the data pattern is all-f data includes: if every programmed data in the data pattern is 8'hff, the data pattern is determined to be all-f data; if there is programmed data in the data pattern that is not 8'hff, the data pattern is determined to be non-all-f data.

[0012] Optionally, the width of the verification data is determined according to the organization of the flash array, including: obtaining the maximum byte length of a single verification of the state machine according to the organization of the flash array; and using the maximum byte length as the width of the verification data.

[0013] Optionally, based on the width of the verification data, multiple data patterns of the same length can be set, including: when the width of the verification data is N, the data pattern is set to 2. N .

[0014] Optionally, data verification can be performed, including: reading data from an address programmed by programming instructions using a read instruction; verifying whether the data from the address programmed by programming instructions is correct, in order to verify the state machine transition.

[0015] Optionally, each set of data patterns is verified sequentially to obtain the verification result, and the method also includes: after the current data pattern is verified, switching to an empty address to verify the next set of data patterns.

[0016] Optionally, executing programming instructions on the address that needs to be programmed to perform data verification until all data patterns have been verified also includes: after the current data pattern has been verified, determining whether the current data pattern is the last group of data patterns; if the current data pattern is the last group of data patterns, determining that all data patterns have been verified; if the current data pattern is not the last group of data patterns, performing verification of the next group of data patterns.

[0017] In some embodiments, the data verification apparatus for programming operations includes a processor and a memory storing program instructions, the processor being configured to execute the data verification method for programming operations as described above when running the program instructions.

[0018] In some embodiments, the electronic device includes: an electronic device body; and a data verification device for programming operations, as described above, installed on the electronic device body.

[0019] The data verification method, apparatus, and electronic device for programming operations provided in this disclosure can achieve the following technical effects:

[0020] In FLASH memory programming operations, to ensure data is correctly written to the storage unit and maintains its integrity, the width of the verification data is first determined according to the organization of the FLASH array. Next, based on the determined verification data width, multiple sets of data patterns of the same length are set, each containing multiple programming data. Then, each set of data patterns is verified sequentially, and the verification result is obtained through a read operation. For addresses where the verification result indicates programming is required, the programming instruction is executed, the data is written to the FLASH memory, and the data verification is completed. This process continues until all preset data patterns have been verified. Through a systematic verification process, the accuracy of the programming operation and the integrity of the data in the FLASH memory are ensured. This disclosed embodiment, from the perspective of state transitions, ignores the details of state machine design, and arranges the programming data according to all possible permutations and combinations of bytes that need to be programmed and bytes that do not need to be programmed. This eliminates the need to design many cases for each state, reducing the number of cases, reducing case maintenance, and increasing case reusability. Even if there are changes in the code design or the state machine changes, it is not necessary to rewrite the cases; only the data verification width needs to be modified. This approach ensures coverage of all state transitions without requiring multiple randomizations, saving simulation time and time spent modifying test cases, thus greatly improving efficiency while guaranteeing the comprehensiveness of data verification.

[0021] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0023] Figure 1This is a schematic diagram of the implementation environment of the data verification method for programming operations according to an embodiment of this disclosure;

[0024] Figure 2 This is a schematic diagram of a data verification method for programming operations provided in an embodiment of this disclosure;

[0025] Figure 3 This is a schematic diagram of another data verification method for programming operations provided in an embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram of another data verification method for programming operations provided in an embodiment of this disclosure;

[0027] Figure 5 This is a schematic diagram of a data verification device for programming operations provided in an embodiment of this disclosure. Detailed Implementation

[0028] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0029] The terms "first," "second," etc., used in the technical solutions described in this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0030] Unless otherwise stated, the term "multiple" means two or more.

[0031] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0032] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0033] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0034] In today's semiconductor technology field, FLASH memory technology has become one of the preferred solutions for data storage due to its non-volatile characteristics. However, the complexity of FLASH memory programming operations requires precise control logic and rigorous verification procedures to ensure the correctness and reliability of the operation. FLASH memory programming involves meticulous management of the internal state machine and strict control of the data transfer process; these factors together determine whether data can be accurately and persistently written to the memory cells.

[0035] Flash memory has a complex storage structure, consisting of a large number of storage cells organized by pages and blocks. Therefore, programming operations must be performed precisely at the correct page and block addresses to avoid data corruption or loss. Furthermore, due to the limited programming / erase cycles of flash memory cells, the accuracy of programming operations directly affects the memory's lifespan. Improper programming can not only lead to data errors but also accelerate the aging of storage cells, shortening the memory's lifespan.

[0036] During data transmission, it is crucial to ensure data integrity and prevent data corruption due to noise, interference, or hardware failure. FLASH programming operations also require specific voltage conditions and strict timing control; improper voltage or timing can lead to programming failure or data errors. Therefore, error detection and verification procedures, such as parity checks and CRC checks, are essential to ensure that data has not been tampered with during transmission.

[0037] In summary, performing a series of verification steps is crucial to ensuring the correctness and reliability of programming operations in FLASH memory. These steps include data integrity verification, state machine verification, and programming result verification, ensuring correct data writing and long-term stability of the memory.

[0038] To verify the correctness of the programming operation, this embodiment of the disclosure verifies it from the perspective of digital state machine control by traversing the combinations of programming and non-programming within a fixed interval length to verify the state machine transitions.

[0039] Figure 1 This is a schematic diagram illustrating the implementation environment of the data verification method for programming operations according to an embodiment of this disclosure. For example... Figure 1 As shown, the implementation environment may include a digital state machine 100 and a processor 500.

[0040] The processor 500 can input all combinations of programmed data, and the digital state machine 100 can perform data verification by traversing these combinations.

[0041] Combination Figure 2 As shown, this disclosure provides a data verification method for programming operations, including:

[0042] S201, the processor determines the width of the verification data based on the organization of the flash array.

[0043] S202, the processor sets multiple sets of data patterns of the same length according to the width of the verification data; each set of data patterns includes multiple programming data.

[0044] S203, the processor sequentially verifies each group of data patterns and obtains the verification result; wherein, the verification result indicates whether the address corresponding to the programming data in the data pattern needs to be programmed.

[0045] S204, the processor executes programming instructions on the address that needs to be programmed to perform data verification until all data patterns have been verified.

[0046] The method provided in this disclosure ensures that data is correctly written to the storage unit and its integrity is maintained during FLASH memory programming operations. First, the width of the verification data is determined based on the organization of the FLASH array. Then, based on the determined verification data width, multiple sets of data patterns of the same length are set, each containing multiple programming data. Next, each set of data patterns is verified sequentially, and the verification result is obtained through a read operation. For addresses where the verification result indicates programming is required, programming instructions are executed, data is written to the FLASH memory, and data verification is completed. This process continues until all preset data patterns have been verified. This systematic verification process ensures the accuracy of programming operations and the integrity of data in the FLASH memory. This disclosure, from the perspective of state transitions, ignores the details of state machine design, arranging programming data according to all possible permutations and combinations of bytes that need programming and bytes that do not need programming. This eliminates the need to design many cases for each state, reducing the number of cases, reducing case maintenance, and increasing case reusability. Even if there are changes in the code design or the state machine changes, it is not necessary to rewrite the cases; only the data verification width needs to be modified. This approach ensures coverage of all state transitions without requiring multiple randomizations, saving simulation time and time spent modifying test cases, thus greatly improving efficiency while guaranteeing the comprehensiveness of data verification.

[0047] Optionally, each data pattern is verified sequentially to obtain the verification result, including: determining whether the data pattern is all-f data; if the data pattern is all-f data, the verification result is that all bytes of the data pattern pass; if the data pattern is not all-f data, the verification result is that the non-f bytes in the data pattern fail.

[0048] In this embodiment, the system sequentially verifies each set of preset data patterns. Each data pattern consists of multiple bytes, which may be all 'f' (i.e., all bits are 1, representing data that does not require programming) or contain non-'f' bytes (i.e., contain 0, representing data that requires programming). The verification process first determines whether the data pattern is all 'f' data. If the data pattern is all 'f' data, the verification result will mark all bytes of that data pattern as 'pass', meaning no further programming operation is required. Conversely, if the data pattern is not all 'f' data, i.e., it contains bytes that require programming, the system will identify these non-'f' bytes and mark them as 'fail', indicating that these addresses need programming. This allows for accurate identification of data that needs programming, thereby avoiding unnecessary programming operations and improving programming efficiency and memory lifespan.

[0049] Optionally, determining whether the data pattern is all-f data includes: if every programmed data in the data pattern is 8'hff, the data pattern is determined to be all-f data; if there is programmed data in the data pattern that is not 8'hff, the data pattern is determined to be non-all-f data.

[0050] In this embodiment, each piece of programming data in each data pattern is checked one by one. "All-f data" refers to each byte in the data pattern being 8'hff, or 1111 in binary representation, indicating that the byte does not require programming and is already in the initial state of FLASH memory programming operations. The system checks each byte to confirm whether each byte in the data pattern conforms to the 8'hff standard. If all bytes are 8'hff, the system determines that the data pattern is all-f data, meaning that all bytes in the entire data pattern are marked as pass, indicating that it meets the requirements and does not require further programming operations. Conversely, if any byte in the data pattern is found to be non-8'hff, i.e., there is non-8'hff programming data, the system determines that the data pattern is non-all-f data. In this case, the system further marks the non-8'hff bytes as fail, indicating that these bytes need programming operations. This precise judgment mechanism improves the accuracy and efficiency of programming operations by quickly identifying data that needs programming and data that does not, thereby reducing unnecessary programming operations. Secondly, traversing combinations of data that need programming and data that do not need programming within a fixed interval length makes data verification more comprehensive.

[0051] Optionally, the width of the verification data is determined according to the organization of the flash array, including: obtaining the maximum byte length of a single verification of the state machine according to the organization of the flash array; and using the maximum byte length as the width of the verification data.

[0052] In this embodiment, based on the organization of the FLASH array, it is necessary to identify and obtain the maximum byte length of a single state machine verification. The length is typically related to the physical structure of the FLASH array; for example, FLASH memory is programmed in page units, and a page is typically 256 bytes in size. This maximum byte length is the maximum amount of data the state machine can process in a single operation. Then, the system uses this maximum byte length as the width of the verification data; that is, during data verification, each operation checks the data with the maximum byte length.

[0053] By determining the width of the verification data, the system can organize and execute verification operations more effectively. Each verification targets a fixed-size data block, which helps reduce redundant operations in the verification process and improves verification efficiency while ensuring accuracy.

[0054] Optionally, based on the width of the verification data, multiple data patterns of the same length can be set, including: when the width of the verification data is N, the data pattern is set to 2. N .

[0055] In this embodiment of the disclosure, when the width of the verification data is determined to be N bytes, the number of data patterns is set to 2. N Each byte has two states: one that needs programming (non-8'hff) and one that doesn't need programming (8'hff), resulting in all possible combinations. Each combination is programmed and verified to check the state machine of the FLASH memory.

[0056] Optionally, data verification can be performed, including: reading data from an address programmed by programming instructions using a read instruction; verifying whether the data from the address programmed by programming instructions is correct, in order to verify the state machine transition.

[0057] In this embodiment, programming instructions are executed in the FLASH memory to write a specific data pattern to a predetermined address. Subsequently, read instructions are sent to read the data from these programmed addresses. After the read instruction is executed, the system retrieves the data from the memory and compares it with the expected programmed data. If the read data matches the expected data, the programming operation at that address is considered successful, and the state machine transition is correct. If they do not match, it indicates that the programming operation failed or there is a problem with the state machine transition. Specifically, if a byte in the data pattern is not 8'hff, then during verification, this byte should change from its initial state (usually all 1s, i.e., 8'hff) to its programmed state (not 8'hff), thereby confirming the success of the programming operation.

[0058] This disclosure provides a direct and effective method to verify the success of FLASH memory programming operations, ensuring data integrity and accuracy. Secondly, verification can detect whether the state machine transitions according to the expected logic, guaranteeing the reliability and stability of the FLASH memory. Furthermore, this method helps to promptly identify and correct errors that may occur during programming, reducing the risk of data corruption and extending the memory's lifespan. Simultaneously, the verification process optimizes development and verification costs, reduces the number of test cases required, and improves testing efficiency and accuracy.

[0059] Optionally, each set of data patterns is verified sequentially to obtain the verification result, and the method also includes: after the current data pattern is verified, switching to an empty address to verify the next set of data patterns.

[0060] Combination Figure 3 As shown, this disclosure provides another data verification method for programming operations, including:

[0061] S301, the processor determines the width of the verification data based on the organization of the flash array.

[0062] S302, the processor sets multiple sets of data patterns of the same length according to the width of the verification data; each set of data patterns includes multiple programming data.

[0063] S303, the processor sequentially verifies each set of data patterns and obtains the verification result; the verification result indicates whether the address corresponding to the programmed data in the data pattern needs to be programmed. After the current data pattern is verified, the processor switches to an empty address to verify the next set of data patterns.

[0064] S304: The processor executes programming instructions on the address that needs to be programmed to perform data verification until all data patterns have been verified.

[0065] In this embodiment, the system selects an empty address, i.e., an unprogrammed address region, as the verification region for the current data pattern. Data is written to the empty address using programming instructions according to the set data pattern. After programming is complete, the data in the address is read using read instructions and compared with the expected data pattern to verify whether the data has been correctly programmed. Once the verification of the current data pattern is complete, regardless of whether the result is successful, the system switches to the next empty address to ensure that the verification of the next set of data patterns is not affected by previous data.

[0066] This ensures that the verification of each data pattern is performed in an independent and consistent environment, avoiding data pollution caused by address reuse. Secondly, this method improves verification accuracy, as each verification is performed on a completely new address, reducing potential errors caused by address state changes.

[0067] Optionally, executing programming instructions on the address that needs to be programmed to perform data verification until all data patterns have been verified also includes: after the current data pattern has been verified, determining whether the current data pattern is the last group of data patterns; if the current data pattern is the last group of data patterns, determining that all data patterns have been verified; if the current data pattern is not the last group of data patterns, performing verification of the next group of data patterns.

[0068] Combination Figure 4 As shown, this disclosure provides another data verification method for programming operations, including:

[0069] S401, the processor determines the width of the verification data based on the organization of the flash array.

[0070] S402, the processor sets multiple sets of data patterns of the same length according to the width of the verification data; each set of data patterns includes multiple programming data.

[0071] S403, the processor sequentially verifies each group of data patterns and obtains the verification result; wherein, the verification result indicates whether the address corresponding to the programming data in the data pattern needs to be programmed.

[0072] S404: The processor executes programming instructions at the address that needs to be programmed in order to perform data verification.

[0073] S405: After the processor completes the verification of the current data mode, it determines whether the current data mode is the last set of data modes.

[0074] S406, when the current data mode is the last group of data modes, the processor determines that all data modes have been verified.

[0075] S407: If the current data mode is not the last data mode, the processor will verify the next data mode.

[0076] In this embodiment, programming instructions are executed for each address requiring programming, writing a predetermined data pattern into the FLASH memory. After programming, the data at the address is read and compared with the expected data to verify whether the data has been correctly programmed. Once the verification of the current data pattern is complete, it is determined whether the current data pattern is the last set of data patterns. If the current data pattern is the last set, the system determines that all data patterns have been verified, and the entire verification process ends. If the current data pattern is not the last set, the system will automatically verify the next set of data patterns until all preset data patterns have been verified. This ensures that each set of data patterns is verified one by one, thereby comprehensively covering all programming states of the FLASH memory and improving the comprehensiveness and accuracy of the verification.

[0077] Combination Figure 5 As shown, this embodiment of the disclosure provides a data verification device 50 for programming operations, including a processor 500 and a memory 501. Optionally, the device 50 may further include a communication interface 502 and a bus 503. The processor 500, communication interface 502, and memory 501 can communicate with each other via the bus 503. The communication interface 502 can be used for information transmission. The processor 500 can call logical instructions in the memory 501 to execute the data verification method for programming operations described in the above embodiment.

[0078] Furthermore, the logic instructions in the aforementioned memory 501 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0079] The memory 501, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 500 executes functional applications and data processing by running the program instructions / modules stored in the memory 501, thereby implementing the data verification method for programming operations described in the above embodiments.

[0080] The memory 501 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 501 may include high-speed random access memory and may also include non-volatile memory.

[0081] This disclosure provides an electronic device, including: an electronic device body, and the aforementioned data verification device for programming operations. The data verification device for programming operations is mounted on the electronic device body. The mounting relationship described herein is not limited to placement within the electronic device body, but also includes mounting connections with other components of the electronic device, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the data verification device for programming operations can be adapted to suitable electronic device bodies to achieve other feasible embodiments.

[0082] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0083] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0084] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0085] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0086] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A data verification method for programming operations, characterized in that, include: Determine the width of the verification data based on the organization of the flash array; Based on the width of the verification data, multiple sets of data patterns of the same length are set; each set of data patterns includes multiple sets of programmed data. Each data pattern is verified sequentially, and the verification result is obtained; the verification result indicates whether the address corresponding to the programmed data in the data pattern needs to be programmed. Execute programming instructions on the addresses that require programming to perform data verification until all data patterns have been verified.

2. The data verification method according to claim 1, characterized in that, Each data pattern was validated sequentially, and the validation results were obtained, including: Determine if the data pattern is all f-data; When the data mode is all f data, the verification result is that all bytes of the data mode pass. When the data mode is not full f data, the verification result is that the non-f bytes in the data mode fail.

3. The data verification method according to claim 2, characterized in that, Determining whether the data pattern is all-f data includes: If every programmed data in the data pattern is 8'hff, the data pattern is determined to be all f data; If the programmed data in the data pattern is not 8'hff, the data pattern is determined to be non-full f data.

4. The data verification method according to claim 1, characterized in that, Based on the organization of the flash array, determine the width of the verification data, including: Based on the organization of the flash array, obtain the maximum byte length of a single state machine check; Use the maximum byte length as the width of the verification data.

5. The data verification method according to claim 1, characterized in that, Based on the width of the validation data, set multiple data patterns of the same length, including: With the width of the validation data being N, the data mode is set to 2. N .

6. The data verification method according to any one of claims 1 to 5, characterized in that, Data validation includes: Data at an address programmed by programming instructions is read using read instructions; Verify the correctness of the data at the address programmed by the programming instructions in order to verify the state machine transitions.

7. The data verification method according to any one of claims 1 to 5, characterized in that, Each data pattern is validated sequentially, and the validation results are obtained. This also includes: After the current data pattern has been verified, switch to an empty address to verify the next set of data patterns.

8. The data verification method according to any one of claims 1 to 5, characterized in that, Execute programming instructions on the addresses that require programming to perform data verification until all data patterns have been verified, and also include: After the current data pattern has been verified, determine whether the current data pattern is the last set of data patterns; If the current data pattern is the last set of data patterns, it is determined that all data patterns have been verified. If the current data pattern is not the last set of data patterns, proceed to verify the next set of data patterns.

9. A data verification device for programming operations, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute, when running the program instructions, the data verification method for programming operations as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, include: The electronic device itself; The data verification device for programming operations as described in claim 9 is installed on the electronic device body.

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