Data access method and device, electronic equipment and computer readable storage medium

Abstract

The invention provides a data access method and device, electronic equipment and a computer readable storage medium, the method is applied to a first processing core in a plurality of processing cores of a many-core system, and a target neural network is deployed in the plurality of processing cores of the many-core system. The method comprises the following steps: acquiring an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture of a software ecosystem for deploying a target neural network and a physical storage address in a processing core of a many-core system; in response to the received first data access request, a first virtual address is obtained, and the first virtual address represents a virtual storage address to be accessed by the first data access request; determining a physical storage address corresponding to the first virtual address as a first physical address based on the association relationship; and executing an access operation of the first data access request on the first physical address. According to the embodiment of the invention, the many-core system can be quickly integrated into the current AI software ecological system.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data access method and device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the development of artificial intelligence (AI) technology, neural network computing has an increasing demand for chip computing power. Multi-core chips have become an ideal choice for large-scale neural network computing due to their excellent parallel capabilities and flexibility. Summary of the invention

[0003] The present disclosure provides a data access method and device based on a many-core system, an electronic device, and a computer-readable storage medium.

[0004] In a first aspect, the present disclosure provides a data access method, which is applied to a first processing core among multiple processing cores of a many-core system, wherein a target neural network is deployed in the multiple processing cores of the many-core system, and the data access method comprises: obtaining an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture and a physical storage address in the processing core of the many-core system, wherein the hierarchical shared storage architecture is a storage architecture of a software ecosystem in which the target neural network is deployed; in response to receiving a first data access request, obtaining a first virtual address, wherein the first virtual address represents a virtual storage address to be accessed by the first data access request; determining a physical storage address corresponding to the first virtual address based on the association relationship as a first physical address; and performing an access operation of the first data access request on the first physical address.

[0005] In a second aspect, the present disclosure provides a data access device, the device being applied to a first processing core among multiple processing cores of a many-core system, wherein a target neural network is deployed in the multiple processing cores of the many-core system, the data access device comprising:

[0006] an acquisition module, configured to acquire an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture and a physical storage address in a processing core of the many-core system, wherein the hierarchical shared storage architecture is a storage architecture of a software ecosystem in which the target neural network is deployed;

[0007] A response module, configured to obtain a first virtual address in response to receiving a first data memory access request, wherein the first virtual address represents a virtual storage address to be accessed by the first data memory access request;

[0008] A determination module, configured to determine, based on the association relationship, a physical storage address corresponding to the first virtual address as a first physical address;

[0009] An execution module is used to execute an access operation of the first data memory access request on the first physical address.

[0010] In a third aspect, the present disclosure provides an electronic device, comprising: multiple processing cores; and an on-chip network configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the above-mentioned data access method.

[0011] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned data memory access method when executed by a processing core.

[0012] In the embodiments provided by the present disclosure, the first processing core of the many-core system first obtains the association relationship between the virtual storage address in the virtualization domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the many-core system; then, after receiving the first data memory access request, obtains the virtual storage address to be accessed by the first data memory access request, namely the first virtual address, and determines the physical storage address corresponding to the first virtual address, namely the first physical address, based on the association relationship obtained previously; finally, performs the access operation of the first data memory access request on the first physical address.

[0013] It can be seen that in the embodiments of the present disclosure, by converting the virtual storage address in the hierarchical shared storage architecture of the software ecosystem of the deployment target neural network into the physical storage address in the processing core of the many-core system of the deployment target neural network, the first processing core can determine the first physical address that actually exists in the many-core system according to the first virtual address provided by the first data memory access request at the software ecosystem level, and perform a memory access operation based on the first physical address, thereby achieving compatibility between the many-core system of the deployment target neural network and the software ecosystem of the deployment target neural network, thereby enabling the many-core system to be quickly integrated into the current AI software ecosystem.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 A schematic diagram of the architecture of a many-core system provided in an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of a hierarchical shared storage architecture provided in an embodiment of the present disclosure;

[0018] Figure 3 A flowchart of a data access method provided by an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of the association relationship between a virtualization domain and a physical storage area provided in an embodiment of the present disclosure

[0020] Figure 5 A schematic diagram of another association relationship between a virtualization domain and a physical storage area provided in an embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a data access method provided by an embodiment of the present disclosure;

[0022] Figure 7 A block diagram of a data access device provided by an embodiment of the present disclosure;

[0023] Figure 8 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0025] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0026] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0029] Many-core chips are an ideal choice for large-scale neural network computing due to their excellent parallel capabilities and flexibility.

[0030] Figure 1 The schematic diagram of the architecture of a multi-core system provided by the embodiment of the present disclosure is as follows. Figure 1 As shown in the figure, the many-core system includes multiple processing cores, each of which is equipped with a private processing unit and storage unit, which can independently execute instructions and access data, that is, the processing cores can use the parallel computing method of multiple instructions and multiple data (MIMD). The processing core also includes a routing unit to connect the routing nodes of the many-core system. The routing unit and the routing nodes are interconnected to form a network on chip (Network-on-Chip, NoC). The processing cores and the processing cores and external devices can communicate through the NoC.

[0031] The processing unit can be used to process data, the storage unit can be used to store data, the processing unit can read data from the storage unit, and can also write data to the storage unit. The data stored in the storage unit can also be sent to other processing cores through the routing unit, and the storage unit can also store data received from other processing cores through the routing unit. For example, the storage unit can be a random access memory (Random Access Memory, RAM), etc., which is not limited in the embodiments of the present disclosure. The routing unit and the routing node constitute an on-chip network.

[0032] Among related technologies, the Graphics Processing Unit (GPU) has taken a dominant position in large-scale neural network computing with its mature software ecosystem and rapid hardware iteration, becoming a commonly used AI software ecosystem. CUDA (Compute Unified Device Architecture) is a parallel computing platform and programming model that can fully utilize the parallel computing capabilities of GPUs to deploy programs. A large number of deep learning frameworks and applications are developed based on CUDA, further consolidating the position of GPUs in the field of AI.

[0033] GPUs generally use streaming multiprocessors (SMs) as the basic parallel processing units. The SMs in GPUs include processing units and private storage. SMs can refer to processing cores in many-core systems. SMs often use single instruction, multiple data (SIMD) parallel computing and use a hierarchical approach to access storage data, making full use of the data locality characteristics in different parallel loads.

[0034] Figure 2 A hierarchical shared storage architecture diagram provided for embodiments of the present disclosure. If Figure 2 As shown in the figure, taking GPU as an example, the hierarchical shared storage architecture includes SM's private storage, primary shared storage shared by multiple SMs, secondary shared storage, and global shared storage shared by all SMs. Figure 2 This is only an exemplary description of the hierarchical shared storage architecture and is not intended to limit the hierarchical relationship and sharing relationship stored in the hierarchical shared storage architecture. The hierarchical shared storage architecture may include fewer or more hierarchies.

[0035] It can be seen that the storage architecture of the AI ​​software ecosystem represented by GPU is a hierarchical shared storage architecture. The storage architecture of many-core chips is a private storage architecture. This makes it difficult for many-core chips to be integrated into the programming and compilation platform designed for the hierarchical shared storage architecture, that is, it is difficult to integrate into the current AI software ecosystem. Therefore, how to quickly integrate many-core systems into the current AI software ecosystem has become an urgent problem to be solved.

[0036] According to the data access method of the embodiment of the present disclosure, the first processing core of the many-core system first obtains the association relationship between the virtual storage address in the virtualization domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the many-core system; then, after receiving the first data access request, obtains the virtual storage address to be accessed by the first data access request, i.e., the first virtual address, and determines the physical storage address corresponding to the first virtual address, i.e., the first physical address, based on the previously obtained association relationship; finally, performs the access operation of the first data access request on the first physical address. It can be seen that in the embodiment of the present disclosure, by converting the virtual storage address in the hierarchical shared storage architecture of the software ecosystem of the target neural network to the physical storage address in the processing core of the many-core system of the target neural network, the first processing core can determine the first physical address that actually exists in the many-core system according to the first virtual address provided by the first data access request at the software ecosystem level, and perform the access operation based on the first physical address, thereby achieving the compatibility between the many-core system of the target neural network and the software ecosystem of the target neural network, so that the many-core system can be quickly integrated into the current AI software ecosystem.

[0037] The data storage access method according to an embodiment of the present disclosure can be applied to the first processing core among the multiple processing cores of a multi-core system. For example, the first processing core may be Figure 1 Any of the many core systems shown are processed.

[0038] According to the data access method of the embodiment of the present disclosure, a target neural network is deployed in multiple processing cores of a many-core system. At the hardware level, the target neural network is deployed in the many-core system. For example, the many-core system can be a many-core chip or board, or any electronic device including a many-core chip or board. At the software level, the target neural network is deployed in a software ecosystem whose storage architecture is a hierarchical shared storage architecture. For example, the software ecosystem can be a CUDA software ecosystem, and the hierarchical shared storage architecture can be a hierarchical shared storage architecture of a GPU.

[0039] The target neural network can be used to perform any one of image processing tasks, speech processing tasks, text processing tasks, and video processing tasks. The disclosed embodiments do not limit the target neural network.

[0040] Figure 3 A flowchart of a data storage method provided for an embodiment of the present disclosure. Reference Figure 3 , the method comprising:

[0041] In step S10, the association relationship between the virtual storage address in the virtualization domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the multi-core system is obtained.

[0042] Among them, the hierarchical shared storage architecture is the storage architecture of the software ecosystem for deploying the target neural network. That is to say, the storage architecture adopted by the software ecosystem for deploying the target neural network is a hierarchical shared storage architecture. In the embodiment of the present disclosure, the hierarchical shared storage architecture may include multiple virtual storage areas, each of which may be referred to as a virtualization domain. The storage address in the virtualization domain may be referred to as a virtual storage address.

[0043] The many-core system includes multiple processing cores, each of which includes physical storage space (which may be referred to as a storage unit), and the storage addresses in these physical storage spaces are the physical storage addresses in the processing core. The storage addresses in the processing core may be referred to as physical storage addresses.

[0044] In the disclosed embodiment, since the target neural network is deployed in a software ecosystem at the software level and in a many-core system at the hardware level, in order to achieve compatibility between software and hardware, the virtual storage addresses in the virtual domain of the hierarchical shared storage architecture and the physical storage addresses in the processing cores of the many-core system are associated.

[0045] When the virtual storage address and the physical storage address are associated, the first processing core can obtain the association relationship between the virtual address in the virtual domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the many-core system.

[0046] In step S11 , in response to receiving a first data access request, a first virtual address is obtained.

[0047] The first data access request may represent a data access request received by the first processing core. The first data access request may be used to request access to a first virtual address. The first virtual address may represent a virtual storage address to be accessed by the first data access request. The first data access request may include the first virtual address.

[0048] Since the software ecosystem for deploying the target neural network adopts a hierarchical shared storage architecture, the storage address carried in the first data access request issued by the software ecosystem should also be a storage address in the hierarchical shared storage architecture. Therefore, the first virtual address is a virtual storage address in the virtualization domain of the hierarchical shared storage architecture.

[0049] In step S12, a physical storage address corresponding to the first virtual address is determined based on the association relationship as a first physical address.

[0050] The first physical address may represent a physical storage address corresponding to the first virtual address. The first physical address is a physical storage address in a processing core of the many-core system, and is a real storage address. Based on the association relationship obtained in step S11, the first processing core may obtain a physical storage address corresponding to the first virtual address, and the physical storage address may be referred to as a first physical address.

[0051] In step S13, the access operation of the first data access request is performed on the first physical address.

[0052] The first data memory access request may be used to request access to the first virtual address and perform a memory access operation at the first virtual address. After the first processing core obtains the first physical address, it may perform the access operation of the first data memory access request on the first physical address.

[0053] The memory access operation may include reading data from the first virtual address or writing data to the first virtual address. Where the memory access operation is to read data from the first virtual address, the first data memory access request also includes the address to which the read data is to be sent; where the memory access operation is to write data to the first virtual address, the first data memory access request also includes the data to be written.

[0054] According to the data access method of the embodiment of the present disclosure, the first processing core of the many-core system first obtains the association relationship between the virtual storage address in the virtualization domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the many-core system; then, after receiving the first data access request, obtains the virtual storage address to be accessed by the first data access request, i.e., the first virtual address, and determines the physical storage address corresponding to the first virtual address, i.e., the first physical address, based on the previously obtained association relationship; finally, performs the access operation of the first data access request on the first physical address. It can be seen that in the embodiment of the present disclosure, by converting the virtual storage address in the hierarchical shared storage architecture of the software ecosystem of the target neural network to the physical storage address in the processing core of the many-core system of the target neural network, the first processing core can determine the first physical address that actually exists in the many-core system according to the first virtual address provided by the first data access request at the software ecosystem level, and perform the access operation based on the first physical address, thereby achieving the compatibility between the many-core system of the target neural network and the software ecosystem of the target neural network, so that the many-core system can be quickly integrated into the current AI software ecosystem.

[0055] In some embodiments, a physical storage area corresponding to a virtualization domain of the hierarchical shared storage architecture may include all or part of a physical storage area in a physical storage space of at least one processing core.

[0056] Assume that the hierarchical shared storage architecture includes N virtualization domains, and the many-core system includes M processing cores. In the disclosed embodiment, the physical storage space of the M processing cores can be uniformly divided into N parts, each corresponding to a virtualization domain. When the physical storage space of the M processing cores is divided, the physical storage space of the same processing core can be divided into the same virtual domain or into different virtualization domains.

[0057] Figure 4 A schematic diagram of the association relationship between a virtualization domain and a physical storage area provided in an embodiment of the present disclosure. Figure 4 As shown in FIG. 1 , the hierarchical shared storage architecture includes four virtualization domains, namely virtualization domain 1, virtualization domain 2, virtualization domain 3, and virtualization domain 4; the many-core system includes nine processing cores, each of which includes physical storage space. The physical storage space of the nine processing cores of the many-core system is uniformly divided into four parts, each of which corresponds to a virtualization domain.

[0058] For ease of description, in the embodiment of the present disclosure, C[i,j] is used to represent the processing core in the i-th row and j-th column of the many-core system, where i and j are positive integers. Figure 4 As shown, taking virtualization domain 1 as an example, the physical storage area corresponding to virtualization domain 1 includes part of the physical storage area in the physical storage space of C[2,2], all the physical storage areas in the physical storage space of C[2,3], all the physical storage areas in the physical storage space of C[3,2], and all the physical storage areas in the physical storage space of C[3,3].

[0059] In some possible implementations, the hierarchical shared storage architecture may further include a hierarchical relationship between virtualization domains, a sharing relationship between virtualization domains, and a storage capacity of a physical storage area corresponding to each virtualization domain.

[0060] like Figure 4 As shown, the hierarchical shared storage architecture includes four virtualization domains. The hierarchical relationship between the virtualization domains is: virtualization domain 1, virtualization domain 2 and virtualization domain 4 are at a lower level, and virtualization domain 3 is at a lower level. The sharing relationship between the virtualization domains is: processing unit 1 and processing unit 2 exclusively occupy virtualization domain 1 and virtualization domain 2 respectively, processing unit 2 and processing unit 4 share virtualization domain 4 respectively, and processing unit 1, processing unit 2, processing unit 3 and processing unit 4 share virtualization domain 4.

[0061] The storage capacity of the physical storage area corresponding to each virtualization domain can be determined according to the needs of the software ecosystem. This embodiment of the present disclosure does not limit this.

[0062] In some possible implementations, physical storage areas corresponding to a same virtualization domain are distributed in processing cores at preset positions of the many-core system.

[0063] The processing cores at the preset positions of the many-core system may refer to multiple processing cores in the preset area of ​​the many-core system, or may refer to multiple adjacent processing cores in the many-core system. In the embodiments of the present disclosure, the data locality of the virtualization domain can be improved by allowing the physical storage areas corresponding to the same virtualization domain to be distributed as much as possible in the processing cores with shorter communication distances between each other. Figure 4 As shown, the physical storage area corresponding to virtualization domain 1 is distributed in adjacent C[2,2], C[2,3], C[3,2] and C[3,3], which improves the data locality of virtualization 1.

[0064] In some possible implementations, the physical storage areas corresponding to the same virtualization domain are distributed among a preset number of processing cores of the many-core system.

[0065] Among them, the preset number can be set as needed, for example, the preset number can be determined according to the hierarchical relationship and sharing relationship of the virtualization domain. For example, the higher the level of the virtualization domain, the larger the preset number; the more computing units the virtualization domain is shared by, the larger the preset number, etc. In the embodiment of the present disclosure, by distributing the physical storage area corresponding to the same virtualization domain to multiple processing cores as much as possible, the concurrent memory access performance of the virtual domain can be improved. For a globally shared virtualization domain, the larger the preset number, the stronger the concurrency performance.

[0066] In some possible implementations, the intersection of physical storage areas corresponding to different virtualization domains may be a non-empty set.

[0067] Figure 5 Another schematic diagram of the association relationship between a virtualization domain and a physical storage area provided in an embodiment of the present disclosure. Figure 5 As shown, the many-core system includes 8 processing cores, wherein the physical storage area corresponding to virtualization domain 1 includes all physical storage areas of the physical storage space of C[1,1], all physical storage areas of the physical storage space of C[1,2], all physical storage areas of the physical storage space of C[2,1], and part of the physical storage area of ​​the physical storage space of C[2,2]. The physical storage area corresponding to virtualization domain 2 includes all physical storage areas of the physical storage space of C[2,1], all physical storage areas of the physical storage space of C[2,2], and all physical storage areas of the physical storage space of C[2,3]. It can be seen that the intersection of the physical storage areas corresponding to virtualization domain 1 and virtualization domain 2 is: all physical storage areas of the physical storage space of C[2,1] and part of the physical storage area of ​​the physical storage space of C[2,2], and the intersection is a non-empty set.

[0068] It should be noted that the intersection of the physical storage areas corresponding to different virtualization domains may also be an empty set. Figure 5 As shown, the intersection of the physical storage areas corresponding to the virtualization domain 1 and the virtualization domain 3 is an empty set, and the intersection of the physical storage areas corresponding to the virtualization domain 2 and the virtualization domain 3 is an empty set.

[0069] In the disclosed embodiment, different virtualization domains are set to correspond to the same physical storage area (ie, the intersection is a non-empty set), so that data can be directly shared between different virtualization domains, which facilitates direct data transmission between different virtualization domains.

[0070] In some embodiments, step S10 determines the association relationship between the virtual storage address in the virtualization domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the many-core system, which may include step S101, and step S12 determines the physical storage address corresponding to the first virtual address based on the association relationship as the first physical address, which may include steps S121 and S122:

[0071] In step S101, a page table stored in the first processing core is obtained, where the page table is used to indicate the association relationship.

[0072] In step S121, the first virtual address is searched in the page table.

[0073] In step S122, when the first virtual address is found, the physical storage address associated with the first virtual address in the page table is determined as the first physical address.

[0074] Considering that the hierarchical shared storage architecture is formed by virtualizing different levels of virtualization domains on real physical hardware. The original physical hardware design of the many-core system cannot be changed in this process, and the processing core of the many-core system still needs to use its original data access strategy, including its original physical storage address system and NoC. Therefore, in the embodiment of the present disclosure, it is necessary to use a page table to associate the virtual storage address with the physical storage address.

[0075] In some possible implementations, a page table is stored in the first processing core, for example, a page table is stored in the physical storage space of the first processing core. The page table can be used to indicate the association between the virtual storage address in the virtualization domain and the physical storage address in the processing core.

[0076] The first processing core may search for the first virtual address in the locally stored page table. If the first virtual address is found, the physical storage address corresponding to the first virtual address found in the page table is determined as the first physical address. In this way, the mapping from the virtual storage address to the physical storage address is realized by searching the page table, and the real physical storage address is provided for the subsequent access operation, thereby providing the conditions for implementing the access operation.

[0077] In some possible implementations, the physical storage addresses in the page table locally stored by the first processing core may all be storage addresses in the physical storage space of the first processing core; or may include both storage addresses in the physical storage space of the first processing core and storage addresses in the physical storage spaces of other processing cores. It is understandable that the more storage addresses in the physical storage spaces of the processing cores included in the page table, the more storage resources the page table occupies, and the longer it takes to search the page table.

[0078] If the first processing core does not find the first virtual address in the locally stored page table, it indicates that the first physical address is not in the physical storage space of the first processing core, or the processing core where the first physical address is located is far away from the first processing core in communication. At this time, the first processing core can send a second data memory access request to other processing cores through the on-chip network to request other processing cores to perform a memory access operation. The second data memory access request can refer to the first data memory access request and will not be described in detail here.

[0079] In some possible implementations, the first virtualization domain is a virtual storage address in the first virtualization domain, the first virtual address includes an identifier of the first virtualization domain and a first intra-domain address, and the first intra-domain address is used to indicate an intra-domain address offset of the first virtualization domain.

[0080] The first virtual address is a virtual storage address in the first virtualization domain of the hierarchical shared storage architecture. The first virtual address includes an identifier of the first virtualization domain and an address within the first domain. Based on the identifier of the first virtualization domain, the first virtual domain where the first virtual address is located can be determined, and based on the address within the first domain, the domain address offset of the first virtual address in the first virtual domain can be determined.

[0081] The page table includes a plurality of records, each record including an identifier of a virtualization domain, an address range of a virtual storage address, an identifier of a processing core, and an address range of a physical storage address.

[0082] The identifier of the virtualization domain is used to identify a unique virtualization domain, and the identifier of the processing core is used to identify a unique processing core. The identifier of the virtualization domain may be an ID or a number, etc., which is not limited in the embodiments of the present disclosure. The identifier of the processing core may be a communication address or location information of the processing core, etc., which is not limited in the embodiments of the present disclosure.

[0083] The address range of the virtual storage address may include a virtual storage address start address and an end address, which may be referred to as a first start address and a first end address in the embodiment of the present disclosure. The address range of the physical storage address may include a physical storage address start address and an end address, which may be referred to as a second start address and a second end address in the embodiment of the present disclosure.

[0084] Correspondingly, step S121 searching for the first virtual address in the page table stored in the first processing core may include step S1211, and step S122, when the first virtual address is found, determining the physical storage address associated with the first virtual address in the page table as the first physical address may include steps S1221 to S1223.

[0085] In step S1211, a target record is searched among the multiple records.

[0086] The identifier of the virtualization domain of the target record is the identifier of the first virtualization domain and the virtual storage address range of the target record includes the address within the first domain.

[0087] When the virtualization domain identifier included in a record in the page table is the identifier of the first virtualization domain, and the virtual storage address range included in the record includes the address in the first domain, it indicates that the record corresponds to the first virtualization address. Therefore, the record can be determined as the target record.

[0088] In step S1221, the target processing core to be accessed is determined according to the identifier of the processing core of the target record.

[0089] In step S1222, when the target processing core is the first processing core, the core address offset is determined according to the first domain address and the virtual storage address range of the target record.

[0090] When the target processing core is the first processing core, it indicates that the first physical address is in the physical storage space of the first processing core. At this time, the specific position of the first physical address in the physical storage space of the first processing core needs to be determined.

[0091] In one example, the first processing core may determine a difference between the first domain address and the first start address, and then determine the difference as an intra-core address offset. The intra-core address offset may be used to indicate an offset of the first physical address in a physical storage space of the first processing core.

[0092] In step S1223, in the physical storage space of the first processing core, the first physical address is determined according to the intra-core address offset and the physical storage address range of the target record.

[0093] In one example, the first processing core may add the second start address to the core address offset to obtain the first physical address.

[0094] In the disclosed embodiment, query efficiency can be improved by setting the identifier of the virtual domain and the address within the domain.

[0095] In some embodiments, step S13 of performing the access operation of the first data access request on the first physical address may include step S131:

[0096] In step S131, when the target processing core is the first processing core, data is read from the first physical address of the physical storage space of the first processing core or data is written to the first physical address of the physical storage space of the first processing core.

[0097] When the target processing core is the first processing core, it indicates that the first physical address is in the physical storage space of the first processing core. Therefore, the first processing core can read or write data at the first physical address in the local physical storage space.

[0098] In the embodiments of the present disclosure, by converting the virtual storage address to the physical storage address, the local physical storage space can be accessed, and fast data reading and writing can be achieved, thereby improving efficiency.

[0099] In some embodiments, the data access method of the embodiment of the present disclosure may further include step S14:

[0100] In step S14, when the target processing core is the second processing core, a second data memory access request is sent to the second processing core.

[0101] The second processing core is one of the plurality of processing cores, and the second processing core is in communication connection with the first processing core. That is, the second processing core and the first processing core represent different processing cores in the many-core system.

[0102] When the target processing core is the second processing core, it indicates that the first physical address is not in the physical storage space of the first processing core, and the first processing core cannot read or write data at the first physical address locally. Therefore, the first processing core needs to send a second data access request to the second processing core.

[0103] The second data access request is used to access the first virtual address. The second data access request may represent a data access request sent by the first processing core to the second processing core. The second data access request may refer to the first data access request. The process of the second processing core processing the second data access request may refer to the process of the first processing core processing the first data access request (steps S11 to S13), which will not be repeated here.

[0104] In an embodiment of the present disclosure, when a first data memory access request is received by a first processing core, when the first physical address is in other processing cores, the data read and write requirements of the first processing core are converted into data transmission requirements between the first processing core and the second processing core.

[0105] Figure 6 A schematic diagram of a data access method provided by an embodiment of the present disclosure. Figure 6 As shown, the method may include: a first processing core receives a first data memory access request, and obtains a first virtual address in response to the first data memory access request; the first processing core searches for a target record in multiple records of a locally stored page table, and determines a target processing core to be accessed based on an identifier of the processing core of the target record.

[0106] like Figure 6 The local branch shown: if the target processing core is the first processing core, the first processing core first determines the in-core address offset according to the first in-domain address and the virtual storage address range of the target record; then, in the physical storage space of the first processing core, the first physical address is determined according to the in-core address offset and the physical storage address range of the target record; then, data is read from the first physical address of the physical storage space of the first processing core or data is written to the first physical address of the physical storage space of the first processing core; finally, a response to the first data access request is returned. It can be understood that, in the case of reading data from the first physical address, the response to the first data access request may include the read data; in the case of writing data to the first physical address, the response to the first data access request may include the written storage address.

[0107] like Figure 6 The external branch shown: if the target processing core is the second processing core, the first processing core sends a second memory access request to the second processing core through the routing unit; then, the first processing core receives a response to the second memory access request returned by the second processing core; finally, the first processing core returns a response to the first memory access request based on the response to the second memory access request.

[0108] Among them, the second memory access request can refer to the first memory access request, the response to the second memory access request can refer to the response to the first memory access request, and the steps executed by the second processing core after receiving the second memory access request can refer to the steps executed by the first processing core after receiving the first memory access request, which will not be repeated here.

[0109] In some embodiments, the hierarchical relationship, sharing relationship and storage capacity ratio of corresponding physical storage areas between virtualization domains in the hierarchical shared storage architecture are adjusted based on one or more of the following: storage utilization of the physical storage area; memory access frequency of the physical storage area; routing congestion level of the many-core system.

[0110] In one example, if the storage utilization rate of the physical storage area corresponding to a virtualization domain is high, the storage capacity of the physical storage area corresponding to the virtualization domain is increased, for example, more physical storage areas of the physical storage space of the processing core are corresponded to the virtualization domain, or more physical storage areas in the physical storage space of the processing core are corresponded to the virtualization domain. Conversely, the physical storage area corresponding to the virtualization domain can be reduced.

[0111] In one example, if the access frequency of the physical storage address in a physical storage area is high, the level of the virtualization domain corresponding to the physical storage area is increased. Otherwise, the level of the virtualization domain corresponding to the physical storage area is decreased.

[0112] In one example, if a processing core accesses the physical storage area corresponding to a higher-level virtualization domain multiple times, a direct communication relationship between the computing core domain and the physical storage area will be established, so that the processing core can directly access the higher-level virtualization domain. This can reduce the sending of data access requests and save communication resources within the many-core system.

[0113] In one example, if the routing congestion level is high, the correspondence between the virtualization domain and the physical storage area is adjusted to reduce the total length of data transmission. In another example, if the routing congestion level is high, the first physical address corresponding to the first data access request is dispersed in different processing cores.

[0114] In some possible embodiments, the many-core system may pre-configure an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture and a physical storage address in a processing core of the many-core system. Based on this association relationship, the first processing core may perform an access operation of the first data memory access request through steps S10 to S13. It should be noted that the pre-configuration process may be performed by an upper-layer control system of a processing core in the many-core system, or may be performed by a processing core in the many-core system.

[0115] The following takes the pre-configuration process performed by the first processing core as an example to describe the pre-configuration process of the data access method according to the embodiment of the present disclosure. The method may also include a pre-configuration process, which may include steps S15 to S17:

[0116] In step S15, a plurality of virtualization domains included in the hierarchical shared storage architecture are determined according to the storage architecture required by the software ecosystem for deploying the target neural network.

[0117] The first processing core may first determine the storage architecture required for the software ecosystem for deploying the target neural network, which is called a hierarchical shared storage architecture; and then determine the number of virtualization domains constituting the storage architecture, the hierarchical relationship and sharing relationship between each virtualization domain, and the storage capacity of each virtualization domain. In other words, the first processing core determines the multiple virtualization domains included in the hierarchical shared storage architecture.

[0118] The levels of the virtualization domain may include private storage, primary shared storage, secondary shared storage, and global shared storage, etc., which is not limited in the embodiments of the present disclosure.

[0119] In step S16, the physical storage spaces of the multiple processing cores of the many-core system are uniformly divided into multiple groups of physical storage areas, so that the multiple groups of physical storage areas correspond to the multiple virtualization domains one by one.

[0120] The first processing core can uniformly divide the physical storage space of each processing core of the many-core system into multiple groups of physical storage areas, so that the multiple groups of physical storage areas correspond one-to-one with the multiple virtualization domains. In this way, each group of physical storage areas corresponds to a virtualization domain, so according to the hierarchical relationship and sharing relationship between the multiple virtualization domains and the storage capacity of each virtualization domain, the hierarchical relationship, sharing relationship between the groups of physical storage areas and the storage capacity of each group of physical storage areas can be determined. For example, assuming that the many-core system includes M processing cores, the physical storage areas of the physical storage space of the M processing cores are divided into N groups of physical storage areas, and the N groups of physical storage areas correspond one-to-one with the N virtualization domains.

[0121] Each group of physical storage areas includes all or part of the physical storage areas in at least one processing core of the many-core system. For example, a group of physical storage areas may include all the storage areas of a processing core, or a group of physical storage areas may include part of the storage areas of a processing core, or a group of physical storage areas may include all the storage areas of a processing core and part of the storage areas of another processing core, and so on.

[0122] The physical storage area corresponding to a virtualization domain is actually a group of physical storage areas corresponding to the virtualization domain.

[0123] In a possible implementation, the physical storage area corresponding to a virtualization domain is distributed as much as possible in a series of connected processing cores, thereby improving the data locality of the shared storage.

[0124] In a possible implementation, a physical storage area corresponding to a virtualization domain is dispersed as much as possible among multiple processing cores, thereby improving the concurrent access performance of virtual storage. In one example, if a virtualization domain is a global shared storage, the physical storage area corresponding to the virtualization domain is dispersed as much as possible among multiple processing cores.

[0125] In step S17, the association relationship is established based on the correspondence between the multiple groups of physical storage areas and the multiple virtualization domains.

[0126] The storage address in the physical storage area is the physical storage address, and the storage address in the virtualization domain is the virtual storage address. The first processing core can establish an association relationship between the virtual storage address in the virtualization domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the many-core system based on the correspondence between the multiple groups of physical storage areas and the multiple virtualization domains.

[0127] On the basis of establishing the above-mentioned association relationship, the first processing core can set a virtualization address protocol. Set a unique identifier for each virtualization domain (i.e., the identifier of the virtualization domain), and allow each virtualization domain to be independently addressed (i.e., the address offset within the domain). When the processing core wants to access a virtual address, the virtual address used is the identifier of the virtualization domain + the address within the domain. In this way, the virtualization domain can be found first through the identifier of the virtualization domain (such as ID), and then the data within the virtual domain can be found through the address within the domain. The above-mentioned association relationship can be configured in the first processing core in the form of a page table. After completing the above configuration process, the first processing core can execute steps S10 to S13.

[0128] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0129] In addition, the present disclosure also provides a data access device, an electronic device, and a computer-readable storage medium, all of which can be used to implement any data access method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to in the corresponding records of the method part and will not be repeated here.

[0130] Figure 7 A block diagram of a data access device provided in an embodiment of the present disclosure.

[0131] Reference Figure 7The embodiment of the present disclosure provides a data access device, which is applied to a first processing core among multiple processing cores of a many-core system, wherein a target neural network is deployed in the multiple processing cores of the many-core system. The data access device 70 includes:

[0132] An acquisition module 700 is used to acquire an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture and a physical storage address in a processing core of the many-core system, wherein the hierarchical shared storage architecture is a storage architecture of a software ecosystem in which the target neural network is deployed;

[0133] A response module 701 is configured to obtain a first virtual address in response to receiving a first data memory access request, where the first virtual address represents a virtual storage address to be accessed by the first data memory access request;

[0134] A determination module 702 is configured to determine, based on the association relationship, a physical storage address corresponding to the first virtual address as a first physical address;

[0135] The execution module 703 is used to execute the access operation of the first data memory access request on the first physical address.

[0136] Figure 8 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0137] Reference Figure 8 An embodiment of the present disclosure provides an electronic device, which includes multiple processing cores 1001 and an on-chip network 1002, wherein the multiple processing cores 1001 are connected to the on-chip network 1002, and the on-chip network 1002 is used to exchange data between the multiple processing cores and external data.

[0138] One or more instructions are stored in one or more processing cores 1001, and the one or more instructions are executed by one or more processing cores 1001, so that one or more processing cores 1001 can execute the above-mentioned data access method.

[0139] In some embodiments, the electronic device may be a brain-like chip, which can use vectorized computing and needs to load the weight information and other parameters of the neural network model through an external memory such as a double data rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing used in the embodiments of the present disclosure has a higher computing efficiency.

[0140] The embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned data access method when executed by the processing core. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0141] The embodiment of the present disclosure also provides a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned data access method.

[0142] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0143] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A data access method, characterized in that: The method is applied to a first processing core among multiple processing cores of a many-core system, wherein a target neural network is deployed in the multiple processing cores of the many-core system, and the method includes: Acquire an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture and a physical storage address in a processing core of the many-core system, wherein the hierarchical shared storage architecture is a storage architecture of a software ecosystem in which the target neural network is deployed; In response to receiving a first data memory access request, obtaining a first virtual address, wherein the first virtual address represents a virtual storage address to be accessed by the first data memory access request; Determine, based on the association relationship, a physical storage address corresponding to the first virtual address as a first physical address; An access operation of the first data memory access request is performed on the first physical address.

2. The method according to claim 1, characterized in that The physical storage area corresponding to the virtualization domain includes all or part of the physical storage area in the physical storage space of at least one processing core.

3. The method according to claim 2, characterized in that The physical storage areas corresponding to the same virtualization domain are distributed in the processing cores at preset positions of the many-core system; and / or, The physical storage areas corresponding to the same virtualization domain are distributed among a preset number of processing cores of the many-core system; and / or, The intersection of physical storage areas corresponding to different virtualization domains is a non-empty set.

4. The method according to claim 1, characterized in that: The determining of the association relationship between the virtual storage address in the virtualization domain of the hierarchical shared storage architecture and the physical storage address in the processing core of the many-core system includes: Obtaining a page table stored in the first processing core, wherein the page table is used to indicate the association relationship; The determining, based on the association relationship, a physical storage address corresponding to the first virtual address as the first physical address includes: Searching the first virtual address in the page table; When the first virtual address is found, the physical storage address associated with the first virtual address in the page table is determined as the first physical address.

5. The method according to claim 4, characterized in that The first virtual address is a virtual storage address in the first virtualization domain, the first virtual address includes an identifier of the first virtualization domain and a first intra-domain address, the first intra-domain address is used to indicate an intra-domain address offset of the first virtualization domain; the page table includes a plurality of records, each record includes an identifier of the virtualization domain, an address range of the virtual storage address, an identifier of a processing core, and an address range of a physical storage address, wherein the identifier of the virtualization domain is used to identify a unique virtualization domain, and the identifier of the processing core is used to identify a unique processing core; The searching the first virtual address in the page table includes: Searching for a target record in the multiple records, wherein the identifier of the virtualization domain of the target record is the identifier of the first virtualization domain and the virtual storage address range of the target record includes the address within the first domain; The step of determining the physical storage address associated with the first virtual address in the page table as the first physical address comprises: Determining a target processing core to be accessed according to an identifier of the processing core of the target record; In a case where the target processing core is the first processing core, determining an intra-core address offset according to the first intra-domain address and a virtual storage address range of the target record; In the physical storage space of the first processing core, the first physical address is determined according to the intra-core address offset and the physical storage address range of the target record.

6. The method according to claim 5, characterized in that: The access operation of performing the first data access request on the first physical address includes: When the target processing core is the first processing core, data is read from the first physical address of the physical storage space of the first processing core or data is written to the first physical address of the physical storage space of the first processing core.

7. The method according to claim 5, characterized in that The method further comprises: In the case where the target processing core is a second processing core, a second data memory access request is sent to the second processing core, the second processing core is one of the multiple processing cores, the second processing core is communicatively connected to the first processing core, and the second data memory access request is used to access the first virtual address.

8. The method according to claim 1, characterized in that The hierarchical shared storage architecture includes a hierarchical relationship between virtualization domains, a sharing relationship between virtualization domains, and a storage capacity of a physical storage area corresponding to each virtualization domain; The hierarchical relationship, sharing relationship and storage capacity ratio of the corresponding physical storage areas between the virtualization domains are adjusted according to one or more of the following: Storage utilization of physical storage areas; The access frequency of the physical storage area; Routing congestion level of many-core systems.

9. The method according to claim 1, characterized in that: The method further comprises: Determining a plurality of virtualization domains included in the hierarchical shared storage architecture according to a storage architecture required by a software ecosystem for deploying the target neural network; uniformly dividing the physical storage spaces of the multiple processing cores of the many-core system into multiple groups of physical storage areas, so that the multiple groups of physical storage areas correspond to the multiple virtualization domains one by one, wherein each group of physical storage areas includes all or part of the physical storage areas of at least one processing core of the many-core system; The association relationship is established based on the correspondence between the multiple groups of physical storage areas and the multiple virtualization domains.

10. A data access device, characterized in that: The device is applied to a first processing core among multiple processing cores of a many-core system, wherein a target neural network is deployed in the multiple processing cores of the many-core system, and the device includes: an acquisition module, configured to acquire an association relationship between a virtual storage address in a virtualization domain of a hierarchical shared storage architecture and a physical storage address in a processing core of the many-core system, wherein the hierarchical shared storage architecture is a storage architecture of a software ecosystem in which the target neural network is deployed; A response module, configured to obtain a first virtual address in response to receiving a first data memory access request, wherein the first virtual address represents a virtual storage address to be accessed by the first data memory access request; A determination module, configured to determine, based on the association relationship, a physical storage address corresponding to the first virtual address as a first physical address; An execution module is used to execute an access operation of the first data memory access request on the first physical address.

11. An electronic device, characterized in that: include: Multiple processing cores; as well as An on-chip network is configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the data access method described in any one of claims 1-9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processing core, the computer program implements the data access method according to any one of claims 1 to 9.

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