A control circuit for an interrupt signal and an electronic device

Abstract

The embodiment of the present application provides a control circuit of an interrupt signal and electronic equipment, the circuit comprises a first register, a second register, a third register, a multiplexer and an XOR gate, a first output end of the first register and a third positive output end of the third register are connected to a fifth input end and a sixth input end of the XOR gate respectively, when signals of the fifth input end and the sixth input end are the same, an interrupt signal is a first value, indicating that the interrupt is cleared, when signals of the fifth input end and the sixth input end are different, the interrupt signal is a second value, indicating that the interrupt is generated, so that only three cascaded registers, a multiplexer and an XOR gate are used to control generation and clearing of the interrupt signal, and the interrupt signal can be reliably and stably generated and cleared under the condition of low hardware overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of control circuit, in particular to an interrupt signal control circuit and electronic equipment. BACKGROUND

[0002] In the design of digital circuit, the interrupt signal of each module in the system on chip is an important window for the interaction between hardware and software. The hardware circuit generates a reliable and stable interrupt signal to correctly access the CPU (Central Processing Unit); the CPU performs a clear operation on the interrupt signal after executing a related scheduling scheme. The reliable and stable generation and correct clear of the interrupt signal are crucial steps in system operation. For chip production, the smaller the area, the lower the cost. However, at present, it is difficult to reliably and stably generate and clear the interrupt signal under the condition of low hardware overhead, and there are problems of interrupt signal generation error, CPU error influence and inability to correctly respond to CPU clear operation. SUMMARY

[0003] In view of the above problems, the present application embodiment is proposed to provide an interrupt signal control circuit and electronic equipment which can overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, the present application embodiment discloses an interrupt signal control circuit, characterized in that the circuit comprises: a first register, a second register, a third register, a multiplexer and an XOR gate.

[0005] The first register comprises a first input end and a first output end.

[0006] The second register comprises a second input end and a second output end; the second input end is connected with the first output end, and is configured to receive the first output signal of the first register.

[0007] The third register comprises a third input end, a third positive output end and a third negative output end; the third input end is connected with the second output end, and is configured to receive the second output signal of the second register.

[0008] The multiplexer comprises a fourth positive input end, a fourth negative input end and a fourth output end; the fourth positive input end is connected with the third positive output end; the fourth negative input end is connected with the third negative output end; the fourth output end is connected with the first input end; and the fourth output end is configured to output based on the input signal of the fourth positive input end or the input signal of the fourth negative input end.

[0009] The exclusive OR gate comprises a fifth input end, a sixth input end and a fifth output end; the fifth input end is connected with the first output end; the sixth input end is connected with the third positive output end; the exclusive OR gate is used for outputting an interrupt signal as a first value to represent interrupt clearing when signals at the fifth input end and the sixth input end are the same, and outputting the interrupt signal as a second value to represent interrupt generation when signals at the fifth input end and the sixth input end are different.

[0010] Optionally, the multiplexer comprises a control end; the control end is used for receiving a selection signal and controlling the fourth output end to output based on an input signal of the fourth positive input end or an input signal of the fourth negative input end according to the selection signal.

[0011] Optionally, in a case where the selection signal is the first value, the control end is used for controlling the fourth output end to output based on the input signal of the fourth positive input end; in a case where the selection signal is the second value, the control end is used for controlling the fourth output end to output based on the input signal of the fourth negative input end.

[0012] Optionally, the second register comprises a second trigger enable end used for receiving an interrupt clear signal; the third register comprises a third trigger enable end used for receiving an inverted signal of the interrupt clear signal;

[0013] In a case where the interrupt clear signal is the first value, an output signal of the second output end remains a current output signal; the inverted signal of the interrupt clear signal is the second value, and an output signal of the third positive output end is updated to the output signal of the second output end;

[0014] In a case where the interrupt clear signal is the second value, the output signal of the second output end is updated to an input signal of the second input end; the inverted signal of the interrupt clear signal is the first value, and the output signal of the third positive output end remains a current output signal.

[0015] Optionally, the first register further comprises a first clock end, a first reset end and a first trigger enable end, the first trigger enable end is used for receiving an enable signal; the second register further comprises a second clock end and a second reset end; the third register further comprises a third clock end and a third reset end; the multiplexer comprises a fourth trigger enable end used for receiving the enable signal;

[0016] In the initialization, the first clock terminal, the second clock terminal and the third clock terminal are used for receiving clock signals respectively; the first reset terminal, the second reset terminal and the third reset terminal are used for receiving reset signals respectively; the interrupt clear signal is configured as the first value, the selection signal is configured as the first value, and the enable signal is configured as the first value; so that the first output terminal outputs the first value, the second output terminal outputs the first value, the third positive output terminal outputs the first value, and the interrupt signal is the first value.

[0017] Optionally, after the initialization, when a first preset condition is met, the selection signal and the enable signal are configured as a second value; when the selection signal and the enable signal are configured as the second value, the input terminal of the multiplexer is the fourth negative input terminal, the fourth output terminal outputs the second value, so that the first input terminal outputs the second value; after one clock cycle, the first output terminal outputs the second value; the second output terminal outputs the first value; the third positive output terminal outputs the first value; so that the fifth output terminal outputs an interrupt signal as the second value, indicating that an interrupt is generated.

[0018] Optionally, when the fifth output terminal outputs an interrupt signal as the second value, and when the interrupt clear signal is configured as the second value, the second output terminal outputs the second value; the third positive output terminal outputs the first value; after one clock cycle, the interrupt clear signal is configured as the first value; the third positive output terminal outputs the second value; so that the fifth output terminal outputs an interrupt signal as the first value, indicating that the interrupt is cleared.

[0019] Optionally, after the fifth output terminal outputs an interrupt signal as the second value, when a second preset condition is met, the selection signal is configured as the first value; when the selection signal is configured as the first value, the input terminal of the multiplexer is the fourth positive input terminal, the fourth output terminal outputs the first value, so that the first input terminal outputs the first value; after one clock cycle, the first output terminal outputs the first value; the second output terminal outputs the first value; the third positive output terminal outputs the first value; so that the fifth output terminal outputs an interrupt signal as the first value, indicating that the interrupt is cleared.

[0020] Optionally, the first preset condition is detecting an interrupt event; and the second preset condition is detecting an interrupt clear event.

[0021] Correspondingly, the embodiment of the present application discloses an electronic device comprising the interrupt signal control circuit as described above.

[0022] Embodiments of the present application include the following advantages:

[0023] The interrupt signal control circuit of the embodiment of the present application comprises a first register, a second register, a third register, a multiplexer and an XOR gate. The first register comprises a first input end and a first output end. The second register comprises a second input end and a second output end. The second input end is connected with the first output end for receiving the first output signal of the first register. The third register comprises a third input end, a third positive output end and a third negative output end. The third input end is connected with the second output end for receiving the second output signal of the second register. The multiplexer comprises a fourth positive input end, a fourth negative input end and a fourth output end. The fourth positive input end is connected with the third positive output end. The fourth negative input end is connected with the third negative output end. The fourth output end is connected with the first input end. The fourth output end is configured to output based on the input signal of the fourth positive input end or the input signal of the fourth negative input end. The XOR gate comprises a fifth input end, a sixth input end and a fifth output end. The fifth input end is connected with the first output end. The sixth input end is connected with the third positive output end. The XOR gate is used to output the interrupt signal as a first value when the signals of the fifth input end and the sixth input end are the same, indicating interrupt clearing, and output the interrupt signal as a second value when the signals of the fifth input end and the sixth input end are different, indicating interrupt generation. By connecting the first output end of the first register and the third positive output end of the third register with the fifth input end and the sixth input end of the XOR gate respectively, the interrupt signal is output as the first value when the signals of the fifth input end and the sixth input end are the same, indicating interrupt clearing, and the interrupt signal is output as the second value when the signals of the fifth input end and the sixth input end are different, indicating interrupt generation. Thus, only three cascaded registers, a multiplexer and an XOR gate are used to control the generation and clearing of the interrupt signal, and the interrupt signal can be reliably and stably generated and cleared under the condition of low hardware overhead. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structural schematic diagram of an interrupt signal control circuit of the embodiment of the present application;

[0025] Figure 2 is a structural schematic diagram of another interrupt signal control circuit of the embodiment of the present application.

[0026] Reference signs: first register 10, first input end 11, first output end 12, first clock end 13, first reset end 14, first trigger enable end 15, second register 20, second input end 21, second output end 22, second trigger enable end 23, second clock end 24, second reset end 25, third register 30, third input end 31, third positive output end 32, third negative output end 33, third trigger enable end 34, third clock end 35, third reset end 36, multiplexer 40, fourth positive input end 41, fourth negative input end 42, fourth output end 43, control end 44, fourth trigger enable end 45, exclusive-OR gate 50, fifth input end 51, sixth input end 52, fifth output end 53. DETAILED DESCRIPTION

[0027] In order to make the above-mentioned purpose, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0028] In digital circuit design, the interrupt signal of each module of the chip in the system is an important window for the interaction of hardware and software. The hardware circuit generates a reliable and stable interrupt signal to correctly access the CPU; the CPU performs a clear operation on the interrupt signal after executing a related scheduling scheme. The reliable and stable generation and correct clearing of the interrupt signal are crucial steps in system operation. For chip production, the smaller the area, the lower the cost. However, at present, it is difficult to reliably and stably generate and clear the interrupt signal under the condition of low hardware overhead, and there are problems of interrupt signal generation error, CPU error influence and inability to correctly respond to the CPU clear operation.

[0029] One of the core ideas of the embodiment of the present application is that the fifth input end and the sixth input end of the exclusive-OR gate are connected to the first output end of the first register and the third positive output end of the third register respectively. When the signals at the fifth input end and the sixth input end are the same, the output interrupt signal is the first value, indicating interrupt clearing. When the signals at the fifth input end and the sixth input end are different, the output interrupt signal is the second value, indicating interrupt generation. Thus, only three cascaded registers, one multiplexer and one exclusive-OR gate are used to control the generation and clearing of the interrupt signal, and the reliable and stable generation and clearing of the interrupt signal are realized under the condition of low hardware overhead.

[0030] REFERENCE Figure 1 Fig. 1 shows a structure schematic diagram of an interrupt signal control circuit according to an embodiment of the present application, which can specifically include the following structure: a first register 10, a second register 20, a third register 30, a multiplexer 40 and an exclusive-OR gate 50.

[0031] Registers are an important component of computer hardware, used for temporary storage of data and instructions. They are located inside the Central Processing Unit (CPU) and are the fastest storage units that the CPU can access directly. The main role of registers is to speed up data processing and operations, as they are faster than main memory.

[0032] The first register 10 includes a first input end 11 and a first output end 12, and INT_1 is the output of the first register 10.

[0033] The port of a register generally refers to the interface between the register and external devices or internal components. These ports are used for the input and output of data, as well as the transmission of control signals. The input port is used to load data from external devices or internal components into the register, and the output port is used to send data in the register to external devices or internal components.

[0034] The second register 20 includes a second input end 21 and a second output end 22, the second input end 21 is connected with the first output end 12 for receiving the first output signal of the first register 10, and INT_2 is the output of the second register 20.

[0035] The third register 30 includes a third input end 31, a third positive output end 32, and a third negative output end 33, the third input end 31 is connected with the second output end 22 for receiving the second output signal of the second register 20.

[0036] The third register 30 has two output ends, namely the third positive output end 32 and the third negative output end 33, where the third positive output end 32 represents the current value stored in the register, and the third negative output end 33 represents the inverse (i.e. negation) of the current value. INT_3 is the output of the third positive output end 32 of the third register 30, and ~INT_3 is the output of the third negative output end 33 of the third register 30.

[0037] The first register 10, the second register 20, and the third register 30 are three cascaded registers, which means that multiple registers are connected in series to form a longer shift register or storage unit. Cascaded registers are commonly used for applications such as shift operations, data delay, pipeline processing, etc. Each register has its own input and output ports, and works synchronously through a clock signal.

[0038] The multiplexer 40 includes a fourth positive input end 41, a fourth negative input end 42, and a fourth output end 43, the fourth positive input end 41 is connected with the third positive output end 32, the fourth negative input end 42 is connected with the third negative output end 33, the fourth output end 43 is connected with the first input end 11, and the fourth output end 43 is configured to output based on the input signal of the fourth positive input end 41 or the input signal of the fourth negative input end 42.

[0039] A multiplexer is used to select one signal from multiple input signals and pass it to an output. Multiplexers are commonly used in applications such as data selection, signal routing, data bus control, etc. The basic structure of a multiplexer includes: input ports, multiple input signals; a selection port, a control signal for selecting an input signal; an output port: a single output signal. The working principle of a multiplexer is to select an input signal through the selection port (control signal) and pass it to the output. The value of the selection port determines which input signal is selected.

[0040] The multiplexer 40 has two input terminals, a fourth positive input terminal 41 and a fourth negative input terminal 42. The fourth positive input terminal 41 is connected to the third positive output terminal 32 of the third register 30 for receiving the output signal of the third positive output terminal 32. The fourth negative input terminal 42 is connected to the third negative output terminal 33 of the third register 30 for receiving the output signal of the third negative output terminal 33. The fourth output terminal 43 is configured to output based on the input signal of the fourth positive input terminal 41 or the input signal of the fourth negative input terminal 42.

[0041] The XOR gate 50 includes a fifth input terminal 51, a sixth input terminal 52, and a fifth output terminal 53. The fifth input terminal 51 is connected to the first output terminal 12, and the sixth input terminal 52 is connected to the third positive output terminal 32. The XOR gate is used to output an interrupt signal as a first value when the signals at the fifth input terminal 51 and the sixth input terminal 52 are the same, indicating that the interrupt is cleared. When the signals at the fifth input terminal 51 and the sixth input terminal 52 are different, the XOR gate outputs an interrupt signal as a second value, indicating that the interrupt is generated. INT is the output of the XOR gate 50.

[0042] An XOR gate is a basic logic gate used to implement XOR logic operations. The output of an XOR gate is high (1) if and only if one and only one of its inputs is high (1). The logical expression of an XOR gate is: Y = A ⊕ B, where A and B are input signals, and Y is the output signal.

[0043] The XOR gate 50 includes two input terminals, a fifth input terminal 51 and a sixth input terminal 52. The fifth input terminal 51 is connected to the first output terminal 12 of the first register 10 for receiving the output signal of the first register 10. The sixth input terminal 52 is connected to the third positive output terminal 32 of the third register 30 for receiving the output signal of the third register 30.

[0044] The fifth output end 53 of the exclusive-OR gate 50 outputs an interrupt signal according to the input signals of the fifth input end 51 and the sixth input end 52. When the signals of the fifth input end 51 and the sixth input end 52 are the same, the interrupt signal is output as a first value, indicating that the interrupt is cleared. Exemplarily, the first value is 0, indicating a low level. That is, when the output signal of the first register 10 and the output signal of the third register 30 are the same, the exclusive-OR gate 50 outputs the interrupt signal as a low level, indicating that the interrupt is cleared.

[0045] When the signals of the fifth input end 51 and the sixth input end 52 are different, the interrupt signal is output as a second value, indicating that the interrupt is generated. Exemplarily, the second value is 1, indicating a high level. That is, when the output signal of the first register 10 and the output signal of the third register 30 are different, the exclusive-OR gate 50 outputs the interrupt signal as a high level, indicating that the interrupt is generated.

[0046] The interrupt signal control circuit in the embodiment of the present application comprises a first register, a second register, a third register, a multiplexer and an exclusive-OR gate. The first register comprises a first input end and a first output end. The second register comprises a second input end and a second output end. The second input end is connected with the first output end, and is configured to receive the first output signal of the first register. The third register comprises a third input end, a third positive output end and a third negative output end. The third input end is connected with the second output end, and is configured to receive the second output signal of the second register. The multiplexer comprises a fourth positive input end, a fourth negative input end and a fourth output end. The fourth positive input end is connected with the third positive output end. The fourth negative input end is connected with the third negative output end. The fourth output end is connected with the first input end. The fourth output end is configured to output based on the input signal of the fourth positive input end or the input signal of the fourth negative input end. The exclusive-OR gate comprises a fifth input end, a sixth input end and a fifth output end. The fifth input end is connected with the first output end. The sixth input end is connected with the third positive output end. The exclusive-OR gate is configured to output the interrupt signal as a first value when the signals of the fifth input end and the sixth input end are the same, indicating that the interrupt is cleared; and output the interrupt signal as a second value when the signals of the fifth input end and the sixth input end are different, indicating that the interrupt is generated. The fifth input end and the sixth input end of the exclusive-OR gate are connected with the first output end of the first register and the third positive output end of the third register respectively. When the signals of the fifth input end and the sixth input end are the same, the interrupt signal is output as the first value, indicating that the interrupt is cleared. When the signals of the fifth input end and the sixth input end are different, the interrupt signal is output as the second value, indicating that the interrupt is generated. Thus, only three cascaded registers, one multiplexer and one exclusive-OR gate are used to control the generation and clearing of the interrupt signal, and the interrupt signal can be reliably and stably generated and cleared under the condition of low hardware overhead.

[0047] Reference Figure 2Fig. 4 shows a structural schematic diagram of another control circuit of an interrupt signal according to an embodiment of the present application, the multiplexer comprises a control terminal 44, which is configured to receive a selection signal and control the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41 or the input signal of the fourth negative input terminal 42 according to the selection signal.

[0048] The control terminal 44 receives a SEL selection signal and controls the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41 or the input signal of the fourth negative input terminal 42 according to the SEL selection signal.

[0049] In the embodiment of the present application, when the selection signal is a first value, the control terminal 44 is configured to control the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41; when the selection signal is a second value, the control terminal 44 is configured to control the fourth output terminal 43 to output based on the input signal of the fourth negative input terminal 42.

[0050] For example, the first value is 0, and the control terminal 44 controls the fourth output terminal 43 to output based on the input signal of the fourth positive input terminal 41 when the received selection signal is 0, that is, based on the output signal of the third positive output terminal 32 of the third register 30.

[0051] For example, the second value is 1, and the control terminal 44 controls the fourth output terminal 43 to output based on the input signal of the fourth negative input terminal 42 when the received selection signal is 1, that is, based on the output signal of the third negative output terminal 33 of the third register 30.

[0052] In the embodiment of the present application, the second register 20 comprises a second trigger enable terminal 23 configured to receive an interrupt clear signal; and the third register 30 comprises a third trigger enable terminal 34 configured to receive an inverted signal of the interrupt clear signal.

[0053] The enable end of the register is a control signal used to control the write operation of the register. When the enable signal is valid, the register can receive input data and store it internally. When the enable signal is invalid, the register keeps its current value and does not receive new input data. The enable end of the register is usually used in combination with the clock signal (Clock). At the rising or falling edge of the clock signal, if the enable signal is valid, the register will receive input data and update its internally stored value. If the enable signal is invalid, the register will keep its current value and not perform a write operation. The enable end as a port means that it is an input port for receiving external control signals. This control signal can come from other circuit modules or external control logic. Through this port, external signals can control the behavior of the register. The enable end as a control signal means that it is used to control the write operation of the register. When the enable signal is valid, the register can receive input data and update its internally stored value; when the enable signal is invalid, the register keeps its current value and does not perform a write operation.

[0054] The second trigger enable end 23 is used to receive an interrupt clear signal (INT_CLR), and when the interrupt clear signal is valid and at the rising or falling edge of the clock signal, the second register 20 will receive input data and update its internally stored value, at which time the second register 20 outputs the updated value; the third trigger enable end 34 is used to receive an inverted signal of the interrupt clear signal (~INT_CLR), and when the inverted signal of the interrupt clear signal is valid and at the rising or falling edge of the clock signal, the third register 30 will receive input data and update its internally stored value.

[0055] That is, when the interrupt clear signal is valid and at the rising or falling edge of the clock signal, the second register 20 will receive input data and update its internally stored value, outputting the updated value, and the third register 30 will keep its current value and not perform a write operation, outputting the current value; when the interrupt clear signal is invalid, the second register 20 will keep its current value and not perform a write operation, outputting the current value, and at the rising or falling edge of the clock signal, the third register 30 will receive input data and update its internally stored value, outputting the updated value.

[0056] The interrupt clear signal (INT_CLR) represents the CPU interrupt clear signal. When the hardware circuit detects that the CPU needs to intervene during operation, it will set a signal, that is, the output signal (INT, the interrupt signal of the module) of the XOR gate 50, which is directly transmitted to the CPU to tell the CPU that the CPU needs to be controlled. After the CPU performs the corresponding interrupt processing according to the scheduling scheme, the CPU will set an interrupt clear signal to tell the hardware that the CPU has completed the processing of the interrupt.

[0057] In the case that the interrupt clear signal is the first value, the output signal of the second output end 22 keeps the current output signal; the inverse signal of the interrupt clear signal is the second value, and the output signal of the third positive output end 32 is updated to the output signal of the second output end 22.

[0058] Exemplarily, the first value is 0, representing a low level, and in the case that the interrupt clear signal is 0, the output signal of the second output end 21 of the second register 20 keeps the current output signal and does not update the value; the inverse signal of the interrupt clear signal 0 is 1, representing a high level, and the output signal of the third positive output end 32 of the third register 30 is updated to the output signal of the second output end 21 of the second register 20, that is, the value is updated. In other words, in the case that the interrupt clear signal is 0, the output signal of the second register 20 keeps the current output signal and does not update the value, and the output signal of the third register 30 is updated to the output signal of the second register 20.

[0059] In the case that the interrupt clear signal is the second value, the output signal of the second output end 22 is updated to the input signal of the second input end 22; the inverse signal of the interrupt clear signal is the first value, and the output signal of the third positive output end 32 keeps the current output signal.

[0060] Exemplarily, the second value is 1, representing a high level, and in the case that the interrupt clear signal is 1, the output signal of the second output end 21 of the second register 20 is updated to the input signal of the second input end 22, and the inverse signal of the interrupt clear signal 1 is 0, representing a low level, and the output signal of the third positive output end 32 of the third register 30 keeps the current output signal and does not update the value.

[0061] In the embodiment of the application, the first register 10 further comprises a first clock end 13, a first reset end 14 and a first trigger enable end 15, the first trigger enable end 15 is used for receiving an enable signal (ENABLE); the second register 20 further comprises a second clock end 24 and a second reset end 25; the third register 30 further comprises a third clock end 35 and a third reset end 36; and the multiplexer 40 comprises a fourth trigger enable end 45, which is used for receiving the enable signal (ENABLE).

[0062] The clock end (CLK) is an important control signal of the register, which is used for synchronizing the operation of the register. The clock signal is usually a periodic square wave signal, and the rising edge or the falling edge thereof is used for triggering the write operation of the register. The reset end (RSTJ) is used for initializing the register to a predefined state. The reset signal is usually asynchronous, that is, not affected by the clock signal.

[0063] In the initialization, the first clock terminal 13, the second clock terminal 24 and the third clock terminal 35 are used for receiving clock signals respectively, and the same clock signal is received; after the clock is opened, the first reset terminal 14, the second reset terminal 25 and the third reset terminal 36 are used for receiving reset signals respectively; the interrupt clear signal is configured as the first value (0), the selection signal is configured as the first value (0), the enable signal is configured as the first value (0), and the first output terminal 12 outputs the first value (0) due to the reset, INT_1 is the output of the first register 10 and is 0; the second output terminal 22 outputs the first value (0), INT_2 is the output of the second register 20 and is 0; the third positive output terminal 32 outputs the first value (0), INT_3 is the output of the third positive output terminal 32 of the third register 30 and is 0, and ~INT_3 is the output of the third negative output terminal 33 of the third register 30 and is 1; at this time, the output signal of the first output terminal 12 and the output signal of the third positive output terminal 32 are the same and are both 0, and the interrupt signal is the first value (0).

[0064] In the embodiment of the application, after the initialization, the selection signal and the enable signal are configured as a second value when the first preset condition is met; when the selection signal and the enable signal are configured as the second value, the input terminal of the multiplexer is the fourth negative input terminal 42, the fourth output terminal 43 outputs the second value, so that the first input terminal 11 outputs the second value; after a clock cycle, the first output terminal 12 outputs the second value; the second output terminal 12 outputs the first value; the third positive output terminal 32 outputs the first value; so that the fifth output terminal 53 outputs the interrupt signal as the second value, indicating that the interrupt is generated.

[0065] Specifically, after the module is initialized, the module starts running, and the interrupt is not detected, when the module detects the interrupt in the running, the selection signal and the enable signal are set to 1, at this time, the trigger enable of the multiplexer 40, the first register 10 and the third register 30 are opened, and the trigger enable of the second register 20 is closed, because the selection signal is 1, the multiplexer 40 transmits ~INT_3 to the fourth output end 43, at this time, ~INT_3 is 1, then the output of the fourth output end 43 of the multiplexer 40 is 1, because the fourth output end 43 is connected to the first input end 11 of the first register 10, at this time, the first input end 11 of the first register 10 is 1, because the enable signal of the first register 10 is 1, after a clock cycle, the first output end 12 of the first register 10 updates the output value from 0 to 1, because there is only one rising edge in a clock cycle, it can be said that it changes once in a period, the first register 10 updates the value when the enable signal is valid and at the rising edge; because INT_CLR is 0 at this time, the trigger enable of the second register 20 is closed, and the value is not updated, the output of the second output end 22 of the second register 20 is still the current value 0; because ~INT_CLR is 1, the trigger enable of the third register 30 is opened, and the third positive output end 32 of the third register 30 updates the value to the value of the third input end 31, because the third input end 31 is the value 0 of the second output end 22, therefore, the third register 30 still has the value 0 after updating; at this time, the first output end 12 is 1, the second output end 22 is 0, and the third positive output end 32 is 0, the fifth input end 51 of the exclusive OR gate 50 is 1, the sixth input end 52 is 0, the two are exclusive OR, the fifth output end 53 outputs the interrupt signal (INT) as 1, indicating that the interrupt is generated, and the interrupt is set.

[0066] The first preset condition is that the interrupt event is detected, and the module is an image data receiver, for example, after a frame of image is received, the hardware circuit sets the interrupt signal (generally called a receiving interrupt) (telling the CPU that the hardware has received a frame of image), and the interrupt is detected, and for the above example, the hardware detects that a frame of image is received, at this time, if the circuit of the application is used to generate the interrupt signal, the selection signal and the enable signal need to be set.

[0067] In the embodiment of the application, when the interrupt signal output by the fifth output end 53 is a second value, and the interrupt clear signal is configured as the second value, the second output end 22 outputs the second value; the third positive output end 32 outputs the first value; after a clock cycle, the interrupt clear signal is configured as the first value; the third positive output end 32 outputs the second value; so that the interrupt signal output by the fifth output end 53 is the first value, indicating that the interrupt is cleared.

[0068] Specifically, the fifth output end 53 outputs the interrupt signal as the second value, that is, the INT signal is 1, indicating that the interrupt is generated, and the INT signal is directly transmitted to the CPU, telling the CPU that the CPU needs to be controlled, and after the CPU executes the corresponding interrupt processing according to the scheduling scheme, the CPU will set an interrupt clear signal (INT CLR), that is, after the CPU executes the interrupt processing, the INT CLR will be set from 0 to 1, telling the hardware that the CPU has completed the processing of the interrupt, and when the hardware detects that the INT CLR is 1, the INT will be pulled low, that is, the INT will be set from 1 to 0, and the interrupt processing is completed.

[0069] Exemplarily, the fifth output end 53 outputs the interrupt signal as 1, indicating that the interrupt is generated, and after the CPU executes the interrupt processing, the INT CLR will be set from 0 to 1, that is, the interrupt clear signal is configured as the second value, at this time, the INT CLR is 1, the trigger enable of the second register 20 is opened, the value of the second output end 22 is updated to the value of the second input end 21, and the value of the second input end 21 is the value of the first output end 12. Since the first output end 12 has been updated to 1 in the process of generating the interrupt, the value of the second input end 21 is also 1, and the value of the second output end 22 is updated from 0 to 1; after a clock cycle, the interrupt clear signal is configured as 0, telling the hardware that the interrupt has been processed, completing the interrupt response, at this time, the inverse signal of the interrupt clear signal is 1, the trigger enable of the third register 30 is opened, the value of the third positive output end 32 is updated to the value of the third input end 31, and the value of the third input end 31 is the value of the second output end 22. Since the second output end 22 is 1, the third positive output end 32 is also 1, at this time, the first output end 12 is 1, the second output end 22 is 1, and the third positive output end 32 is 1, the fifth input end 51 of the exclusive OR gate 50 is 1, the sixth input end 52 is 1, and the fifth output end 53 outputs the interrupt signal (INT) as 0, indicating that the interrupt is cleared.

[0070] In the embodiment of the application, after the fifth output end 53 outputs the interrupt signal as the second value, the selection signal is configured as the first value when the second preset condition is met; when the selection signal is configured as the first value, the input end of the multiplexer 40 is the fourth positive input end 41, the fourth output end 43 outputs the first value, so that the first input end 11 outputs the first value; after a clock cycle, the first output end 12 outputs the first value; the second output end 22 outputs the first value; the third positive output end 32 outputs the first value; so that the fifth output end 53 outputs the interrupt signal as the first value, indicating that the interrupt is cleared.

[0071] Specifically, after the fifth output end 53 outputs the interrupt signal as the second value, that is, INT is 1, the hardware circuit detects the interrupt clear condition to pull down the SEL selection signal, and the selection signal is configured as 0. When the selection signal is configured as 0, the input end of the multiplexer 40 is the fourth positive input end 41. Since the fourth positive input end 41 is 0 at this time, the fourth output end 43 outputs 0, so that the first input end 11 outputs 0. Since the enable signal is 1, after one clock cycle, at the rising edge of the clock, the value of the first output end 12 is updated to the value of the first input end 11, that is, the value of the first output end 12 is updated from 1 to 0. Since the second output end 22 outputs 0, the third positive output end 32 outputs 0, so that the fifth output end 53 outputs the interrupt signal as 0, indicating that the interrupt is cleared.

[0072] The second preset condition is to detect the interrupt clear event. From the initialization to the detection of the interrupt by the hardware circuit, a part of the hardware interrupt clear condition detection circuit can be additionally added. When the condition triggers, the SEL selection signal is pulled down, and the enable signal is set. Then take a module of an image data receiver as an example. After receiving a frame of image, the hardware circuit sets the interrupt signal (which is generally called a reception interrupt) (tells the CPU that the hardware has received a frame of image), but has not yet received the interrupt clear signal in response to the CPU. Due to other interference factors (such as errors in continuous reception of image data), the received data (including the correct image of the last frame) needs to be cleared. At this time, the hardware can be cleared, and the INT is set to 0 (tells the CPU that the CPU does not need to intervene).

[0073] The whole interrupt processing process is as follows:

[0074] The interrupt request refers to that when the hardware circuit detects that the CPU needs to intervene in the running process, an signal (INT, the interrupt signal of the IP) is set. The signal is directly transmitted to the CPU to tell the CPU that the CPU needs to be controlled. After the CPU executes the corresponding interrupt processing according to the scheduling scheme, the CPU sets an interrupt clear signal (INT_CLR) to tell the hardware that the CPU has completed the processing of the interrupt. When the hardware detects that the INT_CLR is 1, the INT is pulled down, and the interrupt processing is completed.

[0075] For an interrupt signal of a digital module, only 3 registers, 1 multiplexer and 1 XOR gate are used to build a circuit, and a lock model is formed by the opening and closing of the trigger enable of the second and third registers. The glitch competition is effectively avoided, the high reliability is ensured, the structure is simple, the area is saved, there is no complicated control logic circuit, and the application is simple. It can be applied to interrupt signals that do not need special processing, to ensure that the hardware and software can correctly interact through the interrupt signal.

[0076] The control circuit of the interrupt signal comprises a first register, a second register, a third register, a multiplexer and an XOR gate.

[0077] It should be noted that, for the method embodiments, in order to simply describe, all are expressed as a series of action combinations, but those skilled in the art should know that the embodiments of the present application are not limited by the action sequence described, because according to the embodiments of the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily necessary for the embodiments of the present application.

[0078] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0079] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer program instructions.

[0080] Embodiments of the present application are described herein with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal apparatus, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0081] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing terminal apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal apparatus to cause a series of operational steps to be performed on the computer or other programmable terminal apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal apparatus provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0083] While preferred embodiments of the present application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such modifications and variations as fall within the scope of the present application.

[0084] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other closure, are intended to cover the non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include those elements alone but can include other elements not expressly listed or even include elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus including the element.

[0085] The above describes in detail the interrupt signal control circuit and electronic device provided by the present application. The principles and implementation modes of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, the specific implementation modes and application ranges can be changed according to the idea of the present application. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A control circuit for an interrupt signal, characterized by The circuit comprises a first register, a second register, a third register, a multiplexer and an XOR gate. The first register comprises a first input end and a first output end. The second register comprises a second input end and a second output end, the second input end being connected with the first output end for receiving a first output signal of the first register. The third register comprises a third input end, a third positive output end and a third negative output end, the third input end being connected with the second output end for receiving a second output signal of the second register. The multiplexer comprises a fourth positive input end, a fourth negative input end and a fourth output end, the fourth positive input end being connected with the third positive output end, the fourth negative input end being connected with the third negative output end, the fourth output end being connected with the first input end, and the fourth output end being configured to output based on an input signal of the fourth positive input end or an input signal of the fourth negative input end. The XOR gate comprises a fifth input end, a sixth input end and a fifth output end, the fifth input end being connected with the first output end, the sixth input end being connected with the third positive output end, and the XOR gate being configured to output an interrupt signal as a first value to represent interrupt clearing when the signals at the fifth input end and the sixth input end are the same, and output the interrupt signal as a second value to represent interrupt generation when the signals at the fifth input end and the sixth input end are different.

2. The control circuit of claim 1, wherein, The multiplexer comprises a control end, the control end being configured to receive a selection signal and control the fourth output end to output based on the input signal of the fourth positive input end or the input signal of the fourth negative input end according to the selection signal.

3. The control circuit of claim 2, wherein, In a case where the selection signal is the first value, the control end is configured to control the fourth output end to output based on the input signal of the fourth positive input end; and in a case where the selection signal is the second value, the control end is configured to control the fourth output end to output based on the input signal of the fourth negative input end.

4. The control circuit of claim 3, wherein, The second register comprises a second trigger enable end configured to receive an interrupt clear signal, and the third register comprises a third trigger enable end configured to receive an inverted signal of the interrupt clear signal. In a case where the interrupt clear signal is the first value, an output signal of the second output end remains a current output signal, the inverted signal of the interrupt clear signal is the second value, and an output signal of the third positive output end is updated to the output signal of the second output end. In a case where the interrupt clear signal is the second value, an output signal of the second output end is updated to an input signal of the second input end, the inverted signal of the interrupt clear signal is the first value, and an output signal of the third positive output end remains a current output signal.

5. The control circuit according to claim 4, wherein The first register further comprises a first clock terminal, a first reset terminal and a first trigger enable terminal, the first trigger enable terminal is used for receiving an enable signal; the second register further comprises a second clock terminal and a second reset terminal; the third register further comprises a third clock terminal and a third reset terminal; the multiplexer comprises a fourth trigger enable terminal, which is used for receiving the enable signal; During initialization, the first clock terminal, the second clock terminal and the third clock terminal are respectively used for receiving a clock signal; the first reset terminal, the second reset terminal and the third reset terminal are respectively used for receiving a reset signal; The interrupt clear signal is configured as the first value, the selection signal is configured as the first value, and the enable signal is configured as the first value; so that the first output terminal outputs the first value, the second output terminal outputs the first value, the third positive output terminal outputs the first value, and the interrupt signal is the first value.

6. The control circuit according to claim 5, wherein, After the initialization, when a first preset condition is met, the selection signal and the enable signal are configured as a second value; when the selection signal and the enable signal are configured as the second value, the input terminal of the multiplexer is the fourth negative input terminal, the fourth output terminal outputs the second value, so that the first input terminal outputs the second value; after one clock cycle, the first output terminal outputs the second value; the second output terminal outputs the first value; the third positive output terminal outputs the first value; so that the fifth output terminal outputs an interrupt signal as the second value, indicating that an interrupt is generated.

7. The control circuit of claim 6, wherein, When the fifth output terminal outputs an interrupt signal as the second value, and the interrupt clear signal is configured as the second value, the second output terminal outputs the second value; the third positive output terminal outputs the first value; after one clock cycle, the interrupt clear signal is configured as the first value; the third positive output terminal outputs the second value; so that the fifth output terminal outputs an interrupt signal as the first value, indicating that the interrupt is cleared.

8. The control circuit according to claim 6, wherein, After the fifth output terminal outputs an interrupt signal as the second value, when a second preset condition is met, the selection signal is configured as the first value; when the selection signal is configured as the first value, the input terminal of the multiplexer is the fourth positive input terminal, the fourth output terminal outputs the first value, so that the first input terminal outputs the first value; after one clock cycle, the first output terminal outputs the first value; The second output terminal outputs the first value; the third positive output terminal outputs the first value; so that the fifth output terminal outputs an interrupt signal as the first value, indicating that the interrupt is cleared.

9. The control circuit of claim 8, wherein, The first preset condition is to detect an interrupt event; and the second preset condition is to detect an interrupt clear event.

10. An electronic device, comprising: The control circuit comprises the interrupt signal according to any one of claims 1-9.

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