IO interaction circuit based on FPGA and use method

Abstract

The invention provides an IO interaction circuit based on an FPGA and a use method. The IO interaction circuit comprises an IO interface circuit and an FPGA circuit. The IO interface circuit is used for performing level conversion on serial data; the FPGA circuit is used for realizing function debugging and data monitoring of the IO interaction circuit; the FPGA circuit comprises a serial-parallel conversion logic module, a UART control logic module, a command analysis logic module, a command configuration table, a resource access logic module and a shared resource pool; the IO interface circuit is connected with the serial-to-parallel conversion logic module, the serial-to-parallel conversion logic module is connected with the UART control logic module, the UART control logic module is connected with the command analysis logic module, the command configuration table is connected with the command analysis logic, and the command analysis logic is connected with the resource access logic. And the resource access logic module is connected with the shared resource pool. And function debugging, data monitoring and fault injection in the embedded system are realized through the IO interaction circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA interactive circuits, and in particular to an IO interactive circuit based on FPGA and a use method thereof. Background Art

[0002] In high-end customized applications such as aviation, aerospace, and industry, there are a large number of non-standard functions, and there is often no suitable ASIC chip to choose from, so FPGA chips are widely used in these devices. Due to the stringent requirements of function, size, weight, power consumption, and reliability, the equipment does not have a general-purpose processor, and the relevant interface information is managed and transmitted through FPGA chips.

[0003] The development and verification of FPGA chips mainly rely on the acquisition and observation of internal and external timing waveforms. In the above application scenarios, due to the limitations of the use environment, it is impossible to use the simulator to directly capture the waveform inside the FPGA chip. Therefore, products that only use FPGA chips as the main control chip have the problem of difficulty in user monitoring and debugging development.

[0004] If there is a simple and easy-to-use interface, development and maintenance personnel can access internal data resources through simple tools and commands, the efficiency of product development and maintenance can be greatly improved, and the degree of product operation monitoring can be improved at the same time. Summary of the invention

[0005] In view of this, the embodiments of this specification provide an IO interaction circuit based on FPGA and a method of use, so as to achieve the purpose of accessing internal resources by using a simple serial port and command configuration table and using probe logic.

[0006] The embodiments of this specification provide the following technical solutions:

[0007] An IO interaction circuit based on FPGA, comprising:

[0008] The IO interface circuit and the FPGA circuit are connected to each other;

[0009] The IO interface circuit is used to perform level conversion on serial data;

[0010] The FPGA circuit is used to realize the function debugging and data monitoring of the IO interaction circuit;

[0011] The FPGA circuit includes a serial-to-parallel conversion logic module, a UART control logic module, a command parsing logic module, a command configuration table, a resource access logic module and a shared resource pool;

[0012] The IO interface circuit is interconnected with the serial-to-parallel conversion logic module, the serial-to-parallel conversion logic module is interconnected with the UART control logic module, the UART control logic module is interconnected with the command parsing logic module, the command configuration table is connected with the command parsing logic, the command parsing logic is interconnected with the resource access logic, and the resource access logic module is interconnected with the shared resource pool.

[0013] Furthermore, the FPGA circuit further includes:

[0014] The serial-to-parallel conversion logic module is used to receive serial data from the IO interface circuit, implement serial-to-parallel conversion of the serial data according to the communication protocol, generate parallel data signals, and send the parallel data signals to the UART control logic module;

[0015] The UART control logic function module is used to control the initialization of the serial-to-parallel conversion logic module, find the status of the serial-to-parallel conversion logic module, receive the parallel data signal from the serial-to-parallel conversion logic module, and send the received parallel data signal to the command parsing logic module in sequence;

[0016] The command parsing logic function module is the same as parsing the parallel data signal output by the UART control logic according to the command format provided by the command configuration table, generating address information, data signal and operation information, and transmitting the address information, data signal and operation information to the resource access logic module;

[0017] The command configuration table is used to store and provide legal command definitions and formats;

[0018] The resource access logic module is used to complete write and read operations according to the address mapping of the resource;

[0019] The shared resource pool is used to realize information sharing between the working resources of the FPGA circuit and the IO interface circuit, and realizes user access to the resources in the FPGA circuit and the flow of working resources in the FPGA circuit through the shared resource pool;

[0020] The UART control logic function module is used to control the initialization of the serial-to-parallel conversion logic module, find the status of the serial-to-parallel conversion logic module, receive the parallel data signal from the serial-to-parallel conversion logic module, and send the received parallel data signal to the command parsing logic module in sequence.

[0021] Furthermore, the write operation transfers the data parsed by the command parsing logic module to the corresponding address of the shared resource pool, and the read operation extracts the data signal from the corresponding address of the shared resource pool and transfers the data signal back to the command parsing logic module.

[0022] Furthermore, the command configuration table includes character formats of read commands, write commands and special commands.

[0023] Furthermore, the interface types of the IO interface circuit include RS422, RS2332 and RS485.

[0024] A method for using an IO interactive circuit based on FPGA, monitoring and debugging an FPGA embedded system based on the IO interactive circuit, comprising:

[0025] Obtaining a usage mode selected by a user, wherein the usage mode includes a monitoring mode and a debugging mode;

[0026] If the usage mode is monitoring mode, the FPGA circuit is monitored through the user's input signal;

[0027] If the usage mode is debug mode, the FPGA circuit is debugged through the user's input signal.

[0028] Furthermore, the FPGA circuit is monitored through the user's input signal, including:

[0029] The IO interface circuit converts the input signal into serial data;

[0030] The serial data is input into the serial-to-parallel conversion logic module to generate a data signal, and the UART control logic module reads the input data signal from the serial-to-parallel conversion logic module;

[0031] The data signal is transmitted to the command parsing logic module, and the command parsing logic module temporarily stores and combines the data signal transmitted from the UART control logic module to generate combined data;

[0032] According to the contents of the command configuration table, determine whether the combined data is a legal command;

[0033] If it is a legal command, the combined data is disassembled into control signals and / or address signals that can be recognized by the resource access logic module;

[0034] The resource access logic transmits the corresponding register value in the shared resource pool to the command parsing logic module through a data signal according to the control signal and / or address signal generated by the command parsing logic module;

[0035] The command parsing logic module transmits the data signal of the resource access logic module to the UART control logic module. The UART control logic controls the serial-to-parallel conversion logic module to convert the data signal into serial data, and transmits the serial data to the user through the IO interface circuit.

[0036] Furthermore, the FPGA circuit is debugged through the user's input signal, including:

[0037] The IO interface circuit converts the user's input signal into serial data, inputs the serial data into the serial-to-parallel conversion logic circuit, and generates a data signal;

[0038] The UART control logic module reads the data signal from the serial-to-parallel conversion logic module and transmits the data signal to the command parsing logic module;

[0039] The command parsing logic module temporarily stores and combines the data signals of the UART control logic to generate combined data;

[0040] According to the content of the command configuration table, determine whether the combined data is a legal command;

[0041] If it is a legal command, the command parsing logic module disassembles the combined data into control signals, address signals and data signals that can be recognized by the resource access logic module;

[0042] The resource access logic module writes the data signal into the corresponding register in the shared resource pool according to the control signal and the address signal.

[0043] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0044] Access to internal resources is achieved through the use of probe logic using a simple serial port and command configuration table. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 It is an overall structural diagram of an IO interaction circuit based on FPGA according to an embodiment of the present invention;

[0047] Figure 2 1 is a state diagram of a UART control logic module according to an embodiment of the present invention;

[0048] Figure 3 is a schematic diagram of the command format of the command parsing logic module of an embodiment of the present invention;

[0049] Figure 4 is a schematic diagram of a special command of an embodiment of the present invention;

[0050] Figure 5 is a schematic diagram of the structure of a resource access logic module according to an embodiment of the present invention;

[0051] Figure 6 It is a schematic diagram of the structure of a shared resource pool according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0053] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0054] An embedded interactive IO system realizes function debugging, data monitoring and fault injection in embedded systems through user access to FPGA internal resources and FPGA control resources. The existing pure FPGA hardware embedded system includes storage circuit, bus interface circuit, analog interface circuit, discrete interface circuit and power monitoring circuit.

[0055] The FPGA-based IO interaction circuit is in a pure FPGA hardware embedded system, such as Figure 1 As shown, the FPGA-based IO interaction circuit includes: a serial-to-parallel conversion logic module, a UART control logic module, a command parsing logic module, a command configuration table, a resource access logic module, a shared resource pool and an IO interface circuit.

[0056] The IO interface circuit is connected to the serial-to-parallel conversion logic module through a serial data path, the serial-to-parallel conversion logic module circuit is connected to the UART control logic module through a control signal and a data signal, the UART control logic module is connected to the command parsing logic module through a data signal, the command configuration table is connected to the command parsing logic module through a command signal, the command parsing logic module is connected to the resource access logic through a control signal, an address signal and a data signal, and the resource access logic is connected to the shared resource pool through a control signal and a data signal.

[0057] The IO interface circuit is used to complete the level conversion of serial signals, the transmission of remote signals, and lightning protection. It is a physical layer conversion circuit for command signal transmission, making the signal suitable for long-distance transmission. Users send commands or obtain command execution information fed back by the system through the IO interface.

[0058] The serial-to-parallel conversion logic module circuit is used to receive serial data signals from the IO interface circuit, realize serial-to-parallel conversion of data according to the communication protocol, and send the converted parallel data to the UART control logic module;

[0059] The UART control logic function is to control the initialization of the serial-to-parallel conversion logic module, find the state of the serial-to-parallel conversion logic module, receive parallel data signals from the serial-to-parallel conversion logic module, and send the received data to the command parsing logic module in sequence;

[0060] The UART control logic module is used to complete UART initialization, initial information printing, receiving status query, receiving register reading, receiving information echo, command processing result query, and command execution result display through a finite state machine.

[0061] like Figure 2 As shown, the UART control logic module includes 7 states:

[0062] S1 initializes, S2 prints welcome information, S3 queries RXRDY, S4 reads RHR, S5 echoes received information, S6 waits for command processing and S7 prints output results.

[0063] Specifically, the 7 states are used for:

[0064] S1. Initialization state configures the baud rate, data length, check bit, interrupt status and other information of the serial-to-parallel conversion logic;

[0065] S2. Print the welcome message status and write the fixed character "CMD START" to the serial-to-parallel conversion logic;

[0066] S3. Query RXRDY status. Query the status of RXRDY in real time. If the received data is valid, go to S4. Read RHR, otherwise continue to query;

[0067] S4. Read RHR status. Read the receive status register RHR in the serial-to-parallel conversion logic;

[0068] S5. Echo the received information status and send the data read in S4 status back to the user through the serial-to-parallel conversion logic, so that the user can confirm that his input is successful;

[0069] S6. Waiting for the status of command processing waiting for the status returned by the command parsing logic. If it is a write command, there is no need to output the result to the user, so directly return to S3 to query the RXRDY status. If it is a read command, enter S7 to print the output result;

[0070] S7. Print output result status: The read-back data returned by the resource access logic is output to the user through the serial-to-parallel conversion logic. After completion, return to S3 to query the RXRDY status.

[0071] like Figure 3As shown, the command parsing logic module is parsed through the following command format. The overall command format includes: command character, command address, separator, command data, and command terminator. The command character is used to represent the type of operation, including write command (character is W or w) and read command (character is R or r). The final data flow of the write command is "user-> shared resource pool", and the final data flow of the read command is "shared resource pool-> user". In order to take into account the user's usage habits, the command address should be the ASCII code corresponding to the hexadecimal number, with a total of 4 hexadecimal addresses. The separator is used to separate the address and data digits, and is fixed to the character P or p. The command data is a unique field of the write command, which is used to transmit the data information sent by the user. Similar to the command address, it uses the ASCII code corresponding to the hexadecimal number, with a total of 4 hexadecimal data. The command terminator represents the end of the command, with a fixed character carriage return. After the command parsing logic detects the carriage return, it parses the relevant elements of the received command.

[0072] The specific implementation process is as follows: the command parsing logic module temporarily stores the 8-bit data read by the UART control logic through a shift register with a bit width of 72 bits. If the received character is not a carriage return, the shift register value is shifted left by 8 bits, and the shift register bit7-bit0 stores the received data; if the received character is a carriage return, the shift register value is passed to the command storage register. The command parsing logic module compares the command storage register with the legal command configuration table, and determines whether it is a read command, a write command, or an error command based on whether there are legal command characters and separators in the command storage register; the address bit of the command storage register is transmitted to the resource access logic; the data bit of the command storage register is converted from ASCII code to HEX code and transmitted to the resource access logic.

[0073] like Figure 4 As shown in the figure, among all the commands, there are two special commands, which are used to enter operation mode 1 (monitoring mode) and operation mode 2 (debugging mode). The specific implementation method is to write special characters to special addresses. The system defaults to operation mode 1 when it is powered on. The two modes can be switched to each other through user commands.

[0074] like Figure 5 As shown, the resource access logic module receives the command type, command address, data and other information parsed and output by the command parsing logic module, generates a resource selection signal according to the address mapping, and determines whether the data flow direction is a write data flow or a read data flow according to the command type. The final operation instruction accesses the back-end shared resource pool through the timing generator.

[0075] The IO interface circuit can use a widely used interface form, including but not limited to industrial buses such as RS422, RS2332, and RS485. It can also be implemented using interface chips such as MAX3490 and MAX3232.

[0076] like Figure 6 As shown in the figure, the shared resource pool is a series of registers that realize information sharing between other working resources and interactive IO inside the FPGA. In the case of no user instructions and the user only reads instructions, the registers realize storage related to the normal function of the system and maintain the function. In the case of a write instruction, the corresponding register is rewritten by the data sent by the user IO according to the write address.

[0077] Through access condition control, normal working data flow can access registers under normal operation, and command data flow can access and rewrite registers under command interaction mode.

[0078] The command configuration table is a multi-dimensional array implemented in the FPGA circuit and used to store resource address allocation and legal command formats.

[0079] The embodiment of the present invention also includes a method for using an IO interactive circuit based on FPGA, which monitors and debugs an FPGA embedded system based on the IO interactive circuit, including:

[0080] Obtaining a usage mode selected by a user, wherein the usage mode includes a monitoring mode and a debugging mode;

[0081] If the usage mode is monitoring mode, the FPGA circuit is monitored through the user's input signal;

[0082] If the usage mode is debug mode, the FPGA circuit is debugged through the user's input signal.

[0083] The FPGA circuit is monitored through the user's input signal, including:

[0084] The IO interface circuit converts the input signal into serial data;

[0085] The serial data is input to the serial-to-parallel conversion logic module to generate a digital signal, and the UART control logic module reads the input data signal from the serial-to-parallel conversion logic module;

[0086] The data signal is transmitted to the command parsing logic module, and the command parsing logic module temporarily stores and combines the data signal transmitted from the UART control logic module to generate combined data;

[0087] According to the contents of the command configuration table, determine whether the combined data is a legal command;

[0088] If it is a legal command, the combined data is disassembled into control signals and / or address signals that can be recognized by the resource access logic module;

[0089] The resource access logic transmits the corresponding register value in the shared resource pool to the command parsing logic module through a data signal according to the control signal and / or address signal generated by the command parsing logic module;

[0090] The command parsing logic module transmits the data signal of the resource access logic module to the UART control logic module. The UART control logic controls the serial-to-parallel conversion logic module to convert the data signal into serial data, and transmits the serial data to the user through the IO interface circuit.

[0091] Debug the FPGA circuit through the user's input signal, including:

[0092] The IO interface circuit converts the user's input signal into serial data, inputs the serial data into the serial-to-parallel conversion logic circuit, and generates a data signal;

[0093] The UART control logic module reads the data signal from the serial-to-parallel conversion logic module and transmits the data signal to the command parsing logic module;

[0094] The command parsing logic module temporarily stores and combines the data signals of the UART control logic to generate combined data;

[0095] According to the content of the command configuration table, determine whether the combined data is a legal command;

[0096] If it is a legal command, the command parsing logic module disassembles the combined data into control signals, address signals and data signals that can be recognized by the resource access logic module;

[0097] The resource access logic module writes the data signal into the corresponding register in the shared resource pool according to the control signal and the address signal.

[0098] Beneficial effects of the embodiments of the present invention:

[0099] The IO interactive circuit of the embodiment of the present invention utilizes a simple serial port and command configuration table, and can access internal resources by using probe logic, and has the functions of online detection and fault injection; the IO interactive circuit of the embodiment of the present invention can solve the problem of difficult human-computer interaction during function debugging and data monitoring in pure FPGA embedded computers, and the communication baud rate and command configuration parameters of the system are configured through programmable logic FPGA, which has good flexibility and versatility, and the system parameters can be modified through programmable logic code; the processor that traditionally undertakes interactive IO functions is eliminated, the system cost is reduced, and the system reliability is improved, which is suitable for use in high-reliability and high-security application fields such as aerospace. At the same time, it has great flexibility, and the command format information can be flexibly modified through the command configuration table, and complex combination command forms can be realized by improving the command configuration table.

[0100] The above is only a specific embodiment of the present invention, and cannot be used to limit the scope of the invention. Therefore, the replacement of equivalent components, or equivalent changes and modifications made according to the scope of protection of the patent of the present invention, should still fall within the scope of this patent. In addition, the technical features of the present invention can be freely combined with each other, with each other, and with each other.

Claims

1. An IO interaction circuit based on FPGA, characterized in that: include: An IO interface circuit and an FPGA circuit, wherein the IO interface circuit and the FPGA circuit are connected to each other; The IO interface circuit is used to perform level conversion on serial data; The FPGA circuit is used to implement function debugging and data monitoring of the IO interaction circuit; The FPGA circuit includes a serial-to-parallel conversion logic module, a UART control logic module, a command parsing logic module, a command configuration table, a resource access logic module and a shared resource pool; The IO interface circuit is interconnected with the serial-to-parallel conversion logic module, the serial-to-parallel conversion logic module is interconnected with the UART control logic module, the UART control logic module is interconnected with the command parsing logic module, the command configuration table is connected with the command parsing logic, the command parsing logic is interconnected with the resource access logic, and the resource access logic module is interconnected with the shared resource pool.

2. The FPGA-based IO interaction circuit according to claim 1, characterized in that: The FPGA circuit further includes: The serial-to-parallel conversion logic module is used to receive the serial data from the IO interface circuit, implement serial-to-parallel conversion of the serial data according to the communication protocol, generate a parallel data signal, and send the parallel data signal to the UART control logic module; The UART control logic function module is used to control the initialization of the serial-to-parallel conversion logic module, find the state of the serial-to-parallel conversion logic module, receive the parallel data signal from the serial-to-parallel conversion logic module, and send the received parallel data signal to the command parsing logic module in sequence; The command parsing logic function module is configured to parse the parallel data signal output by the UART control logic according to the command format provided by the command configuration table, generate address information, data signal and operation information, and transmit the address information, data signal and operation information to the resource access logic module; The command configuration table is used to store and provide legal command character definitions and formats; The resource access logic module is used to complete write operations and read operations according to the address mapping of the resource; The shared resource pool is used to realize information sharing between the working resources of the FPGA circuit and the IO interface circuit, and to realize user access to resources in the FPGA circuit and circulation of working resources in the FPGA circuit through the shared resource pool; The UART control logic function module is used to control the initialization of the serial-to-parallel conversion logic module, find the state of the serial-to-parallel conversion logic module, receive the parallel data signal from the serial-to-parallel conversion logic module, and send the received parallel data signal to the command parsing logic module in sequence.

3. The FPGA-based IO interaction circuit according to claim 2, characterized in that: The write operation transfers the data parsed by the command parsing logic module to the corresponding address of the shared resource pool, and the read operation extracts the data signal from the corresponding address of the shared resource pool and transfers the data signal back to the command parsing logic module.

4. The FPGA-based IO interaction circuit according to claim 1, characterized in that: The command configuration table includes character formats of read commands, write commands and special commands.

5. The FPGA-based IO interaction circuit according to claim 1, characterized in that: The interface forms of the IO interface circuit include RS422, RS2332 and RS485.

6. A method for using an IO interaction circuit based on FPGA, the method monitoring and debugging an FPGA embedded system based on the IO interaction circuit according to any one of claims 1 to 5, characterized in that: include: Acquire a usage mode selected by a user, wherein the usage mode includes a monitoring mode and a debugging mode; If the usage mode is the monitoring mode, the FPGA circuit is monitored through a user input signal; If the usage mode is the debugging mode, the FPGA circuit is debugged through a user's input signal.

7. The method for using the IO interaction circuit according to claim 6, characterized in that: The FPGA circuit is monitored by a user's input signal, including: The IO interface circuit converts the input signal into serial data; The serial data is input into the serial-to-parallel conversion logic module to generate a data signal, and the UART control logic module reads the input data signal from the serial-to-parallel conversion logic module; The data signal is transmitted to the command parsing logic module, and the command parsing logic module temporarily stores and combines the data signal transmitted from the UART control logic module to generate combined data; According to the content of the command configuration table, determining whether the combined data is a legal command; If it is a legal command, disassemble the combined data into control signals and / or address signals recognizable by the resource access logic module; The resource access logic transmits the corresponding register value in the shared resource pool to the command parsing logic module through the data signal according to the control signal and / or the address signal generated by the command parsing logic module; The command parsing logic module transmits the data signal of the resource access logic module to the UART control logic module. The UART control logic controls the serial-to-parallel conversion logic module to convert the data signal into serial data, and transmits the serial data to the user through the IO interface circuit.

8. The method for using the IO interaction circuit according to claim 6, characterized in that: The FPGA circuit is debugged by a user's input signal, including: The IO interface circuit converts the user's input signal into serial data, and inputs the serial data into the serial-to-parallel conversion logic circuit to generate a data signal; The UART control logic module reads the data signal from the serial-to-parallel conversion logic module, and transmits the data signal to the command parsing logic module; The command parsing logic module temporarily stores and combines the data signal of the UART control logic to generate combined data; According to the content of the command configuration table, determining whether the combined data is a legal command; If it is a legal command, the command parsing logic module disassembles the combined data into control signals, address signals and data signals that can be recognized by the resource access logic module; The resource access logic module writes the data signal into a corresponding register in the shared resource pool according to the control signal and the address signal.

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