Single-wire communication method and device, electronic equipment and storage medium

Abstract

The invention provides a single-wire communication method and device, electronic equipment and a storage medium, the method is applied to master equipment, the master equipment is provided with a universal asynchronous receiver / transmitter, slave equipment is provided with a single-wire port, and the universal asynchronous receiver / transmitter is connected with the single-wire port through a single wire. A single-wire timing for transmitting each bit in the byte data is determined based on a programming interface provided by the universal asynchronous transceiver, the single-wire timing following a single-wire communication protocol supported by the single-wire port. And sequentially controlling the level change of the single line according to the single line time sequence of each bit through the universal asynchronous transceiver, so that the slave equipment determines the single line time sequence of each bit according to the level change, and determines the byte data according to the single line time sequence of each bit.

Description

Technical Field

[0001] The present invention relates to the field of single-line communication technology, and in particular to a single-line communication method, device, electronic device and storage medium. Background Art

[0002] Single-line communication is widely used in application scenarios with two connecting wires (single wire, GND). It has the characteristics of unified communication and power supply and is widely used. Compared with traditional multi-line communication, the biggest feature of single-line communication is the simple circuit design, which is suitable for low-cost and space-constrained applications. In the scenario where two devices communicate through a single line, a master device and a slave device are generally distinguished. The master device is a device that controls the communication process, usually an embedded controller, a single-chip microcomputer, etc. During the communication process, the master device and the slave device are communicated by controlling the high and low levels of the single-line transmission. In the non-communication stage, the single line is maintained at a high level to power the slave device. The slave device is a device controlled by the master device, usually a sensor or a security chip, etc. It responds to the communication request of the master device and transmits data to the master device by changing the level on the single line.

[0003] The hardware structure of the master device is usually not designed to support a single-line port for the single-line communication protocol at the beginning of the design. Generally, the GPIO (General Purpose Input / Output) port on the master device is used to simulate the single-line timing to complete the single-line communication with the slave device. However, the above method requires the development of a single-line communication driver for GPIO to simulate the single-line timing at the kernel operation space level on the master device. Especially in a time-sharing operating system, kernel operations are easily affected by factors such as interrupts and scheduling, and may not meet real-time communication requirements. In addition, the development of kernel drivers requires an in-depth understanding of kernel architecture, GPIO operations, and hardware timing, which increases the difficulty of development. Summary of the invention

[0004] To overcome the problems existing in the related art, this specification provides a single-line communication method, device, electronic device and storage medium.

[0005] According to a first aspect of an embodiment of this specification, a single-line communication method is provided, the method being applied to a master device, the master device being equipped with a universal asynchronous receiver / transmitter, the slave device being equipped with a single-line port, the universal asynchronous receiver / transmitter being connected to the single-line port via a single line, the method comprising:

[0006] For the byte data to be sent, determining a single-line timing for transmitting each bit in the byte data based on a program interface provided by the universal asynchronous receiver / transmitter, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port;

[0007] The universal asynchronous receiver and transmitter controls the level change of the single line according to the single line timing of each bit in turn, so that the slave device determines the single line timing of each bit according to the level change, and determines the byte data according to the single line timing of each bit.

[0008] According to a second aspect of an embodiment of this specification, a single-line communication method is provided, the method being applied to a slave device, the slave device being equipped with a single-line port, the master device being equipped with a universal asynchronous receiver / transmitter, the universal asynchronous receiver / transmitter being connected to the single-line port via a single line, the method comprising:

[0009] For the bit data to be sent, determining a single-line timing for transmitting the bit data, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port;

[0010] The level change of the single line is controlled according to the single line timing by the single line port, so that the master device determines the single line timing according to the level change and determines the bit data corresponding to the single line timing.

[0011] According to a third aspect of an embodiment of this specification, a single-line communication device is provided, the device is applied to a master device, the master device is equipped with a universal asynchronous receiver and transmitter, the slave device is equipped with a single-line port, the universal asynchronous receiver and transmitter are connected to the single-line port via a single line, and the device comprises:

[0012] A main single-line timing determination module, for determining, for byte data to be sent, a single-line timing for transmitting each bit in the byte data based on a program interface provided by the universal asynchronous receiver / transmitter, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port;

[0013] The master data sending module is used to control the level change of the single line according to the single line timing of each bit in turn through the universal asynchronous receiver and transmitter, so that the slave device determines the single line timing of each bit according to the level change, and determines the byte data according to the single line timing of each bit.

[0014] According to a fourth aspect of an embodiment of this specification, a single-line communication device is provided, the device being applied to a slave device, the slave device being equipped with a single-line port, the master device being equipped with a universal asynchronous receiver / transmitter, the universal asynchronous receiver / transmitter being connected to the single-line port via a single line, the device comprising:

[0015] A slave single-line timing determination module, configured to determine, for bit data to be sent, a single-line timing for transmitting the bit data, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port;

[0016] The slave data sending module is used to control the level change of the single line according to the single line timing through the single line port, so that the master device determines the single line timing according to the level change and determines the bit data corresponding to the single line timing.

[0017] According to the fifth aspect of the embodiments of this specification, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method described in the first aspect or the second aspect are implemented.

[0018] According to a sixth aspect of the embodiments of this specification, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the steps of the method described in the first aspect or the second aspect are implemented.

[0019] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:

[0020] In the embodiment of this specification, in the application scenario of single-line communication, this solution reuses the universal asynchronous receiver and transmitter installed on the master device and the single-line port of the slave device for single-line communication. This solution can complete the program of simulating single-line timing at the software level based on the program interface provided by the universal asynchronous receiver and transmitter, avoiding the design of a single-line communication driver at the kernel operation space level, thereby reducing the difficulty of development. In addition, during the single-line communication process of this solution, the universal asynchronous receiver and transmitter can automatically process data frames at the hardware level, avoiding the influence of factors such as interrupts and scheduling mechanisms in the kernel operation space on its communication timeliness, thereby improving the stability of communication.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0023] Figure 1 This is a schematic diagram of single-line communication between a master device and a slave device according to an exemplary embodiment of this specification.

[0024] Figure 2 It is a flowchart of a single-line communication method according to an exemplary embodiment of this specification.

[0025] Figure 3 This is a hardware schematic diagram of a universal asynchronous receiver / transmitter connected to a single-wire port according to an exemplary embodiment of this specification.

[0026] Figure 4 This specification is shown according to an exemplary embodiment Figure 1 Schematic diagram of the protocol conversion module 101 in.

[0027] Figure 5 The diagram is a schematic diagram of a single-line timing of a master device sending single-line data to a slave device according to an exemplary embodiment of the present specification.

[0028] Figure 6 The diagram is a schematic diagram of a single-line timing of sending single-line data from a slave device to a master device according to an exemplary embodiment of the present specification.

[0029] Figure 7 is a flow chart of another single-line communication method according to an exemplary embodiment of the present specification.

[0030] Figure 8 It is a structural schematic diagram of an electronic device according to an exemplary embodiment of the present specification.

[0031] Fig. 9 It is a block diagram of a single-line communication device according to an exemplary embodiment of the present specification.

[0032] Fig.10 It is a block diagram of another single-line communication device shown in this specification according to an exemplary embodiment. DETAILED DESCRIPTION

[0033] Single-line communication is widely used in application scenarios with two connecting wires (single wire, GND). It has the characteristics of unified communication and power supply and is widely used. Compared with traditional multi-line communication, the biggest feature of single-line communication is the simple circuit design, which is suitable for low-cost and space-constrained applications. In the scenario where two devices communicate through a single line, the master device and the slave device are generally distinguished. Among them, the master device is the device that controls the communication process, usually an embedded controller, a single-chip microcomputer, etc. During the communication process, it controls the high and low levels of the single-line transmission to achieve communication between the master device and the slave device. In the non-communication stage, the single line is maintained at a high level to power the slave device. The slave device is a device controlled by the master device, usually a sensor or a security chip, etc. It responds to the communication request of the master device and transmits data to the master device by changing the level on the single line.

[0034] The hardware structure of the master device is usually not designed to support a single-line port for the single-line communication protocol at the beginning of the design. Generally, the single-line timing is simulated through the GPIO port on the master device to complete the single-line communication with the slave device. However, the above method requires the development of a single-line communication driver for GPIO to simulate the single-line timing at the kernel operation space level on the master device. Especially in a time-sharing operating system, kernel operations are easily affected by factors such as interrupts and scheduling, and may not meet real-time communication requirements. In addition, the development of kernel drivers requires a deep understanding of kernel architecture, GPIO operations, and hardware timing, which increases the difficulty of development.

[0035] In response to at least one of the above technical problems, this specification proposes a single-line communication method to reduce development difficulty and avoid the impact of factors such as interrupts and scheduling mechanisms in the kernel operation space on communication timeliness.

[0036] like Figure 1 As shown, Figure 1 This is a schematic diagram of a master device and a slave device performing single-line communication according to an exemplary embodiment of this specification. The master device 10 is equipped with a universal asynchronous receiver and transmitter 102 (referred to as "UART"). The type of the master device 10 can be a microcontroller, an industrial controller, a single-chip microcomputer, a computer, etc. equipped with a universal asynchronous receiver and transmitter. This specification does not limit the device type of the master device 10 used in this solution. The slave device 12 is equipped with a single-wire port 122 (also known as a "1-wire port", referred to as "1WI"). The slave device 12 can be various types of sensors, security chips, etc. equipped with a single-wire port 122. This specification does not limit the device type of the slave device 12 used in this solution. The universal asynchronous receiver and transmitter 102 of the master device 10 and the single-wire port 122 of the slave device 12 share a single line 11, and the data transmission between the master device 10 and the slave device 12 is realized by controlling the level change on the single line 11.

[0037] In the case where the master device 10 needs to send data to the slave device 12, if the data is larger than 1 byte, the data can be split into multiple bytes and sent in sequence. For the byte data of 1 byte to be sent, the protocol conversion module 101 of the master device 10 determines the single-line timing for transmitting each bit in the byte data based on the program interface provided by the universal asynchronous receiver and transmitter 102. The single-line timing can follow the single-line communication protocol (such as 1-Wire communication protocol) supported by the single-line port 122 of the slave device 12. The universal asynchronous receiver and transmitter 102 controls the level change of the single line 11 in sequence according to the single-line timing of each bit, so that the transceiver module 121 of the slave device 12 determines the single-line timing of each bit according to the level change detected by the single-line port 122, and determines the byte data according to the single-line timing of each bit.

[0038] In the case where the slave device 12 needs to send data to the master device 10, if the data is larger than 1 bit, the data can be split into multiple bits and sent in sequence. For the 1-bit bit data to be sent, the transceiver module 121 determines the single-line timing for transmitting the bit data, and the single-line timing follows the single-line communication protocol supported by the single-line port 122. The single-line port 122 controls the level change of the single line 11 according to the single-line timing, so that the protocol conversion module 101 of the master device 10 determines the single-line timing according to the level change detected by the universal asynchronous receiver and transmitter 102, and determines the bit data corresponding to the single-line timing.

[0039] like Figure 2 As shown, Figure 2 is a flowchart of a single-line communication method according to an exemplary embodiment of the present specification, which can be applied to a master device, such as Figure 1 The master device 10 in the embodiment includes steps 201-202:

[0040] Step 201: for byte data to be sent, determine a single-wire timing for transmitting each bit in the byte data based on a program interface provided by the universal asynchronous receiver / transmitter, wherein the single-wire timing complies with a single-wire communication protocol supported by the single-wire port.

[0041] Step 202: Control the level change of the single line according to the single line timing of each bit in turn through the universal asynchronous receiver and transmitter, so that the slave device determines the single line timing of each bit according to the level change, and determines the byte data according to the single line timing of each bit.

[0042] In the conventional application scenario of the universal asynchronous receiver and transmitter, it is assumed that device A and device B are equipped with a universal asynchronous receiver and transmitter C and a universal asynchronous receiver and transmitter D respectively, and the transmission port (abbreviated as "TXD") of the universal asynchronous receiver and transmitter C is connected to the receiving port (abbreviated as "RXD") of the universal asynchronous receiver and transmitter D through an independent data line; the receiving port of the universal asynchronous receiver and transmitter C is connected to the transmission port of the universal asynchronous receiver and transmitter D through another independent data line. The universal asynchronous receiver and transmitter can send 1 byte of data to each other at a time, and the format of the data frame of 1 byte of data sent between the universal asynchronous receiver and transmitter C and the universal asynchronous receiver and transmitter D each time includes a start bit, a data bit, a check bit (optional) and a stop bit, wherein the start bit marks the beginning of the data frame, the data bit is used to transmit 1 byte of data, the check bit is used for error detection, and the stop bit marks the completion of the data frame transmission. In addition, since the universal asynchronous receiver and transmitter C and the universal asynchronous receiver and transmitter D share two independent data lines, the functions of sending data to each other and receiving data sent by each other can be realized at the same time.

[0043] It is understandable that the original intention of the design of the universal asynchronous receiver / transmitter is to use the universal asynchronous receiver / transmitter equipped on each of the two devices to perform asynchronous communication between the two devices. Different from the use of conventional universal asynchronous receiver / transmitters, this solution applies the universal asynchronous receiver / transmitter equipped on the master device to the communication scenario of communicating with the single-line port of the slave device. Since the universal asynchronous receiver / transmitter has the ability to automatically process data frames at the hardware level, it is not necessary for developers to specially develop a single-line communication driver for simulating single-line timing at the kernel operation space level. Therefore, the purpose of reducing the difficulty of developing software applications for communication between the single-line ports of the master device and the slave device can be achieved.

[0044] In order to achieve the purpose of enabling the universal asynchronous receiver / transmitter equipped on the master device to communicate with the single-wire port of the slave device, in the design of the hardware structure, the universal asynchronous receiver / transmitter on the master device can share the same single wire with the single-wire port of the slave device. Specifically, Figure 3 As shown, Figure 3 The figure shows the connection relationship between the universal asynchronous receiver and transmitter 102 and the single-line port 122. The sending port 32 and the receiving port 33 of the universal asynchronous receiver and transmitter 102 are connected to the same single line 11, and the single-line port 122 is also connected to the single line 11. In addition, the first grounding port 34 of the master device 10 and the second grounding port 40 of the slave device 12 are grounded respectively. When the master device 10 sends data to the slave device 12, the sending port 32 of the universal asynchronous receiver and transmitter 102 can send the single-line data to the single-line port 122 by controlling the level change on the single line 11. At this time, the receiving port 33 of the universal asynchronous receiver and transmitter 102 can ignore the level change, that is, ignore the single-line data sent by the sending port 32. When the slave device 12 sends the single-line data to the master device 10, the single-line port 122 of the slave device 12 can control the level change on the single line 11 by pulling down the single line 11 and releasing the single line 11, thereby achieving the purpose of sending the single-line data to the receiving port 33 of the universal asynchronous receiver and transmitter 102.

[0045] As mentioned above, the universal asynchronous receiver / transmitter can send and / or receive 1 byte of single-line data each time. The communication method can refer to the above embodiment and will not be described here. The single-line communication protocol supported by the single-line port supports sending and / or receiving 1 bit of single-line data each time. It is not difficult to understand that the amount of single-line data sent by the universal asynchronous receiver / transmitter each time is 8 times that of the single-line port.

[0046] In order to coordinate the communication relationship between the two, the purpose of achieving the communication between the universal asynchronous receiver and transmitter equipped on the master device and the single-line port of the slave device is achieved. Different from the conventional way of mutual communication between universal asynchronous receivers and transmitters, in the stage of sending data from the master device to the slave device, for the byte data to be sent, the program interface provided by the universal asynchronous receiver and transmitter determines the single-line timing for transmitting each bit in the byte data, and the single-line timing can follow the single-line communication protocol supported by the single-line port.

[0047] Exemplarily, for the byte data to be sent, each bit in the byte data can be converted into a data sequence supported by the universal asynchronous receiver and transmitter based on the program interface provided by the universal asynchronous receiver and transmitter. After the conversion, the data volume increases by 8 times, and the single-line timing corresponding to the data sequence is determined.

[0048] Specifically, Figure 4 As shown, Figure 1 The protocol conversion module 101 includes a byte escape submodule 1011 and a timing conversion submodule 1012. The byte escape submodule 1011 is used to process the data escape of each bit in the byte data into a data sequence supported by the universal asynchronous receiver and transmitter based on the program interface provided by the universal asynchronous receiver and transmitter. The timing conversion submodule 1012 is used to determine the single-line timing corresponding to the data sequence.

[0049] In an illustrated embodiment, if the master device needs to send 12345678 to the slave device, for the byte data 12 to be sent, its corresponding byte representation is C0C0C0FFC0C0FFC0; for the byte data 34 to be sent, its corresponding byte representation is C0C0FFFFC0FFC0C0; for the byte data 56 to be sent, its corresponding byte representation is C0FFC0FFC0FFFFC0; for the byte data 78 to be sent, its corresponding byte representation is C0FFFFFFFFC0C0C0. The C0 or FF escape of each bit in the byte representation corresponding to the byte data to be sent can be processed into a data sequence including a start bit, a data bit and an end bit, and the single-line timing corresponding to the data sequence is determined.

[0050] The single-line timing of writing a bit value of 0 to the transmitting port of the universal asynchronous receiver and transmitter may be 0xFF. The wakeup instruction is used to activate the working state of the slave device, and its single-line timing may be 0x80. The reset instruction is used to initialize the working state of the slave device, and its single-line timing may be 0x00. Different single-line timings indicate that the transmitting port of the universal asynchronous receiver and transmitter controls different level changes on the single line to indicate the single-line data transmitted on the single line.

[0051] For example, Figure 5As shown, when the sending port of the universal asynchronous receiver / transmitter sends single-line data with a bit value of 1 to the single-line port, the level change on the single line is controlled according to the single-line timing 0xC0 corresponding to the bit value 1. Among them, the level change corresponding to each single-line timing is divided into three parts: the start bit, the data bit and the end bit according to the corresponding data sequence format. The specific level change corresponding to the start bit is used to indicate that the slave device starts to receive data. The specific level change corresponding to the end bit is used to indicate that the slave device has completed this round of transmission. The data bit is divided into two sampling windows, namely the first sampling window and the second sampling window. If the single-line port of the slave device determines that the level change in the first sampling window is a continuous high level in the first sampling window and the second sampling window is a continuous high level, that is, it is represented by 111111111. Then the slave device can determine that the single-line timing of the single-line data of 1 bit sent by the master device is 0xC0 according to the level change detected by the single-line port, and determine that the data currently sent by the master device is a bit value 1 according to the single-line timing. Similarly, if the single-line port of the slave device determines in the first sampling window and the second sampling window respectively that the level change in the first sampling window is a continuous low level, and the level change in the second sampling window is a continuous high level, that is, represented by 00000011, then the single-line timing of the 1-bit single-line data sent by the master device can be determined to be 0xFF according to the level change, and the data currently sent by the master device is determined to be bit value 0 according to the single-line timing. If the level change in the first sampling window and the second sampling window is a continuous low level, that is, represented by 00000000, then the single-line timing of the single-line data sent by the master device can be determined to be 0x00 according to the level change, and the single-line data currently sent by the master device is determined to be a reset instruction according to the single-line timing. If the first sampling window is a low level and a rising edge of the level appears in the second sampling window, that is, represented by 00000001, then the single-line timing of the single-line data sent by the master device can be determined to be 0x80 according to the level change, and the single-line data currently sent by the master device is determined to be a wake-up instruction according to the single-line timing.

[0052] In an illustrated embodiment, if the slave device needs to send a bit of data 1 or 0 to the master device, Figure 6As shown, the single-line port of the slave device detects a specific level change from the single line, for example, the output port of the universal asynchronous receiver and transmitter pulls down the level on the single line and then pulls up the level. After the level change indicates "starting the read timing", if the bit data currently to be sent by the slave device is 1, the single-line timing for transmitting the bit data is determined, and the level change of the single line is controlled according to the single-line timing through the single-line port, for example, the high level on the single line is maintained for n microseconds through the pull-up resistor. The master device determines the single-line timing according to the level change, and determines that the bit data corresponding to the single-line timing is 1. Similarly, if the bit data to be sent is 0, the slave device determines the single-line timing for transmitting the bit data, and controls the level change of the single line according to the single-line timing through the single-line port, for example, the pull-up resistor is restored after the level on the single line is pulled down for m microseconds. The master device determines the single-line timing according to the level change, and determines that the bit data corresponding to the single-line timing is 0.

[0053] In an embodiment shown, the level driving mode of the universal asynchronous receiver and transmitter is a push-pull mode. The push-pull mode is a level output driving mode, which uses two transistors (or other switching devices) to work alternately, one is responsible for pushing up the level on the single line, and the other is responsible for pulling down the level on the single line. Of course, the level driving mode of the universal asynchronous receiver and transmitter can also be other level driving modes in addition to the push-pull mode, and this specification does not impose any restrictions on the level driving mode of the universal asynchronous receiver and transmitter.

[0054] In one illustrated embodiment, Figure 3 As shown, a power supply circuit 37 is connected between any connection point 39 on the single line 11 and the power supply 36 of the master device 10, and a pull-up resistor 38 is provided on the power supply circuit. The power supply 36 is connected to the power port 31, indicating that the power supply 36 is the internal power supply of the master device 10. Accordingly, the level driving mode of the single-line port 122 is an open-drain mode. Of course, in addition to the above circuit structure, the slave device 12 can also be powered by a power supply independent of the master device 10, and this specification does not impose any restrictions on this.

[0055] In one illustrated embodiment, Figure 3 As shown, in the case where a power supply line is connected between any connection point on the single line and the power supply of the main device, an isolation element 35 can be provided on the single line 11 between the sending port 32 of the universal asynchronous receiver and transmitter 102 and the connection point 39, and the isolation element 35 is used to isolate the influence of the level output by the sending port 32 on the level output by the single line port 122. For example, the level output by the sending port 32 is a high level, and the single line port 122 needs to pull down the level on the single line. At this time, the sending port 32 can be isolated by the isolation element 35 to ensure that the single line port 122 can pull down the level on the single line. Among them, the isolation element 35 can be a resistor or other electronic components with the same function as the resistor. This specification does not impose any restrictions on the isolation element.

[0056] like Figure 7 As shown, Figure 7 is a flow chart of a single-line communication method according to an exemplary embodiment of the present specification. The method can be applied to a slave device, such as Figure 1 The slave device 12 in the embodiment includes steps 701-702:

[0057] Step 701: for bit data to be sent, determine a single-line timing for transmitting the bit data, where the single-line timing complies with a single-line communication protocol supported by the single-line port.

[0058] Step 702: Control the level change of the single line according to the single line timing through the single line port, so that the master device determines the single line timing according to the level change and determines the bit data corresponding to the single line timing.

[0059] In this embodiment, in the application scenario of single-line communication, this solution reuses the universal asynchronous receiver / transmitter installed on the master device and the single-line port of the slave device for single-line communication. This solution can complete the program of simulating single-line timing at the software level based on the program interface provided by the universal asynchronous receiver / transmitter, avoiding the design of a single-line communication driver at the kernel operation space level, thereby reducing the difficulty of development. In addition, during the single-line communication process of this solution, the universal asynchronous receiver / transmitter can automatically process data frames at the hardware level, avoiding the influence of factors such as interrupts and scheduling mechanisms in the kernel operation space on its communication timeliness.

[0060] like Figure 8 As shown, Figure 8 It is a structural diagram of an electronic device shown in this specification according to an exemplary embodiment. At the hardware level, the electronic device 800 includes a processor 802, an internal bus 804, a network interface 806, a memory 808 and a non-volatile memory 810, and of course may also include hardware required for other services. One or more embodiments of this specification can be implemented based on software, such as the processor 802 reading the corresponding computer program from the non-volatile memory 810 into the memory 808 and then running it. Of course, in addition to the software implementation, one or more embodiments of this specification do not exclude other implementations, such as logic devices or a combination of software and hardware, etc., that is to say, the execution subject of the following processing flow is not limited to each logic module, but can also be hardware or logic devices.

[0061] like Fig. 9 As shown, Fig. 9 This is a block diagram of a single-line communication device according to an exemplary embodiment of the present specification. The device can be applied to Figure 8The electronic device 800 shown in the figure is used to implement the technical solution of this specification. The device includes:

[0062] A main single-line timing determination module 902, for determining, for byte data to be sent, a single-line timing for transmitting each bit in the byte data based on a program interface provided by the universal asynchronous receiver / transmitter, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port;

[0063] The master data sending module 904 is used to control the level change of the single line according to the single line timing of each bit in turn through the universal asynchronous receiver and transmitter, so that the slave device determines the single line timing of each bit according to the level change, and determines the byte data according to the single line timing of each bit.

[0064] Optionally, the main single-line timing determination module 902 is specifically used to process the data of each bit in the byte data to be sent into a data sequence supported by the universal asynchronous receiver and transmitter based on the program interface provided by the universal asynchronous receiver and transmitter, and determine the single-line timing corresponding to the data sequence.

[0065] Optionally, the level driving mode of the universal asynchronous receiver and transmitter is a push-pull mode.

[0066] Optionally, a power supply line is connected between any connection point on the single line and the power supply of the master device, and a pull-up resistor is provided on the power supply line.

[0067] Optionally, an isolation element is provided on the single line between the transmitting port of the universal asynchronous receiver / transmitter and the connection point, and the isolation element is used to isolate the influence of the level output by the transmitting port on the level output by the single line port.

[0068] Optionally, the isolation element is a resistor.

[0069] like Fig.10 As shown, Fig.10 is a block diagram of another single-line communication device according to an exemplary embodiment of the present specification. The device can be applied to Figure 8 The electronic device 800 shown in the figure is used to implement the technical solution of this specification. The device includes:

[0070] A single-line timing determination module 1002 is used to determine, for bit data to be sent, a single-line timing for transmitting the bit data, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port;

[0071] The slave data sending module 1004 is used to control the level change of the single line according to the single line timing through the single line port, so that the master device determines the single line timing according to the level change and determines the bit data corresponding to the single line timing.

[0072] The implementation process of the functions and effects of each module in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, which will not be repeated here.

[0073] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. Ordinary technicians in this field can understand and implement it without paying creative work.

[0074] The present specification also provides a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, the steps of any of the aforementioned single-line communication methods provided in the present application are implemented.

[0075] Specifically, computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including, for example, semiconductor memory devices (such as EPROM, EEPROM and flash memory devices), magnetic disks (such as internal hard disks or removable disks), magneto-optical disks, and CD ROM and DVD-ROM disks.

Claims

1. A single-line communication method, characterized in that: The method is applied to a master device, the master device is equipped with a universal asynchronous receiver / transmitter, the slave device is equipped with a single-line port, the universal asynchronous receiver / transmitter is connected to the single-line port via a single line, and the method comprises: For the byte data to be sent, determining a single-line timing for transmitting each bit in the byte data based on a program interface provided by the universal asynchronous receiver / transmitter, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port; The universal asynchronous receiver and transmitter controls the level change of the single line according to the single line timing of each bit in turn, so that the slave device determines the single line timing of each bit according to the level change, and determines the byte data according to the single line timing of each bit.

2. The method according to claim 1, characterized in that: The step of determining, for the byte data to be sent, a single-line timing for transmitting each bit in the byte data based on a program interface provided by the universal asynchronous receiver / transmitter, comprises: For the byte data to be sent, each bit in the byte data is converted into a data sequence supported by the universal asynchronous receiver / transmitter based on a program interface provided by the universal asynchronous receiver / transmitter, and a single-line timing corresponding to the data sequence is determined.

3. The method according to claim 1, characterized in that A power supply line is connected between any connection point on the single line and the power supply of the main device, and a pull-up resistor is arranged on the power supply line.

4. The method according to claim 3, characterized in that An isolation element is provided on the single line between the transmission port of the universal asynchronous receiver / transmitter and the connection point, and the isolation element is used to isolate the influence of the level output by the transmission port on the level output by the single line port.

5. The method according to claim 4, characterized in that The isolation element is a resistor.

6. The method according to any one of claims 1 to 5, characterized in that The level driving mode of the universal asynchronous receiver / transmitter is a push-pull mode.

7. A single-line communication method, characterized in that: The method is applied to a slave device, the slave device is equipped with a single-line port, the master device is equipped with a universal asynchronous receiver / transmitter, the universal asynchronous receiver / transmitter is connected to the single-line port via a single line, and the method comprises: For the bit data to be sent, determining a single-line timing for transmitting the bit data, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port; The level change of the single line is controlled according to the single line timing by the single line port, so that the master device determines the single line timing according to the level change and determines the bit data corresponding to the single line timing.

8. A single-line communication device, characterized in that: The device is applied to a master device, the master device is equipped with a universal asynchronous receiver / transmitter, the slave device is equipped with a single-line port, the universal asynchronous receiver / transmitter is connected to the single-line port via a single line, and the device comprises: A main single-line timing determination module, for determining, for byte data to be sent, a single-line timing for transmitting each bit in the byte data based on a program interface provided by the universal asynchronous receiver / transmitter, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port; The master data sending module is used to control the level change of the single line according to the single line timing of each bit in turn through the universal asynchronous receiver and transmitter, so that the slave device determines the single line timing of each bit according to the level change, and determines the byte data according to the single line timing of each bit.

9. A single-line communication device, characterized in that: The device is applied to a slave device, the slave device is equipped with a single-line port, the master device is equipped with a universal asynchronous receiver / transmitter, the universal asynchronous receiver / transmitter is connected to the single-line port via a single line, and the device comprises: A slave single-line timing determination module, configured to determine, for bit data to be sent, a single-line timing for transmitting the bit data, wherein the single-line timing complies with a single-line communication protocol supported by the single-line port; The slave data sending module is used to control the level change of the single line according to the single line timing through the single line port, so that the master device determines the single line timing according to the level change and determines the bit data corresponding to the single line timing.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method according to any one of claims 1 to 7 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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