Optoelectronic co-packaging heterogeneous chip heat dissipation integration method, device and equipment

Abstract

The present invention relates to the field of chip heat dissipation technology, and discloses an integrated heat dissipation method, device and equipment for optoelectronic co-packaged heterogeneous chips. The method comprises: performing finite element modeling analysis on the optoelectronic co-packaged heterogeneous chips to obtain a three-dimensional thermal characteristic model; performing signal acquisition and frequency domain characteristic analysis on each functional module of the optoelectronic co-packaged heterogeneous chip to generate power consumption prediction data; performing temperature field distribution calculation on the optoelectronic co-packaged heterogeneous chips according to the power consumption prediction data and the three-dimensional thermal characteristic model, and constructing a temperature outer loop control model and a heat flow inner loop control model; performing heat dissipation structure layout optimization calculation based on the temperature outer loop control model and the heat flow inner loop control model to generate a hybrid heat dissipation layout scheme. The present invention realizes dynamic allocation of heat dissipation power and automatic threshold adjustment, avoids frequent mode switching, and improves the thermal characteristic stability of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip heat dissipation technology, and in particular to an integrated method, device and equipment for heat dissipation of optoelectronic co-packaged heterogeneous chips. Background Art

[0002] With the rapid development of optoelectronics and integrated circuit technology, optoelectronic co-packaged heterogeneous chips have attracted widespread attention as a new integration solution. This technology can effectively improve system performance, reduce power consumption and reduce volume by integrating optical devices and electronic devices in the same package. However, due to the large differences in thermal characteristics of different functional modules and the increase in power density caused by high integration, local hot spots are easily formed inside the chip, seriously affecting the reliability and performance of the system.

[0003] Traditional heat dissipation solutions often use a single heat dissipation structure, which is difficult to meet the requirements of overall temperature uniformity and local hot spot control at the same time. Existing temperature monitoring and control strategies are usually based on a fixed monitoring point arrangement, which cannot accurately reflect the temperature distribution characteristics of the chip under different working modes, resulting in unsatisfactory heat dissipation effects. In addition, existing heat dissipation control methods lack the ability to dynamically perceive the actual working status of the chip, and cannot make timely adjustments based on load changes, which easily leads to waste or insufficient heat dissipation resources. Summary of the invention

[0004] The present invention provides a method, device and equipment for integrating heat dissipation of optoelectronic co-packaged heterogeneous chips, which realizes dynamic allocation of heat dissipation power and automatic adjustment of thresholds, avoids frequent mode switching, and improves the stability of chip thermal characteristics.

[0005] In a first aspect, the present invention provides an optoelectronic co-packaged heterogeneous chip heat dissipation integration method, the optoelectronic co-packaged heterogeneous chip heat dissipation integration method comprising:

[0006] Conduct finite element modeling analysis on optoelectronic co-packaged heterogeneous chips to obtain a three-dimensional thermal characteristic model;

[0007] Performing signal acquisition and frequency domain characteristic analysis on each functional module of the optoelectronic co-packaged heterogeneous chip to generate power consumption prediction data;

[0008] Calculating the temperature field distribution of the optoelectronic co-packaged heterogeneous chip according to the power consumption prediction data and the three-dimensional thermal characteristic model, and constructing a temperature outer loop control model and a heat flow inner loop control model;

[0009] Based on the temperature outer loop control model and the heat flow inner loop control model, a heat dissipation structure layout optimization calculation is performed to generate a hybrid heat dissipation layout solution.

[0010] In a second aspect, the present invention provides an optoelectronic co-packaged heterogeneous chip heat dissipation integrated device, the optoelectronic co-packaged heterogeneous chip heat dissipation integrated device comprising:

[0011] Modeling module, used to perform finite element modeling analysis on optoelectronic co-packaged heterogeneous chips to obtain a three-dimensional thermal characteristic model;

[0012] An analysis module, used to perform signal acquisition and frequency domain characteristic analysis on each functional module of the optoelectronic co-packaged heterogeneous chip, and generate power consumption prediction data;

[0013] A calculation module, used to calculate the temperature field distribution of the optoelectronic co-packaged heterogeneous chip according to the power consumption prediction data and the three-dimensional thermal characteristic model, and to construct a temperature outer loop control model and a heat flow inner loop control model;

[0014] A generation module is used to perform heat dissipation structure layout optimization calculation based on the temperature outer loop control model and the heat flow inner loop control model to generate a hybrid heat dissipation layout solution.

[0015] The third aspect of the present invention provides a computer device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the computer device executes the above-mentioned optoelectronic co-packaged heterogeneous chip heat dissipation integration method.

[0016] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the above-mentioned optoelectronic co-packaged heterogeneous chip heat dissipation integration method.

[0017] In the technical solution provided by the present invention, by establishing a three-dimensional thermal characteristic model and combining it with signal analysis, the temperature distribution of the chip is accurately predicted, the heat dissipation design is more targeted, and the hot spot temperature is effectively reduced; a dual-loop control structure of a temperature outer loop and a heat flow inner loop is adopted to achieve coordinated cooperation of global temperature field uniformity control and local hot spot precise adjustment, thereby improving the control accuracy of the heat dissipation system; a centralized and distributed hybrid heat dissipation layout strategy is introduced to overcome the limitations of a single heat dissipation method and achieve the optimal configuration of heat dissipation resources; through transient thermal response testing and parameter correction mechanisms, the accuracy of the heat dissipation model is improved, so that the system can better adapt to actual working conditions; a heat dissipation control method based on dynamic load monitoring is established to solve the problem that the traditional fixed monitoring point solution cannot accurately reflect the temperature distribution; dynamic allocation of heat dissipation power and automatic adjustment of thresholds are achieved to avoid frequent mode switching and improve system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0019] Figure 1 Schematic diagram of the steps of the heat dissipation integration method of optoelectronic co-packaging heterogeneous chips in an embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of the structure of the heat dissipation integrated device for optoelectronic co-packaging heterogeneous chips in an embodiment of the present invention;

[0021] Figure 3 It is a schematic block diagram of the structure of a computer device in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] Embodiments of the present invention provide an optoelectronic co-packaged heterogeneous chip heat dissipation integration method, device and equipment. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 , an embodiment of the heat dissipation integration method of optoelectronic co-packaging heterogeneous chips in the embodiment of the present invention includes:

[0024] Step S1, performing finite element modeling analysis on the optoelectronic co-packaged heterogeneous chip to obtain a three-dimensional thermal characteristic model;

[0025] It is understandable that the execution subject of the present invention can be an optoelectronic co-packaged heterogeneous chip heat dissipation integrated device, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0026] Specifically, the geometric parameters of each functional module of the optoelectronic co-packaged heterogeneous chip are measured to obtain the geometric size data of each module and describe the spatial distribution, shape and boundary characteristics of the internal structure of the chip. Finite element meshing is performed according to the geometric size data to generate initial meshing data, and the complex structure of the chip is discretized into a finite number of simple units. The hot spot area is meshed according to the initial meshing data. The hot spot area refers to the area with high power consumption or obvious heat accumulation. The mesh encryption of these areas describes the local thermal phenomenon more finely, thereby improving the accuracy of thermal analysis. After the mesh encryption process is completed, the encrypted mesh data is obtained. A three-dimensional structural model is constructed based on the encrypted mesh data to reflect the internal geometric characteristics and mesh discrete distribution of the chip. The material thermal conductivity data, heat capacity data and interface thermal resistance data of the optoelectronic co-packaged heterogeneous chip are input into the three-dimensional structural model. The thermal conductivity is used to describe the thermal conductivity inside the material, the heat capacity reflects the material's ability to store heat, and the interface thermal resistance is an important parameter that affects heat transfer, especially between multiple material interfaces. By inputting these thermophysical parameters, the distribution data of the thermophysical parameters inside the chip is obtained. Based on the distribution data of thermal physical parameters, a heat conduction equation is established to describe the heat transfer behavior inside the chip. At the same time, according to the actual working environment of the chip, the boundary conditions of thermal convection and thermal radiation are set to generate a heat transfer coefficient matrix for thermal analysis. The thermal convection boundary condition reflects the heat exchange between the chip surface and the external cooling medium (such as air or liquid), while the thermal radiation boundary condition describes the heat exchange between the chip surface and the surrounding environment through radiation. The ambient temperature data and the initial temperature distribution data of the chip are input into the heat transfer coefficient matrix. Through boundary constraint calculation, boundary condition data that meets the actual working conditions is generated. At the same time, the power consumption distribution of each functional module of the optoelectronic co-packaged heterogeneous chip is calculated, and the power consumption distribution data is obtained by integrating the working status and power consumption characteristics of different modules of the chip. According to the power consumption distribution data, the heat transfer coefficient matrix is ​​adaptively solved by time step. By dynamically adjusting the time step, the calculation efficiency is improved while maintaining the calculation accuracy. Through this solution process, the solution of the heat conduction equation is obtained to describe the dynamic temperature change and heat transfer path inside the chip. The solution of the heat conduction equation is input into the temperature field calculation model to perform multi-heat source coupling analysis, comprehensively consider the interaction of multiple heat sources inside the chip and their impact on the temperature field, and generate a three-dimensional thermal characteristic model.

[0027] Step S2, performing signal acquisition and frequency domain characteristic analysis on each functional module of the optoelectronic co-packaged heterogeneous chip to generate power consumption prediction data;

[0028] Specifically, the load of each functional module of the optoelectronic co-packaged heterogeneous chip is monitored to obtain the load data of the chip under different working modes, reflecting the dynamic working state of each functional module under various operating conditions. Based on the load data, a signal acquisition sequence is established to define the time interval, sampling frequency and sampling priority of each channel for signal acquisition. The signal acquisition sequence is input into the signal acquisition unit, and the signals of each functional module of the chip are sampled using multi-channel parallel sampling technology. Multi-channel parallel sampling simultaneously obtains the signal data of multiple modules, thereby avoiding the timing deviation caused by the signal acquisition sequence. Through this process, the original signal sampling data is obtained, including the signal changes of each module under different load conditions. The power spectrum of the original signal sampling data is calculated, and the time domain signal is converted into the frequency domain representation using the fast Fourier transform to obtain the initial power spectrum data, which describes the frequency distribution of the signal and its energy characteristics. The initial power spectrum data is density normalized to eliminate the dimensional influence that occurs during the data sampling process, and the signal power spectrum density data is generated. According to the signal power spectrum density data, the working frequency of each functional module of the optoelectronic co-packaged heterogeneous chip is extracted. Through the frequency extraction process, the main operating frequency range of each module under different load conditions is identified to obtain frequency characteristic data. The duty cycle analysis of the frequency characteristic data is performed to evaluate the switching frequency characteristics and working cycle of the signal, and the peak power of each module is calculated in combination with the power calculation algorithm to generate power characteristic parameters. The power characteristic parameters are subjected to feature matching calculation to establish a mapping relationship between the power characteristics and the specific physical characteristics of the chip module. The power consumption mapping parameters are generated through feature matching calculation. The power consumption mode of each functional module of the optoelectronic co-packaged heterogeneous chip is identified using the power consumption mapping parameters. The power consumption characteristics under different working conditions are classified and power consumption classification data is generated. The power consumption classification data is numerically predicted. By combining the aforementioned frequency characteristic data, power characteristic parameters and power consumption mapping parameters, algorithms such as regression analysis or neural networks are used to accurately predict the power consumption of the chip, and finally power consumption prediction data is generated to describe the power consumption distribution and change trend of each functional module of the chip under different load conditions.

[0029] Step S3, calculating the temperature field distribution of the optoelectronic co-packaged heterogeneous chip according to the power consumption prediction data and the three-dimensional thermal characteristic model, and constructing a temperature outer loop control model and a heat flow inner loop control model;

[0030] Specifically, based on the power consumption prediction data and the three-dimensional thermal characteristic model, numerical solution methods such as finite element analysis or finite difference method are used to calculate the temperature field evolution process of the chip at different times and under different working conditions, and obtain the temperature distribution matrix with time and space as the dimensions. The temperature monitoring points of the optoelectronic co-packaged heterogeneous chips are arranged according to the temperature distribution matrix. The coordinate data of the key monitoring points are determined by analyzing the change trend of the temperature distribution and the location of the heat concentration area. The selection of monitoring points must take into account the coverage of the hot spot area and the responsiveness to the overall temperature field change to ensure that the monitoring points can accurately reflect the spatial distribution characteristics of the temperature change in the chip. Based on the monitoring point coordinate data, the grid temperature data corresponding to the chip grid is constructed to form a set of discretization foundations for refining the temperature field analysis. The temperature gradient operation is performed on the grid temperature data to obtain the temperature field distribution characteristic data. By calculating the temperature gradient, the direction and intensity of heat transfer inside the chip are revealed, and possible hot spot aggregation areas and heat diffusion bottlenecks are identified. According to the distribution characteristic data, the hot spot area inside the chip is divided to generate temperature monitoring data. The temperature monitoring data is input into the temperature outer loop controller for processing. The task of the temperature outer loop controller is to adjust the overall temperature of the chip. Therefore, the temperature monitoring data is compared with the set temperature threshold, and the temperature deviation matrix is ​​calculated to reflect the difference between the current actual temperature of the chip and the target temperature. On this basis, the global temperature compensation algorithm is used to generate a global temperature compensation coefficient, which is used to correct the overall heat distribution state of the chip, thereby reducing the risk of overheating. Based on the global temperature compensation coefficient, the temperature monitoring data is subjected to feature decomposition operation to extract the most significant distribution characteristics and change trends in the temperature monitoring data to obtain the temperature response data. Using the temperature response data, a temperature outer loop control model is constructed, which achieves the overall temperature control target by adjusting the global parameters of the cooling system in real time, such as the flow rate of air cooling or liquid cooling. At the same time, the local temperature difference calculation is performed on the temperature monitoring data to identify the temperature difference between different areas in the chip and generate a temperature difference matrix. Based on this matrix, the heat flux characteristics inside the chip are refined to local areas through the heat flux density partition mapping method, and local heat flux distribution data is generated to describe the heat flux conduction intensity and direction of each area. The local heat flux distribution data is input into the heat flux inner loop controller, and the heat flux density compensation parameters are obtained through dynamic response calculation. These parameters are used to optimize local thermal management strategies, such as adjusting the properties of thermal interface materials or changing the working state of local heat sinks. Based on these compensation parameters, a heat flow inner loop control model is constructed. This model focuses on precise regulation of heat in local hot spot areas, and achieves rapid cooling of hot spots by optimizing heat flow paths and local heat dissipation efficiency. Through the joint work of the temperature outer loop control model and the heat flow inner loop control model, the global and local thermal management goals of optoelectronic co-packaged heterogeneous chips are achieved.

[0031] Step S4: performing heat dissipation structure layout optimization calculation based on the temperature outer loop control model and the heat flow inner loop control model to generate a hybrid heat dissipation layout solution.

[0032] Specifically, a dual-objective optimization function of temperature uniformity and local hotspot control is constructed based on the temperature outer loop control model and the heat flow inner loop control model. The temperature uniformity goal aims to ensure the stability of the overall temperature distribution of the chip and reduce the mechanical stress and performance fluctuations caused by temperature differences; the local hotspot control goal focuses on eliminating or alleviating the heat concentration problem generated in the high power consumption area to ensure that the key functional modules of the chip operate within a safe temperature range. The constraints of the heat dissipation structure are set for the dual-objective optimization function. The constraints include chip structure size restrictions, heat dissipation material selection constraints, manufacturing process constraints, and cost restrictions. Through a comprehensive analysis of these constraints, layout constraint data is generated to define the feasible space for heat dissipation structure design, that is, the overall layout space of the heat dissipation structure. Within the overall layout space, each design scheme of the heat dissipation structure meets physical and engineering constraints. The overall layout space is input into the heat dissipation structure design unit to arrange the centralized heat dissipation unit. The centralized heat dissipation unit uses a single large heat sink, such as a heat sink, heat pipe, or liquid cooling heat sink, which is located in the high heat flux area of ​​the chip. Through the analysis of the chip hotspot position, the design unit can accurately determine the structural layout data of the central heat sink. The heat transfer path calculation is performed on the layout data, the heat transfer efficiency from the hot spot to the heat sink is analyzed, and the centralized heat dissipation layout parameters are generated. The thermal conductivity of the material, the interface thermal resistance and the characteristics of the cooling medium need to be considered in the heat transfer path calculation process to ensure that the centralized heat dissipation unit can efficiently export heat from the core area of ​​the chip. At the same time, the overall layout space is divided into distributed heat dissipation units. The distributed heat dissipation unit achieves uniform heat distribution and multi-point cooling by arranging multiple small heat sinks on the surface of the chip. According to the heat flux density distribution data provided by the heat flux inner ring model, the design unit determines the specific layout position data of the multi-point heat sink. These data reflect the cooling demand intensity of each area of ​​the chip, thereby guiding the implementation of the distributed layout calculation. In the distributed layout calculation, the position, size and cooling capacity of each small heat sink are optimized to generate distributed heat dissipation layout parameters, which describe the optimal configuration of the multi-point heat sink under the premise of satisfying the global temperature balance. Transient thermal response testing and correction are performed according to the centralized heat dissipation layout parameters and distributed heat dissipation layout parameters. The transient thermal response test evaluates the performance of the heat dissipation structure layout under actual conditions by simulating the dynamic temperature changes of the chip under different operating conditions. The test results can reveal the synergy between centralized and distributed cooling units, as well as the hybrid layout's ability to respond to sudden high power events. Based on the test results, necessary modifications are made to the layout parameters, such as adjusting the size, location, or material properties of the heat sink to ensure the reliability and practicality of the solution. An optimized hybrid cooling layout solution is generated.

[0033] The heat dissipation structure is located according to the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters to determine the key heat dissipation areas and potential hot spots inside the chip. By analyzing the heat flow characteristics and temperature gradients of these areas, the layout positions of the temperature sensors are planned and the temperature sensor layout position data is generated. Based on the temperature sensor layout position data, an array of temperature monitoring points is established to ensure that the monitoring points can cover the main heat sources and heat transfer paths of the chip. The sampling frequency of the temperature monitoring point array is calculated to obtain the adapted sampling timing parameters. The dynamic thermal characteristics of the chip, the time variation of the heating load and the heat transfer rate are comprehensively considered to ensure that the data acquisition network can capture the details of the transient thermal response. Based on the sampling timing parameters, a complete data acquisition network is constructed, the loading timing is designed to apply the test signal, and an adapted test loading timing is generated. Based on the test loading timing, a transient thermal response test model is established to perform continuous pulse heating on the optoelectronic co-packaged heterogeneous chip to simulate the thermal load changes under actual operating conditions. Through the test, transient temperature rise data is obtained and the temperature response behavior of the chip under pulse heating conditions is recorded. Based on these temperature rise data, temperature response analysis is performed to generate a transient characteristic curve to describe the temperature change process of the chip from thermal excitation to reaching a stable state. The transient characteristic curve is exponentially fitted to extract the temperature decay characteristic parameters. The temperature decay characteristic parameters reflect the speed and dynamic behavior of the chip heat dissipation. Through these parameters, the time constant is extracted to generate the thermal time constant data, which describes the speed of heat transfer and heat diffusion inside the chip. Based on the thermal time constant data, the transient temperature rise data is subjected to steady-state thermal resistance calculation to obtain the thermal resistance data of each layer of the chip. These data describe the heat transfer resistance of different material layers in the chip structure. Based on this, a thermal resistance network model is constructed to generate thermal resistance distribution data. The thermal capacity inversion calculation is performed on the thermal resistance distribution data and the thermal time constant data to extract the thermal capacity distribution data of each part of the chip. The thermal capacity distribution data reflects the ability of different regions of the chip to store heat. The characteristic parameters of the thermal resistance distribution data and the thermal capacity distribution data are fused to generate the thermal characteristic comprehensive data. The correction coefficient of the thermal characteristic comprehensive data is calculated to generate the parameter correction matrix. The parameter correction matrix corrects the heat dissipation layout parameters by calibrating the deviation between the experiment and the model prediction, so that the model is more consistent with the actual chip operation characteristics. Based on the parameter correction matrix, the thermal characteristics of the chip are calibrated to obtain the thermal characteristic correction parameters. According to the thermal characteristic correction parameters, the heat flux density is calculated and dynamically adjusted for the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters, and the cooperation mechanism between the two heat dissipation layouts is optimized. By adjusting the centralized heat dissipation layout parameters, the heat in the core area of ​​the chip can be quickly exported; at the same time, by optimizing the distributed heat dissipation layout parameters, the temperature uniformity of the entire chip is ensured to avoid the accumulation of local hot spots.Through the above steps, a hybrid heat dissipation layout solution is generated, which takes into account the high efficiency of centralized heat dissipation and the uniformity of distributed heat dissipation, and meets the high power consumption and high performance heat dissipation requirements of optoelectronic co-packaged heterogeneous chips.

[0034] According to the thermal characteristic correction parameters, the heat flow resistance of the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters is calculated to obtain the heat flow resistance distribution data, which reflects the difficulty of heat conduction in different areas of the chip and the main bottlenecks on the heat flow path. Based on the heat flow resistance distribution data, a heat flow transfer channel is established. The design of the heat flow transfer channel combines the chip heat source distribution, the heat transfer path and the geometric layout of the radiator to form a complete heat flow network for effectively transferring heat from the inside of the chip to the external heat dissipation device. The heat dissipation power is distributed through the heat flow transfer channel to optimize the cooperative relationship between the centralized and distributed heat dissipation units. By analyzing the heat flow distribution, the power control sequence is obtained to define the working power allocation rules of each heat dissipation unit under different heat load conditions. Based on the power control sequence, the switching thresholds of the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters are set to generate threshold control data. These threshold control data can dynamically adjust the switching point of the heat dissipation mode, for example, when the local temperature exceeds a certain value, the centralized heat dissipation is started first, and when the power density is low, the distributed heat dissipation is preferred to save energy. The control mode judgment and dynamic power allocation are performed on the threshold control data to generate heat flow adjustment instructions. The role of heat flow regulation instructions is to coordinate the working status of each heat dissipation unit so that it can respond quickly according to real-time temperature changes. Through these instructions, the temperature load mutation response calculation is realized, so as to stabilize the temperature distribution of the chip in a short time and generate power control data for controlling the power output of the heat dissipation unit. The power control data contains dynamic adjustment strategies under different heat load conditions. The centralized heat dissipation layout parameters are analyzed for local hot spot temperature to obtain centralized temperature field data, which describes the heat distribution characteristics of the centralized heat dissipation unit under different working conditions. Based on the centralized temperature field data, the central heat dissipation control analysis is performed to generate centralized heat dissipation control parameters. These parameters can optimize the operation of the centralized heat dissipation unit, such as adjusting the geometric structure of the heat sink, the material properties of the thermal interface, or the flow rate of the cooling medium. At the same time, a similar local hot spot temperature analysis is performed on the distributed heat dissipation layout parameters to obtain distributed temperature field data, which reflects the multi-point heat dissipation characteristics of the distributed heat dissipation unit and its contribution to the overall temperature uniformity. By analyzing the distributed temperature field data, a distributed heat dissipation control analysis is performed to generate distributed heat dissipation control parameters. The distributed heat dissipation control parameters are used to adjust the position, cooling capacity and working mode of the multi-point heat sink, thereby improving the overall heat dissipation efficiency. Cooperative control calculation is performed based on centralized heat dissipation control parameters and distributed heat dissipation control parameters. The goal of cooperative control calculation is to optimize the cooperation mechanism between centralized and distributed heat dissipation units to ensure rapid heat dissipation under high power loads and maintain temperature stability and minimize heat dissipation energy consumption under low power loads. Through this process, a hybrid heat dissipation layout solution is finally generated, which can find the best balance between centralized heat dissipation and distributed heat dissipation, taking into account both efficient chip heat dissipation and system energy efficiency improvement.

[0035] In the embodiment of the present invention, by establishing a three-dimensional thermal characteristic model and combining it with signal analysis, the temperature distribution of the chip is accurately predicted, the heat dissipation design is more targeted, and the hot spot temperature is effectively reduced; a dual-loop control structure of a temperature outer loop and a heat flow inner loop is adopted to achieve coordinated control of the global temperature field uniformity control and precise adjustment of local hot spots, thereby improving the control accuracy of the heat dissipation system; a centralized and distributed hybrid heat dissipation layout strategy is introduced to overcome the limitations of a single heat dissipation method and achieve the optimal configuration of heat dissipation resources; through transient thermal response testing and parameter correction mechanisms, the accuracy of the heat dissipation model is improved, so that the system can better adapt to actual working conditions; a heat dissipation control method based on dynamic load monitoring is established to solve the problem that the traditional fixed monitoring point solution cannot accurately reflect the temperature distribution; dynamic allocation of heat dissipation power and automatic adjustment of thresholds are achieved to avoid frequent mode switching and improve system stability.

[0036] In a specific embodiment, the process of executing step S1 may specifically include the following steps:

[0037] Measure the geometric parameters of each functional module of the optoelectronic co-packaged heterogeneous chip to obtain geometric dimension data, and divide the grid units according to the geometric dimension data to generate initial grid division data;

[0038] Perform mesh encryption processing on the hot spot area according to the initial mesh division data to obtain encrypted mesh data, and construct a three-dimensional structure model based on the encrypted mesh data;

[0039] The material thermal conductivity data, heat capacity data and interface thermal resistance data of the optoelectronic co-packaged heterogeneous chip are input into the three-dimensional structure model to obtain the distribution data of thermal physical property parameters;

[0040] Construct the heat conduction equation based on the distribution data of thermal physical parameters, and generate the heat transfer coefficient matrix according to the thermal convection and thermal radiation boundary conditions;

[0041] The ambient temperature data and the initial temperature distribution data are input into the heat transfer coefficient matrix, and the boundary constraint calculation is performed to obtain the boundary condition data. The power consumption distribution of each functional module of the optoelectronic co-packaged heterogeneous chip is calculated, and the power consumption distribution data is generated based on the boundary condition data.

[0042] The heat transfer coefficient matrix is ​​adaptively solved in time step according to the power consumption distribution data to obtain the solution of the heat conduction equation. The solution of the heat conduction equation is input into the temperature field calculation model to perform multi-heat source coupling analysis and generate a three-dimensional thermal characteristic model.

[0043] Specifically, the geometric parameters of each functional module of the optoelectronic co-packaged heterogeneous chip are measured to obtain the length of the module ,width ,high , and the spacing between modules These geometric dimension data form the basis of the chip spatial structure and are used for subsequent meshing. In the meshing process, by setting the global mesh size , discretize the complex chip geometry into regular units to form the initial mesh data. The unit volume of the initial mesh is expressed as In order to improve the calculation accuracy of the hot spot area, the mesh is encrypted in these areas. The mesh unit size of the hot spot area Smaller than the global grid to capture local heat transfer details. The encrypted grid data is used to build a three-dimensional structural model that fully reflects the spatial geometric characteristics of the chip and the distribution of discrete units. In the three-dimensional structural model, the thermal physical parameters of the material are input, including the thermal conductivity , heat capacity and interface thermal resistance Thermal conductivity Indicates the thermal conductivity of a material. Its unit is a combination of power, length, and temperature. Heat capacity Indicates the ability of a material to store heat, while the interface thermal resistance Describes the degree of resistance to heat transfer between different materials. These thermophysical parameters are distributed according to modules and interfaces to generate thermophysical parameter distribution data. Based on the thermophysical parameter distribution data, the heat conduction equation of the chip is constructed, and its basic form is:

[0044] ;

[0045] in, is the material density, is the temperature, It's time. is the temperature gradient, is the heat source power per unit volume. This equation describes the temporal and spatial distribution of heat inside the chip. When constructing the heat conduction equation, boundary conditions are considered by introducing boundary coefficients for convection and radiation. and To describe the heat exchange behavior between the chip surface and the external environment, generate the heat transfer coefficient matrix , its discrete form is:

[0046] ;

[0047] Heat transfer coefficient matrix Combining grid division and material thermal properties, a solution framework for heat conduction problems is formed. On this basis, the ambient temperature and the initial temperature distribution Input the heat transfer coefficient matrix, perform boundary constraint calculations, and obtain boundary condition data. Boundary condition data is used to define the heat flow interaction between the chip and the external environment to ensure the physical constraints of the model. Based on these boundary conditions, the power distribution of each functional module of the chip is Calculate and map the power consumption distribution of the module to the grid unit to generate power consumption distribution data. According to the power consumption distribution data, the heat transfer coefficient matrix is ​​adaptively solved in time step. The choice of must satisfy the numerical stability conditions, such as The solution of the heat conduction equation is obtained by implicit solution method. , which describes the temperature distribution inside the chip that evolves over time. The solution to the heat conduction equation is input into the temperature field calculation model to perform multi-heat source coupling analysis. The distribution and interaction of the chip are used to generate a three-dimensional thermal characteristic model. The three-dimensional thermal characteristic model reveals the temperature distribution characteristics, heat flow path and hot spot location inside the chip, providing data support for heat dissipation design.

[0048] In a specific embodiment, the process of executing step S2 may specifically include the following steps:

[0049] Perform load monitoring on each functional module of the optoelectronic co-packaged heterogeneous chip, obtain load data under different working modes, and establish a signal acquisition sequence based on the load data;

[0050] The signal acquisition sequence is input into the signal acquisition unit, and multi-channel parallel signal sampling is performed on each functional module of the optoelectronic co-packaged heterogeneous chip to obtain the original signal sampling data;

[0051] Perform power spectrum calculation on the original signal sampling data to obtain initial power spectrum data, and perform density normalization processing on the initial power spectrum data to generate signal power spectrum density data;

[0052] According to the signal power spectrum density data, the operating frequency of each functional module of the optoelectronic co-packaged heterogeneous chip is extracted to obtain the frequency characteristic data;

[0053] Perform duty cycle analysis and peak power calculation on the frequency characteristic data to generate power characteristic parameters, and perform feature matching calculation on the power characteristic parameters to obtain power consumption mapping parameters;

[0054] According to the power consumption mapping parameters, the power consumption mode of each functional module of the optoelectronic co-packaged heterogeneous chip is identified to obtain power consumption classification data, and the power consumption classification data is numerically predicted to generate power consumption prediction data.

[0055] Specifically, the load of each functional module of the chip is monitored, and its operating status in different working modes is recorded to obtain load data. is a function of time, indicating that each module For different working modes, such as high-performance mode and low-power mode, the load data presents periodic changes or random fluctuations. By analyzing these load data, a signal acquisition sequence is constructed. ,in Indicates the number of the functional module. Indicates time. The design of the signal acquisition sequence needs to take into account the working characteristics of the module to ensure that the collected signal can fully reflect the load change. The generated signal acquisition sequence is input into the signal acquisition unit, and the electrical signals of each functional module are sampled in real time using multi-channel parallel sampling technology to obtain the original signal sampling data. The original signal sampling data represents the voltage or current change of each module at the sampling time. Through multi-channel sampling, the signals of all modules are obtained at the same time to avoid the influence of timing deviation on subsequent analysis. Sampling frequency The choice of needs to satisfy the Nyquist sampling theorem, that is ,in It is the highest frequency of the signal to ensure that the sampled data retains the signal information completely. The power spectrum of the original signal sampling data is calculated to convert the time domain signal to the frequency domain. The power spectrum of the signal is calculated by fast Fourier transform. , whose expression is:

[0056] ;

[0057] in, is the time window length of the signal sampling, is the frequency, is an imaginary unit. Power spectrum Describes the energy distribution of the signal at different frequency components. Perform density normalization to generate signal power spectrum density data :

[0058] ;

[0059] According to the signal power spectral density data , extract the operating frequency of each functional module. Operating frequency is the frequency point where the peak value in the power spectrum density is located, and its formula is:

[0060] ;

[0061] Frequency characteristic data Reflects the main working status of each module, and combines these data to perform duty cycle analysis. It is defined as the proportion of time that the module is in a high load state during a working cycle. The calculation formula is:

[0062] ;

[0063] in, is the high load time, is the duty cycle. Using the operating frequency and duty cycle, calculate the peak power of the module :

[0064] ;

[0065] in, and are the voltage and current of the module respectively. Perform feature matching calculations to generate power consumption mapping parameters The power consumption mapping parameter represents the relationship between the power of the module and its characteristics, for example, it can be expressed as:

[0066] ;

[0067] in, is an undetermined coefficient, which represents the power characteristic weight of the module. , identify the power consumption patterns of each functional module. Use clustering algorithms, such as K-means, to divide the power consumption characteristics of the modules into different patterns and generate power consumption classification data For example, based on the relationship between power and frequency, the module is divided into high-performance mode and energy-saving mode. Combined with the power consumption classification data, the power consumption is numerically predicted through prediction algorithms such as support vector machines or neural networks to generate power consumption prediction data. The basic formula for power consumption prediction is expressed as:

[0068] ;

[0069] in, To predict the function, the characteristic parameters and classification results of the module are comprehensively considered.

[0070] In a specific embodiment, the process of executing step S3 may specifically include the following steps:

[0071] Based on the power consumption prediction data and the three-dimensional thermal characteristic model, the temperature field evolution of the optoelectronic co-packaged heterogeneous chip is calculated to obtain the temperature distribution matrix;

[0072] Arrange temperature monitoring points for optoelectronic co-packaged heterogeneous chips according to the temperature distribution matrix, obtain monitoring point coordinate data, and construct grid temperature data based on the monitoring point coordinate data;

[0073] Perform temperature gradient calculation on the grid temperature data to obtain temperature field distribution characteristic data, and divide the hot spot area according to the temperature field distribution characteristic data to generate temperature monitoring data;

[0074] The temperature monitoring data is input into the temperature outer loop controller to perform temperature threshold comparison calculation to obtain a temperature deviation matrix, and global temperature compensation is performed based on the temperature deviation matrix to generate a global temperature compensation coefficient;

[0075] Perform characteristic decomposition operation on the temperature monitoring data according to the temperature global compensation coefficient to obtain temperature response data, and build a temperature outer loop control model based on the temperature response data;

[0076] Calculate the local temperature difference of the temperature monitoring data to obtain the temperature difference matrix, and perform heat flux density partition mapping based on the temperature difference matrix to generate local heat flux distribution data;

[0077] The local heat flux distribution data is input into the heat flux inner loop controller to perform heat flux density dynamic response calculation, obtain heat flux density compensation parameters, and build a heat flux inner loop control model based on the heat flux density compensation parameters.

[0078] Specifically, based on the power consumption prediction data The heat source input conditions of the chip are constructed based on the three-dimensional thermal characteristic model, and the dynamic evolution of the temperature field in the chip is described using the heat conduction equation. The expression of the heat conduction equation is:

[0079] ;

[0080] in, is the temperature field, is the material density, is the specific heat capacity, is the thermal conductivity, is the power density per unit volume. The equation is discretely solved by finite difference method or finite element method to obtain the temperature distribution matrix ,in Respectively represent the spatial coordinate index of the grid point, After obtaining the temperature distribution matrix, analyze the temperature variation law inside the chip and arrange the temperature monitoring points. According to the principle of prioritizing the area with larger temperature gradient, select the key position as the temperature monitoring point and obtain the coordinate data of the monitoring point. ,in is the index of the monitoring point. Through the interpolation algorithm, the temperature data of the monitoring point is mapped to the grid structure to construct the grid temperature data . Calculate the temperature gradient of the grid temperature data. Temperature Gradient Describes the direction and intensity of heat transfer within the chip, and its calculation formula is:

[0081] ;

[0082] By solving the gradient data, the temperature field distribution characteristic data is obtained Using this data, we can identify hot spots within the chip and divide them into high-risk areas where the temperature exceeds the safety threshold. The hot spot division rules are based on the temperature threshold. , that is, satisfy The area is marked as a hot spot and temperature monitoring data is generated . The temperature monitoring data Input the temperature outer loop controller, perform temperature threshold comparison calculation, and generate the temperature deviation matrix , which is defined as:

[0083] ;

[0084] Based on the temperature deviation matrix, the temperature global compensation coefficient is calculated by the global temperature compensation algorithm , to adjust the global parameters of the cooling system, such as the cooling medium flow rate or the radiator power. The calculation of the global compensation coefficient is expressed as:

[0085] ;

[0086] in, is the chip volume. According to the global compensation coefficient, the temperature monitoring data is subjected to characteristic decomposition operation to extract the main change mode of the chip temperature field. Through singular value decomposition, the temperature field is decomposed into multiple modes, which are expressed as:

[0087] ;

[0088] in, is the characteristic value, and They are spatial features and temporal features respectively. By selecting significant feature components, temperature response data is generated to build a temperature outer loop control model. The local temperature difference of the temperature monitoring data is calculated to generate a temperature difference matrix , represents the temperature difference in the local area. By mapping the temperature difference to the heat flux density, the local heat flux distribution data is obtained. , the relationship is:

[0089] ;

[0090] The local heat flux distribution data is input into the heat flux inner loop controller to calculate the dynamic response of the heat flux density to cope with sudden changes in power consumption. Compensation parameters for dynamic response Indicates the intensity of adjusting the local cooling unit, and its calculation formula is:

[0091] ;

[0092] in, is the area of ​​the local hot spot. The heat flux inner loop control model is constructed using the heat flux density compensation parameters. This model combines real-time heat flux regulation and dynamic heat load response capabilities, and works in conjunction with the temperature outer loop control model to achieve comprehensive control of the chip temperature field and optimize heat dissipation efficiency.

[0093] In a specific embodiment, the process of executing step S4 may specifically include the following steps:

[0094] Based on the temperature outer loop control model and the heat flow inner loop control model, a dual-objective optimization function for temperature uniformity and local hot spot control is constructed;

[0095] Setting heat dissipation structure constraints for the dual-objective optimization function to obtain layout constraint data, and generating an overall layout space of the heat dissipation structure according to the layout constraint data;

[0096] The overall layout space is input into the heat dissipation structure design unit, and the centralized heat dissipation unit is arranged to obtain the structural layout data of the central heat sink, and the heat transfer path of the structural layout data of the central heat sink is calculated to generate the centralized heat dissipation layout parameters;

[0097] The overall layout space is divided into distributed heat dissipation units to obtain the layout position data of the multi-point radiators, and the distributed layout calculation is performed on the layout position data of the multi-point radiators to generate distributed heat dissipation layout parameters;

[0098] Transient thermal response testing and correction are performed according to centralized heat dissipation layout parameters and distributed heat dissipation layout parameters to generate a hybrid heat dissipation layout solution.

[0099] Specifically, according to the global temperature distribution provided by the temperature outer loop control model and the local heat flux density provided by the heat flux inner loop control model , define a bi-objective optimization function. The first objective of the optimization function is to minimize the non-uniformity of the temperature field, which is achieved by calculating the standard deviation of the temperature inside the chip, and its expression is:

[0100] ;

[0101] in, is the average chip temperature, is the chip volume. The second goal is to minimize the risk of temperature exceeding the standard in the hot spot area, which is achieved by weighted integration of the temperature in the hot spot area, and its expression is:

[0102] ;

[0103] in, Indicates the hot spot area. is the safe temperature threshold. These two objectives are combined through multi-objective optimization techniques, such as linear weighted method, to construct a comprehensive optimization objective:

[0104] ;

[0105] in, and is a weight coefficient that reflects the importance of global uniformity and hot spot control. After constructing the optimization target, set constraints on the heat dissipation structure to ensure that the design is physically and engineering feasible. These constraints include heat sink size constraints, chip packaging space constraints, and manufacturing process constraints. For example, the thickness of the heat sink and width Must be smaller than the maximum size allowed by the package. The mathematical form of the constraint is expressed as:

[0106] ;

[0107] The overall layout space of the heat dissipation structure is generated by these constraints and is expressed as , which contains all design solutions that meet the constraints. The overall layout space is input into the heat dissipation structure design unit to arrange the centralized heat dissipation unit. The centralized heat dissipation unit is used in the high heat flux density area of ​​the chip, and its layout needs to ensure direct contact with the hot spot area. By analyzing the heat transfer path in the chip , determine the optimal position and shape of the central radiator, and generate the structural layout data of the central radiator. The heat transfer path is achieved by minimizing the thermal resistance, and its optimization goal is:

[0108] ;

[0109] in, is the heat flow path length, is the thermal conductivity, is the contact area of ​​the heat sink. The calculated heat transfer path optimization results are used to generate the centralized heat dissipation layout parameters. After completing the layout of the centralized heat dissipation unit, the overall layout space is divided into distributed heat dissipation units. Distributed heat dissipation units are arranged at multiple locations on the chip surface to evenly disperse heat and improve the overall heat dissipation performance. Perform cluster analysis to determine the layout location data of the multi-point heat sink. Use optimization algorithms, such as genetic algorithms, to optimize the specific shape and location of the multi-point heat sink and generate distributed heat dissipation layout parameters. After obtaining the centralized and distributed heat dissipation layout parameters, perform transient thermal response testing and correction to evaluate the performance of the heat dissipation structure under dynamic conditions. The transient thermal response test applies pulse power consumption to the chip. , simulating the dynamic changes of heat load during operation. By numerically solving the heat conduction equation, the transient temperature rise inside the chip is calculated. , and the steady-state heat distribution Compare and determine the response efficiency of the heat sink at different time points. The correction process involves adjusting the heat sink parameters to optimize dynamic performance. For example, if the response speed of the centralized cooling unit is slow, increase its contact area Or improve the thermal conductivity of thermal interface materials For distributed cooling units, adjust their position Or the flow rate of the cooling medium to improve the uniformity of heat flow. By integrating the optimization results of centralized and distributed cooling units, a hybrid cooling layout solution is generated. This solution can find a balance between the high efficiency of centralized cooling and the uniformity of distributed cooling, while meeting the dual-objective optimization requirements of global temperature uniformity and local hotspot control.

[0110] In a specific embodiment, the execution step performs transient thermal response testing and correction according to the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters, and the process of generating a hybrid heat dissipation layout solution may specifically include the following steps:

[0111] Perform heat dissipation structure positioning on the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters, obtain the temperature sensor layout position data, and establish a temperature monitoring point array according to the temperature sensor layout position data;

[0112] Calculate the sampling frequency of the temperature monitoring point array to obtain the sampling timing parameters, and build a data acquisition network based on the sampling timing parameters to generate the test loading timing;

[0113] A transient thermal response test model is established based on the test loading sequence, and continuous pulse heating is performed on the optoelectronic co-packaged heterogeneous chip to obtain transient temperature rise data. Temperature response analysis is performed based on the transient temperature rise data to generate a transient characteristic curve.

[0114] Perform exponential fitting calculation on the transient characteristic curve to obtain temperature decay characteristic parameters, and extract time constants based on the temperature decay characteristic parameters to generate thermal time constant data;

[0115] The steady-state thermal resistance is calculated for the transient temperature rise data according to the thermal time constant data to obtain the thermal resistance data of each layer of the chip. A thermal resistance network model is constructed based on the thermal resistance data of each layer of the chip to generate thermal resistance distribution data.

[0116] Perform heat capacity inversion calculation on thermal resistance distribution data and thermal time constant data to obtain heat capacity distribution data, and perform characteristic parameter fusion on thermal resistance distribution data and heat capacity distribution data to obtain comprehensive thermal characteristic data;

[0117] Calculate the correction coefficient of the comprehensive data of thermal characteristics to generate a parameter correction matrix, and calibrate the thermal characteristics based on the parameter correction matrix to obtain thermal characteristic correction parameters;

[0118] The heat flux density of the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters are calculated and dynamically adjusted according to the thermal characteristic correction parameters to generate a hybrid heat dissipation layout solution.

[0119] Specifically, the heat dissipation structure is located through the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters to determine the temperature monitoring requirements of the key areas of the chip. The goal of heat dissipation structure positioning is to identify areas where heat is concentrated or the conduction path is complex, and to analyze the temperature distribution of the chip. and heat flux , place the temperature sensors at these key locations. The coordinate data of the temperature sensor The location of the monitoring point is determined, and based on this, a temperature monitoring point array is established to ensure that each thermally critical area of ​​the chip has accurate temperature feedback. The sampling frequency of the temperature monitoring point array is calculated to ensure that the dynamic characteristics of temperature changes can be captured. Sampling frequency The calculation of must satisfy the Nyquist sampling theorem:

[0120] ;

[0121] in, The highest frequency of temperature change. By analyzing the thermal load change of the chip, determine the appropriate sampling timing parameters , these parameters represent the sampling time interval. Using these sampling timing parameters, the data acquisition network is constructed ,in is a set of sensor nodes, It is the data transmission path between nodes. Combine the sampling timing parameters and the data acquisition network to generate the test loading timing to ensure that data acquisition is synchronized with the thermal load. Based on the test loading timing, a transient thermal response test model is established to apply continuous pulse heating to the chip. The input power of pulse heating is expressed as:

[0122] ;

[0123] in, is the pulse heating power, is the heating time period. Through pulse heating, the transient temperature rise of the chip is measured. , and obtain the temperature change curve over time. According to the transient temperature rise data, the temperature response analysis is performed to generate the transient characteristic curve to describe the thermal dynamic behavior of the chip during heating and cooling. The transient characteristic curve is exponentially fitted to extract the temperature attenuation characteristic parameters. The temperature attenuation is expressed as an exponential function:

[0124] ;

[0125] in, is the steady-state temperature, is the peak value of transient temperature rise, is the time constant, which indicates the time characteristic required for the system to reach a steady state. By fitting the curve, the time constant can be accurately extracted. , generate thermal time constant data. Based on the thermal time constant data, the steady-state thermal resistance is calculated for the transient temperature rise data. Steady-state thermal resistance is defined as:

[0126] ;

[0127] in, , is the ambient temperature. By mapping the thermal resistance distribution to different layers of the chip, the thermal resistance data of each layer of the chip is obtained, and a thermal resistance network model is constructed. The thermal resistance network model is represented as a collection of nodes and edges. , where the node Indicates the layers of the chip, edges The thermal resistance between layers is expressed and thermal resistance distribution data is generated. The thermal capacity is inverted and calculated based on the thermal resistance distribution data and thermal time constant data. It is expressed as:

[0128] ;

[0129] The heat capacity distribution data of each layer is obtained by calculation, and the characteristic parameters are integrated with the thermal resistance distribution data to generate comprehensive thermal characteristic data. The correction coefficient of the comprehensive thermal characteristic data is calculated to generate a parameter correction matrix The correction matrix is ​​used to correct the deviation between thermal characteristic data and experimental measurement, and it is expressed as:

[0130] ;

[0131] in, is the correction coefficient. Based on the correction matrix , calibrate the thermal characteristic data to obtain the thermal characteristic correction parameters. According to the thermal characteristic correction parameters, the heat flux density is calculated and dynamically adjusted for the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters. It is expressed as:

[0132] ;

[0133] in, is the thermal conductivity; The thermal flow response of the centralized and distributed layouts is combined to optimize the final heat dissipation solution and generate a hybrid heat dissipation layout to ensure the temperature uniformity and efficient heat dissipation performance of the chip.

[0134] In a specific embodiment, the execution step calculates and dynamically adjusts the heat flux density of the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters according to the thermal characteristic correction parameters, and the process of generating a hybrid heat dissipation layout solution may specifically include the following steps:

[0135] Calculating heat flow resistance for centralized heat dissipation layout parameters and distributed heat dissipation layout parameters according to thermal characteristic correction parameters, obtaining heat flow resistance distribution data, and establishing a heat flow transfer channel based on the heat flow resistance distribution data;

[0136] The heat dissipation power is distributed through the heat flow transfer channel to obtain a power control sequence, and the switching thresholds of the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters are set according to the power control sequence to generate threshold control data;

[0137] Perform control mode judgment and dynamic power allocation on the threshold control data, generate heat flow regulation instructions, and perform temperature load sudden change response calculation based on the heat flow regulation instructions to generate power control data;

[0138] Conduct local hot spot temperature analysis on centralized heat dissipation layout parameters to obtain centralized temperature field data, and conduct central heat dissipation control analysis based on the centralized temperature field data to generate centralized heat dissipation control parameters;

[0139] Perform local hot spot temperature analysis on distributed heat dissipation layout parameters to obtain distributed temperature field data, and perform distributed heat dissipation control analysis based on the distributed temperature field data to generate distributed heat dissipation control parameters;

[0140] Based on the centralized heat dissipation control parameters and the distributed heat dissipation control parameters, collaborative control calculation is performed to obtain a hybrid heat dissipation layout solution.

[0141] Specifically, the parameters are corrected according to the thermal characteristics , the heat flow resistance is calculated for the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters. It indicates the resistance encountered by heat during conduction. Its calculation formula is:

[0142] ;

[0143] in, is the length of the heat flow path, is the thermal conductivity of the material, For different regions within the chip, the thermal conductivity and path length are adjusted by combining the thermal characteristic correction parameters to generate heat flow resistance distribution data The heat flow resistance distribution data reflects the heat flow transfer capacity of each area inside the chip. Based on the heat flow resistance distribution data, the heat flow transfer channel is established. The heat flow transfer channel describes the heat transfer path from the high temperature area to the low temperature area, and its optimization goal is to minimize the overall thermal resistance. The transfer efficiency of the heat flow channel is expressed as:

[0144] ;

[0145] in, is the heat flux density, is the temperature difference. During the optimization process, the layout and material parameters of the transfer channel are adjusted to ensure that heat is quickly transferred from the inside of the chip to the external heat sink. The heat dissipation power of the chip is allocated in the heat flow transfer channel. By analyzing the heat flow requirements of different areas of the chip, a power control sequence is generated. , and its calculation formula is:

[0146] ;

[0147] in, It is The cooling power requirement of each area is is the area of ​​the corresponding region. Based on the power control sequence, the switching thresholds of the centralized and distributed cooling units are set. Switching threshold It is defined as when the temperature of a region exceeds a certain limit, the corresponding cooling unit is activated first. The setting formula is:

[0148] ;

[0149] in, It is a safe temperature. The threshold adjustment is determined by the heat flow demand and power allocation. The generated threshold control data Used for dynamic cooling unit switching. The control mode is judged based on the threshold control data, and dynamic power allocation is performed to generate heat flow regulation instructions. The control mode is judged based on the real-time temperature distribution of the chip. Whether it exceeds the threshold. If it exceeds the threshold, the system adjusts the instruction according to the heat flow. Dynamically adjust the power and heat dissipation path of the radiator. The formula for generating the heat flow regulation instruction is:

[0150] ;

[0151] in, is the target heat flux, is the current heat flux density. Through dynamic adjustment, it quickly responds to sudden changes in chip temperature load and generates accurate power control data. After the power allocation is completed, the centralized heat dissipation layout parameters are analyzed for local hot spot temperature to obtain centralized temperature field data. . Use these data to perform central cooling control analysis and generate centralized cooling control parameters , whose expression is:

[0152]

[0153] in, is the area volume covered by the centralized radiator. At the same time, a similar local hot spot temperature analysis is performed on the distributed cooling layout parameters to obtain the distributed temperature field data . Based on these data, distributed cooling control analysis is performed to generate distributed cooling control parameters. , whose expression is:

[0154]

[0155] By calculating the centralized and distributed control parameters, the performance of the two cooling units is optimized respectively. and distributed cooling control parameters Combined, collaborative control calculation is performed. The collaborative control goal is to ensure that the centralized and distributed radiators achieve the optimal balance between power and efficiency. The optimization objective function is expressed as:

[0156] ;

[0157] in, and is the weight coefficient. By optimizing the collaborative control function, a hybrid heat dissipation layout solution is finally obtained.

[0158] The above describes the heat dissipation integration method of optoelectronic co-packaged heterogeneous chips in the embodiment of the present invention. The following describes the heat dissipation integration device of optoelectronic co-packaged heterogeneous chips in the embodiment of the present invention. Figure 2 , an embodiment of the optoelectronic co-packaged heterogeneous chip heat dissipation integrated device in the embodiment of the present invention includes:

[0159] Modeling module, used to perform finite element modeling analysis on optoelectronic co-packaged heterogeneous chips to obtain a three-dimensional thermal characteristic model;

[0160] The analysis module is used to collect signals and analyze frequency domain characteristics of each functional module of the optoelectronic co-packaged heterogeneous chip to generate power consumption prediction data;

[0161] A calculation module is used to calculate the temperature field distribution of optoelectronic co-packaged heterogeneous chips based on power consumption prediction data and a three-dimensional thermal characteristic model, and to construct a temperature outer loop control model and a heat flow inner loop control model;

[0162] The generation module is used to perform heat dissipation structure layout optimization calculation based on the temperature outer loop control model and the heat flow inner loop control model to generate a hybrid heat dissipation layout solution.

[0163] Through the coordinated cooperation of the above-mentioned components, by establishing a three-dimensional thermal characteristic model and combining it with signal analysis, the accurate prediction of chip temperature distribution is achieved, making the heat dissipation design more targeted and effectively reducing the hot spot temperature; the dual-loop control structure of the temperature outer loop and the heat flow inner loop is adopted to achieve the coordinated cooperation of global temperature field uniformity control and local hot spot precise adjustment, thereby improving the control accuracy of the heat dissipation system; the introduction of centralized and distributed hybrid heat dissipation layout strategies overcomes the limitations of a single heat dissipation method and achieves the optimal configuration of heat dissipation resources; through transient thermal response testing and parameter correction mechanisms, the accuracy of the heat dissipation model is improved, so that the system can better adapt to actual working conditions; a heat dissipation control method based on dynamic load monitoring is established to solve the problem that the traditional fixed monitoring point solution cannot accurately reflect the temperature distribution; dynamic allocation of heat dissipation power and automatic adjustment of thresholds are achieved to avoid frequent mode switching and improve system stability.

[0164] Reference Figure 3 In an embodiment of the present invention, a computer device is also provided. The computer device may be a server, and its internal structure may be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0165] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0166] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0167] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0168] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0169] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0170] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A heat dissipation integration method for optoelectronic co-packaging heterogeneous chips, characterized in that: The method comprises: Conduct finite element modeling analysis on optoelectronic co-packaged heterogeneous chips to obtain a three-dimensional thermal characteristic model; Performing signal acquisition and frequency domain characteristic analysis on each functional module of the optoelectronic co-packaged heterogeneous chip to generate power consumption prediction data; The temperature field distribution of the optoelectronic co-packaged heterogeneous chip is calculated according to the power consumption prediction data and the three-dimensional thermal characteristic model, and a temperature outer-loop control model and a heat flow inner-loop control model are constructed; specifically comprising: based on the power consumption prediction data and the three-dimensional thermal characteristic model, the temperature field evolution calculation is performed on the optoelectronic co-packaged heterogeneous chip to obtain a temperature distribution matrix; according to the temperature distribution matrix, temperature monitoring points of the optoelectronic co-packaged heterogeneous chip are arranged to obtain monitoring point coordinate data, and grid temperature data is constructed based on the monitoring point coordinate data; temperature gradient calculation is performed on the grid temperature data to obtain temperature field distribution characteristic data, and hot spot area is divided according to the temperature field distribution characteristic data to generate temperature monitoring data; the temperature monitoring data is converted into According to the input temperature outer loop controller, a temperature threshold comparison calculation is performed to obtain a temperature deviation matrix, and a global temperature compensation is performed based on the temperature deviation matrix to generate a global temperature compensation coefficient; a characteristic decomposition operation is performed on the temperature monitoring data according to the global temperature compensation coefficient to obtain temperature response data, and a temperature outer loop control model is constructed based on the temperature response data; a local temperature difference calculation is performed on the temperature monitoring data to obtain a temperature difference matrix, and a heat flux density partition mapping is performed according to the temperature difference matrix to generate local heat flux distribution data; the local heat flux distribution data is input into the heat flux inner loop controller, a heat flux density dynamic response calculation is performed to obtain a heat flux density compensation parameter, and a heat flux inner loop control model is constructed according to the heat flux density compensation parameter; Based on the temperature outer loop control model and the heat flow inner loop control model, the heat dissipation structure layout optimization calculation is performed to generate a hybrid heat dissipation layout scheme; specifically comprising: constructing a dual-objective optimization function of temperature uniformity and local hot spot control based on the temperature outer loop control model and the heat flow inner loop control model; setting heat dissipation structure constraints for the dual-objective optimization function to obtain layout constraint data, and generating an overall layout space of the heat dissipation structure according to the layout constraint data; inputting the overall layout space into a heat dissipation structure design unit to perform centralized heat dissipation unit layout to obtain structural layout data of a central heat sink, and performing heat transfer path calculation on the structural layout data of the central heat sink to generate centralized heat dissipation layout parameters; dividing the overall layout space into distributed heat dissipation units to obtain layout position data of multi-point heat sinks, and performing distributed layout calculation on the layout position data of the multi-point heat sink to generate distributed heat dissipation layout parameters; performing transient thermal response testing and correction according to the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters to generate a hybrid heat dissipation layout scheme.

2. The optoelectronic co-packaging heterogeneous chip heat dissipation integration method according to claim 1, characterized in that: The finite element modeling analysis of the optoelectronic co-packaged heterogeneous chip is performed to obtain a three-dimensional thermal characteristic model, including: Measuring geometric parameters of each functional module of the optoelectronic co-packaged heterogeneous chip to obtain geometric dimension data, and dividing grid units according to the geometric dimension data to generate initial grid division data; Performing mesh encryption processing on the hot spot area according to the initial mesh division data to obtain encrypted mesh data, and constructing a three-dimensional structure model based on the encrypted mesh data; Inputting the material thermal conductivity data, heat capacity data and interface thermal resistance data of the optoelectronic co-packaged heterogeneous chip into the three-dimensional structure model to obtain thermal physical property parameter distribution data; Constructing a heat conduction equation for the thermal physical property parameter distribution data, and generating a heat transfer coefficient matrix according to thermal convection and thermal radiation boundary conditions; Inputting the ambient temperature data and the initial temperature distribution data into the heat transfer coefficient matrix, performing boundary constraint calculation to obtain boundary condition data, and performing power consumption distribution calculation on each functional module of the optoelectronic co-packaged heterogeneous chip, and generating power consumption distribution data based on the boundary condition data; The heat transfer coefficient matrix is ​​adaptively solved in time step according to the power consumption distribution data to obtain a solution to the heat conduction equation, and the solution to the heat conduction equation is input into a temperature field calculation model to perform multi-heat source coupling analysis to generate a three-dimensional thermal characteristic model.

3. The optoelectronic co-packaging heterogeneous chip heat dissipation integration method according to claim 2, characterized in that: The performing signal acquisition and frequency domain characteristic analysis on each functional module of the optoelectronic co-packaged heterogeneous chip to generate power consumption prediction data includes: Performing load monitoring on each functional module of the optoelectronic co-packaged heterogeneous chip to obtain load data under different working modes, and establishing a signal acquisition sequence according to the load data; Inputting the signal acquisition sequence into a signal acquisition unit, performing multi-channel parallel signal sampling on each functional module of the optoelectronic co-packaged heterogeneous chip, and obtaining original signal sampling data; Performing power spectrum calculation on the original signal sampling data to obtain initial power spectrum data, and performing density normalization processing on the initial power spectrum data to generate signal power spectrum density data; Extracting the operating frequency of each functional module of the optoelectronic co-packaged heterogeneous chip according to the signal power spectrum density data to obtain frequency characteristic data; Performing duty cycle analysis and peak power calculation on the frequency characteristic data to generate power characteristic parameters, and performing characteristic matching calculation on the power characteristic parameters to obtain power consumption mapping parameters; The power consumption mode of each functional module of the optoelectronic co-packaged heterogeneous chip is identified according to the power consumption mapping parameters to obtain power consumption classification data, and the power consumption classification data is numerically predicted to generate power consumption prediction data.

4. The optoelectronic co-packaging heterogeneous chip heat dissipation integration method according to claim 1, characterized in that: The performing transient thermal response testing and correction according to the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters to generate a hybrid heat dissipation layout solution includes: Perform heat dissipation structure positioning on the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters to obtain temperature sensor layout position data, and establish a temperature monitoring point array according to the temperature sensor layout position data; Calculating the sampling frequency of the temperature monitoring point array to obtain sampling timing parameters, and constructing a data acquisition network according to the sampling timing parameters to generate a test loading timing; A transient thermal response test model is established based on the test loading sequence, continuous pulse heating is performed on the optoelectronic co-packaged heterogeneous chip to obtain transient temperature rise data, and temperature response analysis is performed based on the transient temperature rise data to generate a transient characteristic curve; Performing exponential fitting calculation on the transient characteristic curve to obtain temperature decay characteristic parameters, and performing time constant extraction according to the temperature decay characteristic parameters to generate thermal time constant data; Performing steady-state thermal resistance calculation on the transient temperature rise data according to the thermal time constant data to obtain thermal resistance data of each layer of the chip, and constructing a thermal resistance network model based on the thermal resistance data of each layer of the chip to generate thermal resistance distribution data; Performing heat capacity inversion calculation on the thermal resistance distribution data and the thermal time constant data to obtain heat capacity distribution data, and performing characteristic parameter fusion on the thermal resistance distribution data and the heat capacity distribution data to obtain thermal characteristic comprehensive data; Calculating correction coefficients for the comprehensive thermal characteristic data to generate a parameter correction matrix, and performing thermal characteristic calibration based on the parameter correction matrix to obtain thermal characteristic correction parameters; The heat flux density of the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters are calculated and dynamically adjusted according to the thermal characteristic correction parameters to generate a hybrid heat dissipation layout solution.

5. The optoelectronic co-packaging heterogeneous chip heat dissipation integration method according to claim 4, characterized in that: The step of calculating and dynamically adjusting the heat flux density of the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters according to the thermal characteristic correction parameters to generate a hybrid heat dissipation layout solution includes: Performing heat flow resistance calculation on the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters according to the thermal characteristic correction parameters to obtain heat flow resistance distribution data, and establishing a heat flow transfer channel based on the heat flow resistance distribution data; Distributing heat dissipation power through the heat flow transfer channel to obtain a power control sequence, and setting switching thresholds for the centralized heat dissipation layout parameters and the distributed heat dissipation layout parameters according to the power control sequence to generate threshold control data; Performing control mode judgment and dynamic power allocation on the threshold control data to generate a heat flow regulation instruction, and performing temperature load sudden change response calculation according to the heat flow regulation instruction to generate power control data; Performing local hot spot temperature analysis on the centralized heat dissipation layout parameters to obtain centralized temperature field data, and performing central heat dissipation control analysis based on the centralized temperature field data to generate centralized heat dissipation control parameters; Performing local hot spot temperature analysis on the distributed heat dissipation layout parameters to obtain distributed temperature field data, and performing distributed heat dissipation control analysis based on the distributed temperature field data to generate distributed heat dissipation control parameters; A hybrid heat dissipation layout solution is obtained by performing collaborative control calculation based on the centralized heat dissipation control parameters and the distributed heat dissipation control parameters.

6. An optoelectronic co-packaged heterogeneous chip heat dissipation integrated device, characterized in that: Used to perform the optoelectronic co-packaged heterogeneous chip heat dissipation integration method according to any one of claims 1 to 5, the optoelectronic co-packaged heterogeneous chip heat dissipation integration device comprising: Modeling module, used to perform finite element modeling analysis on optoelectronic co-packaged heterogeneous chips to obtain a three-dimensional thermal characteristic model; An analysis module, used to perform signal acquisition and frequency domain characteristic analysis on each functional module of the optoelectronic co-packaged heterogeneous chip, and generate power consumption prediction data; A calculation module, used to calculate the temperature field distribution of the optoelectronic co-packaged heterogeneous chip according to the power consumption prediction data and the three-dimensional thermal characteristic model, and to construct a temperature outer loop control model and a heat flow inner loop control model; A generation module is used to perform heat dissipation structure layout optimization calculation based on the temperature outer loop control model and the heat flow inner loop control model to generate a hybrid heat dissipation layout solution.

7. A computer device, characterized in that: It comprises a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the computer program, it implements the optoelectronic co-packaged heterogeneous chip heat dissipation integration method described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the processor executes the optoelectronic co-packaging heterogeneous chip heat dissipation integration method as described in any one of claims 1 to 5.

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