Chip design method and device, equipment, storage medium and program product

Abstract

The embodiment of the invention provides a method, equipment and device for chip design, a medium and a program product, and relates to the field of chip design tools. The method includes determining at least one confinement circuit structure among a plurality of devices designed for a chip of a first process. Dimensions of a set of devices in each of the at least one confinement circuit structure have a dimensional constraint between the dimensions of the set of devices in each of the at least one confinement circuit structure. The method further includes determining device parameter values of the plurality of devices under a second process different from the first process based on the size constraint; and determining that the chip design for the second process satisfies a circuit performance condition by the device parameter value. The method further includes migrating the chip design from the first process to the second process based on determining that the circuit performance condition is satisfied. In this way, by using the size constraint contained in the constraint circuit structure in the chip design of the first process, the device parameter optimization process under the second process can be accelerated, and thus the process migration efficiency is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of chip design tools. More specifically, embodiments of the present disclosure relate to methods, devices, apparatuses, computer-readable storage media, and computer program products for chip design. Background Art

[0002] Electronic design automation (EDA) software is widely used in the chip design process. In terms of analog chips, with the help of EDA tools, circuit design, circuit simulation, layout design, physical verification, parasitic parameter extraction and other processes can be efficiently performed. At present, there is an uneven gap in chip manufacturing capacity, that is, the manufacturing capacity of some processes is obviously insufficient, while the manufacturing capacity of some processes is still surplus. In this case, how to quickly migrate chip design from one process to another, and then make full use of different process capacities, has become a problem that needs to be solved urgently. Summary of the invention

[0003] Embodiments of the present disclosure provide a solution for chip design.

[0004] In a first aspect of the present disclosure, a method for chip design is provided. The method includes determining at least one constrained circuit structure among a plurality of devices in a chip design for a first process. There is a size constraint between the sizes of a group of devices in each of the at least one constrained circuit structure. The method also includes: determining device parameter values ​​of a plurality of devices under a second process different from the first process based on the size constraint. The method also includes: determining that the chip design for the second process meets circuit performance conditions based on the device parameter values ​​of the plurality of devices under the second process; and migrating the chip design from the first process to the second process based on determining that the chip design for the second process meets the circuit performance conditions.

[0005] In this way, by determining the constrained circuit structure in multiple devices designed for the chip of the first process and utilizing the size constraints between devices in the constrained circuit structure, the device parameter optimization process under the second process can be accelerated, thereby improving the efficiency of process migration.

[0006] In some embodiments of the first aspect, the group of devices in each constrained circuit structure includes a main device and at least one auxiliary device, and wherein determining the device parameter values ​​of the plurality of devices under the second process includes: determining an initial parameter set of the plurality of devices under the second process; determining a reduced parameter set of the plurality of devices under the second process from the initial parameter set based on the size constraint, the reduced parameter set including the size parameters of the main device in each constrained circuit structure under the second process and excluding the size parameters of the at least one auxiliary device in each constrained circuit structure under the second process; determining an intermediate parameter value for the reduced parameter set; and determining the device parameter value for the initial parameter set based on the intermediate parameter value and the size constraint. In this way, by using the size constraint to reduce the parameter set to be determined, the search space can be reduced, thereby accelerating the efficiency of device parameter optimization.

[0007] In some embodiments of the first aspect, the method further comprises: determining a process constraint for the second process, the process constraint indicating a plurality of parameter values ​​that meet the manufacturing requirements of the second process, and wherein determining the device parameter values ​​of the plurality of devices under the second process is also based on the process constraint for the second process. In some embodiments of the first aspect, determining the intermediate parameter value for the reduced parameter set comprises: determining an initial parameter value for the reduced parameter set, the initial parameter value comprising an initial size value of the size parameter of the main device in each constrained circuit structure; and based on the initial parameter value and the process constraint, selecting the intermediate parameter value that meets the manufacturing requirements of the second process from the plurality of parameter values ​​indicated by the process constraint. In this way, device parameter values ​​suitable for a target process can be determined based on process constraints.

[0008] In some embodiments of the first aspect, selecting the intermediate parameter value that meets the manufacturing requirements from the multiple parameter values ​​includes: for a first constraint circuit structure in the at least one constraint circuit structure, based on the initial size value of the size parameter of the main device in the first constraint circuit structure, determining an initial size indicator for the first constraint circuit structure; based on the initial size value, selecting a value adjacent to the initial size value from the multiple parameter values ​​as a candidate value for the size parameter of the main device; based on the candidate value of the size parameter of the main device, determining a candidate size indicator for the first constraint circuit structure; and based on determining that the initial size indicator and the candidate size indicator meet a size matching condition, selecting the candidate value as a value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure. In this way, the candidate parameter value that meets the process constraint can be determined based on the size matching condition, thereby reducing the error caused by size matching.

[0009] In some embodiments of the first aspect, determining the candidate size indicator for the first constrained circuit structure includes: determining a corresponding value of the size parameter of at least one auxiliary device in the first constrained circuit structure based on the candidate value of the size parameter of the main device and the size constraint; and determining the candidate size indicator for the first constrained circuit structure based on the candidate value of the size parameter of the main device and the corresponding value of the size parameter of the at least one auxiliary device. In this way, by determining the candidate size indicator based on the candidate parameter values ​​of both the main device and the auxiliary device, the error caused by size matching can be reduced at the level of each constrained circuit structure.

[0010] In some embodiments of the first aspect, the method further includes: based on determining that the initial size indicator and the candidate size indicator do not meet the size matching condition, selecting an updated candidate value of the size parameter of the main device from the multiple parameter values, the updated candidate value being farther from the initial size value than the candidate value; based on the updated candidate value, determining an updated candidate size indicator for the first constraint circuit structure; and based on determining that the initial size indicator and the updated candidate size indicator meet the size matching condition, selecting the updated candidate value as the value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure. In this way, the matched candidate values ​​can be selected in the order of nearest neighbor to next nearest neighbor, thereby improving the efficiency of size matching.

[0011] In some embodiments of the first aspect, the method also includes: based on determining that the chip design for the second process does not meet the circuit performance conditions, determining updated device parameter values ​​using a genetic mutation algorithm; based on the updated device parameter values, determining updated circuit performance of the chip design for the second process; and based on determining that the updated circuit performance meets the circuit performance conditions, migrating the chip design from the first process to the second process, wherein the chip design for the second process includes the updated device parameter values ​​for the multiple devices.

[0012] In some embodiments of the first aspect, determining updated device parameter values ​​using a genetic mutation algorithm includes: determining a first group of parameter values ​​for the reduced parameter set based on at least one of a genetic probability, a crossover probability, and a mutation probability for the initial parameter values ​​of the reduced parameter set; determining updated intermediate parameter values ​​for the reduced parameter set from the first group of parameter values ​​for the reduced parameter set based on the process constraints and the size constraints; and determining the updated device parameter values ​​for the initial parameter set for the multiple devices based on the updated intermediate parameter values ​​for the reduced parameter set. In this way, the genetic mutation algorithm can be used to iteratively optimize device parameter values, thereby improving the efficiency of device parameter optimization in a process migration scenario.

[0013] In some embodiments of the first aspect, the method further comprises: generating a first population, each individual in the first population having a corresponding set of intermediate parameter values ​​for the reduced parameter set; and wherein determining the intermediate parameter values ​​for the reduced parameter set further comprises: determining a second population from the first population, the second population not including repeated individuals having the same set of intermediate parameter values; and determining the intermediate parameter values ​​for the reduced parameter set based on the corresponding set of intermediate parameter values ​​for each individual in the second population for the reduced parameter set. In this way, deduplication of individuals can be performed, thereby improving the efficiency of performing device parameter optimization using a genetic variation algorithm.

[0014] In some embodiments of the first aspect, determining that the chip design for the second process meets the circuit performance condition includes: determining a set of loss values ​​corresponding to a set of performance indicators of the chip design, each loss value in the set of loss values ​​being determined based on a first value of a corresponding performance indicator in the set of performance indicators for the first process and a second value for the second process; and determining that the chip design for the second process meets the circuit performance condition based on determining that the set of loss values ​​meets a predetermined condition. In this way, the chip design before and after process migration can meet the circuit performance condition, thereby improving the accuracy of process migration.

[0015] In some embodiments of the first aspect, at least one constraint circuit structure includes at least one of the following: a symmetrical device circuit structure, a current mirror circuit structure, and a stacked tube circuit structure. In this way, by using these constraint circuit structures to reduce the search space of device parameters, the efficiency of device parameter optimization under the target process can be improved.

[0016] In a second aspect of the present disclosure, a device for chip design is provided. The device includes: a constraint circuit structure determination unit, configured to determine at least one constraint circuit structure among multiple devices of a chip design for a first process, wherein the sizes of a group of devices in each of the at least one constraint circuit structure have size constraints; a parameter value determination unit, configured to determine device parameter values ​​of the multiple devices under a second process based on the size constraints, the second process being different from the first process; a performance determination unit, configured to determine that the chip design for the second process meets circuit performance conditions based on the device parameter values ​​of the multiple devices under the second process; and a migration unit, configured to migrate the chip design from the first process to the second process based on determining that the chip design for the second process meets the circuit performance conditions.

[0017] In this way, by determining the constrained circuit structure in multiple devices designed for the chip of the first process and utilizing the size constraints between devices in the constrained circuit structure, the device parameter optimization process under the second process can be accelerated, thereby improving the efficiency of process migration.

[0018] In some embodiments of the second aspect, the group of devices in each constrained circuit structure includes a main device and at least one auxiliary device, and the parameter value determination unit is further configured to: determine an initial parameter set of the multiple devices under the second process; based on the size constraint, determine a reduced parameter set of the multiple devices under the second process from the initial parameter set, the reduced parameter set including the size parameters of the main device in each constrained circuit structure under the second process and excluding the size parameters of the at least one auxiliary device in each constrained circuit structure under the second process; determine an intermediate parameter value for the reduced parameter set; and determine the device parameter value for the initial parameter set based on the intermediate parameter value and the size constraint. In this way, by using the size constraint to reduce the parameter set to be determined, the search space can be reduced, thereby accelerating the efficiency of device parameter optimization.

[0019] In some embodiments of the second aspect, the apparatus further comprises a process constraint determination unit configured to determine a process constraint for the second process, the process constraint indicating a plurality of parameter values ​​that meet the manufacturing requirements of the second process. The parameter value determination unit further determines the device parameter values ​​of the plurality of devices under the second process based on the process constraint for the second process. In some embodiments of the second aspect, the parameter value determination unit is further configured to: determine an initial parameter value for the reduced parameter set, the initial parameter value comprising an initial size value of the size parameter of the main device in each constrained circuit structure; and based on the initial parameter value and the process constraint, select the intermediate parameter value that meets the manufacturing requirements of the second process from the plurality of parameter values ​​indicated by the process constraint. In this way, device parameter values ​​suitable for the target process can be determined based on the process constraint.

[0020] In some embodiments of the second aspect, the parameter value determination unit is further configured to: for a first constraint circuit structure in the at least one constraint circuit structure, based on the initial size value of the size parameter of the main device in the first constraint circuit structure, determine an initial size indicator for the first constraint circuit structure; based on the initial size value, select a value adjacent to the initial size value from the multiple parameter values ​​as a candidate value for the size parameter of the main device; based on the candidate value of the size parameter of the main device, determine a candidate size indicator for the first constraint circuit structure; and based on determining that the initial size indicator and the candidate size indicator meet the size matching condition, select the candidate value as the value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure. In this way, the candidate parameter value that meets the process constraint can be determined based on the size matching condition, thereby reducing the error caused by size matching.

[0021] In some embodiments of the second aspect, the parameter value determination unit is further configured to: determine the corresponding value of the size parameter of the at least one auxiliary device in the first constrained circuit structure based on the candidate value of the size parameter of the main device and the size constraint; and determine the candidate size indicator for the first constrained circuit structure based on the candidate value of the size parameter of the main device and the corresponding value of the size parameter of the at least one auxiliary device. In this way, by determining the candidate size indicator based on the candidate parameter values ​​of both the main device and the auxiliary device, the error caused by size matching can be reduced at the level of each constrained circuit structure.

[0022] In some embodiments of the second aspect, the parameter value determination unit is further configured to: based on determining that the initial size indicator and the candidate size indicator do not meet the size matching condition, select an updated candidate value of the size parameter of the main device from the multiple parameter values, the updated candidate value being farther from the initial size value than the candidate value; based on the updated candidate value, determine an updated candidate size indicator for the first constraint circuit structure; and based on determining that the initial size indicator and the updated candidate size indicator meet the size matching condition, select the updated candidate value as the value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure. In this way, the matched candidate values ​​can be selected in the order of nearest neighbor to next nearest neighbor, thereby improving the efficiency of size matching.

[0023] In some embodiments of the second aspect, the device also includes an iteration unit, which is configured to: determine updated device parameter values ​​using a genetic variation algorithm based on determining that the chip design for the second process does not meet the circuit performance conditions; determine updated circuit performance of the chip design for the second process based on the updated device parameter values; and migrate the chip design from the first process to the second process based on determining that the updated circuit performance meets the circuit performance conditions, wherein the chip design for the second process includes the updated device parameter values ​​for the multiple devices.

[0024] In some embodiments of the second aspect, the iteration unit is further configured to: determine a first group of parameter values ​​for the reduced parameter set based on at least one of the genetic probability, the crossover probability, and the mutation probability for the initial parameter value of the reduced parameter set; determine updated intermediate parameter values ​​for the reduced parameter set from the first group of parameter values ​​for the reduced parameter set based on the process constraint and the size constraint; and determine the updated device parameter values ​​for the initial parameter set for the multiple devices based on the updated intermediate parameter values ​​for the reduced parameter set. In this way, the genetic mutation algorithm can be used to iteratively optimize the device parameter values, thereby improving the efficiency of device parameter optimization in the process migration scenario.

[0025] In some embodiments of the second aspect, the apparatus further comprises a population generation unit, which is configured to: generate a first population, each individual in the first population having a corresponding set of intermediate parameter values ​​for the reduced parameter set; and the parameter value determination unit is further configured to: determine a second population from the first population, the second population not including repeated individuals having the same set of intermediate parameter values; and determine the intermediate parameter value for the reduced parameter set based on the corresponding set of intermediate parameter values ​​for each individual in the second population for the reduced parameter set. In this way, deduplication of individuals can be performed, thereby improving the efficiency of performing device parameter optimization using a genetic variation algorithm.

[0026] In some embodiments of the second aspect, the performance determination unit is further configured to: determine a set of loss values ​​corresponding to a set of performance indicators of the chip design, each loss value in the set of loss values ​​being determined based on a first value of a corresponding performance indicator in the set of performance indicators for the first process and a second value for the second process; and determine that the chip design for the second process meets the circuit performance condition based on determining that the set of loss values ​​meets a predetermined condition. In this way, the chip design before and after process migration can meet the circuit performance condition, thereby improving the accuracy of process migration.

[0027] In some embodiments of the second aspect, at least one constraint circuit structure includes at least one of the following: a symmetrical device circuit structure, a current mirror circuit structure, and a stacked tube circuit structure. In this way, by using these constraint circuit structures to reduce the search space of device parameters, the efficiency of device parameter optimization under the target process can be improved.

[0028] In a third aspect of the present disclosure, an electronic device is provided, comprising: at least one computing unit; and at least one memory, wherein the at least one memory is coupled to the at least one computing unit and stores instructions for execution by the at least one computing unit, and when the instructions are executed by the at least one computing unit, the device implements the method provided in the first aspect.

[0029] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program is executed by a processor to implement the method provided in the first aspect.

[0030] In a fifth aspect of the present disclosure, a computer program product is provided, comprising computer executable instructions, which implement part or all of the steps of the method of the first aspect when the instructions are executed by a processor.

[0031] It can be understood that the electronic device of the third aspect, the computer storage medium of the fourth aspect, or the computer program product of the fifth aspect provided above are all used to execute the method provided in the first aspect. Therefore, the explanation or description of the first aspect is also applicable to the third aspect, the fourth aspect, and the fifth aspect. In addition, the beneficial effects that can be achieved in the second aspect, the third aspect, the fourth aspect, and the fifth aspect can refer to the beneficial effects in the corresponding method, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0033] Figure 1 A schematic diagram illustrating an example environment in which various embodiments of the present disclosure can be implemented;

[0034] Figure 2 A flowchart showing an example process for chip design according to some embodiments of the present disclosure is shown;

[0035] Figure 3 A schematic diagram showing an example constraint circuit structure according to some embodiments of the present disclosure;

[0036] Figure 4 A schematic diagram showing an example process of determining a device parameter value according to some embodiments of the present disclosure;

[0037] Figure 5 A schematic diagram showing an example process of performing size-constrained matching according to some embodiments of the present disclosure;

[0038] Figure 6 A schematic diagram showing an example process of determining device parameter values ​​for an initial parameter set using a genetic algorithm according to some embodiments of the present disclosure;

[0039] Figure 7 A schematic diagram showing an example process of determining device parameter values ​​based on size constraint matching and genetic algorithm according to some embodiments of the present disclosure;

[0040] Figure 8 A schematic block diagram showing an apparatus for chip design according to some embodiments of the present disclosure; and

[0041] Fig. 9 A block diagram of a computing device capable of implementing various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0042] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0043] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0044] As briefly mentioned above, there is currently a need for a solution to quickly migrate chip design from one process to another, thereby making full use of the production capacity of different processes. In the traditional process migration process, device migration can be completed by relying on some scripts, and then relying on a large amount of manpower to perform multiple rounds of iterative optimization of circuit "adjustment-simulation", so the migration cycle is long, the efficiency is low, and the labor cost is high. At the same time, analog chip design is usually customized for a specific process, so it is necessary to tune the parameters of the devices in the chip design under the target process to achieve the goal of migrating the chip design from the original process to the target process. For example, in analog circuit design, engineers need to modify the size parameters of metal oxide semiconductor field effect transistors (metal oxide semiconductor field effect transistors, MOSFET, also referred to as MOS tubes) to adjust the relevant performance parameters of MOS tubes in the problem of circuit cross-process migration, thereby achieving the goal of optimizing circuit performance (for example, gain, bandwidth, phase, etc.).

[0045] Due to the large number of devices in chip design, the automatic optimization of device parameters is very challenging. At present, a large number of works have been carried out around the automatic optimization of device parameters in analog circuit design, such as using evolutionary algorithms and Bayesian optimization in traditional optimization algorithms, and reinforcement learning in popular deep learning algorithms. These methods regard the parameter optimization of analog circuits as an optimization problem, and therefore solve it based on optimization theory. For example, existing work has proposed a method of using MOS device parameter macro models to establish circuit performance models, and applied them to circuit optimization. Specifically, a double-loop circuit optimization model is proposed with the DC operating point and the channel length of MOS as optimization variables. According to the characteristics of the DC operating point and the channel length, they are used as optimization variables for the outer loop and the inner loop respectively. Both the inner and outer loops can use simpler algorithms to find the optimal parameters of MOS with fewer iterations.

[0046] However, in the application scenario of process migration, when the chip design and corresponding circuit performance indicators for the original process have been determined, the above parameter optimization method fails to utilize the effective information in the chip design for the original process, such as the size constraints of the device in a specific circuit structure, and therefore cannot efficiently migrate the chip design from the original process to the target process to achieve the replication of circuit functions and performance. Therefore, a method is needed to automatically and efficiently complete the device parameter tuning work during process migration, so that the circuit function and accuracy under the target process are as similar as possible to those under the original process, thereby shortening the project design cycle and improving the quality and efficiency of chip design.

[0047] In order to at least partially solve the above problems and other potential problems, various embodiments of the present disclosure provide a solution for chip design. According to various embodiments described herein, a method for chip design is provided. The method includes determining at least one constrained circuit structure among multiple devices of a chip design for a first process. There is a size constraint between the sizes of a group of devices in each constrained circuit structure in at least one constrained circuit structure. The method also includes: based on the size constraint, determining device parameter values ​​of multiple devices under a second process different from the first process. The method also includes: based on the device parameter values ​​of multiple devices under the second process, determining that the chip design for the second process meets the circuit performance conditions; and based on determining that the chip design for the second process meets the circuit performance conditions, migrating the chip design from the first process to the second process.

[0048] In this way, by determining the constrained circuit structure in multiple devices designed for the chip of the first process and utilizing the size constraints between the sizes of the devices in the constrained circuit structure, the device parameter optimization process under the second process can be accelerated, thereby improving the efficiency of process migration.

[0049] Various exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings. Figure 1 1 is a schematic diagram of an example environment 100 in which various embodiments of the present disclosure can be implemented. Figure 1 As shown, the environment 100 includes a size constraint extraction module 110 and a process migration module 120. In the application scenario of process migration, a chip design 111 for a first process has been determined. The chip design 111 for the first process may include multiple devices for realizing the target circuit function, and the device parameter values ​​of the multiple devices under the first process have been determined. According to an embodiment of the present disclosure, the size constraint extraction module 110 may determine at least one constrained circuit structure 113 among the multiple devices in the chip design based on the determined chip design 111 for the first process, and determine a size constraint 114 between the sizes of a group of devices in at least one constrained circuit structure 113. In this document, the term "constrained circuit structure" refers to a specific circuit structure that includes a group of devices with size constraints. In other words, in a constrained circuit structure, there is an association relationship, such as a proportional relationship, between the sizes of at least two devices. The specific details of the constrained circuit structure will be referred to. Figure 3 This is further described below.

[0050] Based on the determined at least one constrained circuit structure 113 and its size constraint 114, the process migration module 120 migrates the chip design 111 for the first process to the second process to determine the chip design 121 for the second process. When determining the chip design 121 for the second process, the process migration module 120 determines the device parameter values ​​122 of multiple devices in the chip design 111 under the second process based on the size constraint 114. The process migration module 120 also determines whether the chip design for the second process meets the circuit performance conditions based on the device parameter values ​​122 under the second process. If the process migration module 120 determines that the chip design 121 for the second process meets the circuit performance conditions, the process migration module 120 can migrate the chip design from the first process to the second process. In this way, the device size information in the chip design for the original process can be used to accelerate process migration.

[0051] In some embodiments, the size constraint extraction module 110 and the process migration module 120 may be implemented by different EDA software. Alternatively, the size constraint extraction module 110 and the process migration module 120 may be units or modules in the same EDA software for performing different functions. The scope of the present disclosure is not limited here. In addition, Figure 1 The examples shown in and the corresponding description are intended to be illustrative only and not limiting.

[0052] Figure 2A flowchart of an example process 200 for chip design according to some embodiments of the present disclosure is shown. Process 200 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, an EDA tool, such as a size constraint extraction module 110 and a process migration module 120, can be implemented by a processor of a computer according to data and / or instructions stored in a memory to perform process 200. Figure 1 An example process 200 for chip design is described.

[0053] In box 210, the processor determines at least one constrained circuit structure among multiple devices designed for a chip of the first process. There is a size constraint between the sizes of a group of devices in each of the at least one constrained circuit structure. As described above, a constrained circuit structure refers to a specific circuit structure including a group of devices with size constraints. The constrained circuit structure may also be referred to as a basic circuit unit, which can be used multiple times in a circuit. The constrained circuit structure contains relevant size constraints designed by engineers. In some embodiments, at least one size of two devices in a single constrained circuit structure is associated. For example, in a constrained circuit structure such as a symmetrical device circuit structure, the sizes of the two symmetrical devices are exactly the same.

[0054] Figure 3 A schematic diagram of an example constraint circuit structure according to some embodiments of the present disclosure is shown. In some embodiments, an example of a constraint circuit structure may include a symmetrical device circuit structure. A symmetrical device circuit structure may include two or more devices with substantially the same circuit connection relationship, completely consistent size, consistent MOS tube type, and the same working state. Figure 3 As shown, the symmetrical device circuit structure 310 may include symmetrical devices M1 and M2. In some embodiments, the symmetrical device circuit structure may be identified based on the netlist and circuit simulation information of the circuit. For example, all MOS tubes in the netlist may be grouped according to device size, type, and working state, and those with the same information may be grouped together. Secondly, multiple iterative judgments may be performed on the MOS tubes in the same group, and MOS tubes with similar connection relationships may be traversed to find out the symmetrical devices that are finally identified. The iterative termination condition may be that the number of iterations exceeds the maximum threshold, or that no new symmetrical devices are added in the current iteration round.

[0055] Alternatively or additionally, an example of the constraint circuit structure may include a mirror current source circuit structure, also known as a current mirror circuit structure. The mirror current source circuit structure may include a MOS transistor with substantially symmetrical parameters to achieve replication of the reference current. Figure 3As shown, the mirror current source circuit structure 320 may include a device M1 having a parameter (W / L) 1 and a device M2 having a parameter (W / L) 2. By utilizing different MOS tube sizes, the current can be mapped in corresponding proportions. In some embodiments, the mirror current source circuit structure can be identified based on the netlist and circuit simulation information of the circuit. For example, the current mirror form can be summarized first, that is, the special connection form and working state of different types of current mirrors can be defined, such as the gates of two MOS tubes are connected, the gate voltage is not a fixed input from the outside, etc. Secondly, the traversal can be started from the power supply or ground of the netlist, and the current mirror that conforms to the form sorted out in the early stage can be identified as the mirror current source circuit structure 320.

[0056] Alternatively or additionally, an example of a constraint circuit structure may include a stacked tube circuit structure. A stacked tube circuit structure may include two or more devices of exactly the same size, type, and series connection. A string of stacked tubes may be considered as one large tube. Figure 3 As shown, the stacked tube circuit structure 330 may include three devices connected in series. In some embodiments, the stacked tube circuit structure can be identified based on the netlist of the circuit. For example, you can start traversing from any device, search for MOS tubes of the same size and type along the drain or source through the netlist connection relationship, and judge whether the gate and substrate are connected. If it is determined to be connected, it is classified into the same stacked tube group. If you encounter MOS tubes of different sizes or types, or the gate and substrate are not connected, or the drain and source, stop searching. Finally, if it is determined that except for the MOS tubes with external drains and sources, the pin lines of the source or drain of other MOS tubes are no longer connected to other devices except the tubes in this group of stacked tubes, then this group of devices constitutes a group of stacked tubes.

[0057] It should be understood that Figure 3 The constrained circuit structure shown is only exemplary and not restrictive. Any suitable circuit structure containing size constraints between devices can be defined, identified and applied to the scheme of the present disclosure, and the scope of the present disclosure is not limited here. According to an embodiment of the present disclosure, by using the size constraints between a set of devices in the constrained circuit structure, after identifying the constrained circuit structure, the parameter variables that need to be tuned can be reduced in dimension, thereby reducing the search space. At the same time, by restoring all parameters to be tuned using the searched parameters based on the size constraints, the parameter values ​​obtained by tuning can naturally meet the size constraints.

[0058] Continue to refer Figure 2In box 220, the processor determines the device parameter values ​​of the plurality of devices under a second process different from the first process based on the size constraint. Based on the device parameter values ​​of the plurality of devices under the second process, the processor can determine the circuit performance of the chip design for the second process and determine whether the circuit performance meets the circuit performance condition. In box 230, if the processor determines that the chip design for the second process meets the circuit performance condition based on the device parameter values ​​of the plurality of devices under the second process. Then in box 240, the processor migrates the chip design from the first process to the second process based on the determination that the chip design for the second process meets the circuit performance condition. On the contrary, if the processor determines that the chip design for the second process does not yet meet the circuit performance condition, the device parameter values ​​of the plurality of devices under the second process can be further updated so that the circuit performance based on the updated device parameter values ​​meets the predetermined circuit performance condition.

[0059] In some embodiments, the circuit performance under the first process can be used as a target to determine the device parameter value of the device under the second process, so that the circuit performance under the second process is close to the circuit performance under the first process, thereby achieving the goal of process migration. Alternatively or additionally, engineers can set circuit performance conditions based on experience, and determine the device parameter value of the device under the second process based on the circuit performance conditions. Figures 4 to 7 The principles and details of determining device parameter values ​​of multiple devices under the second process based on the size constraint are described in detail.

[0060] Figure 4 FIG. 4 is a schematic diagram showing an example process 400 for determining device parameter values ​​according to some embodiments of the present disclosure. Figure 4 As shown, the process 400 of determining the device parameter value can be implemented by a parameter reduction module 410, a parameter value matching module 420, and a parameter restoration module 430. The parameter reduction module 410, the parameter value matching module 420, and the parameter restoration module 430 can be Figure 1 The sub-modules in the process migration module 120 are shown in FIG.

[0061] In some embodiments, a group of devices in each constraint circuit structure may include a main device and at least one auxiliary device. The main device may also be referred to as a reference device, and its parameter value is used as a reference for calculating the parameter value of at least one auxiliary device. In the device parameter optimization process, the parameter value of the main device can be determined in the search space. Then, the parameter value of at least one auxiliary device can be calculated based on the parameter value and size constraint of the main device. In this way, the search space for determining the parameter value can be reduced, thereby improving the efficiency of device parameter optimization. Examples of parameter values ​​may include size values ​​of various dimensions of the device. Alternatively or additionally, examples of parameter values ​​may include various suitable parameter values ​​associated with size values. In some embodiments, the device with the most complex connection relationship in each constraint circuit structure may be defined as a main device, so as to facilitate the maintenance of the size constraint between the main device and at least one auxiliary device. It should be understood that the division or definition of the main device and the auxiliary device in the constraint circuit structure can be carried out according to any suitable standard, and the scope of the present disclosure is not limited here.

[0062] like Figure 4 As shown, when determining the device parameter values ​​of multiple devices under the second process, the initial parameter set 401 of the multiple devices under the second process can be first determined. The initial parameter set 401 may include each parameter to be determined for each device in the multiple devices. In other words, the initial parameter set may include a parameter set for the main device and a parameter set for the auxiliary device. In some embodiments, the initial parameter set 401 of the multiple devices under the second process can be determined based on information of the first process and the second process. For example, when the first process is associated with a two-dimensional chip design and the second process is associated with a three-dimensional chip design, the number of parameters of the same device under the second process may be more than the number of parameters under the first process. In some embodiments, the parameter set of the device under the second process can be determined based on the parameter set of the same device under the first process. For example, in some cases, the parameter set of a specific device under the first process can be directly used as the parameter set of the device under the second process.

[0063] In some embodiments, the parameter reduction module 410 may determine a reduced parameter set 411 for multiple devices under the second process from the initial parameter set 401 based on the size constraint 402. The reduced parameter set 411 may include the size parameters of the main device in the constrained circuit structure under the second process and does not include the size parameters of at least one auxiliary device in each constrained circuit structure under the second process. In other words, the parameter reduction module 410 may reduce the dimension of the device parameter variables that need to be tuned based on the size constraints between the main device and the auxiliary device in the constrained circuit structure, thereby reducing the parameter search space to improve the efficiency of device parameter optimization.

[0064] For the determined reduced parameter set 411, the parameter value matching module 420 may determine an intermediate parameter value 422 for the reduced parameter set 411. The intermediate parameter value 422 includes a parameter value corresponding to each parameter in the reduced parameter set 411. Using the size constraint 402, the parameter restoration module 430 may restore the intermediate parameter value 422 of the reduced parameter set 411 to a device parameter value 431 of the initial parameter set 401. The device parameter value 431 of the initial parameter set 401 may include a parameter value corresponding to each parameter in the initial parameter set 401. That is, the parameter restoration module 430 may determine the parameter value of the auxiliary device corresponding to the main device in the constrained circuit structure based on the parameter value of the main device in the constrained circuit structure.

[0065] In some embodiments, the parameter value matching module 420 can also determine the intermediate parameter value 422 of the streamlined parameter set 411 based on the process constraint 412, and then determine the device parameter value 431 for the initial parameter set 401. The process constraint 412 can indicate multiple parameter values ​​that meet the manufacturing requirements of the second process, that is, the target process. For example, the process constraint 412 for the second process can include multiple process manufacturing grid points, and only when the device parameter value is at the process manufacturing grid point can the device be manufactured under the second process. In this way, device parameter optimization can be performed based on both size constraints and process constraints, so as to efficiently determine device parameter values ​​that meet size constraints and process requirements.

[0066] In some embodiments, when determining the intermediate parameter value 422 of the reduced parameter set 411, the parameter value matching module 420 may determine the initial parameter value for the reduced parameter set, and the initial parameter value may include the initial value of the parameter of the main device in the constrained circuit structure but not the initial value of the parameter of the auxiliary device. Then, the initial parameter value may be mapped to a suitable intermediate parameter value based on the size constraint and the process constraint. This process may also be referred to as the size constraint matching process, which will be referred to below. Figure 5 Describe the principles and details of the size-constrained matching process.

[0067] Figure 5 FIG. 5 is a schematic diagram showing an example process 500 for performing size constraint matching according to some embodiments of the present disclosure. The process 500 may be performed by Figure 4 The parameter value matching module 420 shown in FIG. Figure 5 As shown, in block 501, the original value of the main device and the proportional relationship may be received as input. The original value of the main device may include an initial parameter value of the main device, and the proportional relationship may be indicated by a size constraint. In some embodiments, the initial parameter value may be determined based on the corresponding parameter value of the device under the first process. Alternatively, the initial parameter value of the reduced parameter set may be randomly generated in the search space. Alternatively, in the iterative optimization process, the initial parameter value may be determined by the parameter value obtained in the previous round of iteration.

[0068] Based on the initial parameter value for the reduced parameter set, an intermediate parameter value that matches the size constraint and the process constraint can be determined. In some embodiments, based on the initial parameter value and the process constraint, a parameter value that meets the manufacturing requirements of the second process can be selected from a plurality of parameter values ​​indicated by the process constraint as the intermediate parameter value of the reduced parameter set. For example, the initial parameter value can be matched to a neighboring process manufacturing grid point as the corresponding intermediate parameter value. Specifically, the process manufacturing grid point that is the nearest or second nearest neighbor to the initial parameter value can be selected as the corresponding intermediate parameter value.

[0069] Further, when matching the initial parameter value to a suitable process manufacturing grid point, it is possible to consider minimizing the size change caused by the matching process. In some embodiments, an initial size index associated with the initial parameter value and a candidate size index associated with the matched candidate parameter value may be determined. If it is determined that the initial size index and the candidate size index meet a predetermined condition, such as a difference between the two being less than a threshold, the candidate parameter value may be used as an intermediate parameter value matched with the initial parameter value.

[0070] In some embodiments, the initial size index and the candidate size index may be associated with the statistical value of the size parameter. For example, the initial size index and the candidate size index may be determined by calculating the product of the value of the size parameter. In some embodiments, the initial size index and the candidate size index may be determined separately for each constrained circuit structure. In other words, the initial size index and the candidate size index may be calculated for each constrained circuit structure. Alternatively or additionally, the initial size index and the candidate size index may be determined for all devices whose parameter values ​​are to be determined in the chip design. When evaluating the size index, the parameter values ​​of the streamlined parameter set may be restored to the parameter values ​​of the initial parameter set (that is, all parameters to be determined including multiple devices), and the initial size index and the candidate size index may be determined based on the parameter values ​​for the initial parameter set. Alternatively or additionally, the initial size index and the candidate size index may be determined for the target device in the chip design. The target device may include a device of interest specified by an engineer.

[0071] In some embodiments, for a first constrained circuit structure among multiple devices, an initial size indicator for the first constrained circuit structure can be determined based on an initial size value of a size parameter of a main device in the first constrained circuit structure. For example, a main size indicator of the main device can be determined based on a corresponding value of the size parameter of the main device. Based on the corresponding values ​​of multiple size parameters of the main device, the size constraint can also be used to determine the corresponding value of the size parameter of the auxiliary device in the first constrained circuit structure, thereby determining the auxiliary size indicator for the auxiliary device. The initial size indicator for the first constrained circuit structure can be determined based on both the main size indicator and the auxiliary size indicator. For example, the initial size indicator can be a list including both the main size indicator and the auxiliary size indicator.

[0072] Additionally, in some embodiments, the initial size indicator may be determined based on the actual size value of the device. Figure 5 As shown, in box 502, the true value of the size can be obtained. The true value of the size refers to the size value determined based on the value of the size parameter. As described above, the size parameter can be any suitable parameter associated with the size. The size parameter may not directly represent the size of the device. Instead, (multiple) size parameters can be mapped to the size of the device. The mapping relationship can be process-specific. For example, for the target process, the mapping relationship can be a linear conversion formula of four arithmetic operations in the form of a=(3×(b-2)+80)×1e-9, where a and b represent the size value of a specific device under the same process and the size parameter value associated with it, respectively.

[0073] Based on the initial size value of the main device, a value adjacent to the initial size value can be selected from a plurality of parameter values ​​indicated by the process constraint as a candidate value for the size parameter of the main device. For example, one or more candidate values ​​can be selected in the order of nearest neighbor to next nearest neighbor. Based on the candidate values ​​of the size parameter of the main device, the candidate size index for the first constrained circuit structure can be determined. Similar to the process of determining the initial size index discussed above, the candidate main size index of the main device can be determined based on the candidate value of the main device. The candidate value of the auxiliary device can be determined based on the size constraint. For example, the candidate intermediate value of the auxiliary device can be determined based on the size constraint, and then the process manufacturing grid point adjacent to the candidate intermediate value is selected to determine the candidate value of the auxiliary device. The candidate auxiliary size index can be determined based on the candidate value of the auxiliary device. The candidate size index of the first constrained circuit structure can be determined based on both the candidate main size index and the candidate auxiliary size index.

[0074] If it is determined that the initial size indicator and the candidate size indicator meet the size matching condition, the candidate value of the main device can be selected as the value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure. In some embodiments, the size matching condition may include that the difference between the initial size indicator and the candidate size indicator is less than a predetermined threshold. Additionally or alternatively, the size matching condition may include that the difference between the initial size indicator and the candidate size indicator of more than a predetermined number of devices in the constraint circuit structure is less than a threshold. The difference between the initial size indicator and the candidate size indicator can also be referred to as a size adjustment error, which can reflect the error caused by adjusting the initial size value to a size value that meets the size constraints and process constraints.

[0075] On the contrary, if it is determined that the initial size indicator and the candidate size indicator do not meet the size matching condition, other candidate values ​​can be tried to see if they meet the size matching condition. In some embodiments, an updated candidate value can be selected from a plurality of parameter values ​​indicated by the process constraint, and the updated candidate value is farther from the initial size value of the device than the previously selected candidate value. Based on the updated candidate value, an updated candidate size indicator for the first constraint circuit structure can be determined. Based on determining that the initial size indicator and the updated candidate size indicator meet the size matching condition, the updated candidate value can be selected as the value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure.

[0076] For example, in block 503, a candidate solution set may be generated based on the initial size value. The candidate solution set may include a plurality of process manufacturing grid points adjacent to the initial size value. In some embodiments, for a plurality of size parameters of a device, one of the plurality of size parameters may be used as the last variable to be determined, and the corresponding candidate values ​​of the remaining parameters may be arranged and combined. Then, by making the candidate size index, such as the size product, as close as possible to the initial size index, a candidate value for the last parameter may be determined. In other words, the last parameter of the plurality of size parameters may be determined based on the selected candidate values ​​of the other size parameters and the size matching, rather than just based on the adjacent process manufacturing grid points of the initial size value. In this way, the generation of the candidate solution set may be accelerated.

[0077] In block 504, an optimal solution may be selected. The candidate combinations of parameter values ​​for a group of devices in each constrained circuit structure determined in block 503 may be traversed, and the one that minimizes the overall normalized error of the entire group of devices may be selected as the optimal solution. The overall normalized error of the entire group of devices may be determined based on the difference between the initial size index of each device in the group of devices and the candidate size index. In block 505, it may be determined whether the error is less than a set threshold. For example, it may be determined whether the sizing error of the majority of devices in the group of devices, such as more than 90% of the devices, is less than a set threshold.

[0078] If the above optimal solution cannot ensure that the resizing error of most devices in the group of devices is less than a threshold value, such as 10%, the search range can be expanded in box 506. For example, a new process manufacturing grid point adjacent to the initial size value can be selected, and these process manufacturing grid points can be sampled at intervals to generate a new set of candidate solutions, and then the process of boxes 504 and 505 is repeated. If the optimal solution can ensure that the resizing error of most devices in the group of devices is less than a predetermined threshold, the optimal solution can be output in box 507, that is, the combination of parameter values ​​of the group of devices in the constrained circuit structure. In some embodiments, if a better solution cannot be obtained after two iterations of the process of box 506, the matching process can be terminated and the solution with the smallest resizing error currently found can be output.

[0079] In some embodiments, the device parameter values ​​can be determined based on a genetic variation algorithm (also referred to as a genetic algorithm, geneticalgorithm, GA). The genetic algorithm was proposed by John Holland of the United States in the 1970s. It is a computational model that simulates Darwin's theory of biological evolution, natural selection, and genetics. According to an embodiment of the present disclosure, the genetic variation algorithm can be applied to the device parameter optimization process. The input of the algorithm can be the device parameters that need to be tuned for the circuit, such as the size variable x of the MOS tube. The goal of the algorithm can be to make the circuit performance index under the target process close to the corresponding circuit performance index under the original process, and the goal of the algorithm can be represented by a loss function. The device parameter values ​​under the target process can be determined by iterative optimization to minimize the loss function. The loss function can be defined as follows:

[0080]

[0081] Among them, S(x) is the circuit performance index corresponding to the size value x searched under the target process, and there are a total of n indicators to be considered. T is the circuit performance index corresponding to the original circuit under the original process. Weight represents the weight corresponding to different indicators and can be customized.

[0082] Figure 6 FIG. 6 is a schematic diagram of an example process 600 for determining device parameter values ​​for an initial parameter set using a genetic algorithm according to some embodiments of the present disclosure. Process 600 may be considered as a detailed example of process 400. Figure 6As shown, in block 601, a main device size search range may be determined. The main device size search range indicates a search space in which corresponding values ​​of the size parameters of the main device are determined. The size search range of the main device may be determined based on information of the target process (and the original process). Alternatively or additionally, the size search range of the main device may be determined based on the experience of the engineer and the design goals. In block 602, process constraints may be extracted. All process manufacturing grids supported by the device size parameters may be found according to the process design kit (PDK) of the device type and the target process.

[0083] In block 603, the search value may be initialized. That is, an initial parameter value for a reduced parameter set may be generated. The initial parameter value does not include a parameter value for the auxiliary device. The search value may be initialized by generating an initial population, and each individual in the initial population may have a corresponding set of initial parameter values ​​for the reduced parameter set. For example, an evolution generation counter m=0 may be set, a maximum evolution generation M may be set, and n initial values ​​may be randomly sampled from a search range of a set size variable of the main device as an initial parent population.

[0084] At block 604, individual size constraint matching may be performed by a size constraint matching module. Figure 5 As described, the size constraint matching module can map the initial parameter values ​​obtained by initialization to intermediate parameter values ​​that simultaneously satisfy the size constraint and the process constraint (i.e., are at the process manufacturing grid point), and ensure that the size matching error for a single constrained circuit structure satisfies predetermined conditions, thereby converting the algorithm's search value from an infeasible solution in a continuous space to a feasible solution in a discrete space with as little loss as possible.

[0085] In box 605, the current iteration individual deduplication can be performed. In the current iteration round, individual duplication may occur after being processed by the size constraint matching module, that is, there may be a situation where the corresponding initial parameter values ​​of multiple individuals are the same. This phenomenon is particularly significant in the later stage of genetic algorithm tuning because the algorithm enters the convergence stage at this time. In this case, by deduplicating iterative individuals, the search can be accelerated and computing resources can be saved. For example, individual deduplication can be performed on the initial population to determine a second population, which does not include duplicate individuals with the same set of parameter values.

[0086] In block 606, all device sizes may be converted according to device constraints. That is, the size parameter values ​​of the auxiliary devices may be determined using the size parameter values ​​of the main device based on the size constraints between a group of devices in each constrained circuit structure. Additionally, in order to meet the process constraints (at the process manufacturing grid point), when a size parameter value that does not meet the process constraints is encountered, it may be mapped to the nearest neighbor process manufacturing grid point. This conversion method is similar to the size constraint matching module processing flow.

[0087] In block 607, a loss function may be calculated and it may be determined whether the loss converges. The loss may be calculated with reference to formula (1). In some embodiments, a set of loss values ​​corresponding to a set (e.g., n) of performance indicators of the chip design may be determined. Each loss value in the set of loss values ​​may be determined based on a first value of a corresponding performance indicator in the set of performance indicators for a first process and a second value for a second process. The circuit may be simulated by a circuit simulator to obtain performance indicator data of the circuit. For example, the loss value for performance indicator k may be based on T for the first process. k and S(x) for the second process k Determine. Based on determining that a set of loss values ​​meets a predetermined condition, it can be determined that the chip design for the second process meets the circuit performance condition. For example, if the overall loss determined based on the set of loss values ​​is less than a predetermined threshold, it can be determined that the device parameter values ​​for the second process have been tuned. Then, the size tuning values ​​of all devices can be output in block 609.

[0088] On the contrary, if it is determined that the current device parameter value makes the chip design under the second process not meet the circuit performance conditions, for example, if the loss has not converged, a new solution can be generated by crossover mutation in box 609 and the steps of boxes 604, 605, 606 and 607 are iteratively performed. In some embodiments, the initial parameter values ​​of the simplified parameter set, such as the initial parameter values ​​initialized at box 603 or a set of parameter values ​​obtained by previous iterations, can be determined based on at least one of the genetic probability, the crossover probability and the mutation probability. For example, it can be determined whether the parent individual needs to perform a crossover mutation operation based on the crossover probability and the mutation probability. Additionally or alternatively, some individuals can be selected from the current population based on the genetic probability to be directly inherited or inherited to the next generation after crossover mutation. In this way, the diversity of the population can be maintained and the population can be prevented from falling into a local optimum.

[0089] Then, in box 604, using the size constraint matching module, the first set of parameter values ​​for the streamlined parameter set can be mapped to the second set of parameter values ​​based on the process constraints and the size constraints. In box 605, by performing individual deduplication on the second set of parameter values, the updated intermediate parameter values ​​for the streamlined parameter set can be determined. In box 606, the updated device parameter values ​​for the initial parameter set of multiple devices can be determined by conversion based on the updated intermediate parameter values ​​for the streamlined parameter set. In box 607, the updated circuit performance can be determined based on the updated device parameter values, and it is determined whether the updated circuit performance meets the circuit performance conditions. If it is determined that the circuit performance conditions are met, for example, the loss has converged, the updated device parameter values ​​can be output in box 608. In some embodiments, the above steps can be iteratively repeated for a predetermined number of rounds, or a set of parameter values ​​of the optimal individual with the minimum loss function value (maximum fitness) can be output after the loss function converges as the device parameter values ​​of multiple devices under the target process.

[0090] Figure 7 FIG. 7 is a schematic diagram of an example process 700 for determining device parameter values ​​based on size constraint matching and genetic algorithm according to some embodiments of the present disclosure. Process 700 can be considered as a specific example of process 400, which combines the size constraint matching process shown in process 500 and the genetic algorithm tuning process shown in process 600. Figure 7 As shown, according to an embodiment of the present disclosure, the input of process 700 may be a circuit structure and new and old process information. The circuit structure may include a selected constrained circuit structure. The new and old process information may include information of the original process and the target process. The basic unit, that is, the constrained circuit structure, may be identified first, thereby performing dimensionality reduction based on device constraints. In the genetic algorithm tuning stage, the input of the algorithm may include the size parameters of the device. The parameter dimensionality reduction may be performed based on the identified constrained circuit structure in combination with the size constraint relationship contained therein, and then the genetic algorithm may be used to search for the optimal parameters. Among them, the circuit performance under the original process may be used as a target to guide the optimization process of the device parameter value, and the size constraint matching is performed on the selected individuals in each round of the algorithm. Finally, at the end of the tuning, the device parameter value close to the circuit performance under the original process under the target process may be output, that is, the circuit migrated under the new process may be output. Using process 700, the circuit performance under the original process may be used as the tuning target, and the MOS size parameters may be automatically adjusted by the algorithm under the target process so that the circuit performance under the target process is close to the circuit performance under the original process, thereby achieving the tuning target.

[0091] References Figures 1 to 7The principles and details of the scheme for chip design according to the embodiment of the present disclosure are described. It should be understood that the above processes 200, 400, 500, 600 and 700 are only exemplary and do not constitute a limitation on the scope of the present disclosure. The scheme of the present disclosure can be applied in the design process of analog circuits. In the circuit design link, based on the circuit structure that has been determined under the original process and the performance target for the new process, the circuit device size can be quickly modified and adjusted under the new process to achieve the set indicators and corresponding functional requirements, thereby improving the migration efficiency of the circuit under multiple processes and improving the delivery quality. On the other hand, according to the embodiment of the present disclosure, it can also be applied to the forward design of analog circuits. In the forward design, according to the set circuit performance indicators, this scheme can be applied to start from the randomly generated initialization device size, and automatically tune according to the target, thereby greatly improving the iterative optimization efficiency.

[0092] Example devices and equipment

[0093] Figure 8 FIG. 8 is a block diagram of an apparatus 800 for chip design according to an embodiment of the present disclosure. Specifically, the apparatus 800 may be an EDA software apparatus. The apparatus 800 may include multiple modules for executing the following steps: Figure 2 , Figures 4 to 7 The corresponding steps in the process discussed in . Figure 8 As shown, the device 800 includes: a constrained circuit structure determination unit 810, configured to determine at least one constrained circuit structure among multiple devices of a chip design for a first process, wherein sizes of a group of devices in each of the at least one constrained circuit structure have size constraints; a parameter value determination unit 820, configured to determine device parameter values ​​of the multiple devices under a second process based on the size constraints, the second process being different from the first process; a performance determination unit 830, configured to determine whether the chip design for the second process meets circuit performance conditions based on the device parameter values ​​of the multiple devices under the second process; and a migration unit 840, configured to migrate the chip design from the first process to the second process based on determining that the chip design for the second process meets the circuit performance conditions.

[0094] In this way, by determining the constrained circuit structure in multiple devices designed for the chip of the first process and utilizing the size constraints between devices in the constrained circuit structure, the device parameter optimization process under the second process can be accelerated, thereby improving the efficiency of process migration.

[0095] In some embodiments, the group of devices in each constrained circuit structure includes a main device and at least one auxiliary device, and the parameter value determination unit 820 is further configured to: determine an initial parameter set for the multiple devices under the second process; based on the size constraint, determine a reduced parameter set for the multiple devices under the second process from the initial parameter set, the reduced parameter set including the size parameters of the main device in each constrained circuit structure under the second process and excluding the size parameters of the at least one auxiliary device in each constrained circuit structure under the second process; determine an intermediate parameter value for the reduced parameter set; and determine the device parameter value for the initial parameter set based on the intermediate parameter value and the size constraint. In this way, by using the size constraint to reduce the parameter set to be determined, the search space can be reduced, thereby accelerating the efficiency of device parameter optimization.

[0096] In some embodiments, the apparatus 800 further comprises a process constraint determination unit configured to determine a process constraint for the second process, the process constraint indicating a plurality of parameter values ​​that meet the manufacturing requirements of the second process. The parameter value determination unit 820 further determines the device parameter values ​​of the plurality of devices under the second process based on the process constraint for the second process. In some embodiments, the parameter value determination unit 820 is further configured to: determine an initial parameter value for the reduced parameter set, the initial parameter value comprising an initial size value of the size parameter of the main device in each constrained circuit structure; and based on the initial parameter value and the process constraint, select the intermediate parameter value that meets the manufacturing requirements of the second process from the plurality of parameter values ​​indicated by the process constraint. In this way, device parameter values ​​suitable for the target process can be determined based on the process constraint.

[0097] In some embodiments, the parameter value determination unit 820 is further configured to: for a first constraint circuit structure in the at least one constraint circuit structure, based on the initial size value of the size parameter of the main device in the first constraint circuit structure, determine an initial size indicator for the first constraint circuit structure; based on the initial size value, select a value adjacent to the initial size value from the multiple parameter values ​​as a candidate value for the size parameter of the main device; based on the candidate value of the size parameter of the main device, determine a candidate size indicator for the first constraint circuit structure; and based on determining that the initial size indicator and the candidate size indicator meet the size matching condition, select the candidate value as the value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure. In this way, the candidate parameter value that meets the process constraint can be determined based on the size matching condition, thereby reducing the error caused by size matching.

[0098] In some embodiments, the parameter value determination unit 820 is further configured to: determine the corresponding value of the size parameter of the at least one auxiliary device in the first constrained circuit structure based on the candidate value of the size parameter of the main device and the size constraint; and determine the candidate size indicator for the first constrained circuit structure based on the candidate value of the size parameter of the main device and the corresponding value of the size parameter of the at least one auxiliary device. In this way, by determining the candidate size indicator based on the candidate parameter values ​​of both the main device and the auxiliary device, the error caused by size matching can be reduced at the level of each constrained circuit structure.

[0099] In some embodiments, the parameter value determination unit 820 is further configured to: based on determining that the initial size indicator and the candidate size indicator do not meet the size matching condition, select an updated candidate value of the size parameter of the main device from the multiple parameter values, the updated candidate value being farther from the initial size value than the candidate value; based on the updated candidate value, determine an updated candidate size indicator for the first constraint circuit structure; and based on determining that the initial size indicator and the updated candidate size indicator meet the size matching condition, select the updated candidate value as the value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure. In this way, the matched candidate values ​​can be selected in the order of nearest neighbor to next nearest neighbor, thereby improving the efficiency of size matching.

[0100] In some embodiments, the device 800 also includes an iteration unit, which is configured to: determine updated device parameter values ​​using a genetic mutation algorithm based on determining that the chip design for the second process does not meet the circuit performance conditions; determine updated circuit performance of the chip design for the second process based on the updated device parameter values; and migrate the chip design from the first process to the second process based on determining that the updated circuit performance meets the circuit performance conditions, wherein the chip design for the second process includes the updated device parameter values ​​for the multiple devices.

[0101] In some embodiments, the iteration unit is further configured to: determine a first set of parameter values ​​for the reduced parameter set based on at least one of the genetic probability, the crossover probability, and the mutation probability for the initial parameter value of the reduced parameter set; determine updated intermediate parameter values ​​for the reduced parameter set from the first set of parameter values ​​for the reduced parameter set based on the process constraint and the size constraint; and determine the updated device parameter values ​​for the initial parameter set for the multiple devices based on the updated intermediate parameter values ​​for the reduced parameter set. In this way, the genetic mutation algorithm can be used to iteratively optimize the device parameter values, thereby improving the efficiency of device parameter optimization in the process migration scenario.

[0102] In some embodiments, the apparatus 800 further includes a population generation unit, which is configured to: generate a first population, each individual in the first population has a corresponding set of intermediate parameter values ​​for the reduced parameter set; and the parameter value determination unit 820 is further configured to: determine a second population from the first population, the second population does not include repeated individuals with the same set of intermediate parameter values; and determine the intermediate parameter value for the reduced parameter set based on the corresponding set of intermediate parameter values ​​for each individual in the second population for the reduced parameter set. In this way, deduplication of individuals can be performed, thereby improving the efficiency of performing device parameter optimization using a genetic variation algorithm.

[0103] In some embodiments, the performance determination unit 830 is further configured to: determine a set of loss values ​​corresponding to a set of performance indicators of the chip design, each loss value in the set of loss values ​​being determined based on a first value of a corresponding performance indicator in the set of performance indicators for the first process and a second value for the second process; and determine that the chip design for the second process meets the circuit performance condition based on determining that the set of loss values ​​meets a predetermined condition. In this way, the chip design before and after process migration can meet the circuit performance condition, thereby improving the accuracy of process migration.

[0104] In some embodiments, at least one constraint circuit structure includes at least one of the following: a symmetrical device circuit structure, a current mirror circuit structure, and a stacked tube circuit structure. In this way, by using these constraint circuit structures to reduce the search space of device parameters, the efficiency of device parameter optimization under the target process can be improved.

[0105] Fig. 9A schematic block diagram of an example device 900 that can be used to implement an embodiment of the present disclosure is shown. As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to computer program instructions stored in a random access memory (RAM) 903 and / or a read-only memory (ROM) 902 or computer program instructions loaded from a storage unit 908 into the RAM 903 and / or the ROM 902. In the RAM 903 and / or the ROM 902, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901 and the RAM 903 and / or the ROM 902 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0106] A number of components in the device 900 are connected to the I / O interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0107] The computing unit 901 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 901 performs the various methods and processes described above, such as processes 200, 400, 500, 600, and 700. For example, in some embodiments, processes 200, 400, 500, 600, and 700 may be implemented as a computer software program, specifically an EDA program, which is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 900 via RAM and / or ROM and / or communication unit 909. When the computer program is loaded into the RAM and / or ROM and executed by the computing unit 901, one or more steps of the processes 200, 400, 500, 600 and 700 described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the processes 200, 400, 500, 600 and 700 in any other appropriate manner (e.g., by means of firmware).

[0108] In the above embodiments, the method flow can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or terminal, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a server or terminal or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (such as a floppy disk, a hard disk and a tape, etc.), an optical medium (such as a digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as a solid-state hard disk, etc.).

[0109] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0110] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A method for chip design, characterized in that: include: Determine at least one constrained circuit structure among a plurality of devices designed for a chip of a first process, wherein sizes of a group of devices in each of the at least one constrained circuit structure have size constraints; Based on the size constraint, determining device parameter values ​​of the plurality of devices under a second process, where the second process is different from the first process; Determining, based on the device parameter values ​​of the plurality of devices under the second process, that the chip design for the second process meets a circuit performance condition; as well as Based on determining that the chip design for the second process meets the circuit performance condition, the chip design is migrated from the first process to the second process.

2. The method according to claim 1, characterized in that The group of devices in each constraint circuit structure includes a main device and at least one auxiliary device, and wherein determining the device parameter values ​​of the plurality of devices under the second process includes: Determining initial parameter sets of the plurality of devices under the second process; Based on the size constraint, determining a reduced parameter set of the plurality of devices under the second process from the initial parameter set, the reduced parameter set including the size parameter of the main device in each constrained circuit structure under the second process and excluding the size parameter of the at least one auxiliary device in each constrained circuit structure under the second process; determining an intermediate parameter value for the reduced parameter set; and The device parameter values ​​for the initial parameter set are determined based on the intermediate parameter values ​​and the size constraints.

3. The method according to claim 2, characterized in that The method further comprises: A process constraint for the second process is determined, the process constraint indicating a plurality of parameter values ​​that meet manufacturing requirements of the second process, and wherein determining the device parameter values ​​of the plurality of devices under the second process is further based on the process constraint for the second process.

4. The method according to claim 3, characterized in that Determining the intermediate parameter value for the reduced parameter set includes: Determining initial parameter values ​​for the reduced parameter set, the initial parameter values ​​comprising initial size values ​​of the size parameters of the master device in each constraint circuit structure; and Based on the initial parameter value and the process constraint, the intermediate parameter value that meets the manufacturing requirements of the second process is selected from the plurality of parameter values ​​indicated by the process constraint.

5. The method according to claim 4, characterized in that Selecting the intermediate parameter value that meets the manufacturing requirement from the plurality of parameter values ​​comprises: For a first constraint circuit structure in the at least one constraint circuit structure, Determining an initial size indicator for the first constraint circuit structure based on the initial size value of the size parameter of the main component in the first constraint circuit structure; Based on the initial size value, selecting a value adjacent to the initial size value from the plurality of parameter values ​​as a candidate value of the size parameter for the master device; determining a candidate size indicator for the first constrained circuit structure based on the candidate value of the size parameter of the main device; and Based on determining that the initial size indicator and the candidate size indicator meet a size matching condition, the candidate value is selected as a value in the intermediate parameter value corresponding to the size parameter of the main device in the first constraint circuit structure.

6. The method according to claim 5, characterized in that Determining the candidate size indicator for the first constraint circuit structure includes: determining, based on the candidate value of the size parameter of the primary device and the size constraint, a corresponding value of the size parameter of the at least one secondary device in the first constrained circuit structure; and The candidate size metric for the first constrained circuit structure is determined based on the candidate value of the size parameter of the primary component and the corresponding value of the size parameter of the at least one secondary component.

7. The method according to claim 5 or 6, characterized in that: The method further comprises: selecting, based on determining that the initial size indicator and the candidate size indicator do not meet the size matching condition, an updated candidate value of the size parameter of the master component from the plurality of parameter values, the updated candidate value being further from the initial size value than the candidate value; determining an updated candidate size metric for the first constrained circuit structure based on the updated candidate value; and Based on determining that the initial size indicator and the updated candidate size indicator meet the size matching condition, the updated candidate value is selected as a value in the intermediate parameter value corresponding to the size parameter of the master device in the first constraint circuit structure.

8. The method according to any one of claims 4 to 7, characterized in that The method further comprises: Determining updated device parameter values ​​using a genetic mutation algorithm based on determining that the chip design for the second process does not meet the circuit performance condition; Determining updated circuit performance of the chip design for the second process based on the updated device parameter values; and Based on determining that the updated circuit performance satisfies the circuit performance condition, the chip design is migrated from the first process to the second process, wherein the chip design for the second process includes the updated device parameter values ​​for the plurality of devices.

9. The method according to claim 8, characterized in that The updated device parameter values ​​determined using the genetic mutation algorithm include: For the initial parameter values ​​of the reduced parameter set, determining a first group of parameter values ​​for the reduced parameter set based on at least one of inheritance probability, crossover probability, and mutation probability; determining updated intermediate parameter values ​​for the reduced parameter set from the first set of parameter values ​​for the reduced parameter set based on the process constraint and the size constraint; and The updated device parameter values ​​of the plurality of devices for the initial parameter set are determined based on the updated intermediate parameter values ​​for the reduced parameter set.

10. The method according to any one of claims 8 to 9, characterized in that The method further comprises: generating a first population, each individual in the first population having a corresponding set of intermediate parameter values ​​for the reduced parameter set; and wherein determining the intermediate parameter values ​​for the reduced parameter set further comprises: Determining a second population from the first population, wherein the second population does not include duplicate individuals having the same set of intermediate parameter values; and The intermediate parameter value for the reduced parameter set is determined based on the corresponding set of intermediate parameter values ​​for the reduced parameter set for each individual in the second population.

11. The method according to any one of claims 1 to 10, characterized in that Determining that the chip design for the second process meets a circuit performance condition includes: determining a set of penalty values ​​corresponding to a set of performance indicators of the chip design, each penalty value in the set of penalty values ​​being determined based on a first value of a corresponding performance indicator in the set of performance indicators for the first process and a second value for the second process; and Based on determining that the set of loss values ​​meets a predetermined condition, determining that the chip design for the second process meets the circuit performance condition.

12. The method according to any one of claims 1 to 11, characterized in that The at least one constraint circuit structure includes at least one of the following: Symmetrical device circuit structure, current mirror circuit structure, and stacked tube circuit structure.

13. A device for chip design, characterized in that: include: A constraint circuit structure determination unit is configured to determine at least one constraint circuit structure among a plurality of devices designed for a chip of a first process, wherein sizes of a group of devices in each constraint circuit structure of the at least one constraint circuit structure have size constraints; a parameter value determining unit configured to determine device parameter values ​​of the plurality of devices under a second process based on the size constraint, the second process being different from the first process; a performance determination unit configured to determine, based on the device parameter values ​​of the plurality of devices under the second process, whether the chip design for the second process meets a circuit performance condition; as well as A migration unit is configured to migrate the chip design from the first process to the second process based on determining that the chip design for the second process meets the circuit performance condition.

14. The apparatus according to claim 13, wherein the group of devices in each constraint circuit structure comprises a primary device and at least one secondary device, and wherein the parameter value determination unit is further configured to: Determining initial parameter sets of the plurality of devices under the second process; Based on the size constraint, determining a reduced parameter set of the plurality of devices under the second process from the initial parameter set, the reduced parameter set including the size parameter of the main device in each constrained circuit structure under the second process and excluding the size parameter of the at least one auxiliary device in each constrained circuit structure under the second process; Determining an intermediate parameter value for the reduced parameter set; as well as The device parameter values ​​for the initial parameter set are determined based on the intermediate parameter values ​​and the size constraints.

15. The device according to claim 14, characterized in that The apparatus further comprises a process constraint determining unit, wherein the process constraint determining unit is configured to: determining a process constraint for the second process, the process constraint indicating a plurality of parameter values ​​that meet manufacturing requirements of the second process, and The parameter value determination unit further determines the device parameter values ​​of the plurality of devices under the second process based on the process constraints for the second process.

16. The device according to claim 15, characterized in that The parameter value determination unit is further configured to: Determining initial parameter values ​​for the reduced parameter set, the initial parameter values ​​comprising initial size values ​​of the size parameters of the master device in each constraint circuit structure; as well as Based on the initial parameter value and the process constraint, the intermediate parameter value that meets the manufacturing requirements of the second process is selected from the plurality of parameter values ​​indicated by the process constraint.

17. The device according to any one of claims 13 to 16, characterized in that The at least one constraint circuit structure includes at least one of the following: Symmetrical device circuit structure, current mirror circuit structure, and stacked tube circuit structure.

18. An electronic device, comprising: at least one computing unit; At least one memory, the at least one memory being coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions, when executed by the at least one computing unit, causing the electronic device to execute the method according to any one of claims 1 to 12.

19. A computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 12.

20. A computer program product comprising computer executable instructions, wherein the computer executable instructions, when executed by a processor, implement the method according to any one of claims 1 to 12.

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