UVM verification platform of floating point arithmetic unit based on IEEE754 standard

Abstract

The invention aims to provide a UVM verification platform of a floating point arithmetic unit based on an IEEE754 standard. The platform comprises a master equipment side verification agent module and a slave equipment side verification agent module, the master equipment side verification agent module is connected with the slave equipment side verification agent module through the scoreboard assembly and the reference model assembly; the main equipment side verification agent module is used for packaging, configuring and managing a sequence generator, an excitation driver and a monitor; and the slave equipment side verification agent module is used for packaging, configuring and managing a sequence generator, an excitation driver and a monitor. According to the method, the verification capability and verification efficiency of the floating point arithmetic unit based on the IEEE754 standard can be improved, and the verification process of the floating point arithmetic unit is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a UVM verification platform of a floating point operation unit based on the IEEE754 standard. Background Art

[0002] As the complexity of integrated circuits continues to increase, the number of modules and functional logic involved in the design has increased significantly, resulting in a significant increase in the verification workload. More complex designs require more comprehensive verification strategies and longer verification cycles to ensure the correctness of functions and the stability of the system. However, the extension of verification time directly affects the product development progress, resulting in delayed chip launch time, thus losing the initiative in the fiercely competitive market.

[0003] In digital integrated circuit design, the traditional verification method is to use the hardware description language Verilog HDL to build a verification platform and perform functional simulation to find potential errors in the code. This method not only has low verification coverage, but also lacks hierarchical design in structure, resulting in the developed verification platform usually only applicable to specific projects, and cannot be transplanted between different projects, and has poor reusability.

[0004] The Universal Verification Methodology (UVM) based on SystemVerilog (SV) has significantly improved verification capabilities and efficiency compared to traditional verification methods. UVM adopts a modular and hierarchical verification architecture to make the verification platform more structured and scalable, while improving the reusability and maintainability of the project. By introducing standardized verification components and automated coverage collection and constrained randomization testing, UVM can more comprehensively cover the verification scenarios of complex designs, significantly shorten the development cycle and improve the quality of verification, making it the mainstream verification methodology in modern digital integrated circuit design.

[0005] The floating point unit (FPU) is a hardware module in a computer system that is specifically used to process floating point operations. Its main function is to perform high-precision addition, subtraction, multiplication, division, square root and other complex calculations, supporting scenarios that require efficient numerical processing such as scientific computing, engineering design and data analysis. The FPU is usually independent of the processor core and completes floating point operations through hardware acceleration to reduce the CPU burden and improve overall performance. The FPU involves complex floating point operations and strict standard compliance. If it only relies on the traditional Verilog HDL verification method, since this method mainly relies on directed testing and lacks extensive randomized testing capabilities, it is impossible to fully verify the FPU function and its performance under various boundary conditions. This not only leads to low verification efficiency, but also makes it difficult to reuse the verification environment. Summary of the invention

[0006] The purpose of the present invention is to provide a UVM verification platform for a floating-point operation unit based on the IEEE754 standard, which can improve the verification capability and verification efficiency of the floating-point operation unit based on the IEEE754 standard and simplify the verification process of such floating-point operation units.

[0007] A UVM verification platform for a floating point unit based on the IEEE754 standard, comprising: a master device side verification agent module and a slave device side verification agent module;

[0008] The master device side verification proxy module is connected to the slave device side verification proxy module through the scoreboard component and the reference model component;

[0009] The master device side verification agent module is used to encapsulate, configure and manage the sequence generator, the excitation driver and the monitor;

[0010] The slave device side verification agent module is used to encapsulate, configure and manage the sequence generator, stimulus driver and monitor.

[0011] Preferably, the master device side verification agent module comprises: a sequence generator for the master device side, an excitation driver for the master device side and a monitor for the master device side;

[0012] The sequence generator for the master device side designed based on the APB bus protocol is used to manage and schedule different sequences for the master device side designed based on the APB bus protocol, and send transaction data packets for the master device side created in different sequences for the master device side designed based on the APB bus protocol to the excitation driver for the master device side;

[0013] The excitation driver for the master device side designed based on the APB bus protocol is used to receive the transaction data packet for the master device side from the sequence generator for the master device side, convert it into a signal understandable by the DUT, and drive it to the input port of the DUT through the universal interface designed based on the APB bus protocol in accordance with the timing of the APB bus protocol;

[0014] The monitor for the master device side designed based on the APB bus protocol uses a universal interface designed based on the APB bus protocol to access and capture the input signal of the DUT, and converts the input signal into a high-level transaction data packet for the master device side, and then sends it to the coverage component and the reference model component respectively.

[0015] Preferably, the slave device side verification agent module comprises: a sequence generator for the slave device side, an excitation driver for the slave device side and a monitor for the slave device side;

[0016] The monitor for the slave device side designed based on the APB bus protocol uses a universal interface designed based on the APB bus protocol to access and capture the output signals of the DUT, and converts these signals into high-level transaction data packets for the master device side, and then sends them to the scoreboard component for comparison;

[0017] The sequence generator for the slave device side designed based on the APB bus protocol is controlled by an enable signal is_active at the level of the slave device side verification agent module;

[0018] The excitation driver for the slave device side designed based on the APB bus protocol is controlled by the enable signal is_active at the level of the verification agent module on the slave device side.

[0019] Preferably, it also includes: a container of a floating point unit verification environment;

[0020] The container of the floating point unit verification environment is used to encapsulate, configure and manage the scoreboard component, the coverage component, the reference model component, the master device side verification agent module and the slave device side verification agent module.

[0021] Preferably, it also includes: a test case of a floating point arithmetic unit;

[0022] The test case of the floating-point operation unit includes a container of the floating-point operation unit verification environment. Each instance of the test case represents a specific test scenario and is responsible for managing the entire test scenario and verification environment.

[0023] Preferably, the container of the floating point unit verification environment includes: a coverage component, a reference model component and a scoreboard component;

[0024] The coverage component is used to complete the collection of functional coverage by defining coverage points, coverage groups and opening sampling function sample(), and evaluate whether the verification environment has covered all expected functions and scenarios;

[0025] The reference model component is used to receive information from a monitor designed for the master device side based on the APB bus protocol and generate an expected output to be sent to the scoreboard component for comparison with the output of the DUT;

[0026] The scoreboard component is used to receive and compare the information from the reference model component and the information monitored by the monitor on the device side designed based on the APB bus protocol, and judge whether the DUT performs the operation correctly according to the design specifications based on the comparison result.

[0027] Preferably, it also includes: a transaction data packet for the master device side designed based on the APB bus protocol, a sequence for the master device side designed based on the APB bus protocol, and a universal interface designed based on the APB bus protocol;

[0028] The transaction data packet for the master device side designed based on the APB bus protocol is used to encapsulate the APB bus signals required for use in the verification process into a unified object, which is used to represent an operation on the DUT;

[0029] The sequence designed based on the APB bus protocol for the master device side, in which one or more transaction data packets designed based on the APB bus protocol for the master device side are defined and generated according to actual needs;

[0030] The universal interface designed based on the APB bus protocol is used to connect the UVM verification component and the DUT, abstracting and simplifying the connection of the DUT signal.

[0031] A UVM verification platform control method for a floating-point operation unit based on the IEEE754 standard, comprising:

[0032] Use global statements in the top-level module to start the UVM verification platform;

[0033] Generate a specific test case instance according to the value of the UVM command line parameter UVM_TESTNAME;

[0034] Follow the UVM rules to complete the construction of the entire verification platform and start simulation.

[0035] Preferably, the following UVM rules to complete the construction of the entire verification platform and start simulation includes:

[0036] Generate a large number of random or directed transaction data packets based on the sequence designed for the master device side based on the APB bus protocol;

[0037] The large number of random or directional transaction data packets are sent by a sequence generator for the master device side designed based on the APB bus protocol to an excitation driver for the master device side designed based on the APB bus protocol;

[0038] After receiving a large number of random or directional transaction data packets, the excitation driver designed for the master device side based on the APB bus protocol drives the data packets to the DUT through the universal interface designed based on the APB bus protocol according to the timing of the APB bus protocol.

[0039] The monitor designed for the master device side based on the APB bus protocol monitors and collects the input signals of the DUT and sends them to the coverage component and the reference model component;

[0040] The coverage component is responsible for collecting functional coverage, and the reference model component calculates the input signal of the DUT to obtain the expected output;

[0041] The output is sent to the scoreboard component for comparison with the DUT output collected from the monitor on the device side designed based on the APB bus protocol;

[0042] If the scoreboard component is correctly compared, the test case verification is completed;

[0043] If the comparison is incorrect, use waveform and print log to debug and then re-simulate until the simulation passes.

[0044] Preferably, the process also includes executing regression testing, specifically:

[0045] Prepare written test cases and start regression testing;

[0046] When the regression test is completed, query the regression test log. If all test cases pass the simulation, check the coverage results.

[0047] If there are test cases that fail simulation, perform single test case simulation, and check the coverage results after the simulation passes;

[0048] If the coverage result does not reach the target value, analyze the reasons for the uncovered part, and add random use cases or directed use cases with modified constraints to cover the uncovered part.

[0049] The beneficial effects of the present invention are: 1. The present invention defines a verification platform framework for a floating-point operation unit based on the IEEE754 standard, thereby simplifying the verification process of such modules; 2. The present invention develops a verification platform dedicated to verifying a floating-point operation unit with an APB bus interface, which is more in line with actual scenario requirements; 3. The present invention adopts UVM to verify a floating-point operation unit based on the IEEE754 standard, and the verification platform is highly configurable and reusable; 4. The present invention uses a random test + directed test method to replace traditional directed tests, thereby improving the comprehensiveness of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0052] Figure 1 A schematic diagram of the UVM verification platform structure of a floating-point arithmetic unit based on the IEEE754 standard of the present invention;

[0053] Figure 2 A UVM verification platform control method flow chart of a floating-point operation unit based on the IEEE754 standard of the present invention;

[0054] Figure 3 Flow chart of performing regression testing for the UVM verification platform of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0057] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0058] The floating point unit (FPU) is a hardware module in a computer system that is specifically used to process floating point operations. Its main function is to perform high-precision addition, subtraction, multiplication, division, square root and other complex calculations, supporting scenarios that require efficient numerical processing such as scientific computing, engineering design and data analysis. The FPU is usually independent of the processor core and completes floating point operations through hardware acceleration to reduce the CPU burden and improve overall performance. The FPU involves complex floating point operations and strict standard compliance. If it only relies on the traditional Verilog HDL verification method, since this method mainly relies on directed testing and lacks extensive randomized testing capabilities, it is impossible to fully verify the FPU function and its performance under various boundary conditions. This not only leads to low verification efficiency, but also makes it difficult to reuse the verification environment.

[0059] The present invention defines a verification platform framework of a floating-point operation unit based on the IEEE754 standard, and simplifies the verification process of such modules; the present invention develops a verification platform dedicated to verifying a floating-point operation unit with an APB bus interface, which is more in line with actual scene requirements; the present invention adopts UVM to verify the floating-point operation unit based on the IEEE754 standard, and the verification platform has high configurability and strong reusability; the present invention uses a random test + directional test method to replace traditional directional test, and improves the comprehensiveness of the test.

[0060] Example 1

[0061] A UVM verification platform for floating-point units based on the IEEE754 standard, reference Figure 1 , including: a master device side verification proxy module and a slave device side verification proxy module;

[0062] The master device side verification agent module is connected to the slave device side verification agent module through the scoreboard component and the reference model component;

[0063] The master device side verification agent module is used to encapsulate, configure and manage the sequence generator, stimulus driver and monitor;

[0064] From the device side, the verification agent module is used to encapsulate, configure and manage sequence generators, stimulus drivers and monitors.

[0065] Since the FPU is usually integrated into the System on Chip (SoC) as an independent module, it is necessary to add a bus interface to the outside of it so that it can communicate with other modules through a unified bus protocol and improve the versatility of the module. Although the FPU is a computationally intensive module, its interaction with the processor usually does not require high bandwidth, so the use of the APB (Advanced Peripheral Bus) bus interface can simplify control and configuration while reducing design complexity. Therefore, the development of this platform is based on the actual application needs of the floating-point unit and is dedicated to verifying the floating-point unit with an APB bus interface.

[0066] Preferably, the master device side verification agent module comprises: a sequence generator for the master device side, an excitation driver for the master device side and a monitor for the master device side;

[0067] A sequence generator for the master device side designed based on the APB bus protocol is used to manage and schedule different sequences for the master device side designed based on the APB bus protocol, and send transaction data packets for the master device side created in different sequences for the master device side designed based on the APB bus protocol to an excitation driver for the master device side;

[0068] The excitation driver for the master device side designed based on the APB bus protocol is used to receive the transaction data packet for the master device side from the sequence generator for the master device side, convert it into a signal understandable by the DUT, and drive it to the input port of the DUT through the universal interface designed based on the APB bus protocol in accordance with the timing of the APB bus protocol;

[0069] The monitor for the master device side designed based on the APB bus protocol uses a universal interface designed based on the APB bus protocol to access and capture the input signals of the DUT, and converts the input signals into high-level transaction data packets for the master device side, and then sends them to the coverage component and the reference model component respectively.

[0070] exist Figure 1 In the apb_mst_sqr: A sequence generator designed for the master device side based on the APB bus protocol. Its main function is to manage and schedule different apb_mst_seqs and send the apb_tran created in different apb_mst_seqs to apb_mst_drv.

[0071] apb_mst_drv: An excitation driver for the master device side designed based on the APB bus protocol. Its main function is to receive apb_tran from apb_mst_sqr, convert it into a signal that the DUT can understand, and drive it to the input port of the DUT through apb_vif following the timing of the APB bus protocol.

[0072] apb_mst_mon: A monitor designed for the master device side based on the APB bus protocol. It uses apb_vif to access and capture the input signals of the DUT, and converts these signals into high-level apb_tran, and then sends them to the coverage component and reference_model component respectively.

[0073] Preferably, the slave device side verification agent module comprises: a sequence generator for the slave device side, an excitation driver for the slave device side, and a monitor for the slave device side;

[0074] The monitor designed for the slave device side based on the APB bus protocol uses a universal interface designed based on the APB bus protocol to access and capture the output signals of the DUT, and converts these signals into high-level transaction packets for the master device side, and then sends them to the scoreboard component for comparison;

[0075] The sequence generator designed for the slave side based on the APB bus protocol is controlled by the enable signal is_active at the level of the slave side authentication agent module;

[0076] The excitation driver for the slave device side designed based on the APB bus protocol is controlled by the enable signal is_active at the level of the slave device side verification agent module.

[0077] exist Figure 1 apb_slv_mon: A monitor designed for the slave device based on the APB bus protocol. It uses apb_vif to access and capture the output signals of the DUT, and converts these signals into high-level apb_tran, and then sends them to the scoreboard for comparison.

[0078] apb_slv_sqr: A sequence generator for the slave device side designed based on the APB bus protocol. This component is not needed in this verification, so it is disabled by setting the enable signal is_active at the apb_slv_agt level to 0. In order to demonstrate the high configurability and reusability of the UVM verification platform, Figure 1 The component is not deleted, but placed in a dotted box, indicating that the component is not enabled in the current verification platform.

[0079] apb_slv_drv: An excitation driver for the slave device side designed based on the APB bus protocol. This component is not needed in this verification, so it is disabled by setting the enable signal is_active at the apb_slv_agt level to 0. In order to demonstrate the high configurability and reusability of the UVM verification platform, Figure 1 The component is not deleted, but placed in a dotted box, indicating that the component is not enabled in the current verification platform.

[0080] Preferably, it also includes: a container of a floating point unit verification environment;

[0081] The container of the floating-point unit verification environment is used to encapsulate, configure, and manage the scoreboard component, coverage component, reference model component, master-side verification agent module, and slave-side verification agent module.

[0082] fpu_env: The container of the floating-point unit verification environment, which is responsible for encapsulating, configuring and managing the five verification components: scoreboard, coverage, reference_model, apb_mst_agt, and apb_slv_agt.

[0083] Preferably, it also includes: a test case of a floating point arithmetic unit;

[0084] The test cases of the floating-point unit include the container of the floating-point unit verification environment. Each test case instance represents a specific test scenario and is responsible for managing the entire test scenario and verification environment.

[0085] test_case: Test case for floating point unit, which contains fpu_env. Each test case instance usually represents a specific test scenario. It is the top-level component of UVM verification and is responsible for managing the entire test scenario and verification environment.

[0086] Preferably, the container of the floating point unit verification environment includes: a coverage component, a reference model component and a scoreboard component;

[0087] The coverage component is used to collect functional coverage by defining coverage points, coverage groups, and enabling the sampling function sample(), and to evaluate whether the verification environment has covered all expected functions and scenarios;

[0088] A reference model component is used to receive information from a monitor designed for the master device side based on the APB bus protocol and generate an expected output to be sent to the scoreboard component for comparison with the output of the DUT;

[0089] The scoreboard component is used to receive and compare the information from the reference model component and the information monitored by the monitor on the device side designed based on the APB bus protocol, and judge whether the DUT performs the operation correctly according to the design specifications based on the comparison results.

[0090] exist Figure 1 In the coverage component, coverage is used to collect functional coverage by defining coverage points, coverage groups, and enabling sampling functions sample(), so as to evaluate whether the verification environment has covered all expected functions and scenarios.

[0091] reference_model: The reference model component receives information from apb_mst_mon and generates the expected output to be sent to the scoreboard for comparison with the output of the DUT.

[0092] scoreboard: The scoreboard component receives and compares the information monitored by reference_model and apb_slv_mon, and determines whether the DUT performs the operation correctly according to the design specifications based on the comparison results.

[0093] Preferably, it also includes: a transaction data packet for the master device side designed based on the APB bus protocol, a sequence for the master device side designed based on the APB bus protocol, and a universal interface designed based on the APB bus protocol;

[0094] The transaction data packet designed for the master device side based on the APB bus protocol is used to encapsulate the APB bus signals required in the verification process into a unified object to represent an operation on the DUT;

[0095] A sequence for the master device side designed based on the APB bus protocol, in which one or more transaction data packets for the master device side designed based on the APB bus protocol are defined and generated according to actual needs;

[0096] A universal interface designed based on the APB bus protocol is used to connect UVM verification components and DUT, abstracting and simplifying the connection of DUT signals.

[0097] exist Figure 1 In the , the APB bus signals used are encapsulated into a unified object to represent an operation on the DUT (Design Under Test). These APB bus signals include FPU module enable signal, control signal for selecting FPU calculation mode, floating point operation operands, floating point operation results, etc.

[0098] apb_mst_seq: A sequence designed for the master device side based on the APB bus protocol. One or more apb_tran are defined and generated in the sequence according to actual needs. Figure 1 Placing apb_mst_seq in a dotted box indicates that it is not a component in the UVM verification platform.

[0099] apb_vif: A universal interface designed based on the APB bus protocol. It plays the role of connecting UVM verification components and DUT in the entire verification environment. Its main function is to abstract and simplify the connection of DUT signals.

[0100] Example 2

[0101] A UVM verification platform control method for floating-point units based on the IEEE754 standard, reference Figure 2 ,include:

[0102] S100, use global statements in the top-level module to start the UVM verification platform;

[0103] S200, generating a specific test case instance according to the value of UVM command line parameter UVM_TESTNAME;

[0104] S300, complete the construction of the entire verification platform in accordance with UVM rules and start simulation.

[0105] Preferably, following the rules of UVM to complete the construction of the entire verification platform and start simulation includes:

[0106] Generate a large number of random or directed transaction data packets based on the sequence designed for the master device side based on the APB bus protocol;

[0107] A large number of random or directed transaction data packets are sent from a sequence generator designed for the master device side based on the APB bus protocol to an excitation driver designed for the master device side based on the APB bus protocol;

[0108] After receiving a large number of random or directional transaction data packets, the excitation driver designed for the master device side based on the APB bus protocol drives the data packets to the DUT through the universal interface designed based on the APB bus protocol according to the timing of the APB bus protocol.

[0109] The monitor designed for the master device side based on the APB bus protocol monitors and collects the input signals of the DUT and sends them to the coverage component and the reference model component;

[0110] The coverage component is responsible for collecting functional coverage, and the reference model component calculates the input signal of the DUT to obtain the expected output;

[0111] The output is sent to the scoreboard component for comparison with the DUT output collected from the monitor on the device side designed based on the APB bus protocol;

[0112] If the scoreboard component is correctly compared, the test case verification is completed;

[0113] If the comparison is incorrect, use waveform and print log to debug and then re-simulate until the simulation passes.

[0114] First, use the global run_test statement in the top-level module test_top to start the entire UVM verification platform, generate specific test case instances according to the value of the UVM command line parameter UVM_TESTNAME, and then follow the UVM rules to complete the construction of the entire verification platform and start simulation. In the specific simulation process, apb_mst_seq generates a large number of random or directional transaction data packets apb_tran, which will be sent to apb_mst_drv by apb_mst_sqr. After apb_mst_drv receives apb_tran, it drives it to DUT through apb_vif according to the timing of the APB bus protocol. At the same time, apb_mst_mon monitors and collects the input signal of DUT and sends it to coverage and reference_model. The former is responsible for collecting functional coverage, and the latter calculates the input signal of DUT and obtains the expected output. The output will be sent to scoreboard for comparison with the DUT output collected by apb_slv_mon. If the scoreboard comparison is correct, the test case verification is completed; if the comparison is incorrect, it is necessary to use waveforms and print logs to debug to find out whether it is a design problem or a verification problem, and then re-simulate after making changes until the simulation passes.

[0115] Preferably, reference Figure 3 , and also includes executing regression tests, specifically:

[0116] Prepare written test cases and start regression testing;

[0117] When the regression test is completed, query the regression test log. If all test cases pass the simulation, check the coverage results.

[0118] If there are test cases that fail simulation, perform single test case simulation, and check the coverage results after the simulation passes;

[0119] If the coverage result does not reach the target value, analyze the reasons for the uncovered part, and add random use cases or directed use cases with modified constraints to cover the uncovered part.

[0120] Prepare all the written test cases, fill in the regression test table, including the case name, case regression times, case compilation parameters, and case running parameters, and then start the regression test. When the regression test is completed, query the regression test log. If all test cases pass the simulation, check the coverage results; if there are test cases that fail the simulation, execute Figure 2 The single test case simulation steps are as follows, and the coverage results are checked after the simulation passes. If the coverage result does not reach the target value, it is necessary to analyze the reasons for the uncovered parts and add random test cases or directional test cases with modified constraints to cover the uncovered parts.

[0121] The present invention defines a verification platform framework of a floating-point operation unit based on the IEEE754 standard, and simplifies the verification process of such modules; the present invention develops a verification platform dedicated to verifying a floating-point operation unit with an APB bus interface, which is more in line with actual scene requirements; the present invention adopts UVM to verify the floating-point operation unit based on the IEEE754 standard, and the verification platform has high configurability and strong reusability; the present invention uses a random test + directional test method to replace traditional directional test, and improves the comprehensiveness of the test.

[0122] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A UVM verification platform for a floating-point unit based on the IEEE754 standard, characterized in that: include: A master device side authentication proxy module and a slave device side authentication proxy module; The master device side verification proxy module is connected to the slave device side verification proxy module through the scoreboard component and the reference model component; The master device side verification agent module is used to encapsulate, configure and manage the sequence generator, the excitation driver and the monitor; The slave device side verification agent module is used to encapsulate, configure and manage the sequence generator, stimulus driver and monitor.

2. A UVM verification platform for a floating-point arithmetic unit based on IEEE754 standards according to claim 1, characterized in that, The master device side verification agent module includes: a sequence generator for the master device side, an excitation driver for the master device side, and a monitor for the master device side; The sequence generator for the master device side designed based on the APB bus protocol is used to manage and schedule different sequences for the master device side designed based on the APB bus protocol, and send transaction data packets for the master device side created in different sequences for the master device side designed based on the APB bus protocol to the excitation driver for the master device side; The excitation driver for the master device side designed based on the APB bus protocol is used to receive the transaction data packet for the master device side from the sequence generator for the master device side, convert it into a signal understandable by the DUT, and drive it to the input port of the DUT through the universal interface designed based on the APB bus protocol in accordance with the timing of the APB bus protocol; The monitor for the master device side designed based on the APB bus protocol uses a universal interface designed based on the APB bus protocol to access and capture the input signal of the DUT, and converts the input signal into a high-level transaction data packet for the master device side, and then sends it to the coverage component and the reference model component respectively.

3. A UVM verification platform for a floating-point arithmetic unit based on IEEE754 standards according to claim 1, characterized in that, The slave device side verification agent module includes: a sequence generator for the slave device side, an excitation driver for the slave device side, and a monitor for the slave device side; The monitor for the slave device side designed based on the APB bus protocol uses a universal interface designed based on the APB bus protocol to access and capture the output signals of the DUT, and converts these signals into high-level transaction data packets for the master device side, and then sends them to the scoreboard component for comparison; The sequence generator for the slave device side designed based on the APB bus protocol is controlled by an enable signal is_active at the level of the slave device side verification agent module; The excitation driver for the slave device side designed based on the APB bus protocol is controlled by the enable signal is_active at the level of the verification agent module on the slave device side.

4. A UVM verification platform for a floating-point arithmetic unit based on IEEE754 standards according to claim 1, characterized in that, Also includes: Container for the floating point unit verification environment; The container of the floating point unit verification environment is used to encapsulate, configure and manage the scoreboard component, the coverage component, the reference model component, the master device side verification agent module and the slave device side verification agent module.

5. A UVM verification platform for a floating-point arithmetic unit based on IEEE754 standards according to claim 1, characterized in that, Also includes: Test cases for floating point unit; The test case of the floating-point operation unit includes a container of the floating-point operation unit verification environment. Each instance of the test case represents a specific test scenario and is responsible for managing the entire test scenario and verification environment.

6. A UVM verification platform for a floating-point arithmetic unit based on IEEE754 standards according to claim 4, characterized in that, The container of the floating point unit verification environment includes: a coverage component, a reference model component and a scoreboard component; The coverage component is used to complete the collection of functional coverage by defining coverage points, coverage groups and opening sampling function sample(), and evaluate whether the verification environment has covered all expected functions and scenarios; The reference model component is used to receive information from a monitor designed for the master device side based on the APB bus protocol and generate an expected output to be sent to the scoreboard component for comparison with the output of the DUT; The scoreboard component is used to receive and compare the information from the reference model component and the information monitored by the monitor on the device side designed based on the APB bus protocol, and judge whether the DUT performs the operation correctly according to the design specifications based on the comparison result.

7. A UVM verification platform for a floating-point arithmetic unit based on IEEE754 standards according to claim 1, characterized in that, Also includes: Transaction data packets for the master device side designed based on the APB bus protocol, sequences for the master device side designed based on the APB bus protocol, and general interfaces designed based on the APB bus protocol; The transaction data packet for the master device side designed based on the APB bus protocol is used to encapsulate the APB bus signals required for use in the verification process into a unified object, which is used to represent an operation on the DUT; The sequence designed based on the APB bus protocol for the master device side, in which one or more transaction data packets designed based on the APB bus protocol for the master device side are defined and generated according to actual needs; The universal interface designed based on the APB bus protocol is used to connect the UVM verification component and the DUT, abstracting and simplifying the connection of the DUT signal.

8. A UVM verification platform control method for a floating-point unit based on the IEEE754 standard, characterized in that: include: Use global statements in the top-level module to start the UVM verification platform; Generate a specific test case instance according to the value of the UVM command line parameter UVM_TESTNAME; Follow the UVM rules to complete the construction of the entire verification platform and start simulation.

9. A UVM verification platform control method for a floating-point unit based on IEEE754 standard according to claim 8, characterized in that, The following UVM rules are followed to complete the construction of the entire verification platform and start simulation, including: Generate a large number of random or directed transaction data packets based on the sequence designed for the master device side based on the APB bus protocol; The large number of random or directional transaction data packets are sent by a sequence generator for the master device side designed based on the APB bus protocol to an excitation driver for the master device side designed based on the APB bus protocol; After receiving a large number of random or directional transaction data packets, the excitation driver designed for the master device side based on the APB bus protocol drives the data packets to the DUT through the universal interface designed based on the APB bus protocol according to the timing of the APB bus protocol. The monitor designed for the master device side based on the APB bus protocol monitors and collects the input signals of the DUT and sends them to the coverage component and the reference model component; The coverage component is responsible for collecting functional coverage, and the reference model component calculates the input signal of the DUT to obtain the expected output; The output is sent to the scoreboard component for comparison with the DUT output collected from the monitor on the device side designed based on the APB bus protocol; If the scoreboard component is correctly compared, the test case verification is completed; If the comparison is incorrect, use waveform and print log to debug and then re-simulate until the simulation passes.

10. A UVM verification platform control method for a floating point unit based on the IEEE754 standard according to claim 9, characterized in that, It also includes performing regression testing, specifically: Prepare written test cases and start regression testing; When the regression test is completed, query the regression test log. If all test cases pass the simulation, check the coverage results. If there are test cases that fail simulation, perform single test case simulation, and check the coverage results after the simulation passes; If the coverage result does not reach the target value, analyze the reasons for the uncovered part, and add random use cases or directed use cases with modified constraints to cover the uncovered part.

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