Information flow model generation method for FPGA circuit design

Abstract

The invention relates to an information flow model generation method for FPGA circuit design, and belongs to the field of integrated circuit hardware safety. The method comprises the following steps: inputting a to-be-analyzed FPGA circuit design code; the codes are synthesized into an FPGA netlist; analyzing the generated FPGA netlist, identifying a signal and designing a unit; analyzing the signal list, and adding a corresponding information flow label; analyzing the design units, dynamically generating a corresponding information flow model for each design unit, and obtaining a design-related design unit information flow model library; and adding a corresponding information flow model to each design unit, and connecting the information flow models according to the connection relationship between the signals in the FPGA design netlist and the design units to obtain the information flow model of the whole FPGA circuit design. According to the method, a corresponding information flow model can be generated for FPGA circuit design, a mathematical basis is provided for safety analysis of the FPGA circuit design, and the defect that safety modeling and verification are difficult to achieve due to the fact that a traditional functional FPGA circuit design model can only be used for describing and verifying function correctness is overcome.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit hardware security, and in particular relates to a method for generating an information flow model for FPGA circuit design. Background Art

[0002] FPGA devices are widely used in high-performance computing and aerospace due to their advantages of high performance, low power consumption and reconfigurability. With the continuous increase in the scale and complexity of FPGA circuit design, some security risks may be caused in the design due to design errors, bypass channels, malicious logic and backdoors from untrusted third-party IP designs. The functional circuit design model commonly used in FPGA circuit design can usually only achieve the modeling and description of the correctness of the design function, and cannot achieve the modeling and verification of security-related properties. Due to the lack of security models, it is difficult to effectively analyze and detect security issues in FPGA circuit design. Once the security risks in FPGA design are discovered and exploited by attackers, it will cause serious consequences such as information leakage, denial of service, and even device manipulation, posing a great threat to the hardware security of integrated circuits.

[0003] In response to the security risks and lack of security models faced by integrated circuit design, researchers have proposed a hardware information flow analysis method [1], which models design security-related behaviors from the perspective of information flow security, and detects security vulnerabilities such as information leakage, information tampering, and Trojan backdoors by capturing harmful information flows. Tiwari et al. and Oberg et al. studied and proposed a gate-level information flow tracking method (GLIFT) for gate-level netlists of application-specific integrated circuit (ASIC) design [2, 3]. It can automatically generate information models for gate-level netlists generated by the Design Compiler synthesis tool, and verify the processor design security isolation mechanism by combining the generated gate-level information flow security model. Ardeshiricham et al. studied and proposed an information flow tracking method for register transfer level (RTL) description of integrated circuit design [4]. It can convert RTL code into an abstract syntax tree and automatically generate an information flow model of the circuit design based on the abstract syntax tree structure. Combining the generated model, it can realize the detection of time side channels. The above-mentioned information flow model generation methods all adopt a technical approach based on library mapping. First, an information flow model is generated for the basic logic gates in the gate-level netlist or the basic logic operations in the abstract syntax tree, and an information flow model library of basic units or operations is constructed. Based on the information flow model library, the information flow model of large-scale design is generated through library mapping. However, due to the high configurability of FPGA devices, the number of basic units with different configurations is huge. For example, a 6-input look-up table contains a 26=64-bit configuration vector, and its configurable modes reach 264. Under existing computing conditions, it is difficult to generate and maintain such a huge basic unit information flow model library.

[0004] [1]Wei Hu, Armaiti Ardeshiricham and Ryan Kastner. Hardware InformationFlow Tracking. ACM Computing Surveys, Volume 54, Issue 4, July 2021, Article No.: 83, pp 1–39.

[0005] [2] Mohit Tiwari, Hassan MG Wassel, Bita Mazloom, Shashidhar Mysore, Frederic T Chong and Timothy Sherwood. Complete Information Flow Tracking from the Gates Up. Proceedings of the 14th International Conference on Architectural Support for Programming Languages ​​and Operating Systems, ASPLOS2009, Washington, DC, USA, March 7-11, 2009.

[0006] [3] Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, and Ryan Kastner. Theoretical Analysis of Gate Level Information Flow Tracking, ACM / EDAC / IEEE Design Automation Conference (DAC), 244-247, Jun. 2010.

[0007] [4]Armaiti Ardeshiricham, Wei Hu, Joshua Marxen and RyanKastner. Register Transfer Level Information Flow Tracking for Provably SecureHardware Design, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1695-1700, Mar. 2017. Summary of the invention

[0008] 1. Technical issues to be resolved

[0009] Aiming at the problem that existing methods are difficult to solve the problem of automatic generation of information flow models for FPGA circuit design, the present invention proposes a method for generating information flow models for FPGA circuit design by dynamically constructing information flow models of design units.

[0010] (II) Technical solution

[0011] In order to solve the above technical problems, the present invention provides a method for generating an information flow model for FPGA circuit design, comprising the following steps:

[0012] 1) Input the FPGA circuit design code to be analyzed;

[0013] 2) synthesizing the FPGA circuit design code into an FPGA netlist;

[0014] 3) Analyze the generated FPGA netlist and identify the signals and FPGA design units therein;

[0015] 4) Analyze the signal list and add corresponding information flow labels to it;

[0016] 5) Analyze the FPGA design unit, dynamically generate a corresponding information flow model for each FPGA design unit, and obtain an FPGA design unit information flow model library related to the specific design;

[0017] 6) Attach a corresponding information flow model to each FPGA design unit, and connect the information flow models according to the connection relationship between the signals in the FPGA netlist and the FPGA design units to obtain the information flow model of the entire FPGA circuit design.

[0018] The present invention also provides a method for analyzing the security of FPGA circuit design, which is implemented based on the information flow model generated by the method.

[0019] (III) Beneficial effects

[0020] The present invention has the following advantages:

[0021] 1) The information flow model generation method for FPGA circuit design proposed in the present invention targets the FPGA design process and takes FPGA design units such as LUT as the analysis object for modeling. Existing hardware information flow tracking methods mostly target ASIC design gate-level netlists or abstract syntax trees after RTL code conversion.

[0022] 2) The present invention proposes an effective method for dynamically generating information flow models of FPGA design units, which can overcome the deficiency that the number of LUT units with different configurations in FPGA design is huge and it is difficult to pre-maintain an information flow model library of a basic unit.

[0023] 3) The information flow model generation method for FPGA circuit design proposed in the present invention adopts standard FPGA design and synthesis tools in the analysis process. The constructed basic units and the information flow model of the entire FPGA design are described in the standard EDA design language, which can be effectively integrated with standard EDA design processes and tools.

[0024] 4) The information flow model generation method for FPGA circuit design proposed in the present invention can realize the modeling and description of security-related behaviors of FPGA circuit design, and can be used to verify security attributes such as confidentiality, integrity, and isolation characteristics. By capturing the flow of harmful information, it can detect security risks such as information leakage, information tampering, and Trojan backdoors.

[0025] 5) The FPGA circuit design information flow model constructed by the present invention can provide an effective mathematical basis for security modeling and analysis, which helps to overcome the shortcomings of existing EDA tools that are difficult to achieve security modeling and verification, and solve potential design security risks at a lower cost in the early stages of design. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a flow chart of the information flow model generation method for FPGA circuit design proposed by the present invention;

[0027] Figure 2 It is the schematic diagram of the FPGA design network after synthesis;

[0028] Figure 3 It is a schematic diagram of the FPGA information flow model;

[0029] Figure 4 It is a flow chart of the method for dynamically constructing the information flow model of the LUT design unit. DETAILED DESCRIPTION

[0030] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0031] The present invention proposes a method for generating an information flow model for FPGA circuit design, which overcomes the shortcomings that the existing information flow model generation method is difficult to apply due to the large number of FPGA design unit types and the difficulty in building a design unit information flow model library in advance. The method is a method for generating an information flow model for FPGA circuit design based on dynamic library generation, which realizes the automatic generation of large-scale FPGA circuit design information flow models and provides an effective mathematical basis for FPGA design security analysis.

[0032] The functional circuit design model commonly used in FPGA circuit design can usually only achieve modeling and description of the functional correctness of the design. However, security and functional correctness belong to two different dimensions of attributes. Functional correctness is an important basis for security, but functional correctness cannot guarantee the security of the design. The present invention constructs an information flow model for FPGA circuit design, realizes modeling and description of design security-related behaviors from the perspective of information flow security, and provides an effective mathematical model for FPGA design security analysis. It can detect security risks such as information leakage, information tampering, and Trojan backdoors by capturing harmful information flows, and can effectively address the shortcomings of existing functional circuit design models that are difficult to achieve security modeling and verification, and difficult to effectively detect design security risks. The present invention generally includes the following steps: inputting the FPGA circuit design code to be analyzed; synthesizing the design code into an FPGA design netlist; analyzing the generated FPGA netlist to identify the signals and design units therein; analyzing the signal list and adding corresponding information flow labels to it; analyzing the design units, dynamically generating corresponding information flow models for each design unit, and obtaining a library of design unit information flow models related to a specific design; adding a corresponding information flow model to each design unit, and connecting the information flow models according to the connection relationship between the signals and the design units in the FPGA design netlist, and obtaining an information flow model for the entire FPGA circuit design. The above scheme can provide an effective mathematical basis for the security analysis of FPGA circuit design, help to expand the security dimension beyond the existing functional EDA design process and tools, and detect and eliminate potential design security risks at a lower cost in the early stages of design.

[0033] The information flow model generation method for FPGA circuit design proposed by the present invention is described in detail below with reference to the accompanying drawings.

[0034] Figure 1 FIG. 1 is a flow chart of a method for generating an information flow model for FPGA circuit design according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0035] 1) Inputting the FPGA circuit design code to be analyzed. In a specific embodiment, the FPGA circuit design to be analyzed is input in the form of register transfer level code or gate level netlist;

[0036] 2) Synthesize the FPGA circuit design code into an FPGA netlist. In a specific embodiment, an open source FPGA synthesis tool such as Yosys can be used to perform logic synthesis on the FPGA circuit design to be analyzed, so as to export the synthesized FPGA netlist. During synthesis, FPGA devices of different manufacturers and series can be specified. The synthesized FPGA netlist may include FPGA design units such as 1-input to 6-input LUTs, selectors, inverters, triggers, buffers, etc.;

[0037] 3) Analyze the generated FPGA netlist to identify the signals and FPGA design units therein. In a specific embodiment, the signals and design units therein can be identified by the keywords in the FPGA netlist, where the signal names are followed by the input, output, inout, wire, reg, and tri keywords. The signal connection relationship is followed by the assign keyword. Other keywords such as LUT1, LUT2, LUT3, LUT4, LUT5, LUT6, MUXF7, MUXF8, IBUF, and OBUF are FPGA design units, and their input and output ports also include signal connection relationships;

[0038] 4) Analyze the signal list and add corresponding information flow labels to it, wherein a corresponding information flow label is added to each signal in the FPGA netlist signal list, the label type is consistent with the signal type, and the label width is also consistent with the signal width. In a specific embodiment, each bit of the signal is correspondingly added with a 1-bit information flow label. The following table shows the way of adding labels to single-bit, byte, half-word and word signals of different variable types in the present invention:

[0039] Signal Type Signal width Signal name / information flow label name illustrate input [0:0] sig_bit; Single bit signal input [0:0] sig_bit_t; Single-bit signal label output [7:0] sig_byte; Byte signal output [7:0] sig_byte_t; Byte signal label wire [15:0] sig_halfword; half word signal wire [15:0] sig_halfword_t; Half-word signal label reg [31:0] sig_halfword; word signal reg [31:0] sig_halfword_t; Word signal label

[0040] 5) Analyze the FPGA design unit, dynamically generate a corresponding information flow model for each FPGA design unit, and obtain an information flow model library of FPGA design units related to the specific design, wherein information flow analysis is performed on FPGA design units such as LUT, DFF, MUX, IBUF, OBUF in the FPGA netlist, and information flow models are dynamically established to achieve accurate modeling and description of the information flow behavior of the FPGA design unit from input to output. In a specific embodiment, an information flow model corresponding to the FPGA design unit is attached to all identified FPGA design units. For example, if a 4-input LUT is identified in the FPGA netlist, an information flow model for the LUT is attached accordingly. The input of the attached information flow model includes the input of the original LUT and the information flow labels of the inputs of these original LUTs, and its output is the information flow label of the output of the original LUT. The definition of the original 4-input LUT and its information flow model is given below:

[0041] LUT4 U1(.I0(in0),.I1(in1),.I2(in2),.I3(in3),.O(o1)); / / Definition of original LUT

[0042] LUT4_IFT

[0043] U1_SH(.I0(in0),.I0_t(in0_t),.I1(in1),.I1_t(in1_t),.I2(in2),

[0044] .I2_t(in2_t),.I3(in3),.I3_t(in3_t),.O_t(o1_t)); / / LUT information flow model definition

[0045] Among them, in0, in1, in2, in3 are the inputs of the original LUT, and o1 is the output of the original LUT; in0_t, in1_t, in2_t, in3_t are the information flow labels of the original LUT input, and o1_t is the label of the original LUT output;

[0046] 6) Attach a corresponding information flow model to each FPGA design unit, and connect the information flow model according to the connection relationship between the signals in the FPGA netlist and the FPGA design units to obtain the information flow model of the entire FPGA circuit design. In a specific embodiment, the connection relationship of the information flow label is attached accordingly according to the signal connection relationship of the original FPGA netlist. An embodiment of the connection relationship is given below.

[0047] assign o5=in5; / / Original connection relationship

[0048] assign o5_t=in5_t; / / Information flow label connection relationship

[0049] For additional methods of connection relationships defined by the FPGA design unit, an example has been given in the 4-input LUT in step 5). When the signal sig is connected to the port port, the information flow label sig_t of the signal sig is connected to the information flow label port port_t corresponding to port.

[0050] In the above scheme, for FPGA netlists of any size, according to the design signals, design units and connection relationships in the netlist, it is possible to automatically add information flow labels and information flow models to the design signals and design units in the FPGA netlist, respectively, and according to the connection relationships in the FPGA design netlist, it is possible to determine the connection relationship between the design signal information flow labels and the design unit information flow models accordingly, and automatically generate the information flow model of the entire FPGA circuit design. The generated information flow model of the entire FPGA circuit design can realize the accurate modeling and description of the information flow behavior in the entire FPGA circuit design, provide a mathematical basis for the security analysis of the FPGA circuit design, and can be used to identify security issues caused by harmful information flow in the FPGA circuit design.

[0051] In order to better understand the information flow model generation method for FPGA circuit design in the embodiment of the present invention, the following is combined with the attached Figure 2 To Attachment Figure 4 , the method is further described with a specific example.

[0052] Figure 2 The structure of the FPGA netlist obtained after FPGA synthesis of the FPGA circuit design is shown. The leftmost I1~I6 are input signals connected to the FPGA design unit IBUF, and the outputs of these IBUFs are n1~n6 respectively. For each IBUF, a specific connection relationship is defined, for example, I1 is connected to the input end of the first IBUF, and n1 is connected to the output end of the IBUF. These signals are further connected to FPGA design units such as LUT, BUFG, and MUX. These FPGA design units have their own functions defined, and the combination of these basic unit functions realizes the function of the entire FPGA circuit design.

[0053] Figure 3 The schematic diagram of the FPGA information flow model is shown. Among them, I1 and I2 are the inputs of the original circuit, and O1 is the output of the original circuit; I1_t and I2_t are the information flow labels of the original inputs, and O1_t is the information flow label of the original output. LUT2 implements the function of the original circuit, and the output O1 is calculated by inputting I1 and I2. LUT4 is the information flow model corresponding to the LUT2 unit, and its input includes the inputs I1 and I2 of the original circuit, and also includes its information flow labels I1_t and I2_t. The LUT4 defines the calculation method of the output information flow label O1_t. According to the connection relationship of the original signal, the information connection relationship of the information flow model can be determined.

[0054] Figure 4A flow chart of a method for dynamically constructing an information flow model of a LUT design unit is provided. The method flow is used to analyze a given FPGA unit and dynamically generate its corresponding information flow model. Taking the LUT unit as an example, after a specific LUT unit is given, the initialization vector (INIT value) therein defines the logical function implemented by the LUT, and the initialization vector INIT value is the truth table of its logical function. The dynamic information flow model generation method proposed in the present invention analyzes the initialization vector INIT value and divides it into an open set and a closed set. Among them, the open set contains all truth table entries with an output of 1, and the closed set contains all truth table entries with an output of 0. The present invention further defines a mapping algorithm from an open set to a closed set, which is used to generate a truth table of the information flow model of the LUT design unit. For example, when mapping the 0000 item in the open set to the 0001 item in the closed set, 0000 and the difference (exclusive OR) between the two items are combined into an input vector, that is, 00000001 is added to the truth table description of the information flow model; when mapping the 1111 item in the open set to the 1110 item in the closed set, 1111 and the difference (exclusive OR) between the two items are combined into an input vector, that is, 11110001 is added to the truth table description of the information flow model. When all mappings from open sets to closed sets are completed, a complete truth table description of the information flow model of the LUT design unit can be obtained. Then, a logic simplification tool is used to perform logical simplification on the truth table of the information flow model to obtain the information flow model of the LUT design unit, thereby realizing the dynamic generation of the information flow model of the FPGA design unit. By adopting the above-mentioned dynamic information flow model generation method, the corresponding design unit information flow model can be generated on demand according to the specific configuration of the logic unit in the FPGA netlist, avoiding the dependence on a massive design unit model library.

[0055] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for generating an information flow model for FPGA circuit design, characterized in that: The following steps are involved: 1) Input the FPGA circuit design code to be analyzed; 2) synthesizing the FPGA circuit design code into an FPGA netlist; 3) Analyze the generated FPGA netlist and identify the signals and FPGA design units therein; 4) Analyze the signal list and add corresponding information flow labels to it; 5) Analyze the FPGA design unit, dynamically generate a corresponding information flow model for each FPGA design unit, and obtain an FPGA design unit information flow model library related to the specific design; 6) Attach a corresponding information flow model to each FPGA design unit, and connect the information flow models according to the connection relationship between the signals in the FPGA netlist and the FPGA design units to obtain the information flow model of the entire FPGA circuit design.

2. The method according to claim 1, characterized in that The FPGA circuit design code to be analyzed is input in the form of register transfer level code or gate level netlist.

3. The method according to claim 1, characterized in that In step 2), an FPGA synthesis tool is used to perform logic synthesis on the FPGA circuit design code to be analyzed, and the synthesized FPGA netlist is exported. The synthesized FPGA netlist obtained includes FPGA design units such as 1-input to 6-input LUTs, selectors, inverters, triggers, and buffers.

4. The method according to claim 3, characterized in that In step 3), the signals and FPGA design units are identified through the keywords in the FPGA netlist.

5. The method according to claim 4, characterized in that In step 3), the specific method of identifying signals and FPGA design units is: input, output, inout, wire, reg, tri keywords are followed by signal names, assign keywords are followed by signal connection relationships, LUT1, LUT2, LUT3, LUT4, LUT5, LUT6, MUXF7, MUXF8, IBUF, OBUF keywords are FPGA design units, and their input and output ports also include signal connection relationships.

6. The method according to claim 5, characterized in that In step 4), a corresponding information flow label is added to each signal in the FPGA netlist signal list. The label type is consistent with the signal type, and the label width is also consistent with the signal width. Each bit of the signal is correspondingly attached with a 1-bit information flow label.

7. The method according to claim 6, characterized in that In step 5), information flow analysis is performed on the FPGA design units such as LUT, DFF, MUX, IBUF, and OBUF in the FPGA netlist, and an information flow model is dynamically established to achieve modeling and description of the information flow behavior of the FPGA design unit from input to output.

8. The method according to claim 7, characterized in that In step 5), an information flow model corresponding to the FPGA design unit is attached to all identified FPGA design units. If a 4-input LUT is identified in the FPGA netlist, an information flow model for the LUT is attached accordingly. The input of the attached information flow model of the LUT includes the input of the original LUT and the information flow labels of the inputs of the original LUT, and the output is the information flow label of the original LUT output.

9. The method according to claim 8, characterized in that In step 6), the connection relationship of the information flow label is added accordingly according to the signal connection relationship of the original FPGA netlist.

10. A method for analyzing the security of FPGA circuit design, characterized in that: The method is implemented based on the information flow model generated by the method as described in any one of claims 1 to 9.

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