Wafer defect graph drawing method and device, equipment, storage medium and program product

Abstract

The invention relates to the technical field of integrated circuits, and discloses a wafer defect graph drawing method and device, equipment, a storage medium and a program product. The method comprises the following steps: acquiring a wafer defect two-dimensional array; traversing the wafer defect two-dimensional array, comparing the value of each number in the wafer defect two-dimensional array with a preset defect rule, and judging whether the chip placement position corresponding to each number in the wafer defect two-dimensional array has a defect or not; when the chip placement position corresponding to the target number in the wafer defect two-dimensional array is judged to have a defect, reading a defect type, a defect position coordinate and a defect map path corresponding to the target number; and determining the attribute of the defect mark based on the defect type, determining the position of the defect mark based on the defect position coordinate, and determining the shape of the defect mark based on the defect map path so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map. According to the scheme, when the wafer defect graph drawing function is achieved, the efficiency is high, and the accuracy is good.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a method, device, equipment, storage medium and program product for drawing a wafer defect map. Background Art

[0002] Wafer Map is based on the chip (die) as the unit. It combines the shape of the entire wafer and the status and characteristics of each chip in the wafer to form a wafer map. It is an important reference for tracing the causes of abnormalities in the product process. Through the spatial distribution of the wafer map, the possible causes of product quality abnormalities can be found, such as problematic equipment or abnormal process technology.

[0003] The traditional method uses manual drawing of wafer maps. The relevant technicians adjust the drawing specifications and proportions of the wafer map through calculations, manually check the fault conditions of each chip in the wafer, and draw the wafer map with the help of pencils, rulers, compasses and other manual drawing tools. In related technologies, computer-aided design (CAD) and automated tools are used to assist in drawing wafer maps, which greatly reduces manual operations.

[0004] However, the above solution still relies on manual judgment of wafer defects and wafer mapping, which is inefficient and has poor accuracy. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a method, device, equipment, storage medium and program product for drawing a wafer defect map to solve the problems of low efficiency and poor accuracy when drawing a wafer defect map.

[0006] In a first aspect, the present invention provides a method for drawing a wafer defect map, the method comprising:

[0007] Obtain a two-dimensional array of wafer defects; the two-dimensional array of wafer defects is obtained based on defect identification of a target wafer; the target wafer includes a plurality of chip placement positions, and the plurality of chip placement positions correspond one-to-one to the numbers in the two-dimensional array of wafer defects;

[0008] Traversing the wafer defect two-dimensional array, comparing the value of each number in the wafer defect two-dimensional array with a preset defect rule, and determining whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array;

[0009] When it is determined that there is a defect at the chip placement position corresponding to the target number in the wafer defect two-dimensional array, the defect type, defect position coordinates and defect map path corresponding to the target number are read;

[0010] The properties of the defect mark are determined based on the defect type, the position of the defect mark is determined based on the defect position coordinates, and the shape of the defect mark is determined based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map.

[0011] In an optional embodiment, the defect type includes at least one of contamination, needle mark abnormality, removable foreign matter and edge contamination.

[0012] In an optional implementation, when the defect type is edge contamination, determining the position of the defect mark based on the defect position coordinates includes:

[0013] Determine a first position of a defect mark corresponding to the edge contamination based on the defect position coordinates corresponding to the edge contamination;

[0014] The first position is expanded by a target size to serve as the position of the defect mark corresponding to the edge contamination.

[0015] In an optional implementation, comparing the value of each number in the wafer defect two-dimensional array with a preset defect rule to determine whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array includes:

[0016] When the target number in the wafer defect two-dimensional array is a first value, determining that the chip at the chip placement position corresponding to the target number does not have defects;

[0017] When the target number in the wafer defect two-dimensional array is a second value, determining that the chip placement position corresponding to the target number is empty;

[0018] When the target number in the wafer defect two-dimensional array is a value other than the first value and the second value, it is determined that the chip at the chip placement position corresponding to the target number has a defect.

[0019] In an optional embodiment, the method further includes:

[0020] When the target number in the wafer defect two-dimensional array is a first value, filling the position coordinates corresponding to the target number in the wafer map with a first color;

[0021] When the target number in the wafer defect two-dimensional array is a second value, the position coordinates corresponding to the target number in the wafer map are kept blank.

[0022] In an optional embodiment, the method further includes:

[0023] Create a canvas;

[0024] Based on the width and height of the canvas and the number of rows and columns of the wafer defect two-dimensional array, the width and height of each chip placement position are calculated, and the canvas is filled according to the wafer defect two-dimensional array to draw the wafer map;

[0025] In response to a user's zoom instruction, obtaining the position coordinates of the mouse in the wafer image and the zoom factor of the canvas;

[0026] Get the offset of each chip placement position;

[0027] The scaled wafer map is redrawn based on the width and height of each chip placement position, the current position coordinates of the mouse in the wafer map, the zoom factor of the canvas, and the offset of each chip placement position.

[0028] In a second aspect, the present invention provides a wafer defect map drawing device, the device comprising:

[0029] An array acquisition module is used to acquire a two-dimensional array of wafer defects; the two-dimensional array of wafer defects is obtained based on defect identification of a target wafer; the target wafer includes a plurality of chip placement positions, and the plurality of chip placement positions correspond one-to-one to the numbers in the two-dimensional array of wafer defects;

[0030] A defect judgment module is used to traverse the wafer defect two-dimensional array, compare the value of each number in the wafer defect two-dimensional array with a preset defect rule, and judge whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array;

[0031] A defect reading module, for reading the defect type, defect position coordinates and defect map path corresponding to the target number when it is determined that there is a defect at the chip placement position corresponding to the target number in the wafer defect two-dimensional array;

[0032] A drawing module is used to determine the attributes of the defect mark based on the defect type, determine the position of the defect mark based on the defect position coordinates, and determine the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map.

[0033] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the wafer defect map drawing method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0034] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the wafer defect map drawing method of the first aspect or any corresponding embodiment thereof.

[0035] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the wafer defect map drawing method of the first aspect or any corresponding embodiment thereof.

[0036] The technical solution provided by the present invention may include the following beneficial effects:

[0037] The wafer defect map drawing method provided by the present invention first obtains a wafer defect two-dimensional array obtained by defect identification of a target wafer, then traverses the wafer defect two-dimensional array, compares the value of each number in the wafer defect two-dimensional array with a preset defect rule, and judges whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array. When it is judged that there is a defect in the chip placement position corresponding to the target number in the wafer defect two-dimensional array, reads the defect type, defect position coordinates and defect map path corresponding to the target number, and finally determines the attribute of the defect mark based on the defect type, determines the position of the defect mark based on the defect position coordinates, and determines the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map. By obtaining the wafer defect two-dimensional array obtained by defect identification of the target wafer, and automatically comparing the value of each number in the wafer defect two-dimensional array with the preset defect rule, and then performing corresponding defect marking according to the defect judgment result, there is no need to manually judge chip failures and draw, thereby improving the efficiency and accuracy of wafer defect map drawing. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 is a schematic flow chart of a method for drawing a wafer defect map according to an embodiment of the present invention;

[0040] Figure 2 is a schematic flow chart of another wafer defect map drawing method according to an embodiment of the present invention;

[0041] Figure 3 is a schematic diagram of wafer defects according to an embodiment of the present invention;

[0042] Figure 4 is a schematic diagram of an enlarged wafer defect according to an embodiment of the present invention;

[0043] Figure 5 is a structural block diagram of a wafer defect map drawing device according to an embodiment of the present invention;

[0044] Figure 6 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0046] According to an embodiment of the present invention, an embodiment of a method for drawing a wafer defect map is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0047] In this embodiment, a method for drawing a wafer defect map is provided, which can be used in notebook computers, desktop computers, etc. Figure 1 is a flow chart of a method for drawing a wafer defect map according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0048] Step S101, obtaining a two-dimensional array of wafer defects.

[0049] The target wafer includes multiple chip placement positions, which can be arranged in a matrix form, and a certain distance is maintained between each chip placement position. Therefore, the chip status of each chip placement position in the target wafer can be reflected by a wafer defect two-dimensional array. Each number in the wafer defect two-dimensional array can reflect the status of the chip at the corresponding chip placement position, and the multiple chip placement positions correspond to the numbers in the wafer defect two-dimensional array one by one. The wafer defect two-dimensional array is obtained based on defect identification of the target wafer. Exemplarily, defect identification is performed on the target wafer through a defect identification algorithm to obtain defect data of the target wafer, and then a wafer defect two-dimensional array is generated based on the defect data of the target wafer.

[0050] Step S102, traverse the wafer defect two-dimensional array, compare the value of each number in the wafer defect two-dimensional array with the preset defect rule, and determine whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array.

[0051] The preset defect rule is a correspondence between the value of the number in the preset wafer defect two-dimensional array and the chip defect status, which can be set according to actual needs, for example, 1 means no defect, and 2 means a defect.

[0052] Step S103, when it is determined that there is a defect at the chip placement position corresponding to the target number in the wafer defect two-dimensional array, the defect type, defect position coordinates and defect map path corresponding to the target number are read.

[0053] The target number is one of the numbers in the two-dimensional array of wafer defects. When it is determined that there is a defect in the chip placement position corresponding to the target number, that is, there is a defect in the chip at the chip placement position corresponding to the target number. At this time, the defect type, defect position coordinates and defect map path corresponding to the target number are read from the defect data of the target wafer. The defect type is used to indicate the category of defects in the chip at the chip placement position corresponding to the target number. In actual application scenarios, different defect categories can be reflected by different colors or shapes. The defect position coordinates are used to indicate the specific position of the defect in the chip at the chip placement position corresponding to the target number. The corresponding coordinates in the wafer map. The defect map path is used to indicate the shape when the defect is marked at the defect position coordinates, such as marking the defect as an asterisk, a triangle, etc.

[0054] Step S104, determining the attributes of the defect mark based on the defect type, determining the position of the defect mark based on the defect position coordinates, and determining the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map.

[0055] The attributes of the defect mark can be color, shape, etc., which are selected according to actual needs. After determining the defect type, defect location coordinates, and defect map path corresponding to the target number, the defect mark of the chip placement position corresponding to the target number can be drawn according to the defect type, defect location coordinates, and defect map path corresponding to the target number. Similarly, the marking of the chip placement positions corresponding to all numbers in the wafer defect two-dimensional array is completed to generate the final wafer defect map. It should be noted that not all chips have defects. When it is determined that the chip at the chip placement position corresponding to the target number does not have defects, the corresponding drawing rules can also be set to mark the chip placement position corresponding to the target number.

[0056] The wafer defect map drawing method provided in this embodiment first obtains a wafer defect two-dimensional array obtained by defect identification of a target wafer, then traverses the wafer defect two-dimensional array, compares the value of each number in the wafer defect two-dimensional array with the preset defect rule, and determines whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array. When it is determined that there is a defect in the chip placement position corresponding to the target number in the wafer defect two-dimensional array, reads the defect type, defect position coordinates and defect map path corresponding to the target number, and finally determines the attribute of the defect mark based on the defect type, determines the position of the defect mark based on the defect position coordinates, and determines the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map. By obtaining the wafer defect two-dimensional array obtained by defect identification of the target wafer, and automatically comparing the value of each number in the wafer defect two-dimensional array with the preset defect rule, and then performing corresponding defect marking according to the defect judgment result, there is no need to manually judge chip failures and draw, thereby improving the efficiency and accuracy of wafer defect map drawing.

[0057] In this embodiment, a method for drawing a wafer defect map is provided, which can be used in notebook computers, desktop computers, etc. Figure 2 is a flow chart of a method for drawing a wafer defect map according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0058] Step S201, obtaining a two-dimensional array of wafer defects.

[0059] The target wafer includes multiple chip placement positions, and the wafer defect two-dimensional array is obtained based on defect identification of the target wafer. Exemplarily, the target wafer is optically inspected by automatic optical inspection (VTest AOI) to identify defects in the target wafer, such as surface defects, dimensional deviations, etc., to obtain defect data of the target wafer, and the defect data is embodied in the form of an array to generate a wafer defect two-dimensional array of the target wafer, and the multiple chip placement positions correspond one to one to the numbers in the wafer defect two-dimensional array. Next, the computer device executing this method obtains the wafer defect two-dimensional array through an interface.

[0060] Step S202, traverse the wafer defect two-dimensional array, compare the value of each number in the wafer defect two-dimensional array with the preset defect rule, and determine whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array.

[0061] Specifically, the above step S202 includes:

[0062] Step S2021, traverse the two-dimensional array of wafer defects.

[0063] Optionally, the wafer defect two-dimensional array is traversed in a double loop. Specifically, each row of the wafer defect two-dimensional array is traversed through an outer loop, and each number in the current row of the wafer defect two-dimensional array is traversed through an inner loop, so as to traverse each number in the wafer defect two-dimensional array in a double manner.

[0064] Step S2022: when the target number in the wafer defect two-dimensional array is a first value, it is determined that the chip at the chip placement position corresponding to the target number has no defects.

[0065] The first value can be set according to actual needs, for example, set to 1.

[0066] Step S2023, when the target number in the wafer defect two-dimensional array is a second value, it is determined that the chip placement position corresponding to the target number is empty.

[0067] The second value can be set according to actual needs, for example, set to 0.

[0068] Step S2024: when the target number in the wafer defect two-dimensional array is a value other than the first value and the second value, it is determined that the chip at the chip placement position corresponding to the target number has a defect.

[0069] When the target number is a value other than the first value and the second value, for example, the first value is 1, the second value is 0, and the value of the target number is 2, it is determined that the chip at the chip placement position corresponding to the target number is defective.

[0070] Step S203, when it is determined that there is no defect in the chip placement position corresponding to the target number in the wafer defect two-dimensional array, a first mark is drawn at the position coordinate corresponding to the target number in the wafer map.

[0071] Optionally, first create a canvas, and based on the width and height of the canvas and the number of rows and columns of the wafer defect two-dimensional array, determine the size of the position coordinates corresponding to each number in the wafer defect two-dimensional array in the wafer map, so that the corresponding position coordinates can be drawn according to the defect determination results of each number. Among them, the position coordinates include the upper left corner X coordinate, the upper left corner Y coordinate, the lower right corner X coordinate, and the lower right corner Y coordinate. Exemplarily, the wafer defect map is drawn through the paper.js plug-in.

[0072] The first mark may be to fill the position coordinates of the target number in the wafer map with a preset color or mark it with a preset shape. Optionally, when the target number in the two-dimensional array of wafer defects is a first value, the position coordinates corresponding to the target number in the wafer map are filled with a first color.

[0073] Step S204, when it is determined that the chip placement position corresponding to the target number in the wafer defect two-dimensional array is empty, the position coordinates corresponding to the target number in the wafer map are kept blank.

[0074] When the target number in the wafer defect two-dimensional array is a second value, the position coordinates corresponding to the target number in the wafer map are kept blank.

[0075] Step S205, when it is determined that there is a defect at the chip placement position corresponding to the target number in the wafer defect two-dimensional array, the defect type, defect position coordinates and defect map path corresponding to the target number are read.

[0076] The defect type includes at least one of contamination, needle mark abnormality, removable foreign matter, and edge contamination. The contamination, needle mark abnormality, removable foreign matter, and edge contamination may be marked by different colors or shapes.

[0077] Optionally, the needle mark abnormality includes the needle mark abnormality margin and the needle mark abnormality area. The needle mark abnormality margin requires drawing the path of the needle mark, and the needle mark abnormality area requires drawing the area of ​​an irregular figure used to indicate the needle mark abnormality defect based on the path of the needle mark edge.

[0078] Step S206, determining the attributes of the defect mark based on the defect type, determining the position of the defect mark based on the defect position coordinates, and determining the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map.

[0079] Exemplarily, when the attribute of the defect mark corresponding to the defect type is red and the shape of the defect mark is "×", the defect map path is the two diagonal lines of the defect position coordinates. When drawing, it is necessary to calculate the width, height and diagonal length of the defect position coordinates. The width of the defect position coordinates is obtained by the upper left corner X coordinate and the lower right corner X coordinate of the defect position coordinates, the height of the defect position coordinates is obtained by the upper left corner Y coordinate and the lower right corner Y coordinate of the defect position coordinates, and the diagonal length is obtained based on the upper left corner X coordinate and Y coordinate, and the lower right corner X coordinate and Y coordinate of the defect position coordinates.

[0080] Furthermore, if the width, height and diagonal length of the entire defect area are to be calculated, the four corner coordinates of the rectangular area corresponding to the entire defect area are used for calculation. Exemplarily, the defect position coordinates = [X coordinate of the upper left corner of the defect, Y coordinate of the upper left corner of the defect, X coordinate of the lower right corner of the defect, Y coordinate of the lower right corner of the defect]. The width of the entire defect area is calculated by the X coordinate of the lower right corner of the defect - the X coordinate of the upper left corner of the defect, the height of the entire defect area is calculated by the Y coordinate of the lower right corner of the defect - the Y coordinate of the upper left corner of the defect, and the height of the entire defect area is calculated by Math sqrt(width 2 +High 2) calculates the diagonal length of the entire defect area, where Math sqrt is used to calculate the square root of a number.

[0081] Optionally, when the defect type is edge contamination, a certain size needs to be expanded. Therefore, when determining the position of the defect mark based on the defect position coordinates, first determine the first position of the defect mark corresponding to the edge contamination based on the defect position coordinates corresponding to the edge contamination, and then expand the first position by a target size as the position of the defect mark corresponding to the edge contamination. The target size can be selected according to actual needs, for example, 10px.

[0082] Optionally, in order to realize the generation of a new proportional wafer defect map at different zoom sizes, corresponding algorithm steps can be set. First, a canvas is created, and then the width and height of each chip placement position are calculated based on the width and height of the canvas and the number of rows and columns of the wafer defect two-dimensional array, and the canvas is filled according to the wafer defect two-dimensional array to draw the wafer map. The user can issue a zoom instruction to the computer device in a preset manner, such as rolling the mouse wheel, or typing the zoom factor. Upon receiving the user's zoom instruction, the computer device responds to the user's zoom instruction, obtains the position coordinates of the mouse in the wafer map and the zoom factor of the canvas, and then obtains the offset of each chip placement position, and then redraws the scaled wafer map based on the width and height of each chip placement position, the current position coordinates of the mouse in the wafer map, the zoom factor of the canvas, and the offset of each chip placement position, so as to achieve proportional adaptive scaling of the wafer map. The offset of the chip placement position is calculated based on the width and height of the chip placement position, the number of rows and columns of the chip placement position in the wafer image, the zoom factor of the canvas, and the offset of the canvas. The offset of the canvas is obtained based on the current position of the mouse and the initial position of the mouse. For example, the mouse position is obtained through the @wheel mouse wheel event, and the zoom factor zoomValue of the canvas is obtained through paper.view.zoom in the paper plug-in.

[0083] Optionally, in order to realize proportional adaptive viewing of wafer defect images on different screens, the size of the target screen can be obtained, and the percentage of the wafer defect image in the target screen can be calculated, the height and width of the target document display area can be read, and then the width and height of the wafer defect image after resizing can be calculated based on the percentage of the wafer defect image in the target screen, the height and width of the target document display area, and the initial width and initial height of the wafer defect image, so that the canvas of the wafer defect image can be scaled according to the size of the target screen without deformation. Exemplarily, first calculate the percentage of the screen size and the size of the picture you want to display, and then read window.innerWidth and window.innerHeight. Among them, window.innerWidth returns the height of the document display area of ​​the window, including the height of the vertical scroll bar if there is one; window.innerHeight returns the width of the document display area of ​​the window, including the height of the horizontal scroll bar if there is one. Next, set the width of the adjusted wafer defect map to X = 1 / (window.innerWidth / initial width of the canvas), calculate the height of the adjusted wafer defect map to Y = 1 / (window.innerHeight / initial height of the canvas), and scale the canvas view through the paper.view.scale(X,Y) method to make the canvas adapt to different screen sizes.

[0084] The wafer defect map drawing method provided in this embodiment first obtains a wafer defect two-dimensional array obtained by defect identification of a target wafer, then traverses the wafer defect two-dimensional array, compares the value of each number in the wafer defect two-dimensional array with the preset defect rule, and determines whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array. When it is determined that there is a defect in the chip placement position corresponding to the target number in the wafer defect two-dimensional array, reads the defect type, defect position coordinates and defect map path corresponding to the target number, and finally determines the attribute of the defect mark based on the defect type, determines the position of the defect mark based on the defect position coordinates, and determines the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map. By obtaining the wafer defect two-dimensional array obtained by defect identification of the target wafer, and automatically comparing the value of each number in the wafer defect two-dimensional array with the preset defect rule, and then performing corresponding defect marking according to the defect judgment result, there is no need to manually judge chip failures and draw, thereby improving the efficiency and accuracy of wafer defect map drawing.

[0085] As one or more specific application embodiments of the embodiments of the present invention, the optimal implementation scheme or the scheme that the inventor most wants to embody is described below in combination with specific application scenarios.

[0086] Figure 3is a schematic diagram of wafer defects according to an embodiment of the present invention, Figure 4 : is a schematic diagram of wafer defects magnified according to an embodiment of the present invention. Figure 4 Yes Figure 3 In this embodiment, green is used as the first color to fill the position coordinates of the corresponding chip placement position without defects, gray is used to represent the blank position coordinates, the graphic "×" is used as the shape of the defect mark, red is used to represent contamination, dark green is used to represent abnormal needle marks, yellow is used to represent removable foreign matter, and purple is used to represent edge contamination (pad edge contamination in the figure).

[0087] In this embodiment, a wafer defect map drawing device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0088] This embodiment provides a wafer defect map drawing device, such as Figure 5 As shown, including:

[0089] An array acquisition module 501 is used to acquire a wafer defect two-dimensional array; the wafer defect two-dimensional array is obtained based on defect identification of a target wafer; the target wafer includes a plurality of chip placement positions, and the plurality of chip placement positions correspond one-to-one to the numbers in the wafer defect two-dimensional array;

[0090] The defect judgment module 502 is used to traverse the wafer defect two-dimensional array, compare the value of each number in the wafer defect two-dimensional array with the preset defect rule, and judge whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array;

[0091] The defect reading module 503 is used to read the defect type, defect position coordinates and defect map path corresponding to the target number when it is determined that there is a defect in the chip placement position corresponding to the target number in the wafer defect two-dimensional array;

[0092] The drawing module 504 is used to determine the attributes of the defect mark based on the defect type, determine the position of the defect mark based on the defect position coordinates, and determine the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map.

[0093] In an optional embodiment, the defect type includes at least one of contamination, needle mark abnormality, removable foreign matter and edge contamination.

[0094] In an optional implementation, when the defect type is edge contamination, determining the position of the defect mark based on the defect position coordinates includes:

[0095] Determine a first position of a defect mark corresponding to the edge contamination based on the defect position coordinates corresponding to the edge contamination;

[0096] The first position is expanded by a target size to serve as the position of the defect mark corresponding to the edge contamination.

[0097] In an optional implementation manner, the defect judgment module is further used to:

[0098] When the target number in the wafer defect two-dimensional array is a first value, determining that the chip at the chip placement position corresponding to the target number does not have defects;

[0099] When the target number in the wafer defect two-dimensional array is a second value, determining that the chip placement position corresponding to the target number is empty;

[0100] When the target number in the wafer defect two-dimensional array is a value other than the first value and the second value, it is determined that the chip at the chip placement position corresponding to the target number has a defect.

[0101] In an optional implementation, the drawing module is further used for:

[0102] When the target number in the wafer defect two-dimensional array is a first value, filling the position coordinates corresponding to the target number in the wafer map with a first color;

[0103] When the target number in the wafer defect two-dimensional array is a second value, the position coordinates corresponding to the target number in the wafer map are kept blank.

[0104] In an optional embodiment, the device further includes a scaling module, configured to:

[0105] Create a canvas;

[0106] Based on the width and height of the canvas and the number of rows and columns of the wafer defect two-dimensional array, the width and height of each chip placement position are calculated, and the canvas is filled according to the wafer defect two-dimensional array to draw the wafer map;

[0107] In response to a user's zoom instruction, obtaining the position coordinates of the mouse in the wafer image and the zoom factor of the canvas;

[0108] Get the offset of each chip placement position;

[0109] The scaled wafer map is redrawn based on the width and height of each chip placement position, the current mouse position coordinates in the wafer map, the zoom factor of the canvas, and the offset of each chip placement position.

[0110] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0111] The wafer defect map drawing device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0112] The embodiment of the present invention also provides a computer device having the above Figure 5 The wafer defect mapping apparatus shown.

[0113] See also Figure 6 , Figure 6 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0114] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0115] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0116] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0117] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0118] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 6 The example of connecting through bus is taken in the following.

[0119] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0120] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0121] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0122] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations shall all fall within the scope of protection of the present invention.

Claims

1. A method for drawing a wafer defect map, characterized in that: The method comprises: Obtain a two-dimensional array of wafer defects; the two-dimensional array of wafer defects is obtained based on defect identification of a target wafer; the target wafer includes a plurality of chip placement positions, and the plurality of chip placement positions correspond one-to-one to the numbers in the two-dimensional array of wafer defects; Traversing the wafer defect two-dimensional array, comparing the value of each number in the wafer defect two-dimensional array with a preset defect rule, and determining whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array; When it is determined that there is a defect at the chip placement position corresponding to the target number in the wafer defect two-dimensional array, the defect type, defect position coordinates and defect map path corresponding to the target number are read; The properties of the defect mark are determined based on the defect type, the position of the defect mark is determined based on the defect position coordinates, and the shape of the defect mark is determined based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map.

2. The method according to claim 1, characterized in that The defect type includes at least one of contamination, needle mark abnormality, removable foreign matter, and edge contamination.

3. The method according to claim 2, characterized in that When the defect type is edge contamination, determining the position of the defect mark based on the defect position coordinates includes: Determine a first position of a defect mark corresponding to the edge contamination based on the defect position coordinates corresponding to the edge contamination; The first position is expanded by a target size to serve as the position of the defect mark corresponding to the edge contamination.

4. The method according to claim 1, characterized in that: The step of comparing the value of each number in the wafer defect two-dimensional array with a preset defect rule to determine whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array comprises: When the target number in the wafer defect two-dimensional array is a first value, determining that the chip at the chip placement position corresponding to the target number does not have defects; When the target number in the wafer defect two-dimensional array is a second value, determining that the chip placement position corresponding to the target number is empty; When the target number in the wafer defect two-dimensional array is a value other than the first value and the second value, it is determined that the chip at the chip placement position corresponding to the target number has a defect.

5. The method according to claim 4, characterized in that The method further comprises: When the target number in the wafer defect two-dimensional array is a first value, filling the position coordinates corresponding to the target number in the wafer map with a first color; When the target number in the wafer defect two-dimensional array is a second value, the position coordinates corresponding to the target number in the wafer map are kept blank.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Create a canvas; Based on the width and height of the canvas and the number of rows and columns of the wafer defect two-dimensional array, the width and height of each chip placement position are calculated, and the canvas is filled according to the wafer defect two-dimensional array to draw the wafer map; In response to a user's zoom instruction, obtaining the position coordinates of the mouse in the wafer image and the zoom factor of the canvas; Get the offset of each chip placement position; The scaled wafer image is redrawn based on the width and height of each chip placement position, the current position coordinates of the mouse in the wafer image, the zoom factor of the canvas, and the offset of each chip placement position.

7. A wafer defect map drawing device, characterized in that: The device comprises: An array acquisition module is used to acquire a two-dimensional array of wafer defects; the two-dimensional array of wafer defects is obtained based on defect identification of a target wafer; the target wafer includes a plurality of chip placement positions, and the plurality of chip placement positions correspond one-to-one to the numbers in the two-dimensional array of wafer defects; A defect judgment module is used to traverse the wafer defect two-dimensional array, compare the value of each number in the wafer defect two-dimensional array with a preset defect rule, and judge whether there is a defect in the chip placement position corresponding to each number in the wafer defect two-dimensional array; A defect reading module, for reading the defect type, defect position coordinates and defect map path corresponding to the target number when it is determined that there is a defect at the chip placement position corresponding to the target number in the wafer defect two-dimensional array; A drawing module is used to determine the attributes of the defect mark based on the defect type, determine the position of the defect mark based on the defect position coordinates, and determine the shape of the defect mark based on the defect map path, so as to draw the defect mark of the chip placement position corresponding to the target number in the wafer map.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the wafer defect map drawing method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the wafer defect map drawing method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the wafer defect map drawing method according to any one of claims 1 to 6.

Images