Display panel

Abstract

The present application discloses a display panel; a display panel includes N cascaded driving units, the N driving units are arranged along a first direction, each driving unit includes a first output module, a signal generating module and a second output module arranged along a second direction, the first output module is used to output a first gate driving signal, the second output module is used to output a second gate driving signal, the first gate driving signal and the second gate driving signal are different, the first output module includes a first buffer unit and a second buffer unit stacked in a third direction; the present application reduces the width of the first output module in the frame while ensuring the performance of the transistors in the two output modules by stacking the two buffer units in the first output module, so that the display panel achieves a narrow frame design.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new display technology that has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the related art, the pixel driving circuit of an OLED display panel is usually an 8T2C circuit. For this pixel driving circuit, a complementary metal oxide semiconductor (CMOS) gate driving circuit (Gate On Array, GOA) has been proposed to solve the technical problem of high power consumption of conventional gate driving circuits.

[0004] Since the CMOS GOA circuit needs to generate two signals, Nout and Pout, the gate drive circuit is provided with two buffer parts corresponding to Nout and Pout respectively. The buffer part that outputs the gate drive signal Nout has two buffer units arranged in parallel. Therefore, it is necessary to reserve a wider area on the product frame to set up the gate drive circuit, which is contrary to the narrow frame design of the product.

[0005] Therefore, there is an urgent need to provide a display panel to solve the above technical problems. Summary of the Invention

[0006] The present application provides a display panel to improve the technical problem of excessively large borders in existing display devices.

[0007] To solve the above problem, the technical solution provided by this application is as follows:

[0008] The present application provides a display panel, comprising a display portion and a gate driving circuit located on one side of the display portion, wherein the gate driving circuit comprises N cascaded driving units, the N driving units being arranged along a first direction; wherein each of the driving units comprises a signal generating module, a first output module, and a second output module arranged along a second direction;

[0009] The first output module is provided on a side of the signal generating module close to the display portion, and the first output module is used to output a first gate driving signal;

[0010] The second output module is provided at a side of the signal generating module away from the display unit, and the second output module is used to output a second gate driving signal, wherein the first gate driving signal and the second gate driving signal are different;

[0011] In which, the first output module includes a first buffer unit and a second buffer unit, the first buffer unit and the second buffer unit are stacked in a third direction, the third direction is perpendicular to the plane where the first direction and the second direction are located, the second direction is parallel to the scanning line of the display panel, the angle between the first direction and the second direction is greater than 0° and less than or equal to 90, and N is a positive integer.

[0012] Beneficial effects: The present application discloses a display panel, comprising N cascaded GOA units, the N GOA units being arranged along a first direction, each GOA unit comprising a first output module, a signal generating module and a second output module arranged along a second direction, the first output module being used to output a first gate drive signal, the second output module being used to output a second gate drive signal, the first gate drive signal and the second gate drive signal being different, the first output module comprising a first buffer unit and a second buffer unit stacked in a third direction; the present application reduces the width of the first output module in the frame while ensuring the performance of the transistors in the two output modules by stacking the two buffer units in the first output module, thereby enabling the display panel to achieve a narrow frame design. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0014] Figure 1 A simplified structural diagram of the display panel of this application;

[0015] Figure 2 This is a simplified structural diagram of the gate drive circuit in the display panel of this application;

[0016] Figure 3 This is a first equivalent circuit diagram of the gate driving circuit in the display panel of the present application;

[0017] Figure 4 This is a timing control diagram of the gate drive circuit in the display panel of this application;

[0018] Figure 5 This is a second equivalent circuit diagram of the gate driving circuit in the display panel of the present application;

[0019] Figure 6 This is a schematic diagram of the film layer in the display panel of this application;

[0020] Figure 7 This is a film layer diagram of the first gate layer in the display panel of this application;

[0021] Figure 8 This is a film layer diagram of the second gate layer in the display panel of this application;

[0022] Figure 9 A diagram showing the superposition of the first gate layer and the second gate layer in the display panel of the present application;

[0023] Figure 10 This is a film layer diagram of the third gate layer in the display panel of this application;

[0024] Figure 11 A diagram showing the superimposed film layers of the first gate layer and the third gate layer in the display panel of the present application;

[0025] Figure 12 This is a film layer diagram of the first active layer in the display panel of this application;

[0026] Figure 13 A diagram showing the stacked film layers of the first gate layer, the third gate layer, the first active layer, and the second active layer in the display panel of the present application;

[0027] Figure 14 This is a film layer diagram of the second active layer in the display panel of this application;

[0028] Figure 15 This is a film layer diagram of the first source and drain layer in the display panel of this application;

[0029] Figure 16 This is a diagram of the superimposed film layers of the second gate layer and the first source and drain layer of the display panel of this application;

[0030] Figure 17 This is a diagram of the superimposed film layers of the second gate layer, the first active layer, the second active layer, and the first source and drain layer of the display panel of this application;

[0031] Figure 18 This is a film layer diagram of the second source and drain layer in the display panel of this application;

[0032] Figure 19 This is a film layer diagram of the second gate layer, the first source-drain layer, and the second source-drain layer in the display panel of the present application;

[0033] Figure 20 This is a diagram of the superimposed film layers of the first active layer, the second active layer, and the second source and drain layer in the display panel of this application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0035] Related OLED display panels typically use a complementary metal oxide semiconductor (CMOS) gate drive circuit to address the high power consumption of conventional gate drive circuits. However, because the CMOS GOA circuit needs to generate two signals, Nout and Pout, the gate drive circuit is equipped with two buffer sections corresponding to Nout and Pout, respectively. Conventional signal generation sections are typically located near the bezel, while buffer sections are typically located near the display area. This results in a wider area being reserved on the product's bezel for the buffer section, which conflicts with the product's narrow bezel design. This application proposes the following solution to address these technical issues.

[0036] See also Figures 1 to 20 The present application provides a display panel 100, which may include a display portion 200 and a gate driving circuit 300 located on one side of the display portion 200. The gate driving circuit 300 includes N cascaded driving units 310, and the N driving units 310 are arranged along a first direction X.

[0037] In this embodiment, each driving unit 310 includes a signal generating module 10, a first output module 20 and a second output module 30 arranged along the second direction Y; the first output module 20 is arranged on the side of the signal generating module 10 close to the display unit 200, and the first output module 20 is used to output a first gate driving signal; the second output module 30 is arranged on the side of the signal generating module 10 away from the display unit 200, and the second output module 30 is used to output a second gate driving signal, and the first gate driving signal and the second gate driving signal are different.

[0038] In this embodiment, the first output module 20 may include a first buffer unit 210 and a second buffer unit 220 , and the first buffer unit 210 and the second buffer unit 220 are stacked in the third direction Z.

[0039] In this embodiment, the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°, and the third direction Z is perpendicular to the plane where the first direction X and the second direction Y are located; see Figure 2 The second direction Y is parallel to the scan line of the display panel 100 , and the second direction Y may be perpendicular to the first direction X.

[0040] In this embodiment, the driving unit 310 may be a GOA unit.

[0041] The present application stacks two buffer units in the first output module 20 to reduce the width of the frame occupied by the first output module 20 while ensuring the performance of the transistors in the two output modules, thereby achieving a narrow-frame design for the display panel 100.

[0042] It should be noted that the first gate drive signal is a positive pulse signal, and the second gate drive signal is a negative pulse signal; and, within a frame time interval, the first signal output terminal Nout outputs two positive pulse signals, and the second signal output terminal Pout outputs one negative pulse signal; at the same time, the pulse width of a positive pulse signal is greater than the pulse width of a negative pulse signal.

[0043] In this embodiment, the first buffer unit 210 includes a first output transistor T10, which includes a first active portion T10A. The second buffer unit 220 includes a second output transistor T9, which includes a second active portion T9A. The first active portion T10A is a metal oxide semiconductor, and the second active portion T9A is a silicon-containing semiconductor. At the same time, the first buffer unit 210 is arranged close to the light-emitting side of the display panel 100, and the second buffer unit 220 is arranged away from the light-emitting side of the display panel 100.

[0044] In this embodiment, the silicon-containing semiconductor may be amorphous silicon, polycrystalline silicon, single crystal silicon, or the like.

[0045] In the present application, the first output module 20 is configured as a combination of a low-temperature polysilicon transistor and a metal oxide transistor, and the high mobility of the low-temperature polysilicon transistor and the low leakage current of the metal oxide transistor are utilized to improve the device effect of the first output module 20; at the same time, the stacked first output transistor T10 and the second output transistor T9 reduce the width of the first output module 20 in the frame, so that the display panel 100 achieves a narrow-frame design.

[0046] In this embodiment, since the first output transistor T10 is a metal oxide transistor, although the metal oxide transistor has a small leakage current, the mobility of the metal oxide transistor is low. Therefore, in order to improve the driving capability of the first output transistor T10, the present application increases the length of the first output transistor T10 in the second direction Y as much as possible within a limited space to improve the driving capability of the first output transistor T10; however, since the first output transistor T10 and the second output transistor T9 are stacked, the present application can make the length of the first output transistor T10 in the second direction Y equal to the length of the second output transistor T9 in the second direction Y, thereby increasing the driving capability of the second output transistor T9 as much as possible, thereby increasing the load of the first output module 20.

[0047] In the display panel 100 of the present application, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7. The third output transistor T6 includes a third active portion T6A, and the fourth output transistor T7 includes a fourth active portion T7A. The third active portion T6A and the fourth active portion T7A are silicon-containing semiconductors. The third output transistor T6 and the fourth output transistor T7 are arranged in parallel along the first direction X.

[0048] In this embodiment, since the third output transistor T6 and the fourth output transistor T7 in the second output module 30 are both silicon-containing semiconductors with high mobility, the transistors in the second output module 30 do not need to increase the length in the second direction Y to improve the driving capability of the third output transistor T6 and the fourth output transistor.

[0049] In this embodiment, the second gate drive signal output by the second output module 30 is a negative pulse signal, and the pulse width of the negative pulse signal is smaller than the pulse width of the positive pulse signal output by the first output module 20. Therefore, the output load of the second output module 30 is lower than the output load of the first output module 20. Therefore, the length of the first output module 20 in the second direction Y of this application is smaller than the length of the second output module 30 in the second direction Y.

[0050] The technical solution of this application is now described in conjunction with specific embodiments.

[0051] See also Figure 1 The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA is provided with a display portion 200. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used to perform the display function, and is provided with multiple display units to achieve this display function. The non-display area NA may be a frame area of ​​the display panel 100, and may be provided with functional components that assist the display units in the display area AA in performing display functions.

[0052] See also Figure 1 The lower side of the display area AA is provided with a binding terminal 400. The binding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data line, thereby driving the display panel 100 to display the image. For example, the binding terminal 400 can be bonded to a chip or a chip-on-film to provide power and driving signals to the display panel 100.

[0053] In this embodiment, a plurality of light-emitting devices LED and sub-pixel circuits for driving the light-emitting devices LED may be arranged in an array in the display area AA. The sub-pixel circuits may be pixel driving circuits such as 7T1C, 7T2C, and 8T2C, and this application does not impose any specific restrictions.

[0054] In this embodiment, the gate driving circuit 300 is disposed in the non-display area NA, and the gate driving circuit 300 can be disposed on both sides of the display area AA; the gate driving circuit 300 can include N cascaded driving units 310, and the N driving units 310 can be arranged along the first direction X. The structure of the driving unit 310 can be various, for example Figure 3 The circuit structure in Figure 4 for Figure 3 Timing control diagram.

[0055] by Figure 3 As an example, each driving unit 310 may include:

[0056] The stage transmission signal selection module 301 is electrically connected between the start signal line STV and the fourth node O.

[0057] The pull-up control module 302 controls the potential of the first node K according to the potential of the fourth node O and the potential of the second clock signal line XCK.

[0058] The first filter module 303 is electrically connected between the fifth node W and the first node K. The control end of the first filter module 303 is electrically connected to the reset signal line RST.

[0059] The second filtering module 304 is electrically connected between the fifth node W and the second node Q. The control terminal of the second filtering module 304 receives the first gate driving signal of the N-2th stage.

[0060] The first inverting module 305 is connected between the first node K and the third node P.

[0061] The feedback module 306 is connected between the first node K and the third node P.

[0062] The first output module 20 is connected between the first node K and the first signal output terminal Nout, and is configured to output a first gate driving signal.

[0063] The second output module 30 outputs a second gate driving signal according to the potential of the second node Q and the potential of the third node P.

[0064] The first storage capacitor C1 , a first plate C1 a of the first storage capacitor C1 is connected to the second node Q, and a second plate C1 b of the first storage capacitor C1 is connected to the second signal output terminal Pout.

[0065] The voltage regulating module 307 has a first terminal electrically connected to the first low potential line Nvgl1 , a second terminal electrically connected to the gate of the first output transistor T10 , and a control terminal electrically connected to the third node P.

[0066] In this embodiment, in one frame, the gate drive circuit 300 includes a stage S100 and a stage S200. In the stage S100, the pulses of each first gate drive signal and the pulses of each second gate drive signal are output, while in the stage S200, the pulses of each first gate drive signal and the pulses of each second gate drive signal are not required.

[0067] In this embodiment, the level transfer signal selection module 301 includes a first-level transfer transistor T13 and a second-level transfer transistor T12, and the first-level transfer transistor T13 is a dual-gate transistor; the two gates of the first-level transfer transistor T13 and the gate of the second-level transfer transistor T12 are connected to the start signal line STV, the source of the first-level transfer transistor T13 is connected to the second low-potential line Pvgl, the drain of the first-level transfer transistor T13 and the source of the second-level transfer transistor T12 are connected to the fourth node O, and the drain of the second-level transfer transistor T12 is connected to the second high-potential line Pvgh2.

[0068] In this embodiment, the pull-up control module 302 includes a pull-up transistor T2 , a gate of the pull-up transistor T2 connected to the second clock signal line XCK, a source of the pull-up transistor T2 connected to the fourth node O, and a drain of the pull-up transistor T2 connected to the first node K.

[0069] In this embodiment, the first filtering module 303 includes a first filtering transistor T11 and a second storage capacitor C2, the gate of the first filtering transistor T11 and the third plate C2a of the second storage capacitor C2 are connected to the reset signal line RST, the source of the first filtering transistor T11 is connected to the first node K, and the drain of the first filtering transistor T11 and the fourth plate C2b of the second storage capacitor C2 are connected to the fifth node W.

[0070] In this embodiment, the second filtering module 304 includes a second filtering transistor T8, the gate of the second filtering transistor T8 is connected to the first signal output terminal Nout of the N-2th stage driving unit 310, the source of the second filtering transistor T8 is connected to the fifth node W, and the drain of the second filtering transistor T8 is connected to the second node Q.

[0071] In this embodiment, the first inverting module 305 includes a first inverting transistor T3 and a second inverting transistor T1, and the second inverting transistor T1 is a dual-gate transistor; the gate of the first inverting transistor T3 and the two gates of the second inverting transistor T1 are connected to the first node K, the source of the first inverting transistor T3 is connected to the second high potential line Pvgh2, the drain of the first inverting transistor T3 and the source of the second inverting transistor T1 are connected to the third node P, and the drain of the second inverting transistor T1 is connected to the second low potential line Pvgl.

[0072] In this embodiment, the feedback module 306 includes a first feedback transistor T4 and a second feedback transistor T5; wherein, the gate of the first feedback transistor T4 is connected to the first clock signal line CK, the source of the first feedback transistor T4 is connected to the first node K, the drain of the first feedback transistor T4 is connected to the source of the second feedback transistor T5, the gate of the second feedback transistor T5 is connected to the third node P, and the drain of the second feedback transistor T5 is connected to the first high potential line Pvgh1.

[0073] In this embodiment, the voltage regulation module 307 includes a regulation transistor T14, which is a dual-gate transistor; the two gates of the regulation transistor T14 are connected to the third node P, the source of the regulation transistor T14 is connected to the first node K, and the drain of the regulation transistor T14 is connected to the first low potential line Nvgl1.

[0074] In this embodiment, the first output module 20 includes a first output transistor T10 and a second output transistor T9, the first output transistor T10 is a dual-gate transistor, and the second output transistor T9 is a single-gate transistor; the first gate T10G of the first output transistor T10 and the second gate T9G of the second output transistor T9 are connected to the first node K of the signal generation module 10, the first source T9S of the second output transistor T9 is connected to the first high potential line Pvgh1, the first source T9S of the first output transistor T10 and the second drain T9D of the second output transistor T9 are connected to the first signal output terminal Nout, and the first drain T10D of the first output transistor T10 is connected to the first low potential line Nvgl1.

[0075] In this embodiment, the second output module 30 includes a third output transistor T6 and a fourth output transistor T7; the third gate T6G of the third output transistor T6 is connected to the second node Q of the signal generating module 10, the third source T6S of the third output transistor T6 is connected to the first clock signal line CK, the third drain T6D of the third output transistor T6 and the fourth source T7S of the fourth output transistor T7 are connected to the second signal output terminal Pout, the fourth gate T7G of the fourth output transistor T7 is connected to the third node P of the signal generating module 10, and the fourth drain T7D of the fourth output transistor T7 is connected to the first high potential line Pvgh1.

[0076] In this embodiment, the first-stage pass transistor T13, the second inverting transistor T1, the first output transistor T10, and the regulating transistor T14 are N-type transistors, and the second-stage pass transistor T12, the pull-up transistor T2, the first filter transistor T11, the second filter transistor T8, the first inverting transistor T3, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first feedback transistor T4, and the second feedback transistor T5 are P-type transistors.

[0077] In the gate drive circuit 300 provided in this embodiment, under the control of the third node P, the voltage regulation module 307 can stabilize or reduce the gate potential of the first output transistor T10 through the first low potential line Nvgl1, so that the first output transistor T10 is stabilized or better in the cut-off state to reduce leakage current, and the potential of the first gate drive signal can be maintained at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0078] In this embodiment, the voltage regulating module 307 is used to stabilize or reduce the low potential of the first node K. Alternatively, in another embodiment, the voltage regulating module 307 is further used to stabilize or reduce the gate potential of the first output transistor T10 during the positive pulse of the first gate driving signal.

[0079] It should be noted that the regulating transistor T14 can stabilize or reduce the gate potential of the first output transistor T10 during the positive pulse of the first gate drive signal, so that the first output transistor T10 is stable or better in the cut-off state to reduce leakage current, and thus can maintain the potential of the first gate drive signal at a high potential or pulse amplitude, thereby improving the potential stability of the gate drive signal.

[0080] In this embodiment, the internal node is the third node P, the second low potential line Pvgl and the first low potential line Nvgl1 are low potential lines with the same potential, and the channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10.

[0081] It should be noted that in this embodiment, the first output transistor T10 and the regulating transistor T14 can share the same low-potential line, which can reduce the number of wiring required for the gate drive circuit 300. The regulating transistor T14 has the same channel type as the first output transistor T10. When the first output transistor T10 is in the off state, the regulating transistor T14 can be turned on to further reduce the gate potential of the first output transistor T10.

[0082] In one embodiment, see Figure 5 , the internal node can be the third node P, the channel type of the regulating transistor T14 is the same as the channel type of the first output transistor T10, the first low potential line Nvgl1 transmits a first low potential signal, and the third low potential line Nvgl2 transmits a second low potential signal, and the potential of the second low potential signal is lower than the potential of the first low potential signal.

[0083] It should be noted that the channel type of the regulating transistor T14 is the same as that of the first output transistor T10. When the first output transistor T10 is in the off state, the regulating transistor T14 can transmit the second low-potential signal to the gate of the first output transistor T10, thereby further reducing the gate potential of the first output transistor T10 and thus reducing the leakage current of the first output transistor T10. In this way, the stability of the low potential of the second node QK and the low potential of the intermediate node W can be improved.

[0084] In one embodiment, the difference between the potential of the first low-potential signal and the potential of the second low-potential signal is greater than or equal to 2V.

[0085] It should be noted that this embodiment can not only reduce the leakage current of the first output transistor T10 , but also adjust the threshold voltage of the first output transistor T10 to shift toward the positive direction, thereby increasing the threshold voltage range of the first output transistor T10 .

[0086] The following is for Figure 3 The structure of the display panel 100 of the present application is described.

[0087] See also Figure 1 and Figure 6 The display area AA and non-display area NA of the display panel 100 may include a base substrate 110 and an array drive layer 120 disposed on the base substrate 110. Within the display area AA, the display panel 100 may also include a pixel definition layer disposed on the array drive layer 120, a light-emitting device layer disposed on the same layer as the pixel definition layer, and an encapsulation layer disposed on the pixel definition layer. The following primarily describes the film layer structure within the non-display area NA.

[0088] In this embodiment, the base substrate 110 supports various layers provided on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate can be used.

[0089] In this embodiment, the base substrate 110 is used to support the various film layers provided thereon. The base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. Examples of flexible materials for the flexible substrate include, but are not limited to, polyimide (PI).

[0090] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material, such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0091] In this embodiment, the first flexible substrate 111 is formed by coating a polymeric material on a supporting substrate (not shown) and then curing the polymeric material. The second flexible substrate 113 is formed by coating the same material as the first flexible substrate 111 and curing the material. The second flexible substrate 113 is formed by the same method as the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 can be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, thereby eliminating such defects.

[0092] See also Figure 6 The array driving layer 120 may include a plurality of thin film transistors, which may be of an etch-stop type or a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, and other structures according to the position of the gate electrode and the active layer, or may be classified into an N-type thin film transistor or a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 6 The thin film transistor does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of the various film layers of the display panel 100 of the present application.

[0093] See also Figure 6The array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, and a third gate insulating layer 128 disposed on the second gate layer 127. A second active layer 129 is arranged on the third gate insulation layer 128, a fourth gate insulation layer 130 is arranged on the second active layer 129, a third gate layer 131 is arranged on the fourth gate insulation layer 130, a first interlayer insulation layer 132 is arranged on the third gate layer 131, a first source-drain layer 133 is arranged on the first interlayer insulation layer 132, a second interlayer insulation layer 134 is arranged on the first source-drain layer 133, a second source-drain layer 135 is arranged on the second interlayer insulation layer 134, and a planarization layer 136 is arranged on the second source-drain layer 135.

[0094] See also Figure 6 The light shielding layer 121 is provided on the second barrier layer 114 and is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0095] See also Figure 6 The buffer layer 122 is arranged on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen elements, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0096] See also Figure 6 The first active layer 123 is arranged on the buffer layer 122, and the second active layer 129 can be arranged on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low-temperature polycrystalline silicon. For example, in the present application, the material of the first active layer 123 can be low-temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0097] See also Figure 6The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132, and the second interlayer insulating layer 134 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the material of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, and the second interlayer insulating layer 134 can be an inorganic substance composed of nitride oxide silicon or an organic material with flatness.

[0098] See also Figure 6 The first gate layer 125 , the second gate layer 127 and the third gate layer 131 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 , the second gate layer 127 and the third gate layer 131 may be copper, molybdenum or molybdenum-titanium alloy.

[0099] See also Figure 6 The first source-drain electrode layer 133 is disposed on the first interlayer insulating layer 132 , and the second source-drain electrode layer 135 is disposed on the second interlayer insulating layer 134 . The materials of the first source-drain electrode layer 133 and the second source-drain electrode layer 135 can be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0100] See also Figure 6 The planarization layer 136 is laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120. The material of the planarization layer 136 can be an inorganic material composed of nitride oxide and silicon or an organic material with flatness.

[0101] See also Figure 7 , Figure 7 FIG. 1 is a film layer diagram of the first gate layer 125 in the display panel 100 of the present application.

[0102] In this embodiment, the first gate layer 125 may include a second gate T9G and a third gate T6G, the second gate T9G is arranged on the second active portion T9A; in the second direction Y, the length of the second gate T9G is greater than the length of the third gate T6G, and the area of ​​the second gate T9G is greater than the area of ​​the third gate T6G.

[0103] In this embodiment, since the second output transistor T9 is used to output the first gate drive signal and the third output transistor T6 is used to output the second gate drive signal, and since the load of the first gate drive signal is greater than the load of the second gate drive signal, in order to increase the output load of the first output module 20, this application makes the area of ​​the second gate T9G greater than the area of ​​the third gate T6G.

[0104] See also Figure 7The second gate T9G may include a second trunk gate T9Ga and a plurality of second branch gates T9Gb arranged at intervals, the second trunk gate T9Ga extends along the first direction X, the second branch gates T9Gb extend along the second direction Y, and the plurality of second branch gates T9Gb are electrically connected to the second trunk gate T9Ga at one end facing the signal generating module 10; for example, the second gate T9G may include one second trunk gate T9Ga and four second branch gates T9Gb.

[0105] See also Figure 7 The third gate T6G may include a third trunk gate T6Ga and a plurality of third branch gates T6Gb arranged at intervals, the third trunk gate T6Ga extends along the first direction X, the third branch gates T6Gb extend along the second direction Y, and one end of the plurality of third branch gates T6Gb facing the signal generating module 10 is electrically connected to the third trunk gate T6Ga; for example, the third gate T6G includes one third trunk gate T6Ga and three third branch gates T6Gb.

[0106] In this embodiment, the length and number of the strip branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the second gate T9G and the third gate T6G, the present application sets the second gate T9G and the third gate T6G as a plurality of separately arranged strip branch gates, each strip branch gate bears the load of the corresponding transistor, the strip branch electrode corresponds to the channel of the active part of the corresponding transistor, and the space between two adjacent strip branch gates corresponds to the source and drain of the upper layer. The composite electric field formed by the plurality of separately arranged strip branch gates can improve the driving capability of the transistor.

[0107] In this embodiment, in the first direction X, a distance between two adjacent second branch gates T9Gb and a distance between two adjacent third branch gates T6Gb may be equal.

[0108] See also Figure 7 The first gate layer 125 further includes a fourth gate T7G, which extends along the second direction Y. The fourth gate T7G and a plurality of third branch gates T6Gb in the third gate T6G are parallel and spaced apart.

[0109] In this embodiment, since the third output transistor T6 is connected to the first clock signal line CK, the load it needs to bear is relatively large. Therefore, the present application provides the third gate T6G with three strip-shaped branch gates, while the fourth gate T7G is not connected to the corresponding clock signal line. The load that the fourth output transistor T7 needs to bear is relatively small, so the fourth gate T7G is only provided with one strip-shaped branch gate.

[0110] In this embodiment, in the first direction X, the spacing between the fourth gate T7G and the adjacent third branch gate T6Gb may be equal to the spacing between two adjacent third branch gates T6Gb; that is, the spacing between two adjacent second branch gates T9Gb, the spacing between two adjacent third branch gates T6Gb, and the spacing between the fourth gate T7G and the adjacent third branch gate T6Gb are all equal, that is, the spacing between the strip-shaped branch electrodes is equal, which reduces the difficulty of patterning.

[0111] See also Figure 7 The first gate layer 125 further includes a first electrode plate C1a, and a plurality of third branch gates T6Gb are connected to the first electrode plate C1a at ends away from the signal generating module 10. For example, the first electrode plate C1a is connected to three third branch gates T6Gb, and the three third branch gates T6Gb transmit voltage signals to different locations on the first electrode plate C1a, so that any area of ​​the first electrode plate C1a can simultaneously receive the voltage signals transmitted by the three third branch gates T6Gb.

[0112] See also Figure 7 In the second direction Y, the width of the first electrode plate C1a is greater than the width of the third main gate T6Ga. Since the capacitance of the storage capacitor is positively correlated with the facing panel of the electrode plate in the storage capacitor, the present application can make the width of the first electrode plate C1a greater than the width of the third main gate T6Ga within a limited space, thereby increasing the area of ​​the first electrode plate C1a, thereby increasing the facing area between the two electrode plates and increasing the capacitance of the first storage capacitor C1.

[0113] See also Figure 7 The first gate layer 125 also includes a gate T2G of the pull-up transistor T2, a gate T3G of the first inverting transistor T3, a gate T4G of the first feedback transistor T4, a gate T5G of the second feedback transistor T5, a gate T8G of the second filter transistor T8, a gate T11G of the first filter transistor T11, a gate T12G of the second stage pass transistor T12, and a third plate C2a of the second storage capacitor C2.

[0114] In this embodiment, the gate T2G of the pull-up transistor T2, the gate T3G of the first inverter transistor T3, the gate T11G of the first filter transistor T11, the gate T12G of the second-stage pass transistor T12, and the third plate C2a of the second storage capacitor C2 extend along the second direction Y. The gate T12G of the second-stage pass transistor T12 is disposed near the first output module 20. The gate T3G of the first inverter transistor T3, the gate T2G of the pull-up transistor T2, and the gate T11G of the first filter transistor T11 are sequentially arranged along the first direction X in a central region of the signal generation module 10. The gate T12G of the second-stage pass transistor T12 and the third plate C2a of the second storage capacitor C2 are aligned on the same straight line, and the gate T11G of the first filter transistor T11 is directly connected to the third plate C2a of the second storage capacitor C2.

[0115] In this embodiment, the gate T4G of the first feedback transistor T4, the gate T5G of the second feedback transistor T5, and the gate T8G of the second filtering transistor T8 extend along the first direction X and are disposed proximate to the second output module 30. The gate T4G of the first feedback transistor T4 and the gate T5G of the second feedback transistor T5 are disposed in parallel along the second direction Y, and the gate T4G of the first feedback transistor T4 is disposed away from the fourth gate T7G. The gate T5G of the second feedback transistor T5 is disposed proximate to the fourth gate T7G. The gate T5G of the second feedback transistor T5 and the gate T8G of the second filtering transistor T8 are arranged along the first direction X, and the gate T5G of the second feedback transistor T5 is directly connected to the extension of the fourth gate T7G of the fourth output transistor T7 in the second direction Y.

[0116] In this embodiment, the first gate layer 125 also includes a first gate T1G of the second inverting transistor T1, a first gate T131G of the first-stage pass transistor T13, and a first gate T14G of the regulating transistor T14; the first gate T1G of the second inverting transistor T1 and the first gate T13G of the first-stage pass transistor T13 extend along the second direction Y, the first gate T1G of the second inverting transistor T1 and the gate T3G of the first inverting transistor T3 are shared, the first gate T13G of the first-stage pass transistor T13 and the gate T12G of the second-stage pass transistor T12 are shared, and the first gate T14G of the regulating transistor T14 extends along the first direction X.

[0117] See also Figure 8 , Figure 8 FIG. 1 is a film layer diagram of the second gate layer 127 in the display panel 100 of the present application.

[0118] In this embodiment, the second gate layer 127 includes a second plate C1b of the first storage capacitor C1. The first plate C1a and the second plate C1b are arranged opposite and parallel to each other, and the orthographic projection of the first plate C1a on the second plate C1b is located within the second plate C1b. Since the capacitance of the storage capacitor is positively correlated with the facing surface of the plates in the storage capacitor, the present application can, within a limited space, ensure that the orthographic projection of the first plate C1a on the second plate C1b is located within the second plate C1b, i.e., the area of ​​the first plate C1a is less than or equal to the area of ​​the second plate C1b. In this embodiment, the area of ​​the first plate C1a is less than the area of ​​the second plate C1b, i.e., the area of ​​the second plate C1b is increased as much as possible to increase the facing area between the two plates, thereby increasing the capacitance of the first storage capacitor C1 and improving the output stability of the first signal output terminal Nout.

[0119] In this embodiment, the second gate layer 127 further includes a fourth plate C2 b of the second storage capacitor C2 , and the fourth plate C2 b of the second storage capacitor C2 extends along the second direction Y.

[0120] See also Figure 9 , Figure 9 This is a diagram of the stacked film layers of the first gate layer 125 and the second gate layer 127 in the display panel 100 of the present application.

[0121] In this embodiment, the orthographic projection of the third plate C2a on the fourth plate C2b is located within the fourth plate C2b, that is, the area of ​​the third plate C2a is less than or equal to the area of ​​the fourth plate C2b. In this embodiment, the area of ​​the third plate C2a is smaller than the area of ​​the fourth plate C2b, that is, the area of ​​the fourth plate C2b is increased as much as possible to increase the facing area between the two plates, increase the capacitance of the second storage capacitor C2, and improve the stability of the voltage at the fifth node W.

[0122] In this embodiment, the capacitance of the second storage capacitor C2 needs to be greater than 50F.

[0123] In this embodiment, the area of ​​the first plate C1a is greater than the area of ​​the third plate C2a, and the area of ​​the second plate is greater than the area of ​​the fourth plate C2b. The ratio of the capacitance of the first storage capacitor C1 to the capacitance of the second storage capacitor C2 is greater than 2. Since the first plate C1a of the first storage capacitor C1 is connected to the third gate T6G of the third output transistor T6, the second plate C1b of the first storage capacitor C1 is connected to the third drain T6D of the third output transistor T6, and the third source T6S of the third output transistor T6 is connected to the first clock signal line CK, the output signal of the clock signal line will flip at different times, which will affect the stability of the output signal of the second signal output terminal Pout connected to the third drain T6D of the third output transistor T6. Therefore, the present application ensures the output stability of the first signal output terminal Nout by increasing the capacitance of the first storage capacitor C1.

[0124] exist Figure 8 In the structure of FIG. 1 , the second gate layer 127 further includes a second source electrode T9S, a second drain electrode T9D, a third source electrode T6S, a third drain electrode T6D, a fourth source electrode T7S, and a fourth drain electrode T7D.

[0125] In this embodiment, the second drain T9D includes a plurality of second branch drains T9Db spaced apart and arranged in parallel, and the second source T9S includes a plurality of second branch sources T9Sb spaced apart and arranged in parallel. The second branch drains T9Db and the second branch sources T9Sb extend along the second direction Y.

[0126] In this embodiment, in the top view direction of the display panel 100, two second branch drains T9Db on both sides of the plurality of second branch drains T9Db are arranged on both sides of the second gate T9G, and at least one second branch drain T9Db on the inner side of the plurality of second branch drains T9Db and the plurality of second branch sources T9Sb are arranged between the plurality of second branch gates T9Gb; for example Figure 8 In the structure, the second source T9S includes two second branch source electrodes T9Sb, the second drain T9D includes three second branch drain electrodes T9Db, the two second branch source electrodes T9Sb and the three second branch drain electrodes T9Db are arranged at intervals in the first direction X, that is, the two second branch source electrodes T9Sb can be arranged between two adjacent second branch drain electrodes T9Db; at the same time, the outermost two second branch drain electrodes T9Db of the three second branch drain electrodes T9Db are arranged on both sides of the second gate electrode T9G, and one second branch drain electrode T9Db and two second branch source electrodes T9Sb are arranged between multiple second branch gate electrodes T9Gb.

[0127] See also Figure 8The third source T6S may include a third main source T6Sa and two third branch source electrodes T6Sb arranged in parallel and spaced apart, wherein one end of the two third branch source electrodes T6Sb close to the signal generating module 10 is connected to the third main source T6Sa, and the third drain T6D includes a third branch drain T6Db, wherein one end of the third branch drain T6Db away from the signal generating module 10 is connected to the second plate C1b of the first storage capacitor C1, and the two third branch source electrodes T6Sb and the third branch drain electrodes T6Db are alternately arranged in the first direction X.

[0128] In this embodiment, the fourth source T7S and the fourth drain T7D extend along the second direction Y. The fourth source T7S is disposed close to the third branch source T6DS, and the fourth drain T7D is disposed on a side of the fourth source T7S away from the third branch source T6DS.

[0129] See also Figure 10 , Figure 10 FIG. 1 is a film layer diagram of the third gate layer 131 in the display panel 100 of the present application.

[0130] In this embodiment, the third gate layer 131 includes a first gate T10G disposed on the first active portion T10A. The first gate T10G includes a first main gate T10Ga and a plurality of first branch gates T10Gb connected to the first main gate T10Ga. The first main gate T10Ga extends along a first direction X, and the plurality of first branch gates T10Gb extend along a second direction Y. The first main gate T10Ga is disposed on a side of the first output module 20 close to the signal output module 10. For example, the first gate T10G may include one first main gate T10Ga and four first branch gates T10Gb.

[0131] In this embodiment, since the first branch gate T10Gb is required as a shielding layer for ion doping the first active portion T10A, the length of the channel in the first active portion T10A in the first direction X is equal to the length of the first branch gate T10Gb in the first gate T10G in the first direction X.

[0132] In this embodiment, the orthographic projection of the first main gate T10Ga on the second main gate T9Ga coincides with the second main gate T9Ga, and the orthographic projection of the first branch gate T10Gb on the second branch gate T9Gb is located within the second branch gate T9Gb. That is, to ensure that external light enters the first active portion T10A, the present application can make the width of the lower branch gate greater than the width of the upper branch gate, the spacing between two adjacent first branch gates T10Gb can be smaller than the spacing between two adjacent second branch gates T9Gb in the second output transistor T9, and the spacing between two adjacent second branch gates T9Gb can be smaller than the spacing between two adjacent first branch gates T10Gb. That is, in the first direction, the width of the first branch gate is smaller than the width of the second branch gate.

[0133] In this embodiment, since the length of the first output transistor T10 in the second direction Y is equal to the length of the second output transistor T9 in the second direction Y, the length of the first branch gate and the length of the second branch gate can be equal in the second direction.

[0134] See also Figure 11 , Figure 11 FIG. 1 is a diagram showing the superimposed film layers of the first gate layer 125 and the third gate layer 131 in the display panel 100 of the present application.

[0135] Since the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are all metal oxide semiconductor transistors, to improve the driving capabilities of the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14, the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 can all be dual-gate transistors. That is, the third gate layer 131 can further include a second gate T1H of the second inverter transistor T1, a second gate T13H of the first-stage pass transistor T13, and a second gate T14H of the regulating transistor T14. The second gate T1H of the second inverter transistor T1 and the second gate T13H of the first-stage pass transistor T13 extend along the second direction Y, and the second gate T14H of the regulating transistor T14 extends along the first direction X.

[0136] In this embodiment, to prevent external light from entering the active portions of the second inverter transistor T1, the first-stage pass transistor T13, and the regulating transistor T14, the second gate T1H of the second inverter transistor T1 is orthogonally projected onto and within the corresponding first gate T1G, the second gate T13H of the first-stage pass transistor T13 is orthogonally projected onto and within the corresponding first gate T13G, and the second gate T14H of the regulating transistor T14 is orthogonally projected onto and within the corresponding first gate T14G. The area of ​​the second gate T1H of the second inverter transistor T1 is smaller than the area of ​​the corresponding first gate T1G, the area of ​​the second gate T13H of the first-stage pass transistor T13 is smaller than the area of ​​the corresponding first gate T13G, and the area of ​​the second gate T14H of the regulating transistor T14 is smaller than the area of ​​the corresponding first gate T14G.

[0137] See also Figure 12 and Figure 13 , Figure 12 This is a film layer diagram of the first active layer 123 in the display panel 100 of this application. Figure 13 This is a film layer diagram of the first gate layer 125 , the third gate layer 131 , the first active layer 123 and the second active layer 129 in the display panel 100 of the present application.

[0138] In this embodiment, the array driving layer 120 further includes a first active layer 123 disposed between the first gate layer 125 and the base substrate 110, wherein the first active layer 123 includes a silicon-containing semiconductor; the first active layer 123 includes a second active portion T9A and a third active portion T6A, wherein the second active portion T9A overlaps with a plurality of second branch gates T9Gb, and the third active portion T6A overlaps with a plurality of third branch gates T6Gb.

[0139] In this embodiment, the second output transistor T9 and the third output transistor T6 are top-gate transistors. The second gate T9G can serve as a shielding layer for the second active portion T9A to perform ion doping on the second active portion T9A. The third gate T6G can serve as a shielding layer for the third active portion T6A to perform ion doping on the third active portion T6A. Therefore, the portion of the active portion that overlaps with the corresponding branch gate is the channel, and the portion of the active portion that does not overlap with the corresponding branch gate is the source connection portion and the drain connection portion on both sides of the channel. For example, Figure 13 In the structure, the second active portion T9A overlaps with four second branch gates T9Gb, the third active portion T6A overlaps with three third branch gates T6Gb, the second active portion T9A has four second channels, and the third active portion T6A has three third channels.

[0140] In this embodiment, since the second branch gate T9Gb and the third branch gate T6Gb are sufficiently long in the second direction Y, the dimensions of the second active portion T9A and the third active portion T6A in the second direction Y are increased as much as possible to increase the width of the channel in the active portion. However, when the silicon-containing semiconductor is too large in the second direction Y, static electricity will concentrate in the active portion, potentially damaging the active portion. Therefore, in this application, the second active portion T9A and the third active portion T6A may be configured as two separate sub-active portions.

[0141] See also Figure 12 and Figure 13 The second active portion T9A may include two second sub-active portions T9Aa spaced apart from each other, and the third active portion T6A may include two third sub-active portions T6Aa spaced apart from each other, with the second sub-active portion T9Aa and the third sub-active portion T6Aa extending along the first direction X. The two separately disposed second sub-active portions T9Aa and the two separately disposed third sub-active portions T6Aa reduce the dimensions of the second active portion T9A and the third active portion T6A in the second direction, thereby avoiding the technical problem of static electricity concentration in the active portions.

[0142] In this embodiment, the width of the second sub-active portion T9Aa is greater than the width of the third sub-active portion T6Aa in the second direction Y. Since the output load of the second output transistor T9 is greater than the output load of the third output transistor T6, the present application increases the width of the second sub-active portion T9Aa to increase the second output load.

[0143] It should be noted that the width of the second sub-active portion T9Aa and the width of the third sub-active portion T6Aa are the width dimensions of the corresponding sub-active portions in the second direction Y.

[0144] See also Figure 12 and Figure 13 The first active layer 123 also includes a fourth active portion T7A, the fourth active portion T7A includes two fourth sub-active portions T7Aa arranged at intervals, the two fourth sub-active portions T7Aa overlap with the fourth gate T7G, and the fourth sub-active portion T7Aa is connected to the corresponding third sub-active portion T6Aa; for example, one fourth active portion T7A overlaps with one fourth gate T7G, and the fourth active portion T7A has one fourth channel.

[0145] In this embodiment, in the second direction Y, the width of the fourth sub-active portion T7Aa may be equal to the width of the third sub-active portion T6Aa.

[0146] In this embodiment, in order to simplify the process, the pattern of the third active part T6A can be connected to the pattern of the fourth active part T7A, which increases the pattern area of ​​the active part in the second output module 30, reduces the film forming accuracy of the active part in this area, and simplifies the film forming process.

[0147] exist Figure 13 In the structure, the first active layer 123 also includes an active portion T2A of the pull-up transistor T2, an active portion T3A of the first inverting transistor T3, an active portion T4A of the first feedback transistor T4, an active portion T5A of the second feedback transistor T5, an active portion T8A of the second filter transistor T8, an active portion T11A of the first filter transistor T11, and an active portion T12A of the second-stage pass transistor T12. The active portions of the pull-up transistor T2, the first inverting transistor T3, the first feedback transistor T4, the second feedback transistor T5, the second filter transistor T8, the first filter transistor T11, and the second-stage pass transistor T12 are vertically arranged with the gates of the corresponding transistors and overlap with the gates of the corresponding transistors. The overlap is a channel of the corresponding active portion.

[0148] See also Figure 14 , Figure 14 FIG. 1 is a film layer diagram of the second active layer 129 in the display panel 100 of the present application.

[0149] In this embodiment, the array driving layer 120 further includes a second active layer 129 disposed between the third gate layer 131 and the second gate layer 127. The second active layer 129 includes a metal oxide semiconductor. The second active layer 129 includes a first active portion T10A. The first active portion T10A includes two first sub-active portions T10Aa spaced apart from each other. The first sub-active portion T10Aa extends along the first direction X. The two first sub-active portions T10Aa overlap with a plurality of first branch gates T10Gb.

[0150] In this embodiment, the portion of the first active portion T10A that overlaps with the plurality of first branch gates T10Gb is the first channel of the first active portion T10A, and the portion of the first active portion T10A that does not overlap with the plurality of first branch gates T10Gb is the source connection portion and the drain connection portion on both sides of the first channel; for example Figure 13 and Figure 14 In the structure, the first active portion T10A and the four first branch gates T10Gb overlap, and the first active portion T10A has four first channels.

[0151] In this embodiment, since the first output transistor T10 is a metal oxide semiconductor transistor, which has the advantage of low leakage current but relatively low mobility, in order to improve the mobility of the first output transistor T10, the width of the channel in the first active portion T10A needs to be increased, which is equivalent to the size of the first sub-active portion T10Aa in the second direction Y. Since the length of the first output transistor T10 in the second direction Y is equal to the length of the second output transistor T9 in the second direction Y, in order to maximize the channel width, the length of the first active portion T10A and the length of the second active portion T9A in this application can be equal.

[0152] In this embodiment, since the first channel is arranged above the second channel, and the first channel corresponds to the first branch gate in the first gate T10G, the second channel corresponds to the second branch gate T9Gb in the second gate T9G, and the line width of the first branch gate T10Gb is smaller than the line width of the second branch gate T9Gb, the length of the first channel of the present application can be smaller than the length of the second channel.

[0153] In addition, when the width of the first active portion T10A in the second direction Y is too large, static electricity concentration will occur in the first active portion T10A, which may cause the first active portion T10A to be damaged by static electricity. Therefore, the present application can set the first active portion T10A into two separately set first sub-active portions T10Aa.

[0154] See also Figure 13 and Figure 14 The second active layer 129 also includes an active portion T1A of the second inverting transistor T1, an active portion T13A of the first-stage pass transistor T13, and an active portion T14A of the regulating transistor T14. The active portions of the second inverting transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are vertically arranged with respect to the gates of the corresponding transistors and overlap with the gates of the corresponding transistors. The overlap is a channel of the corresponding active portion. At the same time, in order to improve the mobility of the metal oxide semiconductor transistor, in the signal generating module 10, the channel widths of the active portions of the second inverting transistor T1, the first-stage pass transistor T13, and the regulating transistor T14 are all greater than the channel widths of the active portions of the pull-up transistor T2, the first inverting transistor T3, the first feedback transistor T4, the second feedback transistor T5, the second filter transistor T8, the first filter transistor T11, and the second-stage pass transistor T12.

[0155] See also Figure 15 , Figure 15 FIG. 1 is a film layer diagram of the first source / drain electrode layer 133 in the display panel 100 of the present application.

[0156] In this embodiment, the array driving layer 120 further includes a first source-drain layer 133 disposed on a side of the third gate layer 131 away from the second gate layer 127 . The first source-drain layer 133 includes a first source electrode T10S and a first drain electrode T10D.

[0157] In this embodiment, the first source T10S includes a first main source T10Sa and a plurality of first branch sources T10Sb spaced apart and arranged in parallel. The first main source T10Sa is located on a side of the first output module 20 close to the display unit 200. The first drain T10D includes a plurality of first branch drains T10Db. The first main source T10Sa extends along a first direction X, and the first branch sources T10Sb extend along a second direction Y. The plurality of first branch sources T10Sb are connected to the first main source T10Sa on a side away from the signal generating module 10. The plurality of first branch drains T10Db extend along the second direction Y, and the plurality of first branch drains T10Db are arranged between the plurality of first branch sources T10Sb.

[0158] In this embodiment, in the top view direction of the display panel 100, two first branch source electrodes T10Sb on both sides of the plurality of first branch source electrodes T10Sb are disposed on both sides of the first gate electrode T10G, and at least one first branch source electrode T10Sb on the inner side of the plurality of first branch source electrodes T10Sb and the plurality of first branch drain electrodes T10Db are disposed between the plurality of first branch gate electrodes T10Gb; for example Figure 15 In the structure, the first source T10S includes one first main source T10Sa and three first branch sources T10Sb, the first drain T10D includes two first branch drains T10Db, the three first branch sources T10Sb and the two first branch drains T10Db are arranged at intervals in the first direction X, that is, the two first branch drains T10Db can be arranged between two adjacent first branch sources T10Sb; at the same time, the outermost two first branch sources T10Sb of the three first branch sources T10Sb are arranged on both sides of the first gate T10G, and one first branch source T10Sb and the two first branch drains T10Db are arranged between multiple first branch gates T10Gb.

[0159] See also Figure 16 , Figure 16 This is a film layer diagram of the second gate layer 127 and the first source and drain layer 133 in the display panel 100 of this application. Figure 17 , Figure 17 This is a layer diagram of the second gate layer 127 , the first active layer 123 , the second active layer 129 and the first source and drain layer 133 in the display panel 100 of the present application.

[0160] In this embodiment, the orthographic projection of the first branch source T10Sb on the second branch drain T9Db coincides with the second branch drain T9Db, the orthographic projection of the second branch source T9Sb on the first branch drain T10Db coincides with the first branch drain T10Db, and the first branch source T10Sb is electrically connected to the second branch drain T9Db through at least one connection hole; for example, three first branch sources T10Sb coincide with three second branch drains T9Db, and two second branch sources T9Sb coincide with two first branch drains T10Db.

[0161] In this embodiment, the lengths of the first branch source T10Sb and the second branch drain T9Db in the second direction Y may be equal, and the lengths of the second branch source T9Sb and the first branch drain T10Db in the second direction Y may be equal.

[0162] In this embodiment, the first branch source electrode T10Sb and the first main source electrode T10Sa have a plurality of overlapping portions 180, and the orthographic projection of the connection hole HL0 on the first source electrode T10S is located within the overlapping portions 180. Figure 16 In the embodiment, the first branch source electrode T10Sb and the first main source electrode have three overlapping portions 180, and the three overlapping portions 180 are electrically connected to the second branch drain electrode T9Db in the lower layer through corresponding connection holes HL0. The connection holes HL0 penetrate the first inter-insulating layer 132, the fourth gate insulating layer 130, and the third gate insulating layer 128.

[0163] See also Figure 8 、 Figure 16 and Figure 17 The second gate layer 127 also includes a source T2S and a drain T2D of the pull-up transistor T2, a source T3S and a drain T3D of the first inverting transistor T3, a source T4S and a drain of the first feedback transistor T4, a source and a drain T5D of the second feedback transistor T5, a source T8S and a drain T8D of the second filter transistor T8, a source T11S and a drain T11D of the first filter transistor T11, and a source T12S and a drain T12D of the second stage pass transistor T12. The sources and drains of the above transistors are arranged on both sides of the corresponding active portion.

[0164] Figures 15 to 17 The first source-drain layer 133 also includes a source T1S and a drain T1D of the second inverting transistor T1, a source T13S and a drain T13D of the first-stage pass transistor T13, and a source T14S and a drain T14D of the regulating transistor T14. The sources and drains of the above transistors are arranged on both sides of the corresponding active portions.

[0165] Since the first gate T10G in the first output transistor T10 and the second gate T9G of the second output transistor T9 are electrically connected, but the first gate T10G is on the third gate layer 131 and the second gate T9G is on the first gate layer 125; therefore, in order to electrically connect the first gate T10G and the second gate T9G, the first output transistor T10 further includes a first protrusion 191 connected to the first trunk gate T10Ga, and the first protrusion 191 extends toward the side close to the signal generating module 10, and the second output transistor T9 further includes a second protrusion 192 connected to the second trunk gate T9Ga, and the second protrusion 192 extends toward the side close to the signal generating module 10.

[0166] See also Figure 8 、 Figure 16 and Figure 17 The second gate layer includes a first connecting segment 151, the first connecting segment 151 is located between the drain T12D and the second source of the second-stage pass transistor T12, the first end of the first connecting segment 151 overlaps with the second protrusion 192, and the first end of the first connecting segment 151 can pass through the first via HL1 and be electrically connected to the second protrusion 192; see Figure 15 and Figure 16 The first source-drain layer includes a first extension segment 161, a first end of the first extension segment 161 is electrically connected to the source T14S of the regulating transistor T14, a second end of the first extension segment 161 is connected to the second end of the first connecting segment 151, and an area between the first end and the second end of the first extension segment 161 overlaps with the first protrusion 191. The second end of the first extension segment 161 can be electrically connected to the second end of the first connecting segment 151 through a second via HL2, and the area between the first end and the second end of the first extension segment 161 can be electrically connected to the first protrusion 191 through a third via HL3.

[0167] In this embodiment, the first via hole HL1 penetrates the second gate insulating layer 126 , the second via hole HL2 penetrates the first interinsulating layer 132 , the fourth gate insulating layer 130 , and the third gate insulating layer 128 , and the third via hole HL3 penetrates the first interinsulating layer 132 .

[0168] In this embodiment, since the first gate T10G and the second gate T9G are electrically connected and disposed between the first active portion T10A, when the first gate T10G is turned on, the second gate T9G is also turned on at the same time, so that the first output transistor T10 is a dual-gate transistor, thereby improving the conduction rate of the first output transistor T10.

[0169] In the display panel 100 of the present application, multiple first branch source electrodes T10Sb include a first bottom electrode T10Sc close to the next-stage driving unit 310, and multiple second branch drain electrodes T9Db include a second bottom electrode T9Dc close to the next-stage driving unit 310. The first bottom electrode T10Sc and the second bottom electrode T9Dc are both electrically connected to the first signal output terminal Nout.

[0170] See also Figure 15 The first source T10S includes three first branch source electrodes T10Sb, of which the first branch source electrode T10Sb close to the next-stage driving unit 310 is the first bottom electrode T10Sc. The second drain T9D includes three second branch drain electrodes T9Db, of which the second branch drain electrode T9Db close to the next-stage driving unit 310 is the second bottom electrode T9Dc. The first bottom electrode T10Sc and the second bottom electrode T9Dc are electrically connected and overlap with each other. Secondly, one end of the first bottom electrode T10Sc or / and the second bottom electrode T9Dc away from the signal generating module 10 is electrically connected to the first signal output terminal Nout to transmit the first gate driving signal to the display unit 200.

[0171] See also Figure 16 and Figure 17 The first source-drain layer further includes a second extension segment 162 extending along the second direction Y, part of the second extension segment 162 is located in the driving unit 310 of the current stage, and part of the second extension segment 162 is located in the driving unit 310 of the next stage; see Figure 8 The second gate layer 127 further includes an output wire 170 extending along the second direction Y. The output wire 170 is arranged on a side of the second bottom electrode T9Sc in the second source T9S away from the second branch drain T9Db. The second plate C1b of the first storage capacitor C1 is electrically connected to the first end of the second extension segment 162. The second end of the second extension segment 162 is connected to the first end of the output wire 170 through the fourth via HL4. The second end of the output wire 170 is connected to the second signal output terminal Pout.

[0172] In this embodiment, the fourth via hole HL4 passes through the first inter-insulating layer 132 , the fourth gate insulating layer 130 , the third gate insulating layer 128 , and the second gate insulating layer 126 . The second signal output terminal Pout is used to output a second gate driving signal.

[0173] See also Figure 16 and Figure 17 The first source-drain layer 133 further includes a start signal line STV, a first end of the start signal line STV is connected to the first bottom electrode T10Sc in the previous stage driving unit 310; Figure 10In the structure, the third gate layer includes a third connecting segment 153, which extends from the N-th stage driving unit 310 to the N-1-th stage driving unit 310. The second end of the start signal line STV is connected to the first end of the third connecting segment 153. The first gate of the first-stage pass transistor T13 and the gate of the second-stage pass transistor T12 are shared. Part of the third connecting segment 153 overlaps with and is electrically connected to the first gate of the first-stage pass transistor T13 and the gate of the second-stage pass transistor T12. At the same time, the overlapping portion of the third connecting segment 153 serves as the second gate of the first-stage pass transistor T13.

[0174] Secondly, the second gate layer 127 also includes a fourth connecting segment 154, the first end of the fourth connecting segment 154 is connected to the gate of the second filter transistor T8, the second end of the fourth connecting segment 154 is connected to the first end of the third connecting segment 153, and the second end of the third connecting segment 153 is electrically connected to the start signal line STV in the N-1-th level driving unit 310. Since the signal of the start signal line STV in the N-1-th level driving unit 310 comes from the first signal transmission segment of the N-2-th level driving unit 310, the signal of the gate of the second filter transistor T8 of the present application comes from the first signal output end Nout of the N-2-th level.

[0175] See also Figure 18 , Figure 18 This is a film layer diagram of the second source and drain electrode layer 135 in the display panel 100 of this application. Figure 19 , Figure 19 1 is a film layer diagram of the second gate layer 125 , the first source-drain electrode layer 133 , and the second source-drain electrode layer 135 in the display panel 100 of the present application.

[0176] In this embodiment, the array driving layer 120 further includes a second source-drain layer 135 disposed on a side of the first source-drain layer 133 away from the base substrate 110. The second source-drain layer 135 includes a first low-potential line Nvgl1. The first low-potential line Nvgl1 overlaps with the plurality of first branched source electrodes T10Sb and the plurality of first branched drain electrodes T10Db in each driving unit 310. The first low-potential line Nvgl1 is electrically connected to the plurality of first branched drain electrodes T10Db in each driving unit 310 through a sixth via HL6. For example, The first low potential line Nvgl1 is electrically connected to the two first branch drains T10Db in each stage of the driving unit 310, and the first low potential line Nvgl1 is electrically connected to the first branch drain T10Db through the two sixth vias HL6, and the sixth via HL6 passes through the second inter-insulating layer 134; at the same time, since the drain T14D of the regulating transistor T14 is electrically connected to the first branch drain T10Db, the drain T14D of the regulating transistor T14 also receives the low-level signal transmitted by the first low potential line Nvgl1.

[0177] See also Figure 20 , Figure 20 FIG. 1 is a diagram of the superimposed film layers of the first active layer 123 , the second active layer 129 and the second source / drain layer 135 in the display panel 100 of the present application.

[0178] In this embodiment, the second source-drain layer 135 also includes a first high potential line Pvgh1, the first high potential line Pvgh1 and the first low potential line Nvgl1 are arranged opposite to and in parallel, the first high potential line Pvgh1 overlaps with the third sub-active portion T6Aa and the fourth sub-active portion T7Aa on the side close to the signal generating module 10, and the first high potential line Pvgh1 is electrically connected to the fourth drain T7D through the seventh via HL7.

[0179] In this embodiment, in the second direction Y, the width of the first low potential line Nvgl1 is greater than the width of the first high potential line Pvgh1 .

[0180] See also Figures 18 to 20 The second source-drain layer 135 may further include a second low potential line Pvgl and a second high potential line Pvgh2 overlapping with the signal generating module 10, the second low potential line Pvgl, the second high potential line Pvgh2, and the first high potential line Pvgh1 are parallel and spaced apart, and the second low potential line Pvgl is arranged between the first high potential line Pvgh1 and the second high potential line Pvgh2; the widths of the second high potential line Pvgh2, the first high potential line Pvgh1 and the second low potential line Pvgl are all equal.

[0181] In this embodiment, since the second source electrode T9S of the second output transistor T9 is connected to the high level source, but the region where the second output transistor T9 is located is provided with the first low potential line Nvgl1, the present application can introduce the signal of the first high potential line Pvgh1 into the second source electrode T9S; Figure 8 The second gate layer 127 further includes a second connecting segment 152 disposed on a side of the second output transistor T9 near the signal generation module 10. The first end of the second connecting segment 152 is electrically connected to the drain electrode T12D of the second-stage pass transistor T12, and the second end of the second connecting segment 152 is electrically connected to the second branch source electrode T9Sb. Specifically, the present application removes the high-potential line that originally overlaps with the second output transistor T9 and directs the signal of the high-potential line connected to the second-stage pass transistor T12 into the second output transistor T9. While maintaining the same circuit structure, this reduces the space occupied by the gate drive circuit 300 within the frame, achieving a narrow-frame design for the display panel 100.

[0182] See also Figures 18 to 20The second source and drain layer 135 also includes a first clock signal line CK and a second clock signal line XCK that overlap with the signal generating module 10. The first clock signal line CK and the second clock signal line XCK are parallel to and spaced apart from the first high potential line Pvgh1. The first clock signal line CK and the second clock signal line XCK are arranged between the first high potential line Pvgh1 and the second low potential line Pvgl.

[0183] In this embodiment, in the display panel 100 of the present application, the gate driving circuit 300 includes a plurality of repeating units, each repeating unit includes at least four driving units 310. Hereinafter, four driving units 310 are taken as one repeating unit as an example, and the plurality of repeating units are arranged in the first direction X.

[0184] See also Figures 15 to 20 The repeating unit may include a first GOA unit 311, a second GOA unit 312, a third GOA unit 313, and a fourth GOA unit 314 arranged in sequence along the first direction X. The display panel 100 may include a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4 arranged along the second direction Y, and every two clock signal lines are connected to one driving unit 310.

[0185] In this embodiment, the first clock signal line PCK1, the second clock signal line PCK2 and the first GOA unit 311 are connected, the first clock signal line PCK1 is the first clock signal line CK of the first GOA unit 311, and the second clock signal line PCK2 is the second clock signal line XCK of the first GOA unit 311, that is, the first clock signal line PCK1 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the second clock signal line PCK2 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0186] In this embodiment, the second clock signal line PCK2, the third clock signal line PCK3 and the second GOA unit 312 are connected, the second clock signal line PCK2 is the first clock signal line CK of the first GOA unit 311, and the third clock signal line PCK3 is the second clock signal line XCK of the first GOA unit 311, that is, the second clock signal line PCK2 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the third clock signal line PCK3 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0187] In this embodiment, the third clock signal line PCK3, the fourth clock signal line PCK4 and the third GOA unit 313 are connected, the third clock signal line PCK3 is the first clock signal line CK of the first GOA unit 311, and the fourth clock signal line PCK4 is the second clock signal line XCK of the first GOA unit 311, that is, the third clock signal line PCK3 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0188] In this embodiment, the fourth clock signal line PCK4, the first clock signal line PCK1 and the fourth GOA unit 314 are connected, the fourth clock signal line PCK4 is the first clock signal line CK of the first GOA unit 311, and the first clock signal line PCK1 is the second clock signal line XCK of the first GOA unit 311, that is, the fourth clock signal line PCK4 is connected to the gate of the third output transistor T6 in the first GOA unit 311, and the fourth clock signal line PCK4 is connected to the gate of the pull-up transistor T2 in the first GOA unit 311.

[0189] See also Figures 15 to 20 The second gate layer 127 in each stage of the driving unit 310 further includes a third extension segment 163 connected to the third source electrode T6S. The third extension segment 163 extends along the second direction Y, and the third extension segment 163 is located in the area where the signal generating module 10 is located. The first clock signal line CK in each stage of the driving unit 310 is electrically connected to the third extension segment 163 through the fifth via HL5.

[0190] In this embodiment, since the third output transistors T6 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313, and the fourth GOA unit 314 are connected to different clock signal lines, in the repeating unit, the lengths of the third extension segments 163 in some driving units 310 in the second direction Y are different, that is, the lengths of the third extension segments 163 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313, and the fourth GOA unit 314 are different; for example, the lengths of the third extension segments 163 in the first GOA unit 311, the second GOA unit 312, and the third GOA unit 313 are equal, and the length of the third extension segment 163 in the fourth GOA unit 314 is longer than that of the other three.

[0191] In this embodiment, in the driving unit 310, since the clock signal line is in the second source-drain layer 135 and the third extension segment 163 is in the second gate layer 127, and there are many film layers in between, in order to avoid the depth of the contact hole being too large, the present application provides a fourth extension segment 164 on the first source-drain layer 133 in each driving unit 310, and the second clock signal line PCK2 is electrically connected to the third extension segment 163 through the fourth extension segment 164.

[0192] See also Figure 15 The first gate layer 125 in each stage of the driving unit 310 further includes a fifth extension segment 165 connected to the gate of the pull-up transistor T2. The fifth extension segment 165 extends along the second direction Y, that is, the fifth extension segment 165 mainly extends toward a side away from the first output module 20.

[0193] Also, see Figure 15 and Figure 16 The first source-drain layer 133 in each stage of the driving unit 310 further includes a sixth extension segment 166, which extends along the second direction Y. The first end of the sixth extension segment 166 is connected to the second clock signal line XCK in the corresponding driving unit 310, and the second end of the sixth extension segment 166 is electrically connected to the fifth extension segment 165.

[0194] exist Figure 7 、 Figure 15 and Figure 16 In the embodiment, the lengths of the sixth extension segment 166 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit 313 gradually decrease, and the length of the sixth extension segment 166 in the fourth GOA unit 314 increases compared with the length of the sixth extension segment 166 in the third GOA unit 313; at the same time, the lengths of the fifth extension segment 165 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit 313 are equal, and the length of the fifth extension segment 165 in the fourth GOA unit 314 is longer than the length of the fifth extension segment 165 in the third GOA unit 313.

[0195] exist Figure 7 、 Figure 15 and Figure 16In the embodiment, since the pull-up transistors T2 in the first GOA unit 311, the second GOA unit 312, the third GOA unit 313 and the fourth GOA unit 314 are connected to different clock signal lines, in one repeating unit, the sum of the lengths of the fifth extension segment 165 and the sixth extension segment 166 in different driving units 310 is different; for example, the sum of the lengths of the fifth extension segment 165 and the sixth extension segment 166 in the first GOA unit 311, the second GOA unit 312 and the third GOA unit gradually decreases, and the sum of the lengths of the fifth extension segment 165 and the sixth extension segment 166 in the fourth GOA unit 314 is greater than the sum of the lengths of the fifth extension segment 165 and the sixth extension segment 166 in the first GOA unit.

[0196] See also Figure 18 and Figure 19 The second source-drain layer 135 includes a plurality of reset signal lines RST arranged at intervals, the plurality of reset signal lines RST overlap with the first buffer unit 210, and the plurality of reset signal lines RST are arranged between the first low potential line Nvgl1 and the second high potential line Pvgh2, a first end of the reset signal line RST is connected to the first branch drain T10Db in the N-10th stage driving unit 310, and a second end of the reset signal line RST is connected to the gate of the first filter transistor T11.

[0197] It should be noted that the source and drain in the above-mentioned transistors of the present application are only distinguished in name, as long as one of them is an input terminal and the other is an output terminal.

[0198] It should be noted that the membrane structure diagram provided in this application is not only applicable to Figure 3 and Figure 5 The circuit structure in is applicable to the present application as long as it has the same module structure as the present application, that is, a module structure that outputs two gate drive signals, Nout and Pout.

[0199] The present application also provides a display terminal including the above-mentioned display panel. The display terminal can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0200] The present application proposes a display panel; the display panel includes a display portion and a gate drive circuit located on one side of the display portion, the gate drive circuit includes N cascaded GOA units, the N GOA units are arranged along a first direction, and each of the GOA units includes a signal generation module, a first output module, and a second output module arranged along a second direction; the first output module is arranged on a side of the signal generation module close to the display portion, and the first output module is used to output a first gate drive signal; the second output module is arranged on a side of the signal generation module away from the display portion, and the second output module is used to output a second gate drive signal, and the first gate drive signal and the second gate drive signal are different; in the second direction, the lengths of the first output module and the second output module are different, the second direction is parallel to the scan line of the display panel, and the first direction is perpendicular to the second direction; the present application arranges two output modules that output different gate drive signals and have different lengths on both sides of the signal generation module, so that the two output modules have sufficient width in the first direction, thereby ensuring the performance of the transistors in the two output modules, avoiding the technical problem of an increase in the border due to stacking the two output modules on the same side, and realizing a narrow border design.

[0201] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0202] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The device comprises a display portion and a gate driving circuit located on one side of the display portion, wherein the gate driving circuit comprises N cascaded driving units, and the N driving units are arranged along a first direction; wherein each of the driving units comprises a signal generating module, a first output module, and a second output module arranged along a second direction; The first output module is provided on a side of the signal generating module close to the display portion, and the first output module is used to output a first gate driving signal; The second output module is provided at a side of the signal generating module away from the display unit, and the second output module is used to output a second gate driving signal, wherein the first gate driving signal and the second gate driving signal are different; In which, the first output module includes a first buffer unit and a second buffer unit, the first buffer unit and the second buffer unit are stacked in a third direction, the third direction is perpendicular to the plane where the first direction and the second direction are located, the second direction is parallel to the scanning line of the display panel, the angle between the first direction and the second direction is greater than 0° and less than or equal to 90°, and N is a positive integer.

2. The display panel according to claim 1, wherein: The first buffer unit includes a first active portion, the second buffer unit includes a second active portion, the first active portion is a metal oxide semiconductor, and the second active portion is a semiconductor containing silicon; The first buffer unit is disposed close to the light-emitting side of the display panel, and the second buffer unit is disposed away from the light-emitting side of the display panel.

3. The display panel according to claim 2, wherein: The first buffer unit includes a first output transistor having the first active portion, and the second buffer unit includes a second output transistor having the second active portion; In the second direction, the length of the first output transistor is equal to the length of the second output transistor.

4. The display panel according to claim 3, wherein: The first active portion includes a first channel, and the second active portion includes a second channel; The length of the first active portion is equal to the length of the second active portion, and the length of the first channel is smaller than the length of the second channel.

5. The display panel according to claim 3, wherein: The first output transistor further includes a first gate disposed on the first active portion, and the second output transistor further includes a second gate disposed on the second active portion; The first gate includes a first main gate and a plurality of first branch gates connected to the first main gate, the second gate includes a second main gate and a plurality of second branch gates connected to the second main gate, the first main gate and the second main gate extend in the first direction, and the first branch gates and the second branch gates extend in the second direction; The orthographic projection of the first main gate on the second main gate coincides with the second main gate, and the orthographic projection of the first branch gate on the second branch gate is located within the second branch gate.

6. The display panel according to claim 5, wherein: In the second direction, the length of the first branch gate is equal to the length of the second branch gate; in the first direction, the width of the first branch gate is smaller than the width of the second branch gate.

7. The display panel according to claim 5, wherein: The first output transistor further includes a first source and a first drain disposed on a side of the first gate away from the first active portion, and the second output transistor further includes a second source and a second drain disposed between the second gate and the first active portion; The first source includes a first main source and a plurality of first branch sources connected to the first main source, the first drain includes a plurality of separately arranged first branch drains, the second source includes a plurality of separately arranged second branch sources, and the second drain includes a plurality of separately arranged second branch drains, the first main source extends in the first direction, and the first branch sources, the first branch drains, the second branch sources, and the second branch drains extend in the second direction; A plurality of first branch sources and a plurality of first branch drains are alternately arranged in the first direction, a plurality of second branch sources and a plurality of second branch drains are alternately arranged in the first direction, the orthographic projection of the first branch source on the second branch drain coincides with the second branch drain, the orthographic projection of the second branch source on the first branch drain coincides with the first branch drain, and the first branch source is electrically connected to the second branch drain through at least one connection hole.

8. The display panel according to claim 7, wherein: The first main source electrode is located on a side of the first output module close to the display portion; The first branch source electrode and the first main source electrode have a plurality of overlapping portions, and the orthographic projection of the connection hole on the first source electrode is located within the overlapping portions.

9. The display panel according to claim 7, wherein: The display panel further includes a first high potential line and a first low potential line disposed on the first source or the first drain, the first high potential line being electrically connected to the first branch drains, and the first low potential line being electrically connected to the second branch sources.

10. The display panel according to any one of claims 1 to 9, characterized in that: The first gate driving signal is a positive pulse signal, and the second gate driving signal is a negative pulse signal; Wherein, within a time interval of one frame, the first output module outputs two positive pulse signals, and the second output module outputs one negative pulse signal.

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