Partition display driving method, display driving circuit and display screen

Abstract

The invention discloses a partition display driving method, a display driving circuit and a display screen, and the method comprises the steps: obtaining the pixel ranges of a first display region and a second display region, and controlling the absolute value of a gate turn-off voltage received by a switching transistor in a pixel driving unit corresponding to the second display region to decrease according to the pixel range of the second display region; according to the pixel range of the first display area, the gate turn-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is controlled to be reduced, so that when the display panel starts the partition refreshing function, differential processing can be performed on the positive voltage and the negative voltage of the gate of the switch transistor; and the purpose of reducing the brightness difference caused by the PBS or the NBS is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of display screens, and in particular to a partition display driving method, a display driving circuit, and a display screen. Background Art

[0002] As people's living standards improve, electronic products play an important role in people's lives. Display panels are important components of electronic products, so the demand for display panels is increasing.

[0003] Nowadays, ordinary display effects can no longer meet people's quality of life, and people's demand for display panels with high refresh rates is increasing. However, the display panel will cause brightness differences in different areas under the condition of zoned refresh. Summary of the invention

[0004] In view of the above problems, the present application provides a partition display driving method, a display driving circuit, and a display screen, aiming to provide a partition refresh solution to solve the problem that different areas of the display panel will have brightness differences under partition refresh conditions.

[0005] A first aspect of an embodiment of the present application provides a partition display driving method, the partition display driving method comprising:

[0006] Acquire the pixel range of the first display area and the second display area;

[0007] Controlling the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area to decrease according to the pixel range of the second display area;

[0008] The gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area.

[0009] In some embodiments, the greater the difference in refresh rate between the first display area and the second display area, the greater the decrease in the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area.

[0010] In some embodiments, a drop amplitude of a gate-on voltage received by a switch transistor in a pixel driving unit corresponding to the first display area is related to a refresh rate difference between the second display area and the first display area.

[0011] In some embodiments, the greater the difference in refresh rate between the first display area and the second display area, the greater the drop in gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area.

[0012] In some embodiments, the partition display driving method further includes:

[0013] Obtaining a difference in refresh rate between the first display area and the second display area;

[0014] The drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is determined according to the difference in refresh rate between the first display area and the second display area.

[0015] In some embodiments, determining the drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area according to the difference between the refresh rates of the first display area and the second display area includes:

[0016] The gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is determined according to the difference in refresh rate between the first display area and the second display area and a preset refresh rate-gate voltage relationship table.

[0017] In some embodiments, determining the drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area according to the difference between the refresh rates of the first display area and the second display area includes:

[0018] The gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is gradually reduced according to the difference in refresh rate between the first display area and the second display area.

[0019] In some embodiments, the partition display driving method further includes:

[0020] The high-level pulse width of the gate pulse signal of the switch transistor in the pixel driving unit corresponding to the first display area is controlled to be reduced.

[0021] A second aspect of the embodiments of the present application further provides a display driving circuit, the display driving circuit comprising a plurality of pixel driving units and a main control circuit, the main control circuit being used to execute the partition display driving method as described in any one of the above embodiments;

[0022] The plurality of pixel driving units are used to respectively drive a plurality of display pixels to light up.

[0023] A third aspect of the embodiments of the present application further provides a display screen, which includes a display driving circuit as described in any one of the above embodiments.

[0024] The beneficial effects of the embodiments of the present application are as follows: by acquiring the pixel range of the first display area and the second display area, the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area is controlled to decrease according to the pixel range of the second display area; the gate turn-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area, so that when the partition refresh function of the display panel is turned on, the gate positive voltage and negative voltage of the switching transistor can be differentiated, thereby achieving the purpose of reducing the brightness difference caused by PBS or NBS.

[0025] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0027] Figure 1 A first schematic diagram of a partition display driving method provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a pixel driving unit provided in an embodiment of the present application;

[0029] Figure 3 A second schematic diagram of the partition display driving method provided in an embodiment of the present application;

[0030] Figure 4 A third schematic diagram of the partition display driving method provided in an embodiment of the present application;

[0031] Figure 5a and Figure 5b Timing diagrams of the first scanning control signal SN1, the second scanning control signal SN2, the first data control signal SP1, the second data control signal SP2, and the dimming control signal EM in the first display area before and after modification;

[0032] Figure 6 A schematic diagram of a display driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0035] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0036] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present application. The phrase "second connection port" at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0038] In the description of the embodiments of the present application, the term "multi-frame" refers to more than two (including two).

[0039] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0040] In the related art, in order to achieve better power consumption benefits and thus extend the use time of electronic products, different refresh frequencies can be set in different areas of the screen. However, when the display screen of the display screen is refreshed in different areas, the refresh rates of each display area are different. Due to the different characteristic offsets of the switching transistors in the pixel driving circuit of the thin film transistor (TFT) device at different refresh rates, different areas have different brightness. For example, the switching transistor performing scan drive in the 120hz state is in a positive bias stress (Positive Bias Stress, PBS) / negative bias stress (Negative Bias Stress, NBS) cycle state, and the switching transistor is in a long-term NBS state at a low refresh rate. In the PBS state, the gate of one of the switching transistors has a positive voltage of about 8V, causing the electrons in the thin film to be attracted close to the interface of the indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) and the gate insulating layer (GI), thereby being captured by the defects at the interface, causing the transfer characteristic curve of the device to move toward the positive value direction of the gate-source voltage (Vgs). In the NBS state, the holes in the film will be attracted by defects near the interface, causing the TFT characteristics to drift in the negative direction of Vgs, resulting in brightness differences under partition refresh.

[0041] In order to solve the above technical problems, the present application embodiment provides a partition display driving method, see Figure 1 As shown, the partition display driving method in this embodiment includes steps S100 to S300.

[0042] In step S100, pixel ranges of the first display area and the second display area are obtained.

[0043] In this embodiment, the second display area represents an area in the display panel that uses a lower refresh rate for display, and the first display area represents an area in the display panel that uses a higher refresh rate for display, and the image refresh rate of the first display area is higher than that of the second display area. When the display panel displays an image, it can display an image with a low refresh rate in some areas according to user needs or image display needs. For example, in an area where only text needs to be displayed, the display refresh rate of the area can be reduced to achieve the purpose of reducing display power consumption.

[0044] In some embodiments, the image refresh rate of the second display area may be less than 30 Hz.

[0045] In some embodiments, the frame refresh rate of the second display area may be 1 Hz.

[0046] In some embodiments, the image refresh rate of the first display area may be greater than 60 Hz.

[0047] In some embodiments, the image refresh rate of the first display area may be 120 Hz.

[0048] In step S200, the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area is controlled to decrease according to the pixel range of the second display area.

[0049] In this embodiment, the display panel includes a plurality of display pixels, and the plurality of display pixels can be arranged in an array, each display pixel is driven by a corresponding pixel driving unit, and the pixel driving unit can generate a pixel driving signal according to the received gate scanning signal, thereby driving the corresponding display pixel to light up, and the plurality of display pixels can display corresponding pictures when driven to light up. Under the condition of low refresh rate, due to the long opening time of the switch transistor in the NBS effect, the stress (stress) degree of the low refresh rate area is higher than that of the high refresh rate area, and the gate voltage of the drive transistor (DTFT) is higher, resulting in a negative bias of the threshold voltage (Vth), weakening the degree of coupling of the switch transistor from PVGL_N (off gate voltage) to PVGH_N (on gate voltage) to the DTFT gate, resulting in the high refresh rate area being brighter, therefore, the absolute value of the gate off voltage received by the switch transistor in the corresponding pixel driving unit can be controlled to decrease according to the pixel range of the second display area, reducing the influence of NBS, thereby achieving the purpose of balancing the brightness of the display areas with different refresh rates.

[0050] In step S300, the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area.

[0051] In the present embodiment, when the partition refresh function of the display panel is turned on, the refresh frequencies of the display images in various areas may be inconsistent. For example, the refresh frequencies of the display images in the upper, middle and lower areas of the display panel are 1 Hz, 120 Hz and 1 Hz respectively. At a refresh rate of 120 Hz, the opening time of the switching transistor is longer, and the PBS effect causes the middle high refresh rate area to have a higher stress level than the upper and lower low refresh rate areas, causing Vth to be positively biased. Therefore, by reducing the gate on-voltage received by the switching transistor in the pixel driving unit, the influence of PBS can be reduced, thereby achieving the purpose of balancing the brightness of the display areas with different refresh rates.

[0052] In some embodiments, see Figure 2As shown, the pixel driving unit includes: a first P-type transistor T1, a second P-type transistor T2, a first switch transistor T3, a second switch transistor T4, a third P-type transistor T5, a fourth P-type transistor T6 and a storage capacitor Cst.

[0053] In this embodiment, the first end of the second P-type transistor T2 is used to receive the display data signal, and the control end of the second P-type transistor T2 is used to receive the first data control signal Data; the control end of the second switching transistor T4 is used to receive the first scanning control signal SN1, and the control end of the first switching transistor T3 is used to receive the second scanning control signal SN2. The second scanning control signal SN2 can be provided by a level conversion circuit, and the partition enable signal can be output to the control end of the first switching transistor T3 as the second scanning control signal SN2 via the output end GOUT of the level conversion circuit, thereby realizing partition refresh control of the pixel driving unit 530.

[0054] The control end of the third P-type transistor T5 and the controller of the fourth P-type transistor T6 are connected together to receive the dimming control signal EM; the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are connected together to receive the second data control signal SP2. The first end of the third P-type transistor T5 and the first end of the storage capacitor Cst are commonly connected to the first power supply terminal ELVDD, the second end of the second P-type transistor T2, the second end of the third P-type transistor T5, and the first end of the first P-type transistor T1 are commonly connected, the second end of the storage capacitor Cst, the control end of the first P-type transistor T1, and the first end of the first switch transistor T3 are commonly connected, the second end of the first switch transistor T3, the first end of the second switch transistor T4, the second end of the first P-type transistor T1, the first end of the fourth P-type transistor T6, and the first end of the eighth switch transistor T8 are commonly connected, the second end of the second switch transistor T4 is connected to the first reference signal terminal Vrefn1, the second end of the fourth P-type transistor T6 and the first end of the seventh switch transistor T7 are commonly connected to the positive electrode of the display diode OLED, the negative electrode of the display diode is connected to the reference ground, the second end of the seventh switch transistor T7 is connected to the second reference signal terminal Vrefn2, and the second end of the eighth switch transistor T8 is connected to the third reference signal terminal Vrefp.

[0055] In this embodiment, in the area with high refresh rate, where the first switch transistor T3 is in the open state for a long time, the PBS effect of the first switch transistor T3 causes the stress level in the area with high refresh rate to be higher than that in the area with low refresh rate, thereby causing the threshold voltage (Vth) of the first switch transistor T3 to be positively biased, weakening the degree of coupling of the first switch transistor T3 from the gate-on voltage (PVGH_N) to the gate-off voltage (PVGL_N) to the DTFT gate, causing the area with high refresh rate to be dark. Therefore, by reducing the gate-on voltage (PVGH_N) of the first switch transistor T3, the influence of PBS can be reduced, thereby achieving the purpose of balancing the brightness of display areas with different refresh rates.

[0056] In this embodiment, in the low refresh rate area, the first switch transistor T3 is in the NBS effect open time for a longer time, resulting in a higher stress level in the low refresh rate area than in the high refresh rate area (the DTFT gate is higher), causing the threshold voltage (Vth) of the first switch transistor T3 to be negatively biased, weakening the degree of coupling of the first switch transistor T3 from the gate turn-off voltage (PVGL_N) to the gate turn-on voltage (PVGH_N) to the DTFT gate (the DTFT gate is lower), resulting in the high refresh rate area being brighter. Therefore, by reducing the gate turn-off voltage (PVGL_N) of the first switch transistor T3, the NBS effect is reduced, thereby achieving the purpose of balancing the brightness of display areas with different refresh rates.

[0057] In some embodiments, the second P-type transistor T2 , the seventh switch transistor T7 , the eighth switch transistor T8 , the third P-type transistor T5 , and the fourth P-type transistor T6 are P-type MOS transistors.

[0058] The first switch transistor T3 and the second switch transistor T4 are N-type MOS transistors.

[0059] In some embodiments, the decrease in the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area is related to the refresh rate difference between the second display area and the first display area.

[0060] In this embodiment, combined with Figure 2As shown, the characteristic offset of the switching transistor (for example, the first switching transistor T3 and the second switching transistor T4) in the pixel driving unit is related to the refresh rate of the display area in which it is located, that is, the PBS / NBS influence of the first switching transistor T3 and the second switching transistor T4 will cause a brightness difference between different refresh rate areas, and the greater the difference in refresh rate, the greater the impact of the brightness difference, and further the greater the impact on the optical visual effect. Therefore, in the case where multiple sub-areas in the display area have different refresh rates, the brightness difference between the second display area and the first display area can be balanced by matching the refresh rate difference between the second display area and the first display area with the decrease in the absolute value of the gate turn-off voltage received by the switching transistor in the pixel driving unit corresponding to the second display area.

[0061] In some embodiments, the greater the difference in refresh rate between the first display area and the second display area, the greater the decrease in the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area.

[0062] In this embodiment, combined with Figure 2 As shown, the characteristic offset of the first switch transistor T3 and the second switch transistor T4 is related to the refresh rate of the display area where they are located, that is, the PBS / NBS of the first switch transistor T3 and the second switch transistor T4 corresponding to different refresh rate areas are different, which will cause brightness differences between different refresh rate areas. The greater the difference in refresh rate, the greater the impact of the brightness difference, and further the greater the impact on the optical visual effect. Therefore, in the case where multiple sub-areas in the display area have different refresh rates, by calculating the refresh rate difference between the second display area and the first display area, the greater the difference in refresh rate between the first display area and the second display area, the greater the decrease in the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area, and the smaller the absolute value of the gate turn-off voltage provided to the first switch transistor T3 and the second switch transistor T4, the brightness difference between the second display area and the first display area can be reduced.

[0063] In some embodiments, the drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is related to the refresh rate difference between the second display area and the first display area.

[0064] In this embodiment, combined with Figure 2As shown, the characteristic offset of the switch transistor (e.g., the first switch transistor T3 and the second switch transistor T4) in the pixel driving unit is related to the refresh rate of the display area in which it is located, that is, the PBS / NBS effect of the first switch transistor T3 and the second switch transistor T4 will cause a brightness difference between different refresh rate areas, and the greater the difference in refresh rate, the greater the impact of the brightness difference, and further the greater the impact on the optical visual effect. Therefore, in the case where multiple sub-areas in the display area have different refresh rates, the brightness difference between the second display area and the first display area can be balanced by matching the refresh rate difference between the second display area and the first display area with the drop amplitude of the gate conduction voltage received by the first switch transistor T3 and the second switch transistor T4 in the pixel driving unit corresponding to the first display area.

[0065] In some embodiments, the greater the difference in refresh rate between the first display area and the second display area, the greater the drop in gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area.

[0066] In this embodiment, combined with Figure 2 As shown, the characteristic offset of the first switch transistor T3 and the second switch transistor T4 is related to the refresh rate of the display area where they are located, that is, the PBS / NBS of the first switch transistor T3 and the second switch transistor T4 corresponding to different refresh rate areas are different, which will cause brightness differences between different refresh rate areas. The greater the difference in refresh rate, the greater the impact of the brightness difference, and further the greater the impact on the optical visual effect. Therefore, in the case where multiple sub-areas in the display area have different refresh rates, by calculating the refresh rate difference between the second display area and the first display area, the greater the difference in refresh rate between the first display area and the second display area, the greater the decrease in the gate-on voltage received by the first switch transistor T3 and the second switch transistor T4 in the pixel driving unit corresponding to the second display area, and the smaller the absolute value of the gate-on voltage provided to the first switch transistor T3 and the second switch transistor T4, the brightness difference between the second display area and the first display area can be reduced.

[0067] In some embodiments, the gate-on voltage received by the first switch transistor T3 and the second switch transistor T4 in the pixel driving unit in the first display area (high refresh area) can be reduced from 7.8V to 6.8V.

[0068] In some embodiments, the gate turn-off voltage received by the first switch transistor T3 and the second switch transistor T4 in the pixel driving unit in the second display area (low refresh area) can be adjusted from -9.8V to -8.8V.

[0069] In some embodiments, Figure 3 As shown, the partition display driving method further includes step S410 and step S420.

[0070] In step S410, a refresh rate difference between the first display area and the second display area is obtained.

[0071] In step S420, the drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is determined according to the difference in refresh rate between the first display area and the second display area.

[0072] In this embodiment, the difference in refresh rate between the first display area and the second display area may be in direct proportion to the decrease in gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area. The decrease in gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is determined according to the difference in refresh rate between the first display area and the second display area, thereby effectively balancing the brightness difference between the first display area and the second display area.

[0073] In some embodiments, in step S420, a decrease amplitude of a gate-on voltage received by a switching transistor in a pixel driving unit corresponding to the first display area is determined according to a difference in refresh rates between the first display area and the second display area, including: determining a gate-on voltage received by a switching transistor in a pixel driving unit corresponding to the first display area according to a difference in refresh rates between the first display area and the second display area and a preset refresh rate-gate voltage relationship table.

[0074] In this embodiment, a refresh rate-gate voltage relationship table can be established through preliminary tests. The refresh rate-gate voltage relationship table can represent the corresponding relationship between the difference in refresh rate between the first display area and the second display area and the amplitude of the change in the gate conduction voltage. Therefore, after obtaining the difference in refresh rate between the first display area and the second display area, the corresponding gate voltage is read from the preset refresh rate-gate voltage relationship table according to the difference, and the gate conduction voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is set to the gate voltage read from the refresh rate-gate voltage relationship table.

[0075] In some embodiments, in step S420, the decrease amplitude of the gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area is determined according to the difference in refresh rates between the first display area and the second display area, including: gradually reducing the gate-on voltage received by the switching transistor in the pixel driving unit corresponding to the first display area according to the difference in refresh rates between the first display area and the second display area.

[0076] In some embodiments, the partition display driving method in this embodiment further includes: generating a corresponding partition enable signal according to a pixel range of the second display area.

[0077] In this embodiment, the scanning area where the display refresh rate needs to be reduced is determined by the pixel range of the second display area, thereby generating a corresponding partition enable signal, and the partition enable signal is used to control the corresponding pixel driving unit to reduce the duty cycle of the pixel driving signal, thereby achieving a reduction in the switching duty cycle of the pixels in the corresponding area.

[0078] In some embodiments, in combination Figure 4 As shown, the partition display driving method in this embodiment further includes step S500.

[0079] In step S500, the high-level pulse width of the gate pulse signal of the switch transistor in the pixel driving unit corresponding to the first display area is controlled to decrease.

[0080] In the partition refresh scheme, different display areas have different refresh rates, which may lead to different working conditions of transistors, such as turn-on time, threshold voltage drift, etc. By setting different PVGH / PVGL voltages for different display areas, these differences can be compensated, so that the first switch transistor T3 and the second switch transistor T4 maintain consistent performance in different refresh rate areas, reducing the problem of uneven display.

[0081] In this embodiment, based on the voltage differentiation, the high level pulse width of the gate pulse signal of the switch transistor in the pixel driving unit corresponding to the first display area is controlled to be reduced, for example, Figure 5a is a timing diagram of the first scanning control signal SN1, the second scanning control signal SN2, the first data control signal SP1, the second data control signal SP2, and the dimming control signal EM in the first display area before modification, Figure 5b As shown, the timing corresponding to the scanning control signal received by the gate of the first switching transistor T3 and the second switching transistor T4 is modified, wherein the high-level pulse width of the first scanning control signal SN1 received by the gate of the first switching transistor T3 is reduced from 10H to 2H, the high-level pulse width of the second switching transistor T4 is reduced from 22H to 18H, and the high-level pulse width of the first data control signal SP1, the second data control signal SP2, and the dimming control signal EM remain unchanged. By reducing the high-level pulse width of the gate pulse signal of the first switching transistor T3 and the second switching transistor T4, the PBS / NBS opening time for the first display area (high refresh area) is reduced, thereby reducing the threshold voltage (Vth) bias caused by PBS / NBS and the brightness difference of different areas under the partition refresh.

[0082] In some embodiments, in combination Figure 6 As shown, the partition enable signal can also be logically processed with the scan drive signal output by the scan drive module 520, so as to adjust the duty cycle of the scan drive signal output to the gate scan line 501, thereby achieving the purpose of controlling the corresponding pixel drive unit to reduce the duty cycle of the pixel drive signal, thereby realizing the partition refresh display of the display panel.

[0083] In some embodiments, the main control circuit 510 can provide a corresponding partition scanning signal to the scanning driving module 520 according to the content to be displayed on the display panel, so as to adjust the refresh rate of the corresponding display screen. For example, according to the coordinates of the display screen and the refresh rate requirements, by providing a corresponding partition scanning signal for the partition display driving method, the refresh rate of the display screen is set according to a frequency distribution such as 60hz-120hz-60hz, 30hz-120hz-30hz, 1hz-120hz-1hz, etc. Specifically, in realizing the function of displaying different refresh rates in multiple regions of a mobile phone, if the mobile phone is watching a video (requiring a high refresh rate display) and reading text (low refresh rate display) at the same time, the refresh rate of the text display area in the display screen is set to a low refresh rate (such as 1Hz, 30Hz, etc.), thereby reducing the power consumption of the display panel without affecting the display effect.

[0084] The present application also provides a display driving circuit. Figure 6 As shown, the display driving circuit in the embodiment of the present application includes multiple pixel driving units 530 and a main control circuit 510. The main control circuit 510 is used to execute the partition display driving method in any of the above embodiments; the multiple pixel driving units 530 are used to drive multiple display pixels to light up respectively.

[0085] In this embodiment, the display panel includes a plurality of display pixels, and the plurality of display pixels may be arranged in an array, and each display pixel is driven by a corresponding pixel driving unit 530, and the pixel driving unit 530 may generate a pixel driving signal according to a received gate scanning signal, thereby driving the corresponding display pixel to light up, and the plurality of display pixels may display corresponding images when driven to light up. The main control circuit 510 may control the corresponding pixel driving unit 530 to generate a pixel driving signal with a lower duty cycle according to the pixel range of the second display area, thereby reducing the refresh rate of the display image of the second display area.

[0086] In some embodiments, in combination Figure 6As shown, the display driving circuit also includes multiple scanning driving modules 520, and multiple gate scanning lines 501 are respectively connected to the multiple scanning driving modules 520; the scanning driving modules 520 are controlled by the main control circuit 510 to provide gate scanning signals for the multiple gate scanning lines 501, and multiple pixel driving units 530 are respectively connected to the corresponding gate scanning lines 501; each pixel driving unit 530 is used to drive the corresponding display pixel to light up according to the received gate scanning signal and data signal.

[0087] An embodiment of the present application further provides a display screen, which includes a display driving circuit as described in any one of the above embodiments.

[0088] In this embodiment, the display screen includes a display panel and a display driving circuit. The display panel includes a plurality of display pixels. Each display pixel includes at least one display diode. The display diode can emit a corresponding color when it is lit. For example, the display diode can emit one of red light, blue light or green light. The display diodes of three colors can form a display pixel. By obtaining the pixel range of the first display area and the second display area, the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area is controlled to decrease according to the pixel range of the second display area; the gate turn-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area, so that when the display panel turns on the partition refresh function, the gate positive voltage and negative voltage of the switch transistor can be processed differently, so as to achieve the purpose of reducing the brightness difference caused by PBS or NBS.

[0089] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0090] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0091] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0092] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0093] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0094] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A partition display driving method, characterized in that: The partition display driving method comprises: Acquire a pixel range of a first display area and a second display area; wherein a refresh rate of the first display area is greater than a refresh rate of the second display area; Controlling the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area to decrease according to the pixel range of the second display area; The gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is controlled to decrease according to the pixel range of the first display area.

2. The partition display driving method according to claim 1, characterized in that: The decrease range of the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area is related to the refresh rate difference between the second display area and the first display area.

3. The partition display driving method according to claim 2, characterized in that: The greater the difference in refresh rate between the first display area and the second display area, the greater the decrease in the absolute value of the gate turn-off voltage received by the switch transistor in the pixel driving unit corresponding to the second display area.

4. The partition display driving method according to claim 1, characterized in that: The drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is positively correlated with the refresh rate difference between the second display area and the first display area.

5. The partition display driving method according to claim 4, characterized in that: The partition display driving method further includes: Obtaining a difference in refresh rate between the first display area and the second display area; The drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is determined according to the difference in refresh rate between the first display area and the second display area.

6. The partition display driving method according to claim 5, characterized in that: The step of determining the drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area according to the difference between the refresh rates of the first display area and the second display area includes: The gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is determined according to the difference in refresh rate between the first display area and the second display area and a preset refresh rate-gate voltage relationship table.

7. The partition display driving method according to claim 5, characterized in that: The step of determining the drop amplitude of the gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area according to the difference between the refresh rates of the first display area and the second display area includes: The gate-on voltage received by the switch transistor in the pixel driving unit corresponding to the first display area is gradually reduced according to the difference in refresh rate between the first display area and the second display area.

8. The partition display driving method according to any one of claims 1 to 7, characterized in that: The partition display driving method further includes: The high-level pulse width of the gate pulse signal of the switch transistor in the pixel driving unit corresponding to the first display area is controlled to be reduced.

9. A display driving circuit, characterized in that: The display driving circuit includes a plurality of pixel driving units and a main control circuit, and the main control circuit is used to execute the partition display driving method according to any one of claims 1 to 8 to control the plurality of pixel driving units to drive a plurality of display pixels to light up.

10. A display screen, characterized in that: The display screen includes the display driving circuit as claimed in claim 9.

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