Display device and method for driving display device

Abstract

A display device and a method for driving the same are provided. The display device includes: a display panel including first to third pixels; a data driver for supplying first to third data voltages to the first to third pixels; and a scan driver for supplying the first scan signal and the second scan signal to each of the first to third pixels. The scan driver performs a first effective scan operation of sequentially supplying the first scan signal and the second scan signal to the first to third pixels in a first frame period, and performs a dummy scan operation of sequentially supplying the second scan signal to the first to third pixels after the first effective scan operation. The data driver changes a voltage level of at least one of the first to third data voltages in an overlapping period in which a dummy scan operation and a second effective scan operation of a second frame period are simultaneously performed.

Description

Technical Field

[0001] Embodiments relate to a display device and more particularly to a display device that performs a dummy scan operation and a method for driving the display device. Background Art

[0002] Typically, a display device is configured to display images at a frame frequency (or refresh frequency) of about 60 Hz, about 120 Hz, about 240 Hz, or the like. However, the frame rate of rendering performed by a host processor (e.g., a graphics processing unit (“GPU”), an application processor (“AP”), or a graphics card) configured to provide frame data to the display device may not match the frame frequency of the display device. In particular, when the host processor provides frame data for a game image that requires complex rendering to the display device, such a frame frequency mismatch may become severe, and the frame frequency mismatch may result in tearing of boundary lines in an image displayed on the display device, and the like.

[0003] In order to prevent the tearing phenomenon, a variable frame mode (e.g., a free sync mode, a G sync mode, etc.) has been developed in which a host processor changes a blank period for each frame cycle to provide frame data to a display device at a variable frame frequency. A display device supporting the variable frame mode can prevent the tearing phenomenon by displaying an image in synchronization with the variable frame frequency (i.e., by driving a display panel at a variable frame frequency or a variable driving frequency). Summary of the invention

[0004] The embodiment provides a display device having reduced color deviation when driven at a variable frequency.

[0005] The embodiment provides a method for driving a display device having reduced color deviation when driven at a variable frequency.

[0006] A display device according to an embodiment includes: a display panel including a first pixel configured to display a first color, a second pixel configured to display a second color, and a third pixel configured to display a third color; a data driver configured to provide a first data voltage, a second data voltage, and a third data voltage to the first pixel, the second pixel, and the third pixel, respectively; a scan driver configured to provide a first scan signal and a second scan signal to each of the first pixel to the third pixel; and a controller configured to control the data driver and the scan driver, and receive first pixel data, second pixel data, and third pixel data corresponding to the first data voltage, the second data voltage, and the third data voltage, respectively. Each of the first pixel to the third pixel is set in plurality. The scan driver is configured to perform a first effective scan operation of sequentially providing the first scan signal and the second scan signal to the first pixel to the third pixel row by row in a first frame period corresponding to a first driving frequency, and perform a dummy scan operation of sequentially providing the second scan signal to the first pixel to the third pixel row by row after the first effective scan operation. The data driver is configured to, when a second frame period corresponding to a second driving frequency different from the first driving frequency starts without completing a dummy scan operation, change a voltage level of at least one of a first data voltage to a third data voltage in an overlapping period in which the dummy scan operation and a second valid scan operation of the second frame period are simultaneously performed.

[0007] In an embodiment, the first color, the second color, and the third color may be green, blue, and red, respectively.

[0008] In an embodiment, the data driver may be configured to change a voltage level of the first data voltage in the overlapping period.

[0009] In an embodiment, for the same grayscale, a voltage level of the first data voltage in the overlap period may be higher than a voltage level of the first data voltage in a non-overlap period in which only the second valid scan operation and the second valid scan operation of the dummy scan operation are performed after the dummy scan operation is completed.

[0010] In an embodiment, the data driver may be configured to change both a voltage level of the first data voltage and a voltage level of the second data voltage in an overlapping period.

[0011] In an embodiment, for the same gray level, the voltage level of the first data voltage in the overlap period may be higher than the voltage level of the first data voltage in the non-overlap period in which only the second valid scan operation and the second valid scan operation of the dummy scan operation are performed after the dummy scan operation is completed. For the same gray level, the voltage level of the second data voltage in the overlap period may be higher than the voltage level of the second data voltage in the non-overlap period.

[0012] In an embodiment, the controller may include: an overlapping area detector configured to calculate an overlapping area of ​​overlapping pixel rows configured to receive the first scanning signal and the second scanning signal in the overlapping period among all pixel rows of the display panel based on a frequency difference between the first driving frequency and the second driving frequency; and a data compensator configured to compensate for at least one of the first pixel data to the third pixel data of the overlapping area.

[0013] In an embodiment, the first color, the second color, and the third color may be green, blue, and red, respectively.

[0014] In an embodiment, the display device may further include: a compensation lookup table configured to store a plurality of compensation values ​​corresponding to a plurality of input gray levels. The data compensator may be configured to obtain a compensation value corresponding to an input gray level indicated by the first pixel data of the overlapped area among the plurality of input gray levels by using the compensation lookup table, and compensate the first pixel data of the overlapped area by adding the compensation value to the input gray level.

[0015] In an embodiment, the display device may further include: a first compensation lookup table configured to store a plurality of first compensation values ​​corresponding to a plurality of input gray levels; and a second compensation lookup table configured to store a plurality of second compensation values ​​corresponding to the plurality of input gray levels and different from the plurality of first compensation values. The data compensator may be configured to compensate the first pixel data of the overlapped area by using the first compensation lookup table, and to compensate the second pixel data of the overlapped area by using the second compensation lookup table.

[0016] In an embodiment, the display device may further include: a first range compensation lookup table configured to store a plurality of first range compensation values ​​corresponding to a plurality of input gray levels; and a second range compensation lookup table configured to store a plurality of second range compensation values ​​corresponding to the plurality of input gray levels and different from the plurality of first range compensation values. The data compensator may be configured to: when the frequency difference is within a first frequency range, compensate the first pixel data of the overlapping area by using the first range compensation lookup table; and when the frequency difference is within a second frequency range different from the first frequency range, compensate the first pixel data of the overlapping area by using the second range compensation lookup table.

[0017] In an embodiment, when the second driving frequency is greater than the first driving frequency, the second driving frequency may be a non-integer multiple of the first driving frequency.

[0018] In an embodiment, each of the first to third pixels may include: a capacitor including a first electrode connected to a first node and a second electrode connected to a second node; a first transistor including a gate connected to the first node, a drain configured to receive a first power voltage, and a source connected to the second node; a second transistor configured to transmit one of a first data voltage to a third data voltage to the first node in response to a first scan signal; a third transistor configured to transmit an initialization voltage to the second node in response to a second scan signal; and a light emitting element including an anode connected to the second node and a cathode configured to receive a second power voltage.

[0019] According to an embodiment, a method for driving a display device includes: in a first frame period corresponding to a first driving frequency, performing a first effective scanning operation in which a first scanning signal and a second scanning signal are sequentially provided row by row to a first pixel configured to display a first color, a second pixel configured to display a second color, and a third pixel configured to display a third color; after the first effective scanning operation, performing a dummy scanning operation in which the second scanning signal is sequentially provided row by row to the first pixel to the third pixel; and when a second frame period corresponding to a second driving frequency different from the first driving frequency starts without completing the dummy scanning operation, changing a voltage level of at least one of a first data voltage, a second data voltage, and a third data voltage provided to the first pixel, the second pixel, and the third pixel, respectively, in an overlapping period in which the dummy scanning operation and the second effective scanning operation of the second frame period are simultaneously performed.

[0020] In an embodiment, the first color, the second color, and the third color may be green, blue, and red, respectively.

[0021] In an embodiment, the voltage level of the first data voltage may be changed in the overlapping period.

[0022] In an embodiment, for the same grayscale, a voltage level of the first data voltage in the overlap period may be higher than a voltage level of the first data voltage in a non-overlap period in which only the second valid scan operation and the second valid scan operation of the dummy scan operation are performed after the dummy scan operation is completed.

[0023] In an embodiment, both the voltage level of the first data voltage and the voltage level of the second data voltage may be changed in the overlapping period.

[0024] In an embodiment, for the same gray level, the voltage level of the first data voltage in the overlap period may be higher than the voltage level of the first data voltage in the non-overlap period in which only the second valid scan operation and the second valid scan operation of the dummy scan operation are performed after the dummy scan operation is completed. For the same gray level, the voltage level of the second data voltage in the overlap period may be higher than the voltage level of the second data voltage in the non-overlap period.

[0025] In an embodiment, when the second driving frequency is greater than the first driving frequency, the second driving frequency may be a non-integer multiple of the first driving frequency.

[0026] In the display device and the method for driving the display device according to the embodiment, the voltage level of at least one of the first to third data voltages may be changed in the overlapping period in which the dummy scan operation of the first frame period and the second effective scan operation of the second frame period are simultaneously performed. Therefore, the color deviation between the upper area of ​​the display panel in which the pixel row receiving the first to third data voltages in the overlapping period is located and the lower area of ​​the display panel in which the pixel row receiving the first to third data voltages in the non-overlapping period in which only the second effective scan operation and the second effective scan operation in the dummy scan operation are performed after the dummy scan operation is completed can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a block diagram showing a display device according to an embodiment.

[0029] Figure 2 It is shown that the Figure 1 A view of an example of first to third pixels in a display device of FIG.

[0030] Figure 3 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0031] Figure 4 is shown with variable frequency input to Figure 1 is a timing diagram of an example of input image data to a display device.

[0032] Figure 5 is a view showing an example of luminance of display panels driven at mutually different driving frequencies in a display device according to a comparative example.

[0033] Figure 6 It is shown in Figure 1A view of an example of a valid scanning operation and a dummy scanning operation performed in a display device.

[0034] Figure 7 is a view showing an example of luminance of display panels driven at mutually different driving frequencies in the display device according to the embodiment.

[0035] Figure 8 is a view for describing an example of a color deviation between an upper area and a lower area of ​​a display panel in a display device according to a comparative example.

[0036] Fig. 9 is a view for describing a change in a voltage level of a first data voltage in an overlap period according to an embodiment.

[0037] Fig.10 is a view for describing changes in voltage levels of a first data voltage and a second data voltage in an overlap period according to an embodiment.

[0038] Fig.11 It is shown that the Figure 1 A block diagram of an example of a controller and a memory in a display device.

[0039] Fig.12 It is shown that the Fig.11 A view of an example of a compensation lookup table in memory.

[0040] Fig.13 It is shown that the Figure 1 A block diagram of another example of a controller and a memory in a display device.

[0041] Fig.14 It is shown that the Fig.13 A view of an example of a first compensation lookup table and a second compensation lookup table in a memory of FIG.

[0042] Fig.15 It is shown that the Figure 1 A block diagram of an example of a controller and a memory in a display device.

[0043] Fig.16 It is shown that the Fig.15 A view of an example of multiple range compensation lookup tables in a memory of FIG.

[0044] Fig.17 is a flowchart illustrating a method for driving a display device according to an embodiment.

[0045] Fig.18 is a block diagram showing an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0046] The terms used herein are only used to describe the purpose of a particular embodiment, and are not intended to be limited. As used herein, unless the context clearly states otherwise, "at least one (kind / person)" does not indicate a limitation on quantity, and is intended to include both the singular and the plural. For example, unless the context clearly states otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" should not be interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the listed items in question. It will also be understood that when the terms "include" and / or "comprising" and variations thereof are used in this specification, it is specified that there are stated features, regions, entireties, steps, operations, elements and / or components, but it is not excluded that there are or add one or more other features, regions, entireties, steps, operations, elements, components and / or their groups.

[0047] It will be understood that although the terms "first", "second", "third", etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings here, the "first element", "first component", "first region", "first layer" or "first part" discussed below can be referred to as the second element, second component, second region, second layer or second part. Hereinafter, the display device according to the embodiment of the present disclosure and the method for driving the display device will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals will be used for the same elements.

[0048] Figure 1 is a block diagram showing a display device according to an embodiment. Figure 2 It is shown that the Figure 1 A view of an example of first to third pixels in a display device of FIG. Figure 3 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device. Figure 4 is shown with variable frequency input to Figure 1 is a timing diagram of an example of input image data to a display device. Figure 5 is a view showing an example of luminance of display panels driven at mutually different driving frequencies in a display device according to a comparative example. Figure 6 It is shown in Figure 1 A view of an example of a valid scanning operation and a dummy scanning operation performed in a display device. Figure 7is a view showing an example of luminance of display panels driven at mutually different driving frequencies in the display device according to the embodiment. Figure 8 is a view for describing an example of a color deviation between an upper area and a lower area of ​​a display panel in a display device according to a comparative example. Fig. 9 is a view for describing a change in a voltage level of a first data voltage in an overlap period according to an embodiment. Fig.10 is a view for describing changes in voltage levels of a first data voltage and a second data voltage in an overlap period according to an embodiment.

[0049] Reference Figure 1 , the display device 100 may include: a display panel 110 including a plurality of pixels PX; a data driver 120 configured to provide a data voltage VDAT to each of the pixels PX; a scan driver 130 configured to provide a first scan signal SC and a second scan signal SS to each of the pixels PX; a power management circuit 140 configured to generate voltages ELVDD, ELVSS, and VINT; and a controller 160 configured to control the operation of the display device 100. According to an embodiment, the display device 100 may further include a memory 170.

[0050] The display panel 110 may further include a plurality of data lines DL connected to the pixels PX, a plurality of first scan lines, a plurality of second scan lines, and a plurality of initialization lines SL. According to an embodiment, each of the pixels PX may include a light emitting element, and the display panel 110 may be a light emitting display panel.

[0051] In an embodiment, for example, Figure 2 As shown in , the pixel PX may include a first pixel PX1 configured to display a first color, a second pixel PX2 configured to display a second color, and a third pixel PX3 configured to display a third color. A first data voltage VDAT1, a second data voltage VDAT2, and a third data voltage VDAT3 may be provided to the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively. According to an embodiment, the first color, the second color, and the third color may be green, blue, and red, respectively. In other words, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be a green pixel, a blue pixel, and a red pixel, respectively.

[0052] In an embodiment, for example, Figure 3 As shown in , each of the pixels PX may include a first transistor T1, a second transistor T2, a third transistor T3, a capacitor CST, and a light emitting element LED.

[0053] The capacitor CST may store the data voltage VDAT transmitted from the data line DL through the second transistor T2. The capacitor CST may be referred to as a storage capacitor configured to store the data voltage VDAT, but is not limited thereto. According to another embodiment, the capacitor CST may include a first electrode connected to the first node NG and a second electrode connected to the second node NS.

[0054] The first transistor T1 may generate a driving current based on the data voltage VDAT stored in the capacitor CST. The first transistor T1 may be referred to as a driving transistor configured to generate a driving current, but is not limited thereto. According to another embodiment, the first transistor T1 may include a gate connected to the first node NG, a drain configured to receive the first power voltage ELVDD, and a source connected to the second node NS.

[0055] The second transistor T2 may transmit the data voltage VDAT to the first node NG in response to the first scan signal SC. The second transistor T2 may be referred to as a scan transistor, but is not limited thereto. According to another embodiment, the second transistor T2 may include a gate configured to receive the first scan signal SC, a drain connected to the data line DL, and a source connected to the first node NG.

[0056] The third transistor T3 may connect the initialization line SL to the second node NS in response to the second scan signal SS. The power management circuit 140 may apply the initialization voltage VINT to the initialization line SL, and the third transistor T3 may transmit the initialization voltage VINT of the initialization line SL to the second node NS in response to the second scan signal SS. According to an embodiment, the third transistor T3 may include a gate configured to receive the second scan signal SS, a drain connected to the second node NS, and a source connected to the initialization line SL.

[0057] The light emitting element LED may emit light in response to a driving current flowing from a line configured to transmit a first power voltage ELVDD to a line configured to transmit a second power voltage ELVSS. According to an embodiment, the light emitting element LED may include an anode connected to a second node NS and a cathode configured to receive the second power voltage ELVSS. According to an embodiment, the light emitting element LED may be an organic light emitting diode ("OLED"). According to an embodiment, the light emitting element LED may be a nano light emitting diode ("NED"), a quantum dot ("QD") light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or the like.

[0058] According to an embodiment, Figure 3As shown in , the first transistor T1, the second transistor T2, and the third transistor T3 may be implemented as N-type metal oxide semiconductor ("NMOS") transistors, but are not limited thereto. In addition, according to another embodiment, as Figure 3 As shown in FIG. 1 , the pixel PX may include three transistors T1, T2, and T3 and one capacitor CST, but is not limited thereto. In addition, the connection structure between the components of the pixel PX is not limited to Figure 3 The connection structure shown in .

[0059] The data driver 120 may generate a data voltage VDAT based on a data control signal DCTRL and output image data ODAT received from the controller 160, and provide the data voltage VDAT to the pixel PX through the data line DL. According to an embodiment, the data control signal DCTRL may include an output data enable signal, a horizontal start signal, and / or a load signal, etc., but is not limited thereto. In addition, according to another embodiment, the data driver 120 may receive the output image data ODAT from the controller 160 at a driving frequency DF that varies within a variable frequency range (e.g., from about 48 Hz to about 240 Hz).

[0060] The scan driver 130 may generate a first scan signal SC and a second scan signal SS based on a scan control signal SCTRL received from the controller 160, and sequentially provide the first scan signal SC and the second scan signal SS to the pixels PX row by row through the first scan line and the second scan line. According to an embodiment, the scan control signal SCTRL may include a first scan start signal and a first scan clock signal for generating the first scan signal SC and a second scan start signal and a second scan clock signal for generating the second scan signal SS, but is not limited thereto.

[0061] The power management circuit 140 may generate voltages ELVDD, ELVSS, and VINT for operation of the display device 100. According to an embodiment, the power management circuit 140 may generate a first power voltage ELVDD (e.g., a high power voltage), a second power voltage ELVSS (e.g., a low power voltage), and an initialization voltage VINT provided to the display panel 110. The power management circuit 140 may provide the initialization voltage VINT to the pixel PX through the initialization line SL.

[0062] The controller 160 (e.g., a timing controller ("TCON")) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit ("GPU"), an application processor ("AP"), or a graphics card). The input image data IDAT may include first pixel data PDAT1, second pixel data PDAT2, and third pixel data PDAT3. The first pixel data PDAT1, the second pixel data PDAT2, and the third pixel data PDAT3 may correspond to a first data voltage VDAT1, a second data voltage VDAT2, and a third data voltage VDAT3, respectively. According to an embodiment, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, and / or a main clock signal, etc., but is not limited thereto. The controller 160 may generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a power management signal PCTRL based on the input image data IDAT and the control signal CTRL. The controller 160 may control the operation of the data driver 120 by providing the output image data ODAT and the data control signal DCTRL to the data driver 120 , control the operation of the scan driver 130 by providing the scan control signal SCTRL to the scan driver 130 , and control the operation of the power management circuit 140 by providing the power management signal PCTRL to the power management circuit 140 .

[0063] The host processor may change the time length of the blank period of each frame cycle to provide the input image data IDAT to the display device 100 at a variable frequency VF (or a variable frame rate), and the controller 160 may receive the input image data IDAT from the host processor at a variable frequency VF that varies within a variable frequency range. According to an embodiment, the maximum frequency of the variable frequency range may be about 240 Hz, and the minimum frequency of the variable frequency range may be about 48 Hz, but the frequency is not limited thereto. In addition, the driving frequency DF of the display panel 110 may be determined as a variable frequency VF that varies within a variable frequency range. In other words, the controller 160 may control the data driver 120 and the scan driver 130 to drive the display panel 110 at the same driving frequency DF as the variable frequency VF. According to an embodiment, a mode of the display device 100 in which the display panel 110 is driven at a variable frequency VF (or a variable frame rate) may be referred to as a variable frame mode. Meanwhile, the variable frame mode may be a free sync mode or a G sync mode, etc., but is not limited thereto.

[0064] In an embodiment, for example, Figure 4As shown in , the period or frequency of the rendering 210, 220, and 230 of the host processor may not be constant, and the host processor may provide the input image data IDAT (i.e., the frame data FD1, FD2, and FD3) to the display device 100 in the variable frame mode in synchronization with such a non-constant period or frequency of the rendering 210, 220, and 230. In other words, in the variable frame mode, when the frame periods FP1, FP2, and FP3 may have effective periods AP1, AP2, and AP3 having a constant time length, respectively, the host processor may change the time length of the blank periods BP1, BP2, and BP3 of the frame periods FP1, FP2, and FP3, thereby providing the frame data FD1, FD2, and FD3 to the display device 100 at a variable frequency VF.

[0065] according to Figure 4 In the example shown in , in the first frame period FP1, when the rendering 210 for the second frame data FD2 is performed at a frequency of about 240 Hz, the host processor may provide the first frame data FD1 to the display device 100 at a variable frequency VF of about 240 Hz. In addition, the host processor may output the second frame data FD2 during the second effective period AP2 of the second frame period FP2, and continue the second blank period BP2 of the second frame period FP2 until the rendering 220 for the third frame data FD3 is completed. Therefore, in the second frame period FP2, when the rendering 220 for the third frame data FD3 is performed at a frequency of about 48 Hz, the host processor may increase the time length of the second blank period BP2 of the second frame period FP2, thereby providing the second frame data FD2 to the display device 100 at the variable frequency VF of about 48 Hz. In the third frame period FP3, when the rendering 230 for the fourth frame data FD4 is performed again at a frequency of about 240 Hz, the host processor may again provide the third frame data FD3 to the display device 100 at a frame frequency of about 240 Hz.

[0066] However, a conventional display device configured to operate in a variable frame mode may have mutually different brightness at mutually different driving frequencies DF. In other words, according to the conventional display device, each of the pixels PX may receive the second scan signal SS only once in each of the frame periods FP1, FP2, and FP3, the second node NS of each of the pixels PX may be initialized only once in each of the frame periods FP1, FP2, and FP3 based on the initialization voltage VINT, and the light-emitting element LED of each of the pixels PX may be turned off only once in each of the frame periods FP1, FP2, and FP3. In addition, when the driving frequency DF changes (i.e., when the time length of the frame periods FP1, FP2, and FP3 changes), the number of times the second scan signal SS is applied to each of the pixels PX within a predetermined time (i.e., the number of times the light-emitting element LED of each of the pixels PX is turned off) may change. Therefore, even when the conventional display device displays an image with the same grayscale level, when the driving frequency DF of the display panel 110 changes, the brightness of the display panel 110 may also change. For example, as Figure 5 As shown in , according to a conventional display device, within the same time (e.g., about 53 milliseconds (ms)), each of the light emitting element LEDs of the display panel 110 driven at a driving frequency DF of about 48 Hz may be turned off about 2.5 times, and each of the light emitting element LEDs of the display panel 110 driven at a driving frequency DF of about 240 Hz may be turned off about 12.5 times. Therefore, the average brightness AVGLUM2 of the display panel 110 driven at a driving frequency DF of about 240 Hz may be lower than the average brightness AVGLUM1 of the display panel 110 driven at a driving frequency DF of about 48 Hz.

[0067] However, in order to reduce such a brightness deviation of the display panel 110 driven at mutually different driving frequencies DF, according to the display device 100 of the embodiment, the scan driver 130 may perform an effective scanning operation of sequentially providing the first scan signal SC and the second scan signal SS to the pixel PX row by row in the effective period of each of the frame periods, and may perform a dummy scanning operation of sequentially providing the second scan signal SS to the pixel PX row by row in the blank period of each of the frame periods. According to the embodiment, when a reference blank time passes after the blank period starts, the scan driver 130 may start the dummy scanning operation. According to the embodiment, the reference blank time may be substantially equal to the time length of the blank period of the minimum frame period (about 4.2 ms) corresponding to the maximum frequency of the variable frequency range (for example, about 240 Hz). According to the embodiment, when the blank period continues the reference blank time after the dummy scanning operation is completed, the scan driver 130 may repeatedly perform the dummy scanning operation.

[0068] In an embodiment, for example, Figure 6As shown in FIG. 1 , in a first effective period AP1 of a first frame period FP1 corresponding to a frequency of about 48 Hz, the scan driver 130 may perform a first effective scan operation ASCAN1 that sequentially outputs a first scan signal SC and a second scan signal SS from a first scan line SCL1 and a second scan line SSL1 for a first pixel row of the display panel 110 to a first scan line SCLN and a second scan line SSLN for an N-th pixel row (where N is an integer greater than or equal to 2) of the display panel 110. When a reference blank time RBT (e.g., a time length of a blank period of a minimum frame period corresponding to a maximum frequency) elapses after a first blank period BP1 of the first frame period FP1 begins, the scan driver 130 may perform a first dummy scan operation DSCAN1 that sequentially outputs a second scan signal SS from a second scan line SSL1 for the first pixel row to a second scan line SSLN for the N-th pixel row. Meanwhile, when the first dummy scan operation DSCAN1 is performed, since the first scan signal SC is not applied to each of the pixels PX, the data voltage VDAT stored in each of the pixels PX may be maintained, the second node NS of each of the pixels PX may be initialized, and the light emitting element LED of each of the pixels PX may be turned off. In addition, the second dummy scan operation DSCAN2 may be performed after another reference blank time RBT has passed from the time when the first dummy scan operation DSCAN1 is completed, the third dummy scan operation DSCAN3 may be performed after another reference blank time RBT has passed from the time when the second dummy scan operation DSCAN2 is completed, and the fourth dummy scan operation DSCAN4 may be performed after another reference blank time RBT has passed from the time when the third dummy scan operation DSCAN3 is completed. In addition, the second effective scan operation ASCAN2 may be performed in the second effective period AP2 of the second frame period FP2 corresponding to a frequency of about 240 Hz, and the dummy scan operation may not be performed in the second blank period BP2 of the second frame period FP2.

[0069] As described above, according to the display device 100 of the embodiment, the dummy scanning operations DSCAN1, DSCAN2, DSCAN3, and DSCAN4 may be performed during the first blank period BP1 so that the luminance may be substantially the same at mutually different driving frequencies DF. Figure 7As shown in, according to the display device 100 of the embodiment, for the same time (for example, about 53ms), each of the light emitting elements LED of the display panel 110 driven at a driving frequency DF of about 48Hz and each of the light emitting elements LED of the display panel 110 driven at a driving frequency DF of about 240Hz can be turned off the same number of times (for example, about 12.5 times). Therefore, according to the display device 100 of the embodiment, the brightness of the display panel 110 driven at a driving frequency DF of about 48Hz can be substantially the same as the brightness of the display panel 110 driven at a driving frequency DF of about 240Hz.

[0070] However, when the second driving frequency corresponding to the second frame period FP2 is greater than the first driving frequency corresponding to the first frame period FP1 and the second driving frequency is a non-integer multiple of the first driving frequency, color deviation may occur between the upper area and the lower area of ​​the display panel 110. When the second driving frequency (e.g., about 240 Hz) is a non-integer multiple of the first driving frequency (e.g., about 49 Hz to about 59 Hz, about 61 Hz to about 79 Hz, about 81 Hz to about 119 Hz, or about 121 Hz to about 239 Hz), the second frame period FP2 may start before the dummy scanning operation started in the blank period of the first frame period FP1 is completed, and color deviation may occur between the upper area and the lower area of ​​the display panel 110. For example, as Figure 8As shown in , when the second nodes NS of the pixels PX positioned in one row may be initialized (or discharged) in the non-overlapping period NOP, the second scan signal SS may be applied to the pixels PX positioned in two rows substantially at the same time in the overlapping period OP, and the second nodes NS of the pixels PX positioned in the two rows may be initialized (or discharged) substantially at the same time, wherein only the effective scan operation ASCAN and the effective scan operation ASCAN in the dummy scan operation DSCAN are performed in the non-overlapping period NOP after the dummy scan operation DSCAN is completed, and the dummy scan operation DSCAN started in the blank period BP of the first frame period FP1 and the effective scan operation ASCAN in the effective period AP of the second frame period FP2 are simultaneously performed in the overlapping period OP. Therefore, the sink current flowing through the initialization line SL in the overlapping period OP may be greater than the sink current flowing through the initialization line SL in the non-overlapping period NOP, and the voltage drop through the initialization line SL in the overlapping period OP may be greater than the voltage drop through the initialization line SL in the non-overlapping period NOP. Therefore, the brightness of the overlap region OR (e.g., the upper region of the display panel 110) receiving the data voltage VDAT in the overlap period OP may be lower than the brightness of the non-overlap region NOR (e.g., the lower region of the display panel 110) receiving the data voltage VDAT in the non-overlap period NOP, and a brightness deviation may occur between the overlap region OR and the non-overlap region NOR of the display panel 110. The overlap region OR may include an “overlap pixel row” receiving the first scan signal SC and the second scan signal SS in the overlap period OP among all pixel rows of the display panel 110. In addition, since the characteristics of the light-emitting elements LED included in the first pixel PX1, the second pixel PX2, and the third pixel PX3 configured to display mutually different colors (for example, the capacitance and / or the driving current of the light-emitting element LED) are different from each other, the brightness deviation between the first pixel PX1 in the overlapping area OR and the first pixel PX1 in the non-overlapping area NOR, the brightness deviation between the second pixel PX2 in the overlapping area OR and the second pixel PX2 in the non-overlapping area NOR, and the brightness deviation between the third pixel PX3 in the overlapping area OR and the third pixel PX3 in the non-overlapping area NOR may be different from each other, and color deviation may occur between the overlapping area OR and the non-overlapping area NOR of the display panel 110.For example, the brightness deviation between the first pixel PX1 in the overlapping area OR and the first pixel PX1 in the non-overlapping area NOR may be greater than each of the brightness deviation between the second pixel PX2 in the overlapping area OR and the second pixel PX2 in the non-overlapping area NOR and the brightness deviation between the third pixel PX3 in the overlapping area OR and the third pixel PX3 in the non-overlapping area NOR, and the brightness deviation between the second pixel PX2 in the overlapping area OR and the second pixel PX2 in the non-overlapping area NOR may be greater than the brightness deviation between the third pixel PX3 in the overlapping area OR and the third pixel PX3 in the non-overlapping area NOR, so that when the non-overlapping area NOR of the display panel 110 displays a white image, the overlapping area OR of the display panel 110 may display an image with a slightly purple color.

[0071] To reduce color deviation between the upper region OR and the lower region NOR of the display panel 110 , the display device 100 according to the embodiment may change a voltage level of at least one of the first data voltage VDAT1 , the second data voltage VDAT2 , and the third data voltage VDAT3 in the overlap period OP.

[0072] According to an embodiment, Fig. 9 As shown in , the display device 100 can change the voltage level of the first data voltage VDAT1 in the overlap period OP. For the same grayscale, the voltage level of the first data voltage VDAT1 in the overlap period OP can be higher than the voltage level of the first data voltage VDAT1 in the non-overlap period NOP. Therefore, the brightness deviation between the first pixel PX1 in the overlap region OR and the first pixel PX1 in the non-overlap region NOR can be effectively reduced, and the color deviation between the overlap region OR and the non-overlap region NOR of the display panel 110 can be effectively reduced.

[0073] According to an embodiment, Fig.10As shown in , the display device 100 can change the voltage level of the first data voltage VDAT1 and the voltage level of the second data voltage VDAT2 in the overlapping period OP. For the same grayscale, the voltage level of the first data voltage VDAT1 in the overlapping period OP can be higher than the voltage level of the first data voltage VDAT1 in the non-overlapping period NOP, and for the same grayscale, the voltage level of the second data voltage VDAT2 in the overlapping period OP can be higher than the voltage level of the second data voltage VDAT2 in the non-overlapping period NOP. Therefore, the brightness deviation between the first pixel PX1 in the overlapping area OR and the first pixel PX1 in the non-overlapping area NOR and the brightness deviation between the second pixel PX2 in the overlapping area OR and the second pixel PX2 in the non-overlapping area NOR can be effectively reduced, and the color deviation between the overlapping area OR and the non-overlapping area NOR of the display panel 110 can be effectively reduced.

[0074] Fig.11 It is shown that the Figure 1 A block diagram of an example of a controller and a memory in a display device. Fig.12 It is shown that the Fig.11 A view of an example of a compensation lookup table in memory.

[0075] Reference Figure 1 and Fig.11 , the controller 160a may include an overlap region detector 161 and a data compensator 162a. The memory 170a may include a compensation lookup table ("LUT") 171a.

[0076] The overlap region detector 161 may calculate the overlap region OR of the display panel 110 based on a frequency difference between a first driving frequency DF1 corresponding to the first frame period FP1 and a second driving frequency DF2 corresponding to the second frame period FP2 .

[0077] The data compensator 162a may compensate at least one of the first pixel data PDAT1, the second pixel data PDAT2, and the third pixel data PDAT3 of the overlap region OR. According to an embodiment, the data compensator 162a may compensate the first pixel data PDAT1 of the overlap region OR by using the compensation lookup table 171a. In an embodiment, for example, Fig.12As shown in , the compensation lookup table 171a may store a plurality of compensation values ​​("COMPV1") V1[0] to V1

[255] corresponding to a plurality of input gray levels ("IGRAY") 0 to 255. In an embodiment, for example, the compensation values ​​V1[0] to V1

[255] may be greater than 0. The data compensator 162a may obtain the compensation value COMPV1 corresponding to the input gray level IGRAY indicated by the first pixel data PDAT1 of the overlap area OR by using the compensation lookup table 171a, and compensate the first pixel data PDAT1 of the overlap area OR by adding the compensation value COMPV1 to the input gray level IGRAY. Therefore, the data driver 120 may increase the voltage level of the first data voltage VDAT1 in the overlap period OP based on the output image data ODAT including the compensated first pixel data. Therefore, as Fig. 9 As shown in , the brightness deviation between the first pixel PX1 in the overlap region OR and the first pixel PX1 in the non-overlap region NOR can be reduced, and the color deviation between the overlap region OR and the non-overlap region NOR of the display panel 110 can be effectively reduced.

[0078] Fig.13 It is shown that the Figure 1 A block diagram of another example of a controller and a memory in a display device. Fig.14 It is shown that the Fig.13 A view of an example of a first compensation lookup table and a second compensation lookup table in a memory of FIG.

[0079] Reference Figure 1 and Fig.13 , the controller 160b may include an overlap area detector 161 and a data compensator 162b. The memory 170b may include a first compensation lookup table ("LUT") 171b and a second compensation lookup table ("LUT") 172b. Fig.13 The controller 160b and the memory 170b described above will be omitted with reference to Fig.11 The components of the controller 160a and the memory 170a described herein are substantially the same as or similar to the components described herein.

[0080] According to an embodiment, the data compensator 162b may compensate the first pixel data PDAT1 of the overlap region OR by using the first compensation lookup table 171b, and compensate the second pixel data PDAT2 of the overlap region OR by using the second compensation lookup table 172b. Fig.14As shown in , the first compensation lookup table 171b may store a plurality of first compensation values ​​("COMPV1") V1[0] to V1

[255] corresponding to a plurality of input gray levels ("IGRAY") 0 to 255, and the second compensation lookup table 172b may store a plurality of second compensation values ​​("COMPV2") V2[0] to V2

[255] corresponding to a plurality of input gray levels ("IGRAY") 0 to 255 and different from the first compensation values ​​V1[0] to V1

[255] . In an embodiment, for example, the first compensation values ​​V1[0] to V1

[255] and the second compensation values ​​V2[0] to V2

[255] may be greater than 0. Therefore, the data driver 120 may increase the voltage level of the first data voltage VDAT1 and the voltage level of the second data voltage VDAT2 in the overlapping period OP based on the output image data ODAT including the compensated first pixel data and the compensated second pixel data. Therefore, as Fig.10 As shown in, the brightness deviation between the first pixel PX1 in the overlapping area OR and the first pixel PX1 in the non-overlapping area NOR and the brightness deviation between the second pixel PX2 in the overlapping area OR and the second pixel PX2 in the non-overlapping area NOR can be effectively reduced, and the color deviation between the overlapping area OR and the non-overlapping area NOR of the display panel 110 can be effectively reduced.

[0081] Fig.15 It is shown that the Figure 1 A block diagram of an example of a controller and a memory in a display device. Fig.16 It is shown that the Fig.15 A view of an example of multiple range compensation lookup tables in a memory of FIG.

[0082] Reference Figure 1 and Fig.15 , the controller 160c may include an overlap area detector 161 and a data compensator 162c. The memory 170c may include a plurality of range compensation lookup tables ("LUT"). In an embodiment, for example, the memory 170c may include a first range compensation lookup table ("LUT") 171-1c, a second range compensation lookup table ("LUT") 171-2c, and a third range compensation lookup table ("LUT") 171-3c, but the number of range compensation lookup tables is not limited thereto. Fig.15 The controller 160c and the memory 170c described above will be omitted with reference to Fig.11 The components of the controller 160a and the memory 170a described herein are substantially the same as or similar to the components described herein.

[0083] According to an embodiment, when the frequency difference between the first driving frequency DF1 corresponding to the first frame period FP1 and the second driving frequency DF2 corresponding to the second frame period FP2 is within the first frequency range, the data compensator 162c may compensate the first pixel data PDAT1 of the overlapping area OR by using the first range compensation lookup table 171-1c; when the frequency difference is within the second frequency range different from the first frequency range, the data compensator 162c may compensate the first pixel data PDAT1 of the overlapping area OR by using the second range compensation lookup table 171-2c; and when the frequency difference is within the third frequency range different from the first frequency range and the second frequency range, the data compensator 162c may compensate the first pixel data PDAT1 of the overlapping area OR by using the third range compensation lookup table 171-3c. According to an embodiment, the first frequency range may be from about 240 Hz to about 120 Hz, the second frequency range may be from about 120 Hz to about 80 Hz, and the third frequency range may be from about 80 Hz to about 60 Hz. In an embodiment, for example, as Fig.16 As shown in FIG. 1 , the first range compensation lookup table 171-1c can store a plurality of first range compensation values ​​("COMPV1-1") V1-1[0] to V1-1

[255] corresponding to a plurality of input gray levels ("IGRAY") 0 to 255, and the second range compensation lookup table 171-2c can store a plurality of second range compensation values ​​V1-1[0] to V1-1

[255] corresponding to the input gray levels ("IGRAY") 0 to 255 and different from the first range compensation values ​​V1-1[0] to V1-1

[255] . The third range compensation lookup table 171-3c may store a plurality of third range compensation values ​​("COMPV1-3") V1-3[0] to V1-3

[255] corresponding to the input grayscale ("IGRAY") 0 to 255 and different from the first range compensation values ​​V1-1[0] to V1-1

[255] and the second range compensation values ​​V1-2[0] to V1-2

[255] . Therefore, the first pixel data PDAT1 of the overlap area OR may be compensated by using the range compensation lookup tables 171-1c, 171-2c, and 171-3c suitable for the frequency difference between the first driving frequency DF1 and the second driving frequency DF2.

[0084] Fig.17 is a flowchart illustrating a method for driving a display device according to an embodiment.

[0085] Reference Figure 1 , Figure 2 , Fig. 9 , Fig.10 and Fig.17, a method for driving the display device 100 may include: performing a first effective scanning operation ASCAN1 (S110) in which a first scanning signal SC and a second scanning signal SS are sequentially provided to a first pixel PX1, a second pixel PX2, and a third pixel PX3 row by row in a first frame period FP1 corresponding to a first driving frequency DF1; performing a dummy scanning operation DSCAN (S120) in which a second scanning signal SS is sequentially provided to the first pixel PX1, the second pixel PX2, and the third pixel PX3 row by row after the first effective scanning operation ASCAN1; and changing a voltage level of at least one of a first data voltage VDAT1, a second data voltage VDAT2, and a third data voltage VDAT3 in an overlapping period OP in which the dummy scanning operation DSCAN and a second effective scanning operation ASCAN2 of the second frame period FP2 are simultaneously performed when the second frame period FP2 starts without completing the dummy scanning operation DSCAN (S130).

[0086] In the step (S110) of performing the first effective scan operation ASCAN1, the scan driver 130 may sequentially output the first scan signal SC and the second scan signal SS from the first scan line SCL1 and the second scan line SSL1 for the first pixel row of the display panel 110 to the first scan line SCLN and the second scan line SSLN for the N-th pixel row of the display panel 110. In the step (S120) of performing the dummy scan operation, the scan driver 130 may sequentially output the second scan signal SS from the second scan line SSL1 for the first pixel row to the second scan line SSLN for the N-th pixel row.

[0087] According to an embodiment, in the step (S130) of changing the voltage level of at least one of the first data voltage VDAT1, the second data voltage VDAT2, and the third data voltage VDAT3 in the overlap period OP, as shown in FIG. Fig. 9 As shown in , the data driver 120 may change the voltage level of the first data voltage VDAT1 in the overlap period OP. For the same grayscale, the voltage level of the first data voltage VDAT1 in the overlap period OP may be higher than the voltage level of the first data voltage VDAT1 in the non-overlap period NOP. Therefore, the brightness deviation between the first pixel PX1 in the overlap region OR and the first pixel PX1 in the non-overlap region NOR may be effectively reduced, and the color deviation between the overlap region OR and the non-overlap region NOR of the display panel 110 may be effectively reduced.

[0088] According to an embodiment, in the step (S130) of changing the voltage level of at least one of the first data voltage VDAT1, the second data voltage VDAT2, and the third data voltage VDAT3 in the overlap period OP, as shown in FIG. Fig.10As shown in , the data driver 120 may change the voltage level of the first data voltage VDAT1 and the voltage level of the second data voltage VDAT2 in the overlap period OP. For the same grayscale, the voltage level of the first data voltage VDAT1 in the overlap period OP may be higher than the voltage level of the first data voltage VDAT1 in the non-overlap period NOP, and for the same grayscale, the voltage level of the second data voltage VDAT2 in the overlap period OP may be higher than the voltage level of the second data voltage VDAT2 in the non-overlap period NOP. Therefore, the brightness deviation between the first pixel PX1 in the overlap region OR and the first pixel PX1 in the non-overlap region NOR and the brightness deviation between the second pixel PX2 in the overlap region OR and the second pixel PX2 in the non-overlap region NOR may be effectively reduced, and the color deviation between the overlap region OR and the non-overlap region NOR of the display panel 110 may be effectively reduced.

[0089] Fig.18 is a block diagram showing an electronic device including a display device according to an embodiment.

[0090] Reference Fig.18 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output ("I / O") device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, and / or a USB device, etc., or communicating with other systems.

[0091] The processor 1110 may perform a specific calculation or task. Depending on the embodiment, the processor 1110 may be a microprocessor or a central processing unit ("CPU"), etc. The processor 1110 may be connected to other components via an address bus, a control bus, and / or a data bus, etc. Depending on the embodiment, the processor 1110 may also be connected to an expansion bus such as a peripheral component interconnect ("PCI") bus. Depending on the embodiment, the processor 1110 may process the input image data ( Figure 1 IDAT) and a control signal CTRL are provided to the display device 1160.

[0092] The memory device 1120 may store data used for the operation of the electronic device 1100. In an embodiment, for example, the memory device 1120 may include: a non-volatile memory device such as an erasable programmable read-only memory ("EPROM"), an electrically erasable programmable read-only memory ("EEPROM"), a flash memory, a phase change random access memory ("PRAM"), a resistive random access memory ("RRAM"), a nano floating gate memory ("NFGM"), a polymer random access memory ("PoRAM"), a magnetic random access memory ("MRAM"), or a ferroelectric random access memory ("FRAM"); and / or a volatile memory device such as a dynamic random access memory ("DRAM"), a static random access memory ("SRAM"), or a mobile DRAM. According to an embodiment, Figure 1 The memory 170 may be replaced by the memory device 1120 .

[0093] The storage device 1130 may include a solid-state drive ("SSD"), a hard disk drive ("HDD"), and / or a CD-ROM, etc. The I / O device 1140 may include: an input device such as a keyboard, a keypad, a touch pad, a touch screen, or a mouse; and an output device such as a speaker or a printer. The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be connected to other components through a bus or other communication link. The display device 1160 may correspond to Figure 1 A display device 100 is provided.

[0094] According to the display device 1160, the voltage level of at least one of the first data voltage to the third data voltage can be changed in the overlapping period in which the dummy scanning operation of the first frame period and the second effective scanning operation of the second frame period are simultaneously performed. Therefore, the color deviation between the upper area of ​​the display panel and the lower area of ​​the display panel can be effectively reduced, wherein the pixel row receiving the first data voltage to the third data voltage in the overlapping period is located in the upper area of ​​the display panel, and the pixel row receiving the first data voltage to the third data voltage in the non-overlapping period in which only the second effective scanning operation and the second effective scanning operation in the dummy scanning operation are performed after the dummy scanning operation is completed is located in the lower area of ​​the display panel.

[0095] The display device according to the embodiment may be applied to a display device included in a computer, a notebook, a mobile phone, a smart phone, a smart tablet, a smart watch, a PMP, a PDA, an MP3 player, or the like.

[0096] As used in connection with the various disclosed embodiments, each of the overlap region detector and the data compensator may be implemented in hardware, software, or firmware (eg, in the form of an application specific integrated circuit ("ASIC")).

[0097] Although the display device and the driving method of the display device according to the embodiment have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by a person of ordinary skill in the relevant technical field without departing from the technical spirit described in the claims.

Claims

1. A display device, comprising: a display panel including a first pixel configured to display a first color, a second pixel configured to display a second color, and a third pixel configured to display a third color; a data driver configured to provide a first data voltage, a second data voltage, and a third data voltage to the first pixel, the second pixel, and the third pixel, respectively; a scan driver configured to provide a first scan signal and a second scan signal to each of the first to third pixels; as well as a controller configured to control the data driver and the scan driver and receive first pixel data, second pixel data, and third pixel data corresponding to the first data voltage, the second data voltage, and the third data voltage, respectively, Wherein, each of the first to third pixels is provided in plurality, The scan driver is configured to perform a first effective scan operation of sequentially supplying the first scan signal and the second scan signal to the first to third pixels row by row in a first frame period corresponding to a first driving frequency, and to perform a dummy scan operation of sequentially supplying the second scan signal to the first to third pixels row by row after the first effective scan operation, and The data driver is configured to, when a second frame period corresponding to a second driving frequency different from the first driving frequency starts without completing the dummy scanning operation, change the voltage level of at least one of the first data voltage to the third data voltage in an overlapping period in which the dummy scanning operation and a second valid scanning operation of the second frame period are simultaneously performed.

2. The display device according to claim 1, wherein: The first color, the second color, and the third color are green, blue, and red, respectively.

3. The display device according to claim 2, wherein: The data driver is configured to change a voltage level of the first data voltage in the overlap period.

4. The display device according to claim 3, wherein: For the same grayscale, the voltage level of the first data voltage in the overlapping period is higher than the voltage level of the first data voltage in a non-overlapping period in which only the second valid scanning operation and the second valid scanning operation of the dummy scanning operations are performed after completing the dummy scanning operation.

5. The display device according to claim 2, wherein: The data driver is configured to change both a voltage level of the first data voltage and a voltage level of the second data voltage in the overlap period.

6. The display device according to claim 5, wherein: For the same gray level, the voltage level of the first data voltage in the overlapping period is higher than the voltage level of the first data voltage in a non-overlapping period in which only the second effective scanning operation and the second effective scanning operation of the dummy scanning operations are performed after the dummy scanning operation is completed, and For the same gray scale, the voltage level of the second data voltage in the overlap period is higher than the voltage level of the second data voltage in the non-overlap period.

7. The display device according to claim 1, wherein: The controller comprises: an overlap area detector configured to calculate an overlap area of ​​overlapped pixel rows configured to receive the first scanning signal and the second scanning signal in the overlap period among all pixel rows of the display panel based on a frequency difference between the first driving frequency and the second driving frequency; and A data compensator is configured to compensate at least one of the first pixel data to the third pixel data in the overlapping area.

8. The display device according to claim 7, wherein: The first color, the second color, and the third color are green, blue, and red, respectively.

9. The display device according to claim 8, further comprising: a compensation lookup table configured to store a plurality of compensation values ​​corresponding to a plurality of input gray levels, Wherein, the data compensator is configured to obtain a compensation value among the multiple compensation values ​​corresponding to the input gray level indicated by the first pixel data of the overlapping area among the multiple input gray levels by using the compensation lookup table, and compensate the first pixel data of the overlapping area by adding the compensation value to the input gray level.

10. The display device according to claim 8, further comprising: a first compensation lookup table configured to store a plurality of first compensation values ​​corresponding to a plurality of input gray levels; as well as a second compensation lookup table configured to store a plurality of second compensation values ​​corresponding to the plurality of input gray levels and different from the plurality of first compensation values, The data compensator is configured to compensate the first pixel data of the overlapped area by using the first compensation lookup table, and to compensate the second pixel data of the overlapped area by using the second compensation lookup table.

11. The display device according to claim 8, further comprising: a first range compensation lookup table configured to store a plurality of first range compensation values ​​corresponding to a plurality of input gray levels; as well as a second range compensation lookup table configured to store a plurality of second range compensation values ​​corresponding to the plurality of input gray levels and different from the plurality of first range compensation values, Wherein, the data compensator is configured to: when the frequency difference is within a first frequency range, compensate the first pixel data of the overlapping area by using the first range compensation lookup table; and when the frequency difference is within a second frequency range different from the first frequency range, compensate the first pixel data of the overlapping area by using the second range compensation lookup table.

12. The display device according to claim 1, wherein: When the second driving frequency is greater than the first driving frequency, the second driving frequency is a non-integer multiple of the first driving frequency.

13. The display device according to claim 1, wherein: Each of the first to third pixels includes: a capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a first transistor including a gate connected to the first node, a drain configured to receive a first power voltage, and a source connected to the second node; a second transistor configured to transmit one of the first data voltage to the third data voltage to the first node in response to the first scan signal; a third transistor configured to transmit an initialization voltage to the second node in response to the second scan signal; and The light emitting element includes an anode connected to the second node and a cathode configured to receive a second power voltage.

14. A method for driving a display device, the method comprising: performing a first effective scanning operation, wherein the first effective scanning operation sequentially provides a first scanning signal and a second scanning signal to a first pixel configured to display a first color, a second pixel configured to display a second color, and a third pixel configured to display a third color, wherein each of the first to third pixels is provided in plural, and the first effective scanning operation is performed on the first to third pixels row by row in a first frame period corresponding to a first driving frequency; After the first effective scanning operation, performing a dummy scanning operation that sequentially supplies the second scanning signal to the first to third pixels row by row; and When the second frame period corresponding to a second driving frequency different from the first driving frequency starts without completing the dummy scanning operation, the voltage levels of at least one of the first data voltage, the second data voltage and the third data voltage respectively provided to the first pixel, the second pixel and the third pixel are changed in an overlapping period in which the dummy scanning operation and the second valid scanning operation of the second frame period are simultaneously performed.

15. The method according to claim 14, wherein: The first color, the second color, and the third color are green, blue, and red, respectively.

16. The method according to claim 15, wherein: A voltage level of the first data voltage is changed in the overlapping period.

17. The method according to claim 16, wherein: For the same grayscale, the voltage level of the first data voltage in the overlapping period is higher than the voltage level of the first data voltage in a non-overlapping period in which only the second valid scanning operation and the second valid scanning operation of the dummy scanning operations are performed after completing the dummy scanning operation.

18. The method according to claim 15, wherein: Both a voltage level of the first data voltage and a voltage level of the second data voltage are changed in the overlapping period.

19. The method according to claim 18, wherein: For the same gray level, the voltage level of the first data voltage in the overlapping period is higher than the voltage level of the first data voltage in a non-overlapping period in which only the second effective scanning operation and the second effective scanning operation of the dummy scanning operations are performed after the dummy scanning operation is completed, and For the same gray scale, the voltage level of the second data voltage in the overlap period is higher than the voltage level of the second data voltage in the non-overlap period.

20. The method according to claim 14, wherein: When the second driving frequency is greater than the first driving frequency, the second driving frequency is a non-integer multiple of the first driving frequency.

Images