Storage circuit for integration of storage and calculation

Abstract

The invention provides a storage and calculation integrated storage circuit, and relates to the technical field of storage, the storage circuit comprises a storage structure with expandable storage depth and / or storage width; the storage depth is the number of the storage addresses, and the storage width is the bit number of the storage data corresponding to each storage address; a basic unit of the storage structure comprises an address decoding line, a data line and a gate circuit set, the address decoding line is connected with the input end of the gate circuit in the gate circuit set; the data line is connected with the output end of the gate circuit; aiming at the expansion of the storage width, the number of data lines is increased on the basis of the basic unit, and each data line is connected with the output end of the corresponding gate circuit in the gate circuit set; and for the expansion of the storage depth, increasing the number of the basic units or the basic units after the expansion of the storage width. The method has the advantages of high capacity density, low reading delay, good engineering application prospect, controllable data updating cost and the like.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a storage circuit for storage and computing integration. Background Art

[0002] Over the past 20 years, processor performance has increased rapidly at a rate of about 55% per year, while memory performance has only increased at a rate of about 10% per year. As a result of long-term accumulation, the uneven development speed has caused the current memory access speed to lag seriously behind the processor's computing speed. The memory bottleneck makes it difficult for high-performance processors to perform as they should, which has greatly restricted the growing high-performance computing (HPC).

[0003] A typical scenario is a large language model (LLM), which usually contains hundreds of millions to tens of billions of parameters. These parameters are learning weights that determine how the LLM processes and generates language. Training these parameters requires multiple passes through a large data set, a process that requires a lot of computing resources. In order to speed up these calculations, GPUs and other chip products are currently used in LLMs due to their intensive computing power. However, the architectural evolution of GPU chips has not solved the challenges of large computing power and LLMs. Under the traditional von Neumann architecture, GPU chips face the "storage wall" problem when performing computationally intensive tasks, which results in the power consumption and performance of computing chips being limited by the data transfer between the processor and the memory, severely limiting the improvement of artificial intelligence chips in terms of computing scale, density, efficiency, etc.

[0004] In order to solve the above problems, Computing in Memory is proposed, that is, embedding computing power in memory and performing two-dimensional and three-dimensional matrix multiplication / addition operations with a new computing architecture. This architecture tightly couples data storage and data processing, reducing data transmission between storage and processors, thereby significantly improving performance and energy efficiency. This is also one of the research hotspots in the past decade.

[0005] At present, the mature processes that can be used for storage and computing integration include: Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), and Flash. However, the intellectual property (IP) core process node of DRAM is not advanced, and the read latency is large; the capacity density of SRAM is small, and its application in scenarios such as large models is limited; Flash is very slow, and the process is incompatible with normal chip processes. In addition, the academic community is more concerned about the introduction of various memristors (Resistive Random Access Memory, RRAM) in neural network computing. However, the RRAM process yield is still in progress, and it is still a long way from mass production and engineering use.

[0006] Some computing scenarios (such as large models) have a very low update frequency for most of the parameters required for calculation. For example, Meta first publicly released LLaMA 1 in February 2022 and LLaMA 3 in July 2023. Thanks to the LoRA fine-tuning technology, only a small number of fine-tuning parameters are required to adapt to various large model application scenarios.

[0007] Based on this, there is an urgent need to develop a storage circuit for storage and computing scenarios (such as large models) with huge data volumes and infrequent data updates. Summary of the invention

[0008] The present invention provides a storage circuit for storage and computing integration, which has the advantages of high capacity density, low reading delay, good engineering use prospects, and controllable data update cost.

[0009] The present invention provides a storage circuit for storage and computing integration, comprising: a storage structure with expandable storage depth and / or storage width; the storage depth is the number of storage addresses, and the storage width is the number of bits of storage data corresponding to each storage address; The basic unit of the storage structure includes: an address decoding line, a data line and a gate circuit set; the address decoding line is connected to the input end of the gate circuit in the gate circuit set, and the data line is connected to the output end of the gate circuit; In order to expand the storage width, the number of the data lines is increased on the basis of the basic unit, and each of the data lines is connected to the output end of the corresponding gate circuit in the gate circuit set; In order to expand the storage depth, the number of the basic units or the basic units after the storage width is expanded is increased, and multiple basic units or the basic units after the storage width is expanded are cascaded.

[0010] According to a storage circuit for storage and computing provided by the present invention, the basic unit after the storage width is expanded is used to store a second number of groups of storage data at a first number of storage addresses, and each group of storage data includes storage data of the same bits of the first number of storage addresses; Among them, the first number of storage addresses are decoded to obtain the first number of one-hot code addresses, and the first number of one-hot code addresses are input to the input end of the corresponding gate circuit in the gate circuit set through the first number of address decoding lines of the basic unit, and the second number of groups of storage data are output through the second number of data lines after operation by the corresponding gate circuit in the gate circuit set.

[0011] According to a storage circuit for integrated storage and computing provided by the present invention, for any two groups of storage data, the two groups of storage data are the same, and the gate circuits corresponding to the two groups of storage data are the same.

[0012] According to a storage circuit for integrated storage and computing provided by the present invention, for any two groups of storage data, the two groups of storage data are different, and the gate circuits corresponding to the two groups of storage data are different.

[0013] According to a storage circuit for storage and computing integration provided by the present invention, the storage structure after the storage depth is expanded includes a plurality of cascaded storage units, and the storage unit is the basic unit or the basic unit after the storage width is expanded; Each of the gate circuits in the cascaded multiple storage units is also provided with an AND gate as a new gate circuit; the signal line of the enable signal is connected to the first input end of the AND gate, the output end of the gate circuit is connected to the second input end of the AND gate, and the output end of the AND gate serves as the output end of the new gate circuit; An OR gate is also provided between each two storage units, and the storage data of corresponding bits of the two storage units are respectively input into two input ends of the OR gate; When accessing the target storage data of the target storage address, each storage address of each storage unit is decoded and an enable signal is obtained. The enable signals corresponding to each storage address of the storage unit to which the target storage address belongs are valid, and the enable signals corresponding to each storage address of other storage units are invalid. The output end of the OR gate outputs the target storage data.

[0014] According to a storage circuit for integrated storage and computing provided by the present invention, the storage unit is the basic unit, the number of bits of the basic unit is the first number, and the number of data lines of the basic unit is 1; the first number of OR gates are also arranged between every two of the storage units, and each of the OR gates corresponds to the storage data of the same bit from the data lines of the two storage units.

[0015] According to a storage circuit for integrated storage and computing provided by the present invention, the storage unit is the basic unit after the storage width is expanded, the number of data lines of the basic unit after the storage width is expanded is the second number, and the number of bits corresponding to each data line is the first number; the first number of OR gates are also arranged between every two storage units; for each data line, each OR gate corresponds to the storage data of the same bit of the data lines of the two storage units.

[0016] According to a storage circuit for integrated storage and computing provided by the present invention, the number of the address decoding lines in the basic unit is related to the manufacturing process or manufacturing tools of the metal routing.

[0017] According to a storage circuit for integrated storage and computing provided by the present invention, the number of each gate circuit in the gate circuit set is a value with 2 as the base and the number of the address decoding lines in the basic unit as the exponent.

[0018] According to a storage circuit for storage and computing provided by the present invention, the basic unit is used to store the storage data of the first number of bits at the first number of storage addresses, and the first number of storage addresses corresponds to the storage data of the first number of bits in a one-to-one manner; Among them, the first number of storage addresses are decoded to obtain the first number of one-hot code addresses, and the first number of one-hot code addresses are input to the input end of the specified gate circuit in the gate circuit set through the first number of address decoding lines of the basic unit, and the storage data of the first number of bits are output through the data line after operation by the specified gate circuit in the gate circuit set.

[0019] The storage circuit for storage and computing provided by the present invention includes: a storage structure with expandable storage depth and / or storage width, the storage depth is the number of storage addresses, and the storage width is the number of bits of storage data corresponding to each storage address. The basic unit of the storage structure includes: an address decoding line, a data line and a gate circuit set, the address decoding line is connected to the input end of the gate circuit in the gate circuit set, and the data line is connected to the output end of the gate circuit. When the stored data needs to be modified, only the connection of the data line needs to be modified, and when re-stripping, only the metal mask of the metal routing needs to be re-manufactured, and this cost will be a fraction of the cost of re-stripping from the beginning, so the data update cost of the storage structure is controllable. For the expansion of storage width, the number of data lines is increased on the basis of the basic unit, and each data line is connected to the output end of the corresponding gate circuit in the gate circuit set, so that the storage width of the storage structure can be infinitely expanded. For the expansion of storage depth, the number of basic units or basic units after the storage width is expanded is increased, and multiple basic units or basic units after the storage width is expanded are cascaded, so that the storage depth of the storage structure can be wirelessly expanded. Since the storage circuit for storage and computing provided by the present invention has a simple structure, the chip area is small and the capacity density is high. Since the storage circuit for storage and computing provided by the present invention is a conventional circuit inside, it can be manufactured using conventional chip technology, so that the reading delay is low. Since the storage circuit for storage and computing provided by the present invention has a low production cost, low subsequent tape-out cost, small area, and fast reading speed, it has good prospects for engineering use. Therefore, the storage circuit for storage and computing provided by the present invention has the advantages of large capacity density, low reading delay, good prospects for engineering use, and controllable data update costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a schematic diagram of the structure of a storage circuit for storage and computing provided in an embodiment of the present invention.

[0022] Figure 2 It is a structural diagram of a basic unit of a storage structure provided by an embodiment of the present invention.

[0023] Figure 3 It is a schematic diagram of the structure of a basic unit after the storage width is expanded provided by an embodiment of the present invention.

[0024] Figure 4It is a structural diagram of the storage structure after the storage depth is expanded provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] Combine the following Figure 1-Figure 4 The present invention is described as a storage circuit for storage and computing integration.

[0027] Please refer to Figure 1 , Figure 1 Schematic diagram of the structure of a storage circuit for storage and computing provided by an embodiment of the present invention. Figure 1 As shown, the storage circuit includes: a storage structure with expandable storage depth and / or storage width. The storage depth is the number of storage addresses, for example: if the storage address is address 0-n, then the storage depth is n+1. The storage width is the number of bits of storage data corresponding to each storage address, for example: if the number of bits of storage data corresponding to each address in address 0-n is 4, then the storage width is 4.

[0028] The basic unit of the storage structure includes: an address decoding line, a data line and a gate circuit set. The address decoding line is connected to the input end of the gate circuit in the gate circuit set, and the data line is connected to the output end of the gate circuit.

[0029] Specifically, the basic unit of the storage structure is the smallest storage unit of the storage structure. With respect to the storage depth of the basic unit, if the storage depth of the basic unit is too large, it will lead to more address decoding lines in the basic unit, which is not beneficial to the chip area; if the storage depth of the basic unit is too small, it will lead to too many cascades and more gate circuits, which is also not beneficial to the chip area. Preferably, the number of address decoding lines in the basic unit is related to the manufacturing process or manufacturing tools of the metal routing.

[0030] Optionally, the number of each gate circuit in the gate circuit set is a value with 2 as the base and the number of address decoding lines in the basic unit as the exponent. For example, for a basic unit with a storage depth of 4, the number of each gate circuit in the gate circuit set is 2. 4 =16 Optionally, the basic unit is used to store a first number of bits of storage data at a first number of storage addresses, and the first number of storage addresses corresponds to the first number of bits of storage data one by one. The first number of storage addresses are decoded to obtain a first number of one-hot code addresses, and the first number of one-hot code addresses are input to the input end of a specified gate circuit in the gate circuit set through the first number of address decoding lines of the basic unit, and the first number of bits of storage data are output through the data line after being calculated by the specified gate circuit in the gate circuit set.

[0031] The following takes a basic unit with a storage depth of 4 and a storage width of 1 as an example to specifically explain the structure and working principle of the basic unit.

[0032] Assume that the storage data of the basic unit is as shown in Table 1.

[0033] Table 1

[0034] like Figure 2 As shown, the basic unit includes four address decoding lines, one data line and 16 gate circuits. The 16 gate circuits include: 0, c, d, c||d, b, b||d, b||c, b||c||d, a, a||d, a||c, a||c||d, a||b, a||b||d, a||b||c and a||b||c||d.

[0035] Exemplarily, the first number is 4, as shown in Table 1, the basic unit is used to store 4-bit storage data (0101) at addresses 0-3, and addresses 0-3 correspond to 4-bit storage data (0101) one by one. Among them, the mapping relationship between the 4 unique hot code addresses a~d and addresses 0-3 is: unique hot code address 0000~address 0, unique hot code address 0010~address 1, unique hot code address 0100~address 2, unique hot code address 1000~address 3. The unique hot code addresses a~d are input to the input end of the specified gate circuit b||d in the gate circuit set through the 4 address decoding lines of the basic unit, and the 4-bit storage data 0101 is output through the data line after the specified gate circuit b||d in the gate circuit set is calculated.

[0036] In order to expand the storage width, the number of data lines is increased on the basis of the basic unit, and each data line is connected to the output end of the corresponding gate circuit in the gate circuit set.

[0037] In one embodiment, the basic unit after the storage width is expanded is used to store a second number of groups of storage data at a first number of storage addresses, and each group of storage data includes storage data of the same bit positions of the first number of storage addresses. The first number of storage addresses are decoded to obtain a first number of one-hot code addresses, and the first number of one-hot code addresses are input to the input end of the corresponding gate circuit in the gate circuit set through the first number of address decoding lines of the basic unit, and the second number of groups of storage data are output through the second number of data lines after the corresponding gate circuit in the gate circuit set is operated.

[0038] Optionally, for any two groups of stored data, the two groups of stored data are identical, and the gate circuits corresponding to the two groups of stored data are identical.

[0039] Optionally, for any two groups of stored data, the two groups of stored data are different, and the gate circuits corresponding to the two groups of stored data are different.

[0040] For example, assuming that Figure 2 The storage width of the basic unit shown is expanded to 4, and the storage data of the substrate unit after the storage width is expanded is shown in Table 2.

[0041] Table 2

[0042] like Figure 3 As shown, in Figure 2 Three data lines are added to the basic unit shown, the first data line is connected to the output end of the specified gate circuit b||d in the gate circuit set, the second data line is connected to the output end of the specified gate circuit a||d in the gate circuit set, the third data line is connected to the output end of the specified gate circuit a||b||c||d in the gate circuit set, and the fourth data line is connected to the output end of the specified gate circuit a||b||d in the gate circuit set.

[0043] Exemplarily, the first number is 4, and the second number is 4, as shown in Table 2, the basic unit after the storage width expansion is used to store 4 groups of storage data at addresses 0-3, and each group of storage data includes storage data with the same number of bits of 4 storage addresses. Among them, the mapping relationship between the 4 unique hot code addresses a~d and addresses 0-3 is: unique hot code address 0000~address 0, unique hot code address 0010~address 1, unique hot code address 0100~address 2, unique hot code address 1000~address 3. The unique hot code addresses a~d are input to the input terminals of the designated gate circuits b||d, a||d, a||b||c||d and a||b||d in the gate circuit set through the four address decoding lines of the basic unit. After the designated gate circuit b||d in the gate circuit set is calculated, the first group of stored data 0101 is output through the first data line. After the designated gate circuit a||d in the gate circuit set is calculated, the second group of stored data 1001 is output through the second data line. After the designated gate circuit a||b||c||d in the gate circuit set is calculated, the third group of stored data 1111 is output through the third data line. After the designated gate circuit a||b||d in the gate circuit set is calculated, the fourth group of stored data 1101 is output through the fourth data line. According to this expansion idea, the storage width of the storage structure can be infinitely expanded.

[0044] To expand the storage depth, the number of basic units or basic units after the storage width is expanded is increased, and multiple basic units or basic units after the storage width is expanded are cascaded.

[0045] For example, assuming that Figure 3 The storage depth of the basic unit after the storage width is expanded is shown to be 8. One basic unit after the storage width is expanded is added, and two basic units after the storage width are cascaded. In this way, the number of address decoding lines is increased from 4 to 8, and the storage depth is doubled. According to this expansion idea, the storage depth of the storage structure can be infinitely expanded.

[0046] In one embodiment, the storage structure after the storage depth is expanded includes a plurality of cascaded storage units, and the storage unit is a basic unit or the basic unit after the storage width is expanded. Among them, each gate circuit in the cascaded multiple storage units is also correspondingly provided with an AND gate as a new gate circuit; the signal line of the enable signal is connected to the first input end of the AND gate, the output end of the gate circuit is connected to the second input end of the AND gate, and the output end of the AND gate is used as the output end of the new gate circuit. An OR gate is also provided between every two storage units, and the storage data of the corresponding bits of the two storage units are respectively input into the two input ends of the OR gate. When accessing the target storage data of the target storage address, each storage address of each storage unit is decoded and an enable signal is obtained. The enable signals corresponding to each storage address of the storage unit to which the target storage address belongs are valid, and the enable signals corresponding to each storage address of other storage units are invalid, and the output end of the OR gate outputs the target storage data.

[0047] Optionally, the storage unit is a basic unit, the number of bits of the basic unit is a first number, and the number of data lines of the basic unit is 1; a first number of OR gates are also arranged between every two storage units, and each OR gate corresponds to the storage data of the same bit from the data lines of the two storage units.

[0048] Exemplarily, the storage unit is a basic unit, and the storage data of the basic unit is shown in Table 1. The basic unit has 4 bits of storage data and 1 data line. Four OR gates are also arranged between the two cascaded basic units. The storage data of the first bit of the data line of each of the two cascaded basic units is respectively input into the two input ends of the first OR gate, the storage data of the second bit of the data line of each of the two cascaded basic units is respectively input into the two input ends of the second OR gate, the storage data of the third bit of the data line of each of the two cascaded basic units is respectively input into the two input ends of the third OR gate, the storage data of the fourth bit of the data line of each of the two cascaded basic units is respectively input into the two input ends of the fourth OR gate, and the four OR gates output 4 bits of storage data.

[0049] Optionally, the storage unit is a basic unit after the storage width is expanded, the number of data lines of the basic unit after the storage width is expanded is the second number, and the number of bits corresponding to each data line is the first number; a first number of OR gates are also arranged between every two storage units; for each data line, each OR gate corresponds to the storage data of the same bit from the data lines of the two storage units.

[0050] For example, assuming that Figure 3 The storage depth of the basic unit after the storage width is expanded is expanded to 8, and the storage data of the storage structure after the storage depth is expanded is shown in Table 3.

[0051] Table 3

[0052] like Figure 4 As shown in the figure, the storage structure after the storage depth is expanded includes two cascaded storage units, and the storage unit is the basic unit after the storage width is expanded. Among them, each storage unit has 4 groups of storage data and 4 data lines, and each group of storage data includes storage data of the same bits of 4 storage addresses. The unique hot code address of the first storage unit is a~d, and the 16 gate circuits in the gate circuit set of the first storage unit include: 0, c, d, c||d, b, b||d, b||c, b||c||d, a, a||d, a||c, a||c||d, a||b, a||b||d, a||b||c and a||b||c||d. The unique hot code address of the second storage unit is e~h, and the 16 gate circuits in the gate circuit set of the second storage unit include: 0, g, h, g||h, f, f||h, f||g, f||g||h, e, e||h, e||g, e||g||h, e||f, e||f||h, e||f||g and e||f||g||h. Each gate circuit in the two cascaded storage units is also correspondingly provided with an AND gate as a new gate circuit. The signal line of the enable signal is connected to the first input end of the AND gate, the output end of the gate circuit is connected to the second input end of the AND gate, and the output end of the AND gate is used as the output end of the new gate circuit. Four OR gates are also arranged between the two cascaded storage units. For each data line, the first bit of the storage data of the data line from the two cascaded basic units is respectively input into the two input ends of the first OR gate, the second bit of the storage data of the data line from the two cascaded basic units is respectively input into the two input ends of the second OR gate, the third bit of the storage data of the data line from the two cascaded basic units is respectively input into the two input ends of the third OR gate, and the fourth bit of the storage data of the data line from the two cascaded basic units is respectively input into the two input ends of the fourth OR gate. The storage data from each data line passes through four OR gates to output 4 bits of storage data, and a total of 16 bits of storage data are output.

[0053] When accessing the storage data 0011 at address 7, the addresses 0-7 of the two storage units are decoded and the enable signal en is obtained. The enable signals corresponding to the addresses 4-7 of the second storage unit to which address 7 belongs are valid, and the enable signals corresponding to the addresses 0-3 of the first storage unit are invalid. The output end of the OR gate outputs the storage data 0011 at address 7.

[0054] The storage circuit for storage and computing integration provided by the embodiment of the present invention includes: a storage structure with expandable storage depth and / or storage width, the storage depth is the number of storage addresses, and the storage width is the number of bits of storage data corresponding to each storage address. The basic unit of the storage structure includes: an address decoding line, a data line and a gate circuit set, the address decoding line is connected to the input end of the gate circuit in the gate circuit set, and the data line is connected to the output end of the gate circuit. When the stored data needs to be modified, only the connection of the data line needs to be modified, and when re-stripping, only the metal mask of the metal routing needs to be re-manufactured, and this cost will be a fraction of the cost of re-stripping from scratch, so the data update cost of the storage structure is controllable. For the expansion of storage width, the number of data lines is increased on the basis of the basic unit, and each data line is connected to the output end of the corresponding gate circuit in the gate circuit set, so the storage width of the storage structure can be infinitely expanded. For the expansion of storage depth, the number of basic units or basic units after the storage width is expanded is increased, and multiple basic units or basic units after the storage width is expanded are cascaded, so the storage depth of the storage structure can be wirelessly expanded. Since the storage circuit for storage and computing integrated provided by the embodiment of the present invention has a simple structure, the chip area is small and the capacity density is high. Since the storage circuit for storage and computing integrated provided by the embodiment of the present invention is a conventional circuit inside, it can be manufactured using conventional chip processes, so that the read delay is low. Since the storage circuit for storage and computing integrated provided by the embodiment of the present invention has a low production cost, low subsequent tape-out cost, small area, and fast reading speed, it has good prospects for engineering use. Therefore, the storage circuit for storage and computing integrated provided by the embodiment of the present invention has the advantages of large capacity density, low read delay, good prospects for engineering use, and controllable data update costs.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage circuit for storage and computing, characterized in that: include: A storage structure with expandable storage depth and / or storage width; The storage depth is the number of storage addresses, and the storage width is the number of bits of storage data corresponding to each storage address; The basic unit of the storage structure includes: an address decoding line, a data line and a gate circuit set; The address decoding line is connected to the input end of the gate circuit in the gate circuit set, and the data line is connected to the output end of the gate circuit; In order to expand the storage width, the number of the data lines is increased on the basis of the basic unit, and each of the data lines is connected to the output end of the corresponding gate circuit in the gate circuit set; In order to expand the storage depth, the number of the basic units or the basic units after the storage width is expanded is increased, and multiple basic units or the basic units after the storage width is expanded are cascaded.

2. The storage circuit for storage and computing integration according to claim 1, characterized in that: The basic unit after the storage width is expanded is used to store a second number of groups of storage data at the first number of storage addresses, each group of storage data includes storage data of the same bits of the first number of storage addresses; Among them, the first number of storage addresses are decoded to obtain the first number of one-hot code addresses, and the first number of one-hot code addresses are input to the input end of the corresponding gate circuit in the gate circuit set through the first number of address decoding lines of the basic unit, and the second number of groups of storage data are output through the second number of data lines after operation by the corresponding gate circuit in the gate circuit set.

3. The storage circuit for storage and computing as claimed in claim 2, characterized in that: For any two groups of stored data, the two groups of stored data are the same, and the gate circuits corresponding to the two groups of stored data are the same.

4. The storage circuit for storage and computing integration according to claim 2, characterized in that: For any two groups of stored data, the two groups of stored data are different, and the gate circuits corresponding to the two groups of stored data are different.

5. The storage circuit for storage and computing integration according to claim 1, characterized in that: The storage structure after the storage depth is expanded includes a plurality of cascaded storage units, and the storage unit is the basic unit or the basic unit after the storage width is expanded; Each of the gate circuits in the cascaded multiple storage units is also provided with an AND gate as a new gate circuit; the signal line of the enable signal is connected to the first input end of the AND gate, the output end of the gate circuit is connected to the second input end of the AND gate, and the output end of the AND gate serves as the output end of the new gate circuit; An OR gate is also provided between each two storage units, and the storage data of corresponding bits of the two storage units are respectively input into two input ends of the OR gate; When accessing the target storage data of the target storage address, each storage address of each storage unit is decoded and an enable signal is obtained. The enable signals corresponding to each storage address of the storage unit to which the target storage address belongs are valid, and the enable signals corresponding to each storage address of other storage units are invalid. The output end of the OR gate outputs the target storage data.

6. The storage circuit for storage and computing integration according to claim 5, characterized in that: The storage unit is the basic unit, the number of bits of the basic unit is the first number, and the number of data lines of the basic unit is 1; the first number of OR gates are also arranged between every two storage units, and each of the OR gates corresponds to the storage data of the same bit from the data lines of the two storage units.

7. The storage circuit for storage and computing as claimed in claim 5, characterized in that: The storage unit is the basic unit after the storage width is expanded, the number of data lines of the basic unit after the storage width is expanded is the second number, and the number of bits corresponding to each data line is the first number; the first number of OR gates are also arranged between every two storage units; for each data line, each OR gate corresponds to the storage data of the same bit from the data lines of the two storage units.

8. The storage circuit for storage and computing integration according to claim 1, characterized in that: The number of the address decoding lines in the basic unit is related to the manufacturing process or manufacturing tools of the metal routing.

9. The storage circuit for storage and computing integration according to claim 1, characterized in that: The number of each gate circuit in the gate circuit set is a value with 2 as the base and the number of the address decoding lines in the basic unit as the exponent.

10. The storage circuit for storage and computing integration according to claim 1, characterized in that: The basic unit is used to store the storage data of the first number of bits at the first number of storage addresses, and the first number of storage addresses corresponds to the storage data of the first number of bits in a one-to-one manner; Among them, the first number of storage addresses are decoded to obtain the first number of one-hot code addresses, and the first number of one-hot code addresses are input to the input end of the specified gate circuit in the gate circuit set through the first number of address decoding lines of the basic unit, and the storage data of the first number of bits are output through the data line after operation by the specified gate circuit in the gate circuit set.

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