Sensitive amplifier, readout circuit, and module based on bit line switch and capacitive coupling

Abstract

This invention relates to the field of DRAM circuit design technology, specifically to a sensitive amplifier, readout circuit, and module based on bit-line switches and capacitive coupling. The invention discloses a DRAM sensitive amplifier based on bit-line switches and capacitive coupling, comprising: nine NMOS transistors N1-N9, two PMOS transistors P1-P2, and two capacitors Cc1-Cc2. This invention designs a Selective Sensing Amplifier (SCSA) and, with corresponding control logic, incorporates a pre-charge phase, offset calibration phase, charge sharing phase, pre-sensing phase, and main sensing phase during DRAM memory cell readout. This ensures that the bit line BLT or BLB potential changes correctly, guaranteeing the SCSA readout amplification function. Compared to traditional DRAM sensitive amplifiers, the SCSA provided by this invention achieves a significant reduction in offset voltage and effectively increases sensing margin with only a small increase in the number of components.

Description

Technical Field

[0001] This invention relates to the field of DRAM circuit design technology, and more specifically, to: 1. a DRAM sensitive amplifier (SCSA) based on bit line switching and capacitive coupling; 2. a readout circuit based on the SCSA; and 3. a sensitive amplifier module designed based on the SCSA. Background Technology

[0002] DRAM (Dynamic RAM) is a dynamic random access memory that uses one transistor and one capacitor to store one bit of data. It requires periodic power supply to maintain the stored data.

[0003] As the density and capacity of DRAM circuits continue to increase, and process nodes gradually shrink, problems such as MOSFET size mismatch, data leakage in memory cells, parasitic capacitance of bit lines, and coupling noise between bit lines become increasingly severe, leading to a decrease in the effective voltage difference. The DRAM sensitive amplifier is a crucial component for reading DRAM stored data—it reads and amplifies the voltage of the bit lines to retrieve DRAM data. Because the effective voltage difference in DRAM circuits is decreasing, a DRAM sensitive amplifier with a smaller offset voltage is needed to achieve correct reading and amplification. However, the offset voltage of existing traditional DRAM sensitive amplifiers is relatively large, which can easily lead to erroneous amplification and errors in reading DRAM data.

[0004] Therefore, reducing the offset voltage of DRAM sensitive amplifiers is an important research direction. At the same time, it is also necessary to ensure that the improved DRAM sensitive amplifier does not contain too many components, so as to ensure that the circuit area occupied is not too large. Summary of the Invention

[0005] Therefore, it is necessary to provide a sensitive amplifier, readout circuit, and module based on bit line switching and capacitive coupling to address the problem of excessive offset voltage in existing traditional DRAM sensitive amplifiers.

[0006] This invention is achieved using the following technical solution:

[0007] In a first aspect, the present invention provides a DRAM sensitive amplifier based on bit line switching and capacitive coupling, comprising: nine NMOS transistors N1 to N9, two PMOS transistors P1 to P2, and two capacitors Cc1 to Cc2.

[0008] P1 source connection control signal SAP1;

[0009] The source of N1 is connected to the control signal SAN1, the drain is connected to the drain of P1, and the gate is connected to the gate of P1.

[0010] P2 source connection control signal SAP2;

[0011] The source of N2 is connected to the control signal SAN2, the drain is connected to the drain of P2, and the gate is connected to the gate of P2.

[0012] The gate of N3 is connected to the control signal OC, the drain is connected to the gate of P1, and the source is connected to the drain of P1.

[0013] The gate of N4 is connected to OC, the drain is connected to the gate of P2, and the source is connected to the drain of P2.

[0014] The gate of N5 is connected to the control signal TSE2, the source is connected to the bit line BLB, and the drain is connected to the drain of P1.

[0015] The gate of N6 is connected to the control signal TSE1, the source is connected to the bit line BLT, and the drain is connected to the drain of P2.

[0016] The gate of N7 is connected to the control signal BSE1, the source is connected to BLB, and the drain is connected to the drain of N6.

[0017] The gate of N8 is connected to the control signal BSE2, the source is connected to BLT, and the drain is connected to the drain of N5.

[0018] The gate of N9 is connected to the control signal BLEQ, the source is connected to the input signal VEQ, and the drain is connected to the drain of N6.

[0019] The first terminal of Cc1 is connected to BLT, and the second terminal is connected to the gate of P1;

[0020] The first end of Cc2 is connected to BLB, and the second end is connected to the gate of P2;

[0021] In this circuit, P1 and N1 constitute inverter one, and P2 and N2 constitute inverter two. Inverter one and inverter two are cross-coupled through Cc1 to Cc2 and form a latch structure.

[0022] This implementation of a DRAM sensitive amplifier based on bit-line switching and capacitive coupling is a method or process according to embodiments of this disclosure.

[0023] In a second aspect, the present invention discloses a readout circuit, comprising: a DRAM storage cell one, a DRAM storage cell two, and a DRAM sensitive amplifier based on bit line switching and capacitive coupling as disclosed in the first aspect.

[0024] DRAM storage cell one is used to store 0 or 1. DRAM storage cell two is used to store 0 or 1.

[0025] A DRAM sensitive amplifier based on bit line switching and capacitive coupling is used to read DRAM memory cell one or DRAM memory cell two.

[0026] This type of readout circuit is implemented according to the method or process of an embodiment of this disclosure.

[0027] Thirdly, the present invention discloses a sensitive amplifier module that adopts the circuit layout of a DRAM sensitive amplifier based on bit line switches and capacitive coupling as disclosed in the first aspect.

[0028] The implementation of this sensitive amplifier module is based on the method or process of an embodiment of this disclosure.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. This invention designs a DRAM sensitive amplifier based on bit line switching and capacitive coupling, and with corresponding control logic, it incorporates the following stages during DRAM memory cell reading: pre-charge stage, offset calibration stage, charge sharing stage, pre-sensing stage, and main sensing stage. Specifically, in the offset calibration stage, the offset is reduced by storing the difference between the inverter's flip voltage and the bit line voltage in a capacitor. Through the coordination of the pre-sensing stage and the main sensing stage, the bit line potential can be correctly varied and pulled to its full swing, ensuring the SCSA read amplification function.

[0031] 2. Compared with traditional DRAM sensitive amplifiers, the SCSA provided by this invention achieves a significant reduction in offset voltage and effectively increases sensing margin without a large increase in the number of components. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a circuit diagram of the SCSA disclosed in Embodiment 1 of the present invention;

[0034] Figure 2 For based on Figure 1 Circuit diagram of the readout circuit constructed using SCSA;

[0035] Figure 3 for Figure 2 Timing diagram of the read circuit;

[0036] Figure 4 For based on Figure 1 Pinout diagram of the sensitive amplifier module designed by SCSA;

[0037] Figure 5 The present invention discloses a circuit diagram of a readout circuit based on a conventional DRAM sensitive amplifier (BLSA) in Embodiment 2 of the present invention;

[0038] Figure 6 for Figure 5 Timing diagram of the read circuit;

[0039] Figure 7 for Figure 5 Offset voltage distribution diagram of BLSA in China;

[0040] Figure 8 for Figure 1 The diagram shows the offset voltage distribution of the SCSA. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] Example 1

[0045] First, see Figure 1 This is a circuit diagram of a DRAM sensitive amplifier (SCSA) based on bit line switching and capacitive coupling provided in Embodiment 1.

[0046] For SCSA, it includes: 9 NMOS transistors N1 to N9, 2 PMOS transistors P1 to P2, and 2 capacitors Cc1 to Cc2.

[0047] like Figure 1As shown, the connection relationships of each component are as follows:

[0048] P1 source connection control signal SAP1;

[0049] The source of N1 is connected to the control signal SAN1, the drain is connected to the drain of P1, and the gate is connected to the gate of P1.

[0050] P2 source connection control signal SAP2;

[0051] The source of N2 is connected to the control signal SAN2, the drain is connected to the drain of P2, and the gate is connected to the gate of P2.

[0052] The gate of N3 is connected to the control signal OC, the drain is connected to the gate of P1, and the source is connected to the drain of P1.

[0053] The gate of N4 is connected to OC, the drain is connected to the gate of P2, and the source is connected to the drain of P2.

[0054] The gate of N5 is connected to the control signal TSE2, the source is connected to the bit line BLB, and the drain is connected to the drain of P1.

[0055] The gate of N6 is connected to the control signal TSE1, the source is connected to the bit line BLT, and the drain is connected to the drain of P2.

[0056] The gate of N7 is connected to the control signal BSE1, the source is connected to BLB, and the drain is connected to the drain of N6.

[0057] The gate of N8 is connected to the control signal BSE2, the source is connected to BLT, and the drain is connected to the drain of N5.

[0058] The gate of N9 is connected to the control signal BLEQ, the source is connected to the input signal VEQ, and the drain is connected to the drain of N6.

[0059] The first terminal of Cc1 is connected to BLT, and the second terminal is connected to the gate of P1;

[0060] The first end of Cc2 is connected to BLB, and the second end is connected to the gate of P2.

[0061] In this circuit, P1 and N1 constitute inverter one, and P2 and N2 constitute inverter two. Inverter one and inverter two are cross-coupled through Cc1 to Cc2 and form a latch structure.

[0062] For ease of explanation later, the inputs and outputs of inverter 1 and inverter 2 can be represented using nodes:

[0063] The input of inverter 1 is node GB (i.e., the gate of P1, the gate of N1, the drain of N3, and the second terminal of Cc1 are connected to node GB), and the output is node IT (i.e., the drain of P1, the drain of N1, the source of N3, and the drain of N5 are connected to node IT).

[0064] The input of inverter 2 is node GT (i.e., the gate of P2, the gate of N2, the drain of N4, and the second terminal of Cc2 are connected to node GT), and the output is node IB (the drain of P2, the drain of N2, the source of N4, and the drain of N6 are connected to node IB).

[0065] Secondly, see Figure 2 Based on the aforementioned SCSA, a read circuit, i.e., the SCSA usage circuit, was constructed. This read circuit includes: SCSA, DRAM storage cell one, and DRAM storage cell two.

[0066] DRAM storage cell one is used to store 0 or 1. DRAM storage cell two is used to store 0 or 1. SCSA is used to read DRAM storage cell one or DRAM storage cell two.

[0067] DRAM storage cell one and DRAM storage cell two can adopt the common 1T1C structure.

[0068] See Figure 2 DRAM memory cell one includes: one NMOS transistor N11 and one capacitor C0. The drain of N11 is connected to BLT, and the gate is connected to word line WL0; the first terminal of C0 is connected to the source of N11, and the second terminal is grounded to GND. DRAM memory cell two includes: one NMOS transistor N10 and one capacitor C2. The drain of N10 is connected to BLB, and the gate is connected to word line WL1; the second terminal of C1 is connected to the source of N10, and the second terminal is grounded to GND.

[0069] It should be noted that WL0 and WL1 should not be turned on at the same time to prevent damage to the data in the DRAM storage cells.

[0070] The data reading operation using the disclosed reading circuit includes the following timing sequence: pre-charge (PC) stage, offset calibration (OC) stage, charge sharing (CS) stage, pre-sensing (PS) stage, and main sensing (MS) stage.

[0071] The principles behind each stage are explained below:

[0072] 1) During the pre-charging phase:

[0073] BLEQ is set to high level (N9 is on), VEQ is set to VDD / 2, OC is set to high level (N3 and N4 are on), TSE1, TSE2, BSE1, and BSE2 are set to high level (N5, N6, N7, and N8 are on), and SAN1, SAN2, SAP1, and SAP2 are set to VDD / 2 (inverter one and inverter two are not working). BLT and BLB are both precharged to VDD / 2 (VEQ charges BLT through N9 and N6, and VEQ charges BLB through N9 and N7. BLT and BLB are shorted through N8 and N5 to maintain VDD / 2).

[0074] 2) During the offset calibration phase:

[0075] BLEQ is set to low (N9 is off), OC remains high (N3 and N4 are on), TSE1, TSE2, BSE1, and BSE2 are set to low (N5, N6, N7, and N8 are off), SAN1 and SAN2 are set to low, and SAP1 and SAP2 are set to high (inverter one and inverter two are working, GB is shorted to IT through N3, and GT is shorted to IB through N4, so that the voltage of GB is the flip point voltage of inverter one, and the voltage of GT is the flip point voltage of inverter two). The voltage difference between the input terminal (GB) of inverter one and BLT is stored in Cc1, and the voltage difference between the input terminal (GT) of inverter two and BLB is stored in Cc2, thereby reducing offset.

[0076] 3) During the charge sharing phase:

[0077] BLEQ remains low (N9 is off), OC is set to low (N3 and N4 are off), TSE1, TSE2, BSE1, and BSE2 remain low (N5, N6, N7, and N8 are off), and SAN1, SAN2, SAP1, and SAP2 are set to VDD / 2 (inverter one and inverter two are not working).

[0078] 301. To read DRAM storage cell one, set WL0 to high level (N11 is turned on), and C1 and BLT share charge (C1 is turned on through N11 and BLT is turned on).

[0079] 302. To read DRAM storage cell 2, set WL1 to high level (N10 is turned on), and C2 and BLB share charge (C2 is turned on to BLB through N10).

[0080] 4) In the pre-sensing stage:

[0081] 401. To read DRAM storage cell one, WL0 is high during the charge sharing phase. During the pre-sensing phase, WL0 remains high (N11 is on), BLEQ remains low (N9 is off), OC remains low (N3 and N4 are off), TSE1 and TSE2 are high (N6 and N5 are on), BSE1 and BSE2 are low (N7 and N8 are off), SAN1 is low, SAP1 is high, and SAN2 and SAP2 remain at VDD / 2. Thus:

[0082] Inverter 1 operates and widens the voltage difference between its input (GB) and output (IT); since IT and BLB are connected through N5, this increases the voltage difference between the input (GB) and BLB of inverter 1.

[0083] Although inverter 2 is not working, IB and BLT are connected through N6, making their voltage levels the same.

[0084] 402. To read DRAM storage cell two, WL1 is high during the charge sharing phase. During the pre-sensing phase, WL1 remains high (N10 is on), BLEQ remains low (N9 is off), OC remains low (N3 and N4 are off), TSE1 and TSE2 are high (N6 and N5 are on), BSE1 and BSE2 are low (N7 and N8 are off), SAN2 is low, SAP2 is high, and SAN1 and SAP1 remain at VDD / 2. Thus:

[0085] Inverter 2 operates and widens the voltage difference between its input (GT) and output (IB); since IB and BLT are connected through N11, this increases the voltage difference between the input (IB) and BLT of inverter 2.

[0086] Although inverter 2 is not working, IT and BLB are connected through N5, making their voltage levels the same.

[0087] 5) During the main induction stage:

[0088] In general, during the main sensing phase, WL0 and WL1 remain in the same state as during the pre-sensing phase, BLEQ remains low (N9 is off), OC remains low (N3 and N4 are off), TSE1 and TSE2 remain high (N6 and N5 are on), BSE1 and BSE2 remain low (N7 and N8 are off), SAN1 and SAN2 are set to low, and SAP1 and SAP2 are set to high (inverter one and inverter two are working).

[0089] 501. To read DRAM storage cell one, and DRAM storage cell one is stored as 1, during the main sensing phase, WL0 is kept at a high level (N11 is on), and the cross-coupled inverter one and inverter two increase the voltage difference (inverter one increases the voltage difference between GB and IT, and inverter two increases the voltage difference between GT and IB). Based on the pre-sensing phase, the BLT voltage is quickly pulled up to VDD and the BLB voltage is quickly dropped to 0. Then, reading the BLT potential will obtain the stored data of DRAM storage cell one.

[0090] 502. If we want to read DRAM storage cell one, and DRAM storage cell one is stored as 0, then during the main sensing phase, WL0 is kept at a high level (N11 is on), and the cross-coupled inverter one and inverter two increase the voltage difference (inverter one increases the voltage difference between GB and IT, and inverter two increases the voltage difference between GT and IB). Then, based on the pre-sensing phase, the BLT voltage is quickly reduced to 0 and the BLB voltage is quickly pulled up to VDD. Then, reading the BLT potential will obtain the stored data of DRAM storage cell one.

[0091] 503. To read DRAM storage cell two, and DRAM storage cell two is stored as 1, during the main sensing phase, WL1 is kept at a high level (N10 is on), and the cross-coupled inverters one and two increase the voltage difference (inverter one increases the voltage difference between GB and IT, and inverter two increases the voltage difference between GT and IB). Based on the pre-sensing phase, the BLB voltage is quickly pulled up to VDD and the BLT voltage is quickly dropped to 0. Then, reading the BLB potential will obtain the stored data of DRAM storage cell two.

[0092] 504. If we want to read DRAM storage cell two and DRAM storage cell two stores 0, then during the main sensing stage, WL1 is kept at a high level (N10 is on), and the cross-coupled inverter one and inverter two increase the voltage difference (inverter one increases the voltage difference between GB and IT, and inverter two increases the voltage difference between GT and IB). Then, based on the pre-sensing stage, the BLB voltage is quickly reduced to 0 and then quickly pulled to VDD. Then, reading the BLB potential will obtain the stored data of DRAM storage cell two.

[0093] To facilitate understanding of the above stages, a timing diagram of each signal at each stage is drawn, taking the reading of DRAM storage cell one as an example. Figure 3 As shown.

[0094] Furthermore, this embodiment 1 also discloses a sensitive amplifier module, which adopts the circuit layout of the DRAM sensitive amplifier based on bit line switches and capacitive coupling disclosed above. The modular packaging facilitates the promotion and application of the aforementioned circuit.

[0095] like Figure 4 As shown, this sensitive amplifier module has 13 pins:

[0096] Pin 1 is used to connect to BLT; pin 2 is used to connect to BLB; pin 3 is used to connect to BLEQ; pin 4 is used to connect to VEQ; pin 5 is used to connect to SAP1; pin 6 is used to connect to SAP2; pin 7 is used to connect to SAN1; pin 8 is used to connect to SAN2; pin 9 is used to connect to TSE1; pin 10 is used to connect to TSE2; pin 11 is used to connect to BSE1; pin 12 is used to connect to TSE2; and pin 13 is used to connect to OC.

[0097] Example 2

[0098] This embodiment 2 aims to verify the performance of the DRAM sensitive amplifier based on bit line switching and capacitive coupling proposed in embodiment 1:

[0099] This embodiment 2 introduces a readout circuit built with an existing conventional DRAM sensitive amplifier (BLSA), and compares it with the readout circuit based on SCSA proposed in embodiment 1 through simulation.

[0100] First, the read circuit built based on BLSA is input. Figure 5 As shown, it includes: BLSA, DRAM storage unit three, and DRAM storage unit four.

[0101] The BLSA includes: 5 NMOS transistors NM1 to NM5 and 2 PMOS transistors PM1 to PM2. The sources of PM1 and PM2 are connected to the control signal SAP; the sources of N1 and N2 are connected to the control signal SAN; the drain of P1 is connected to the drain of N1, and its gate is connected to the gate of N1; the drain of P2 is connected to the drain of N2, the gate of P1, and connected to the bit line BLT', and its gate is connected to the gate of N2, the drain of P1, and the bit line BLB'; the source of N3 is connected to BLB', the drain is connected to BLT', and its gate is connected to the control signal BLEQ'; the source of N4 is connected to the source of N3, the drain is connected to the input signal VEQ', and its gate is connected to the gate of N3; the source of N5 is connected to the drain of N3, the drain is connected to the drain of N4, and its gate is connected to the gate of N4.

[0102] In this circuit, PM1 and NM1 form inverter three, and PM2 and NM2 form inverter four. Inverter three and inverter four are cross-coupled and form a latch structure.

[0103] DRAM storage cell three includes: one NMOS transistor NM7 and one capacitor CM1. The drain of NM7 is connected to BLT', and the gate is connected to word line WL3; the first terminal of CM1 is connected to the source of NM7, and the second terminal is grounded to GND.

[0104] DRAM memory cell four includes: one NMOS transistor NM6 and one capacitor CM2. The drain of NM7 is connected to BLB', and the gate is connected to word line WL4; the first terminal of CM2 is connected to the source of NM6, and the second terminal is grounded to GND.

[0105] For the read circuit based on BLSA with the above structure, its working timing for reading data includes: precharge (PC) stage, charge sharing (CS) stage, and main sensing (MS) stage.

[0106] 1) During the pre-charging phase:

[0107] BLEQ' is set to high level (NM3, NM4, and NM5 are turned on), VEQ' is set to VDD / 2, SAP and SAN are set to VDD / 2 (inverter three and inverter four are not working), BLT' and BLB' are both precharged to VDD / 2 (VEQ' charges BLT' through NM5, VEQ' charges BLB' through NM4, and BLT' and BLB' are turned on through NM3).

[0108] 2) During the charge sharing phase:

[0109] When BLEQ' is set to low (NM3, NM4, and NM5 are disconnected), SAP and SAN remain at VDD / 2 (inverter three and inverter four are not working).

[0110] To read DRAM storage cell three, WL3 is set to high level (NM7 is turned on), and CM1 and BLT' share charge (CM1 is connected to BLT' through NM7).

[0111] To read DRAM storage cell four, WL4 is set to high level (NM6 is turned on), and CM2 and BLB' share charge (CM2 is connected to BLB' through NM6).

[0112] 3) During the main induction stage:

[0113] In general, during the main sensing phase, WL3 and WL4 remain in the same state as during the charge sharing phase, BLEQ' remains at a low level (NM3, NM4, and NM5 are disconnected), SAN is set to a low level, and SAP is set to a high level (inverter three and inverter four are working).

[0114] 301. If we want to read DRAM storage cell three and DRAM storage cell one is stored as 0, then during the main sensing phase, WL3 is kept at a high level (NM7 is turned on). The cross-coupled inverters three and four quickly widen the voltage difference, causing the BLT' voltage to drop to 0 and the BLB' voltage to be pulled up to VDD. Then, reading the BLT' potential will obtain the stored data of DRAM storage cell three.

[0115] 302. If we want to read DRAM storage cell three and DRAM storage cell one is stored as 1, then during the main sensing phase, WL3 is kept at a high level (NM7 is turned on). The cross-coupled inverters three and four quickly widen the voltage difference, causing the BLB' voltage to drop to 0 and the BLT' voltage to be pulled up to VDD. Then, reading the BLT' potential will obtain the stored data of DRAM storage cell three.

[0116] 303. If we want to read DRAM storage cell four and DRAM storage cell four is storing 0, then during the main sensing phase, WL4 is kept at a high level (NM6 is turned on). The cross-coupled inverters three and four quickly widen the voltage difference, causing the BLB' voltage to drop to 0 and the BLT' voltage to be pulled up to VDD. Then, reading the BLB' potential will obtain the stored data of DRAM storage cell four.

[0117] 304. If we want to read DRAM storage cell four and DRAM storage cell four is stored as 1, then during the main sensing phase, WL4 is kept at a high level (NM6 is turned on). The cross-coupled inverters three and four quickly widen the voltage difference, causing the BLT' voltage to drop to 0 and the BLB' voltage to be pulled up to VDD. Then, reading the BLB' potential will obtain the stored data of DRAM storage cell four.

[0118] To facilitate understanding of the above stages, a timing diagram of each signal at each stage is drawn, taking the reading of DRAM storage cell three as an example. Figure 6 As shown.

[0119] Next, the read circuit based on SCSA in Example 1 and the read circuit based on BLSA described above are simulated.

[0120] The simulation conditions are as follows: based on 28nm CMOS process, the aspect ratio of PMOS transistor is 200:30, the aspect ratio of NMOS transistor is 100:30; the capacitance values ​​of Cc1 and Cc2 are 4fF.

[0121] 500 Monte Carlo simulations were performed at room temperature to obtain the offset voltage distribution under different process angles. See the results below. Figure 7 , Figure 8 .

[0122] Figure 7 , Figure 8 All figures are normal distribution curves of offset voltage, with the standard deviation taken as the offset voltage. It can be seen that the offset voltage of the SCSA (2.48mV) is much lower than that of the BLSA (18.01mV), demonstrating the significant performance advantage of the SCSA proposed in Example 1: a substantial reduction in offset voltage, effectively increasing the sensing margin.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0124] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A DRAM sense amplifier based on bit line switching and capacitive coupling, characterized by, Comprise: 9 NMOS tubes N1~N9, 2 PMOS tubes P1~P2, 2 capacitors Cc1~Cc2; The source of P1 is connected with control signal SAP1; The source of N1 is connected with control signal SAN1, the drain is connected with the drain of P1, and the gate is connected with the gate of P1; The source of P2 is connected with control signal SAP2; The source of N2 is connected with control signal SAN2, the drain is connected with the drain of P2, and the gate is connected with the gate of P2; The gate of N3 is connected with control signal OC, the drain is connected with the gate of P1, and the source is connected with the drain of P1; The gate of N4 is connected with OC, the drain is connected with the gate of P2, and the source is connected with the drain of P2; The gate of N5 is connected with control signal TSE2, the source is connected with bit line BLB, and the drain is connected with the drain of P1; The gate of N6 is connected with control signal TSE1, the source is connected with bit line BLT, and the drain is connected with the drain of P2; The gate of N7 is connected with control signal BSE1, the source is connected with BLB, and the drain is connected with the drain of N6; The gate of N8 is connected with control signal BSE2, the source is connected with BLT, and the drain is connected with the drain of N5; The gate of N9 is connected with control signal BLEQ, the source is connected with input signal VEQ, and the drain is connected with the drain of N6; The first end of Cc1 is connected with BLT, and the second end is connected with the gate of P1; The first end of Cc2 is connected with BLB, and the second end is connected with the gate of P2; Wherein, P1 and N1 constitute inverter one, P2 and N2 constitute inverter two; inverter one and inverter two realize cross coupling through Cc1~Cc2, and form a latch structure.

2. A reading circuit, characterized by Comprise: DRAM storage unit one for storing 0 or 1; DRAM storage unit two for storing 0 or 1; And The DRAM sensitive amplifier based on bit line switch and capacitor coupling as claimed in claim 1 is used for reading DRAM storage unit one or DRAM storage unit two.

3. The read circuit of claim 2, wherein, The DRAM storage unit one comprises: 1 NMOS tube N11, 1 capacitor C0; The drain of N11 is connected with BLT, and the gate is connected with word line WL0; The first end of C0 is connected with the source of N11, and the second end is connected with ground GND; The DRAM storage unit two comprises: 1 NMOS tube N10, 1 capacitor C2; The drain of N10 is connected with BLB, and the gate is connected with word line WL1; The second end of C1 is connected with the source of N10, and the second end is connected with ground GND; Wherein, WL0 and WL1 are not opened at the same time.

4. The read circuit of claim 3, wherein, The working timing of the reading circuit comprises pre-charging stage, unbalance calibration stage, charge sharing stage, pre-induction stage, main induction stage.

5. The read circuit of claim 4, wherein, In the pre-charging stage, BLEQ is set as high level, VEQ is set as VDD / 2, OC is set as high level, TSE1, TSE2, BSE1, BSE2 are set as high level, SAN1, SAN2, SAP1, SAP2 are set as VDD / 2, and BLT, BLB are all pre-charged to VDD / 2.

6. The read circuit of claim 5, wherein, In the misalignment calibration phase, BLEQ is low, OC is high, TSE1, TSE2, BSE1, BSE2 are low, SAN1, SAN2 are low, SAP1, SAP2 are high, the voltage difference between the input end of inverter one and BLT is stored in Cc1, and the voltage difference between the input end of inverter two and BLB is stored in Cc2.

7. The read circuit of claim 6, wherein, In the charge sharing phase, BLEQ remains low, OC is low, TSE1, TSE2, BSE1, BSE2 remain low, SAN1, SAN2, SAP1, SAP2 are VDD / 2; If WL0 is high, C1 shares charge with BLT; If WL1 is high, C2 shares charge with BLB.

8. The read circuit of claim 7, wherein, If WL0 is high in the charge sharing phase, in the pre-sensing phase, WL0 remains high, BLEQ remains low, OC remains low, TSE1, TSE2 are high, BSE1, BSE2 remain low, SAN1 is low, SAP1 is high, SAN2, SAP2 remain VDD / 2, and the voltage difference between the input end of inverter one and BLB is increased; If WL1 is high in the charge sharing phase, in the pre-sensing phase, WL1 remains high, BLEQ remains low, OC remains low, TSE1, TSE2 are high, BSE1, BSE2 remain low, SAN2 is low, SAP2 is high, SAN1, SAP1 remain VDD / 2, and the voltage difference between the input end of inverter two and BLT is increased.

9. The read circuit of claim 8, wherein, In the main sensing phase, WL0, WL1 remain the same as in the pre-sensing phase, BLEQ remains low, OC remains low, TSE1, TSE2 remain high, BSE1, BSE2 remain low, SAN1, SAN2 are low, SAP1, SAP2 are high; If DRAM storage unit one stores 1 and WL0 is high in the main sensing phase, the voltage of BLT is pulled to VDD, and the voltage of BLB is reduced to 0; If DRAM storage unit one stores 0 and WL0 is high in the main sensing phase, the voltage of BLT is reduced to 0, and the voltage of BLB is pulled to VDD; If DRAM storage unit two stores 1 and WL1 is high in the main sensing phase, the voltage of BLB is pulled to VDD, and the voltage of BLT is reduced to 0; If DRAM storage unit two stores 0 and WL1 is high in the main sensing phase, the voltage of BLB is reduced to 0, and the voltage of BLB is pulled to VDD.

10. A sensitive amplifier module characterized by, The circuit layout of the DRAM sensitive amplifier based on bit line switch and capacitor coupling is adopted. The circuit layout of the DRAM sensitive amplifier based on bit line switch and capacitor coupling is adopted.

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