Memory and operation method thereof, memory system and computer readable storage medium

Abstract

The embodiment of the invention discloses a memory and an operation method thereof, a memory system and a computer readable storage medium, the memory comprises a memory cell array and a peripheral circuit coupled with the memory cell array, the memory cell array comprises a plurality of memory cells, the plurality of memory cells have 2N data states, and N is an integer greater than or equal to 1; the peripheral circuit is configured to: read the memory cell array using a first read voltage, determine a first number of memory cells whose threshold voltages are greater than the first read voltage; the first reading voltage is greater than the first initial threshold voltage of the 2Nth data state; reading the memory cell array by using a second reading voltage, and determining a second number of memory cells of which the threshold voltage is greater than the second reading voltage; the second read voltage is greater than a second initial threshold voltage of the (2N-1) th data state and less than the first initial threshold voltage; and determining the trough position of the threshold voltage distribution interval of the 2Nth data state based on the difference between the second number and the first number.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to but are not limited to a memory and an operating method thereof, a memory system, and a computer-readable storage medium. Background Art

[0002] NAND memory has developed from single-level cell (SLC), double-level cell (MLC) to triple-level cell (TLC) and even quad-level cell (QLC). The number of stacking layers has also developed from 32 layers to 64 layers, 128 layers, 256 layers and even more layers.

[0003] As the integration and bit density of NAND memory increase, the bit error rate of data increases, and the reliability of data becomes more and more prominent. In order to enhance the reliability of data, Low Density Parity Check Code (LDPC) technology with stronger error correction capability is adopted to ensure that data can be written or read correctly. Summary of the invention

[0004] The present disclosure provides a memory and an operating method thereof, a memory system, and a computer-readable storage medium.

[0005] According to a first aspect of an embodiment of the present disclosure, a memory is provided, including:

[0006] A memory cell array, the memory cell array comprising a plurality of memory cells, the memory cells being configured to store N bits of data, the plurality of memory cells having 2 N data states, N is an integer greater than or equal to 1;

[0007] A peripheral circuit is coupled to the memory cell array, and the peripheral circuit is configured as follows:

[0008] The memory cell array is read using a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage; wherein the first read voltage is greater than a second N a first initial threshold voltage of a data state;

[0009] The memory cell array is read using a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage; wherein the second read voltage is greater than (2 N -1) a second initial threshold voltage of a data state and is less than the first initial threshold voltage;

[0010] Based on the difference between the second number and the first number, determine the second N The trough position of the threshold voltage distribution interval of each data state.

[0011] In some embodiments, the peripheral circuit is specifically configured as follows:

[0012] determining the difference between the second amount and the first amount;

[0013] Determine whether the difference is substantially equal to a preset value; wherein the preset value is the second N The number of storage cells in each data state;

[0014] When the difference is substantially equal to the preset value, it is determined that the valley position is located between the second read voltage and the first initial threshold voltage.

[0015] In some embodiments, the peripheral circuit is specifically configured as follows:

[0016] When the difference is smaller than the preset value, it is determined that the valley position is located between the second initial threshold voltage and the second read voltage.

[0017] In some embodiments, the peripheral circuit is further configured to:

[0018] When the difference is less than the preset value, the memory cell array is read using at least one offset read voltage until the difference between the number of memory cells having a threshold voltage greater than the offset read voltage and the first number is substantially equal to the preset value; wherein the offset read voltage is offset relative to the second read voltage, and the offset read voltage is greater than the second initial threshold voltage and less than the second read voltage.

[0019] In some embodiments, the at least one offset read voltage includes a first offset read voltage and a second offset read voltage, the second offset read voltage being less than the first offset read voltage; and the peripheral circuit is further configured to:

[0020] Based on the second read voltage, generating the first offset read voltage; wherein the first offset read voltage has a first offset relative to the second read voltage;

[0021] Based on the first offset read voltage, the second offset read voltage is generated; wherein the second offset read voltage has a second offset relative to the first offset read voltage, and the second offset is less than or equal to the first offset.

[0022] In some embodiments, the second N The number of storage cells in a data state includes the total number of the plurality of storage cells and 2N ratio.

[0023] In some embodiments, the peripheral circuit is configured to:

[0024] Based on the trough position, determine to distinguish the (2 N -1) data state and the second N The optimal read voltage for each data state.

[0025] In some embodiments, the peripheral circuit is further configured to:

[0026] A write operation is performed on the memory cell array so that a plurality of the memory cells have the 2 N Data state;

[0027] Based on the 2 N The first initial threshold voltage and the second initial threshold voltage are determined by a data state.

[0028] In some embodiments, the memory comprises flash memory.

[0029] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory is provided, the method comprising:

[0030] The memory cell array is read using a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage; wherein the memory cell array includes a plurality of the memory cells, the memory cells are configured to store N bits of data, and the plurality of the memory cells have 2 N data states, N is an integer greater than or equal to 1; the first read voltage is greater than the second N a first initial threshold voltage of a data state;

[0031] The memory cell array is read using a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage; wherein the second read voltage is greater than (2 N -1) a second initial threshold voltage of a data state and is less than the first initial threshold voltage;

[0032] Based on the difference between the second number and the first number, determine the second N The trough position of the threshold voltage distribution interval of each data state.

[0033] In some embodiments, the second number is determined based on the difference between the second number and the first number. N The trough position of the threshold voltage distribution interval of each data state includes:

[0034] determining the difference between the second amount and the first amount;

[0035] Determine whether the difference is substantially equal to a preset value; wherein the preset value is the second N The number of storage cells in each data state;

[0036] When the difference is substantially equal to the preset value, it is determined that the valley position is located between the second read voltage and the first initial threshold voltage.

[0037] In some embodiments, when the difference is less than the preset value, it is determined that the valley position is located between the second initial threshold voltage and the second read voltage.

[0038] In some embodiments, the operating method further includes:

[0039] When the difference is less than the preset value, the memory cell array is read using at least one offset read voltage until the difference between the number of memory cells having a threshold voltage greater than the offset read voltage and the first number is substantially equal to the preset value; wherein the offset read voltage is offset relative to the second read voltage, and the offset read voltage is greater than the second initial threshold voltage and less than the second read voltage.

[0040] In some embodiments, the at least one offset read voltage includes a first offset read voltage and a second offset read voltage, the second offset read voltage being less than the first offset read voltage; and the operating method further includes:

[0041] Based on the second read voltage, generating the first offset read voltage; wherein the first offset read voltage has a first offset relative to the second read voltage;

[0042] Based on the first offset read voltage, the second offset read voltage is generated; wherein the second offset read voltage has a second offset relative to the first offset read voltage, and the second offset is less than or equal to the first offset.

[0043] In some embodiments, the second N The number of storage cells in a data state includes the total number of the plurality of storage cells and 2 N ratio.

[0044] In some embodiments, the operating method further includes:

[0045] Based on the trough position, determine to distinguish the (2 N -1) data state and the second N The optimal read voltage for each data state.

[0046] In some embodiments, the operating method further includes:

[0047] A write operation is performed on the memory cell array so that a plurality of the memory cells have the 2 N Data state;

[0048] Based on the 2 N The first initial threshold voltage and the second initial threshold voltage are determined by a data state.

[0049] According to a third aspect of an embodiment of the present disclosure, a memory system is provided, including:

[0050] One or more memories as described in any one of the embodiments of the first aspect of the present disclosure;

[0051] A memory controller is coupled to the memory and is configured to control the memory.

[0052] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed, the operating method as described in any embodiment of the second aspect of the embodiment of the present disclosure is implemented.

[0053] In the embodiment of the present disclosure, a memory cell array is read by a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage, a memory cell array is read by a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage, and a second number of memory cells having a threshold voltage greater than the second read voltage is determined based on a difference between the second number and the first number. N The trough position of the threshold voltage distribution interval of each data state. On the one hand, the second N The trough position of each data state can be determined by the LDPC logic, which can reduce the number of times the read voltage is adjusted, thereby reducing the read time. Secondly, it can reduce the probability of error and improve the error correction capability of LDPC. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0055] Figure 1 is a schematic diagram of a system according to an embodiment of the present disclosure;

[0056] Figure 2a is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0057] Figure 2b is a schematic diagram of a solid state hard disk according to an embodiment of the present disclosure;

[0058] Figure 3 is a schematic diagram of the structure of a memory according to an embodiment of the present disclosure;

[0059] Figure 4 is a cross-sectional schematic diagram of a memory cell array according to an embodiment of the present disclosure;

[0060] Figure 5 is a schematic diagram of a peripheral circuit of a memory according to an embodiment of the present disclosure;

[0061] Figure 6 is a flow chart of a method for operating a memory according to an embodiment of the present disclosure;

[0062] Figure 7 Schematic diagram of a threshold voltage distribution of a memory according to an embodiment of the present disclosure Figure 1 ;

[0063] Figure 8 is a second schematic diagram of a threshold voltage distribution of a memory according to an embodiment of the present disclosure;

[0064] Fig. 9 Schematic diagram of a threshold voltage distribution of a memory according to an embodiment of the present disclosure Figure 3 ;

[0065] Fig.10 Schematic diagram of a threshold voltage distribution of a memory according to an embodiment of the present disclosure Figure 4 ;

[0066] Fig.11 Schematic diagram of a threshold voltage distribution of a memory according to an embodiment of the present disclosure Figure 5 ;

[0067] Fig.12 It is a flowchart of finding the valley position of the P7 state according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0069] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0070] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, terms such as "one" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0071] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0072] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0073] Figure 1 1 is a schematic diagram of a system 100 according to an embodiment of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0074] The memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital Memory Card (SD Card), a Compact Flash Card (CF Card), a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded MultiMedia Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0075] The memory controller 106 may be configured to control the operation of the memory 104, such as read, erase, and write operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with a host (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCIE) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced System Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0076] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in , the memory controller 106 and the single memory 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (Smart Media, SM) card, a memory stick, a Multi Media Card (Multi Media Card, MMC), a Reduced-Size MMC (RS-MMC), a Micro Multi Media Card (Multi Media Card Micro, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a Universal Flash Storage (Univeral Flash Storage, UFS), etc. The memory card 202 may also include a method for connecting the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 The memory 104 may include an SSD connector 208 coupled to the host 108 in the memory card 202. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. The memory 104 may include a volatile memory and a non-volatile memory, such as a NAND flash memory, a dynamic random access memory, a ferroelectric random access memory, a magnetic random access memory, a phase change random access memory, a resistive random access memory, a nano random access memory, etc.

[0077] Figure 3 is a schematic diagram of a structure of a memory 300 according to an embodiment of the present disclosure. The memory 300 may be Figure 1 An example of the memory 104 in FIG. Figure 3As shown, the memory 300 includes a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as a 3D NAND memory cell array for illustration, wherein the memory cell 306 is a NAND memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0078] like Figure 3 As shown, each memory string 308 may include a bottom select transistor (Bottom Selected Transistor, BST) 310 at its source terminal and a top select transistor (Top Selected Transistor, TST) 312 at its drain terminal. The bottom select transistor 310 and the top select transistor 312 may be configured to activate the selected memory string 308 during read and write operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (Source Line, SL) 314 (e.g., a common source line SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (Array Common Source, ACS). According to some embodiments, the top select transistor 312 of each memory string 308 is coupled to a corresponding bit line (Bit Line, BL) 316, and data can be read or written from the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top selection transistor 312) or a deselection voltage (e.g., 0V) to the corresponding top selection transistor 312 via one or more top selected lines (TSL) 313 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom selection transistor 310) or a deselection voltage (e.g., 0V) to the corresponding bottom selection transistor 310 via one or more bottom selected lines (BSL) 315.

[0079] like Figure 3As shown, the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits may be related to the number of memory strings 308 coupled by the word lines 318 in one memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding memory page 320 and a gate line coupling the control gates.

[0080] Figure 4 FIG. 3 is a cross-sectional schematic diagram of a memory cell array 301 according to an embodiment of the present disclosure. Figure 4 As shown, the memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of memory cells included in the memory cell array 301 is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0081] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as a top selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a bottom selection gate line, and the gate layer 411 extending laterally between the top selection gate line and the bottom selection gate line may serve as a word line.

[0082] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0083] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also known as "charge trapping"), and a barrier layer. The channel structure may have a cylindrical shape. According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO).

[0084] Return to reference Figure 3, the peripheral circuit 302 may be coupled to the memory cell array 301 via the bit line 316, the word line 318, the source line 314, the bottom selection line 315, and the top selection line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the bottom selection line 315, and the top selection line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0085] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and write (also referred to as program) data to the memory cell array 301 according to a control signal from the control logic unit 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic unit 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0086] The row decoder / word line driver 508 may be configured to be controlled by the control logic unit 512, and select / deselect the memory block 304 of the memory cell array 301, and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the bottom selection line 315 and the top selection line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic unit 512, and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0087] The control logic unit 512 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic unit 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic unit 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 512, and to buffer status information received from the control logic unit 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0088] Increased erase and write times, aging of storage cells, loss of electrons in storage cells due to long storage time, threshold voltage shift due to many reads, interference between storage cells, write errors, etc. will all lead to read errors, affecting the reliability of data stored in the memory. In order to enhance data reliability, LDPC technology with stronger error correction capability is adopted to ensure that data can be written or read correctly.

[0089] LDPC includes hard decoding and soft decoding. Compared with hard decoding, soft decoding has more advantages. However, in the process of soft decoding, multiple iterative calculations are required to find the trough, which not only wastes reading time but also often makes mistakes.

[0090] Based on one or more of the above problems, an embodiment of the present disclosure provides a method for operating a memory.

[0091] Figure 6 is a flow chart of a method for operating a memory according to an embodiment of the present disclosure. Figure 6 As shown, the operation method at least includes the following steps:

[0092] S610: Reading a memory cell array using a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage; wherein the memory cell array includes a plurality of memory cells, each of which is configured to store N bits of data, and each of the plurality of memory cells has 2 N data states, N is an integer greater than or equal to 1; the first read voltage is greater than the second N a first initial threshold voltage of a data state;

[0093] S620: Read the memory cell array using a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage; wherein the second read voltage is greater than (2 N -1) a second initial threshold voltage of a data state and is less than the first initial threshold voltage;

[0094] S630: Determine the second quantity based on the difference between the second quantity and the first quantity. N The trough position of the threshold voltage distribution interval of each data state.

[0095] In this embodiment, the memory includes an SLC memory, an MLC memory, a TLC memory, or a QLC memory, etc., wherein one storage unit of the SLC memory stores one bit of data, and multiple SLC storage units have two data states; one storage unit of the MLC memory stores two bits of data, and multiple MLC storage units have four data states; one storage unit of the TLC memory stores three bits of data, and multiple TLC storage units have eight data states; one storage unit of the QLC memory stores four bits of data, and multiple QLC storage units have 16 data states. For ease of understanding, the following description will be made by taking the TLC memory as an example.

[0096] The TLC memory has 8 data states, wherein 1 data state is an erased state, 7 data states are programmed states, the erased state is denoted as P0, and the programmed states are denoted as P1, P2, P3, P4, P5, P6 and P7 from the 1st state to the 7th state. It can be understood that the threshold voltage gradually increases from the P0 state to the P7 state. Figure 7 As shown, Figure 7The threshold voltages before the shift from the P0 state to the P7 state are shown. For simplicity, the threshold voltages before the shift from the P7 state to the P6 state are respectively recorded as the first initial threshold voltage and the second initial threshold voltage in the following text.

[0097] It should be noted that the above-mentioned increased number of erase and write times, aging of storage cells, loss of electrons in storage cells due to long storage time, large number of read times, interference between storage cells, write errors, etc. will cause the initial threshold voltage of at least one data state in multiple data states to shift, resulting in read errors, for example, Figure 8 The threshold voltage after the shift from the P0 state to the P7 state is shown. Therefore, it is necessary to find the trough position of the threshold voltage distribution interval of the data state after the shift. Here, the trough refers to the minimum number of storage cells corresponding to the threshold voltage distribution of the data state, that is, the minimum value of the threshold voltage of the data state.

[0098] Exemplarily, in step S610, a first read voltage is used to read the memory cell array, and the first read voltage is greater than the first initial threshold voltage of the P7 state, so as to determine a first number Cnt1 of memory cells whose threshold voltage is greater than the first read voltage. Figure 8 The first read voltage V1 shown performs a read operation, thereby determining that the first number Cnt1 is 0, that is, the threshold voltages of the P0 state to the P7 state are all less than the first read voltage. In practical applications, the threshold voltage is usually not a fixed value, but an interval. Therefore, the first read voltage V1 can be set to a maximum value greater than the first initial threshold voltage.

[0099] Exemplarily, in step S620, the memory cell array is read using a second read voltage, the second read voltage being greater than the second initial threshold voltage of the P6 state and less than the first initial threshold voltage of the P7 state, thereby determining a second number Cnt2 of memory cells having a threshold voltage greater than the second read voltage. Fig. 9 The second read voltage V2 shown in FIG. 1 performs a read operation, thereby determining the second number Cnt2 (eg, Fig. 9 In this case, the second number Cnt2 is less than the number of memory cells in the P7 state. In a specific example, the second read voltage V2 may be Figure 7 As shown, RL7 may be a default read voltage for distinguishing the second initial threshold voltage from the first initial threshold voltage. For example, RL7 is 0V.

[0100] Exemplarily, in step S630, based on the difference between the second number Cnt2 and the first number Cnt1, the valley position of the threshold voltage distribution interval of the P7 state is determined. For example, based on Cnt2-Cnt1, it is determined that the P7 state is shifted to the left, and the valley of the threshold voltage of the P7 state is located on the left side of the second read voltage V2.

[0101] In practical applications, when the threshold voltage of the memory cell being read is greater than the first read voltage, a first logic value may be output, and when the threshold voltage of the memory cell being read is less than or equal to the first read voltage, a second logic value may be output. By counting the number of the first logic value and / or the second logic value, the first number Cnt1 may be determined. The first logic value may be one of the logic values ​​"1" or "0", and the second logic value may be the other of the logic values ​​"1" or "0". The statistical method of the second number Cnt2 may be similar to the statistical method of the first number Cnt1, and for the sake of brevity, it will not be repeated.

[0102] In the embodiment of the present disclosure, a memory cell array is read by a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage, a memory cell array is read by a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage, and a second number of memory cells having a threshold voltage greater than the second read voltage is determined based on a difference between the second number and the first number. N The trough position of the threshold voltage distribution interval of each data state. On the one hand, the second N The trough position of each data state can be determined by the LDPC logic, which can reduce the number of times the read voltage is adjusted, thereby reducing the read time. Secondly, it can reduce the probability of error and improve the error correction capability of LDPC.

[0103] In some embodiments, the above step S630 includes: determining the difference between the second quantity and the first quantity; determining whether the difference is substantially equal to a preset value; wherein the preset value is the second N When the difference is substantially equal to the preset value, determining that the valley position is located between the second read voltage and the first initial threshold voltage.

[0104] In some embodiments, when the difference is less than a preset value, it is determined that the valley position is between the second initial threshold voltage and the second read voltage.

[0105] Exemplarily, when the difference between the second number Cnt2 and the first number Cnt1 is based on the number of memory cells in the P7 state, it is determined that the valley of the threshold voltage of the P7 state is between the second read voltage and the first initial threshold voltage. In a specific embodiment, the valley of the threshold voltage of the P7 state is between the second read voltage and the minimum value of the first initial threshold voltage. Here, substantially equal to includes: the difference between the second number Cnt2 and the first number Cnt1 is completely equal to the number of memory cells in the P7 state; or, the absolute value of the difference between the second number Cnt2 and the first number Cnt1 and the difference between the number of memory cells in the P7 state is within the allowable error range.

[0106] Exemplarily, when the difference between the second number Cnt2 and the first number Cnt1 is less than or equal to the number of memory cells in the P7 state, it is determined that the valley of the threshold voltage of the P7 state is between the second initial threshold voltage and the second read voltage, such as Fig. 9 In a specific embodiment, the valley of the threshold voltage of the P7 state is located between the maximum value of the second initial threshold voltage and the second read voltage.

[0107] It is understandable that after programming a plurality of memory cells to the P1 state to the P7 state respectively, the number of memory cells corresponding to each data state is determined. For example, the number of memory cells in the P7 state may be Figure 7 The integral of the threshold voltage distribution curve of the P7 state (ie, the preset value).

[0108] In the embodiment of the present disclosure, by determining the difference between the second quantity and the first quantity, and comparing the difference with the second quantity, N The number of storage cells in each data state is compared; when the difference is substantially equal to the second N When the number of storage cells in the data state is determined, the second N The valley position of the data state is located between the second read voltage and the first initial threshold voltage; N When the number of storage cells in the data state is determined, the second N The valley position of the first data state is located between the second initial threshold voltage and the second read voltage, so that the second data state can be determined quickly and efficiently. N The trough position of a data state.

[0109] In some embodiments, the above-mentioned operating method also includes: when the difference is less than a preset value, using at least one offset read voltage to read the memory cell array until the difference between the number of memory cells whose threshold voltage is greater than the offset read voltage and the first number is substantially equal to the preset value; wherein the offset read voltage is offset relative to the second read voltage, and the offset read voltage is greater than the second initial threshold voltage and less than the second read voltage.

[0110] For example, when using Fig. 9 After the second read voltage V2 shown is used to read the memory cell array, at least one offset read voltage can be generated based on the second read voltage V2. The offset read voltage is shifted to the left compared to the second read voltage V2, that is, the offset read voltage is less than the second read voltage V2. By continuing to read the memory cell array using the offset read voltage, the valley position of the threshold voltage distribution interval of the P7 state can be further accurately found.

[0111] In this embodiment, the default read voltage can be offset to obtain at least one offset read voltage, and the offset read voltage is used to read the memory cell array until the difference between the number of memory cells whose threshold voltage is greater than the offset read voltage and the first number is substantially equal to the number of memory cells in the P7 state. The valley position of the threshold voltage distribution interval of the P7 state can be accurately found, thereby assisting in finding the valley position of the threshold voltage distribution interval after the offset of other data states (for example, the P1 state to the P6 state).

[0112] In some embodiments, the at least one offset read voltage includes a first offset read voltage and a second offset read voltage, and the second offset read voltage is less than the first offset read voltage; and the above operation method further includes:

[0113] Based on the second read voltage, generating a first offset read voltage; wherein the first offset read voltage has a first offset relative to the second read voltage;

[0114] Based on the first offset read voltage, a second offset read voltage is generated; wherein the second offset read voltage has a second offset relative to the first offset read voltage, and the second offset is less than or equal to the first offset.

[0115] For example, refer to Fig. 9 As shown, based on the second read voltage V2, a first offset read voltage V21 is generated; the memory cell array is read using the first offset read voltage V21, the first offset read voltage V21 is greater than the second initial threshold voltage and less than the second read voltage V2; the third number of memory cells having a threshold voltage greater than the first offset read voltage V21 is determined, and at this time the third number is still less than the number of memory cells in the P7 state, and the read voltage needs to be continuously offset to the left to accurately find the valley position of the threshold voltage of the P7 state. In this embodiment, the first offset read voltage V21 can be set to be greater than the maximum value of the second initial threshold voltage.

[0116] For example, refer to Fig. 9 As shown, based on the first offset read voltage V21, a second offset read voltage V22 is generated; the memory cell array is read using the second offset read voltage V22, the second offset read voltage V22 is greater than the second initial threshold voltage and less than the first offset read voltage V21; the fourth number of memory cells having a threshold voltage greater than the second offset read voltage V22 is determined, and at this time the fourth number is substantially equal to the number of memory cells in the P7 state, thereby accurately finding the valley position of the threshold voltage of the P7 state. In this embodiment, the second offset read voltage V22 can be set to be greater than the maximum value of the second initial threshold voltage.

[0117] It should be noted that, in the above, a plurality of different offset read voltages are generated based on the second read voltage, for example, the first offset read voltage V21 and the second offset read voltage V22. When the first offset read voltage V21 is used but still fails to find the valley position of the threshold voltage of the P7 state, the voltage offset can be reduced, that is, the second offset is smaller than the first offset, so as to find more accurately. Of course, in other embodiments, the second offset can be equal to the first offset.

[0118] In the implementation of the present disclosure, a first offset read voltage is generated based on a second read voltage, and the first offset read voltage has a first offset relative to the second read voltage; a second offset read voltage is generated based on the first offset read voltage, and the second offset read voltage has a second offset relative to the first offset read voltage, and the second offset is less than or equal to the first offset. By adjusting the size of the offset of the read voltage, the second offset read voltage can be quickly and accurately found. N The trough position of the threshold voltage distribution interval after the data state is shifted can be found to assist in finding the trough position of the threshold voltage distribution interval after the other data states are shifted.

[0119] In other embodiments, the first offset read voltage may be greater than a minimum value of the second initial threshold voltage and less than or equal to a maximum value of the second initial threshold voltage.

[0120] For example, refer to Fig.10 As shown, based on the second read voltage V2, a first offset read voltage V21' is generated; the memory cell array is read using the first offset read voltage V21', the first offset read voltage V21' is greater than the minimum value of the second initial threshold voltage and less than the maximum value of the second initial threshold voltage; a third number Cnt21' (such as Fig.10 In this case, the third number is greater than the number of storage cells in the P7 state, and the offset of the offset read voltage is too large. The read voltage needs to be offset to the right to accurately find the valley position of the threshold voltage of the P7 state.

[0121] For example, refer to Fig.11 As shown, a second offset read voltage V22' is generated based on the first offset read voltage V21'; the memory cell array is read using the second offset read voltage V22' to determine a fourth number Cnt22' (eg, Fig.11 At this time, the fourth number Cnt22′ is substantially equal to the number of memory cells in the P7 state, so that the valley position of the threshold voltage of the P7 state can be accurately found.

[0122] In practical applications, the offset of the read voltage can be reasonably adjusted according to the result of each reading, so as to quickly and accurately find the valley position of the highest state threshold voltage distribution interval.

[0123] In some embodiments, the second N The number of storage units in a data state includes the total number of storage units and 2 N In this embodiment, the plurality of memory cells have 8 data states, and the number of memory cells in each data state may be the same. For example, the number of memory cells in any one data state from the P0 state to the P7 state may be 1 / 8 of the total number of memory cells. Of course, in other embodiments, the number of memory cells in any two data states from the P0 state to the P7 state may be different.

[0124] In practical applications, after programming, the memory cell array can be read to obtain Figure 7 The threshold voltage distribution is shown, thereby determining the number of memory cells in each data state. Here, the number of memory cells in each data state is the integral of the threshold voltage distribution curve of the data state.

[0125] In some embodiments, the above operation method further includes: determining, based on the trough position, to distinguish the second N -1) data state and the 2nd N For example, referring to Fig. 9 As shown, the second offset read voltage V22 can be determined as the optimal read voltage, so as to accurately distinguish the threshold voltages of the P6 state and the P7 state after the offset.

[0126] In some embodiments, the above operation method further includes: performing a write operation on the memory cell array so that the plurality of memory cells have 2 N Data state; based on 2 N The data states determine the first initial threshold voltage and the second initial threshold voltage.

[0127] Fig.12 FIG. 1 is a flowchart of a method for finding the valley position of the P7 state according to an embodiment of the present disclosure. Fig.12As shown, it specifically includes: initialization; setting the read voltage to a first read voltage, which may be a maximum value greater than the initial threshold voltage of the P7 state; using the first read voltage to read the NAND array, and determining a first number of storage cells whose threshold voltage is greater than the first read voltage, and the first number may be 0; setting the read voltage to a second read voltage, which may be a default read voltage for distinguishing the initial threshold voltage of the P6 state from the initial threshold voltage of the P7 state, for example, 0V; using the second read voltage to read the NAND array, and determining a second number of storage cells whose threshold voltage is greater than the second read voltage; judging whether the difference between the second number and the first number is substantially equal to the number of storage cells in the P7 state, if the difference is less than the number of storage cells in the P7 state, then continuing to adjust the read voltage until the difference is substantially equal to 1 / 8 of the total number of multiple storage cells, thereby determining the valley position of the P7 state; if the difference is substantially equal to the number of storage cells in the P7 state, directly determining the valley position of the P7 state, and not continuing to adjust the read voltage. In this embodiment, the number of storage cells in the P7 state is 1 / 8 of the total number of multiple storage cells.

[0128] Based on the above memory operation method, the present disclosure further provides a memory, including:

[0129] A memory cell array, wherein the memory cell array includes a plurality of memory cells, the memory cells are configured to store N bits of data, and the plurality of memory cells have 2 N data states, N is an integer greater than or equal to 1;

[0130] The peripheral circuit is coupled to the memory cell array, and the peripheral circuit is configured as follows:

[0131] The memory cell array is read using a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage; wherein the first read voltage is greater than a second N a first initial threshold voltage of a data state;

[0132] The memory cell array is read using a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage; wherein the second read voltage is greater than (2 N -1) a second initial threshold voltage of a data state and is less than the first initial threshold voltage;

[0133] Based on the difference between the second quantity and the first quantity, determine the second N The trough position of the threshold voltage distribution interval of each data state.

[0134] In some embodiments, the peripheral circuit is specifically configured as follows:

[0135] determining a difference between the second amount and the first amount;

[0136] Determine whether the difference is substantially equal to a preset value; wherein the preset value is the second N The number of storage cells in each data state;

[0137] When the difference is substantially equal to the preset value, it is determined that the valley position is located between the second read voltage and the first initial threshold voltage.

[0138] In some embodiments, the peripheral circuit is specifically configured as follows:

[0139] When the difference is smaller than the preset value, it is determined that the valley position is located between the second initial threshold voltage and the second read voltage.

[0140] In some embodiments, the peripheral circuit is further configured to:

[0141] When the difference is less than a preset value, at least one offset read voltage is used to read the memory cell array until the difference between the number of memory cells whose threshold voltage is greater than the offset read voltage and the first number is substantially equal to the preset value; wherein the offset read voltage is offset relative to the second read voltage, and the offset read voltage is greater than the second initial threshold voltage and less than the second read voltage.

[0142] In some embodiments, the at least one offset read voltage includes a first offset read voltage and a second offset read voltage, the second offset read voltage being less than the first offset read voltage; and the peripheral circuit is further configured to:

[0143] Based on the second read voltage, generating a first offset read voltage; wherein the first offset read voltage has a first offset relative to the second read voltage;

[0144] Based on the first offset read voltage, a second offset read voltage is generated; wherein the second offset read voltage has a second offset relative to the first offset read voltage, and the second offset is less than or equal to the first offset.

[0145] In some embodiments, the second N The number of storage units in a data state includes the total number of storage units and 2 N ratio.

[0146] In some embodiments, the peripheral circuit is configured to:

[0147] Based on the trough position, determine the difference between (2 N -1) data state and the 2nd N The optimal read voltage for each data state.

[0148] In some embodiments, the peripheral circuit is further configured to:

[0149] A write operation is performed on the memory cell array so that a plurality of memory cells have 2N Data state;

[0150] Based on 2 N The data states determine the first initial threshold voltage and the second initial threshold voltage.

[0151] In some embodiments, the memory includes flash memory.

[0152] Here, the specific structure and composition of the memory can be referred to in the above Figure 3 , Figure 4 , Figure 5 The other details about the memory are similar to those in the aforementioned memory operation method, and for the sake of brevity, they are not repeated here.

[0153] Based on the above memory, an embodiment of the present disclosure further provides a memory system, including:

[0154] One or more memories according to any of the above embodiments;

[0155] A memory controller is coupled to the memory and is configured to control the memory.

[0156] Here, the specific structure and composition of the memory system can be referred to in the above Figure 1 , Figure 2a , Figure 2b , Figure 3 , Figure 4 , Figure 5 The other details about the memory system are similar to those mentioned above and will not be described here for the sake of brevity.

[0157] The embodiments of the present disclosure further provide a computer-readable storage medium, on which instructions are stored, and when the instructions are executed, an operation method as in any of the above embodiments is implemented.

[0158] Here, all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk (HDD) or a solid state drive, etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0159] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0160] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0161] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0162] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0163] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: A memory cell array, the memory cell array comprising a plurality of memory cells, the memory cells being configured to store N bits of data, the plurality of memory cells having 2 N data states, N is an integer greater than or equal to 1; A peripheral circuit is coupled to the memory cell array, and the peripheral circuit is configured as follows: The memory cell array is read using a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage; wherein the first read voltage is greater than a second N a first initial threshold voltage of a data state; The memory cell array is read using a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage; wherein the second read voltage is greater than (2 N -1) a second initial threshold voltage of a data state and is less than the first initial threshold voltage; Based on the difference between the second number and the first number, determine the second N The trough position of the threshold voltage distribution interval of each data state.

2. The memory according to claim 1, characterized in that: The peripheral circuit is specifically configured as follows: determining the difference between the second amount and the first amount; Determine whether the difference is substantially equal to a preset value; wherein the preset value is the second N The number of storage cells in each data state; When the difference is substantially equal to the preset value, it is determined that the valley position is located between the second read voltage and the first initial threshold voltage.

3. The memory according to claim 2, characterized in that: The peripheral circuit is specifically configured as follows: When the difference is smaller than the preset value, it is determined that the valley position is located between the second initial threshold voltage and the second read voltage.

4. The memory according to claim 2, characterized in that: The peripheral circuit is further configured as: When the difference is less than the preset value, the memory cell array is read using at least one offset read voltage until the difference between the number of memory cells having a threshold voltage greater than the offset read voltage and the first number is substantially equal to the preset value; wherein the offset read voltage is offset relative to the second read voltage, and the offset read voltage is greater than the second initial threshold voltage and less than the second read voltage.

5. The memory according to claim 4, characterized in that: The at least one offset read voltage includes a first offset read voltage and a second offset read voltage, wherein the second offset read voltage is less than the first offset read voltage; and the peripheral circuit is further configured to: Based on the second read voltage, generating the first offset read voltage; wherein the first offset read voltage has a first offset relative to the second read voltage; Based on the first offset read voltage, the second offset read voltage is generated; wherein the second offset read voltage has a second offset relative to the first offset read voltage, and the second offset is less than or equal to the first offset.

6. The memory according to claim 2, characterized in that: The second N The number of storage cells in a data state includes the total number of the plurality of storage cells and 2 N ratio.

7. The memory according to claim 1, characterized in that: The peripheral circuit is configured as: Based on the trough position, determine to distinguish the (2 N -1) data state and the second N The optimal read voltage for each data state.

8. The memory according to claim 1, characterized in that: The peripheral circuit is further configured as: A write operation is performed on the memory cell array so that a plurality of the memory cells have the 2 N Data state; Based on the 2 N The first initial threshold voltage and the second initial threshold voltage are determined by a data state.

9. The memory according to claim 1, characterized in that: The memory includes flash memory.

10. A method for operating a memory, characterized in that: The operation method comprises: The memory cell array is read using a first read voltage to determine a first number of memory cells having a threshold voltage greater than the first read voltage; wherein the memory cell array includes a plurality of the memory cells, the memory cells are configured to store N bits of data, and the plurality of the memory cells have 2 N data states, N is an integer greater than or equal to 1; the first read voltage is greater than the second N a first initial threshold voltage of a data state; The memory cell array is read using a second read voltage to determine a second number of memory cells having a threshold voltage greater than the second read voltage; wherein the second read voltage is greater than (2 N -1) a second initial threshold voltage of a data state and is less than the first initial threshold voltage; Based on the difference between the second number and the first number, determine the second N The trough position of the threshold voltage distribution interval of each data state.

11. The operating method according to claim 10, characterized in that: The second number is determined based on the difference between the second number and the first number. N The trough position of the threshold voltage distribution interval of each data state includes: determining the difference between the second amount and the first amount; Determine whether the difference is substantially equal to a preset value; wherein the preset value is the second N The number of storage cells in each data state; When the difference is substantially equal to the preset value, it is determined that the valley position is located between the second read voltage and the first initial threshold voltage.

12. The operating method according to claim 11, characterized in that: When the difference is smaller than the preset value, it is determined that the valley position is located between the second initial threshold voltage and the second read voltage.

13. The operating method according to claim 11, characterized in that: The operation method also includes: When the difference is less than the preset value, the memory cell array is read using at least one offset read voltage until the difference between the number of memory cells having a threshold voltage greater than the offset read voltage and the first number is substantially equal to the preset value; wherein the offset read voltage is offset relative to the second read voltage, and the offset read voltage is greater than the second initial threshold voltage and less than the second read voltage.

14. The operating method according to claim 13, characterized in that: The at least one offset read voltage includes a first offset read voltage and a second offset read voltage, the second offset read voltage being less than the first offset read voltage; The operation method also includes: Based on the second read voltage, generating the first offset read voltage; wherein the first offset read voltage has a first offset relative to the second read voltage; Based on the first offset read voltage, the second offset read voltage is generated; wherein the second offset read voltage has a second offset relative to the first offset read voltage, and the second offset is less than or equal to the first offset.

15. The operating method according to claim 11, characterized in that: The second N The number of storage cells in a data state includes the total number of the plurality of storage cells and 2 N ratio.

16. The operating method according to claim 10, characterized in that: The operation method also includes: Based on the trough position, determine to distinguish the (2 N -1) data state and the second N The optimal read voltage for each data state.

17. The operating method according to claim 10, characterized in that: The operation method also includes: A write operation is performed on the memory cell array so that a plurality of the memory cells have the 2 N Data state; Based on the 2 N The first initial threshold voltage and the second initial threshold voltage are determined by a data state.

18. A memory system, characterized in that: include: One or more memories as claimed in any one of claims 1 to 9; A memory controller is coupled to the memory and is configured to control the memory.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed, the operating method according to any one of claims 10 to 17 is implemented.

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